Commit | Line | Data |
---|---|---|
89dd0842 JS |
1 | /* |
2 | * Freescale MPC5200 PSC DMA | |
3 | * ALSA SoC Platform driver | |
4 | * | |
5 | * Copyright (C) 2008 Secret Lab Technologies Ltd. | |
dbcc3475 | 6 | * Copyright (C) 2009 Jon Smirl, Digispeaker |
89dd0842 JS |
7 | */ |
8 | ||
89dd0842 | 9 | #include <linux/module.h> |
89dd0842 | 10 | #include <linux/of_device.h> |
5a0e3ad6 | 11 | #include <linux/slab.h> |
f0fba2ad | 12 | #include <linux/of_platform.h> |
89dd0842 | 13 | |
89dd0842 | 14 | #include <sound/soc.h> |
89dd0842 JS |
15 | |
16 | #include <sysdev/bestcomm/bestcomm.h> | |
17 | #include <sysdev/bestcomm/gen_bd.h> | |
18 | #include <asm/mpc52xx_psc.h> | |
19 | ||
20 | #include "mpc5200_dma.h" | |
21 | ||
89dd0842 JS |
22 | /* |
23 | * Interrupt handlers | |
24 | */ | |
cebe7767 | 25 | static irqreturn_t psc_dma_status_irq(int irq, void *_psc_dma) |
89dd0842 | 26 | { |
cebe7767 JS |
27 | struct psc_dma *psc_dma = _psc_dma; |
28 | struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs; | |
89dd0842 JS |
29 | u16 isr; |
30 | ||
31 | isr = in_be16(®s->mpc52xx_psc_isr); | |
32 | ||
33 | /* Playback underrun error */ | |
cebe7767 JS |
34 | if (psc_dma->playback.active && (isr & MPC52xx_PSC_IMR_TXEMP)) |
35 | psc_dma->stats.underrun_count++; | |
89dd0842 JS |
36 | |
37 | /* Capture overrun error */ | |
cebe7767 JS |
38 | if (psc_dma->capture.active && (isr & MPC52xx_PSC_IMR_ORERR)) |
39 | psc_dma->stats.overrun_count++; | |
89dd0842 | 40 | |
dbcc3475 | 41 | out_8(®s->command, MPC52xx_PSC_RST_ERR_STAT); |
89dd0842 JS |
42 | |
43 | return IRQ_HANDLED; | |
44 | } | |
45 | ||
46 | /** | |
cebe7767 | 47 | * psc_dma_bcom_enqueue_next_buffer - Enqueue another audio buffer |
89dd0842 JS |
48 | * @s: pointer to stream private data structure |
49 | * | |
50 | * Enqueues another audio period buffer into the bestcomm queue. | |
51 | * | |
52 | * Note: The routine must only be called when there is space available in | |
53 | * the queue. Otherwise the enqueue will fail and the audio ring buffer | |
54 | * will get out of sync | |
55 | */ | |
cebe7767 | 56 | static void psc_dma_bcom_enqueue_next_buffer(struct psc_dma_stream *s) |
89dd0842 JS |
57 | { |
58 | struct bcom_bd *bd; | |
59 | ||
60 | /* Prepare and enqueue the next buffer descriptor */ | |
61 | bd = bcom_prepare_next_buffer(s->bcom_task); | |
62 | bd->status = s->period_bytes; | |
8f159d72 | 63 | bd->data[0] = s->runtime->dma_addr + (s->period_next * s->period_bytes); |
89dd0842 JS |
64 | bcom_submit_next_buffer(s->bcom_task, NULL); |
65 | ||
66 | /* Update for next period */ | |
8f159d72 | 67 | s->period_next = (s->period_next + 1) % s->runtime->periods; |
89dd0842 JS |
68 | } |
69 | ||
70 | /* Bestcomm DMA irq handler */ | |
a68cc8da | 71 | static irqreturn_t psc_dma_bcom_irq(int irq, void *_psc_dma_stream) |
89dd0842 | 72 | { |
dbcc3475 | 73 | struct psc_dma_stream *s = _psc_dma_stream; |
89dd0842 | 74 | |
dbcc3475 JS |
75 | spin_lock(&s->psc_dma->lock); |
76 | /* For each finished period, dequeue the completed period buffer | |
77 | * and enqueue a new one in it's place. */ | |
78 | while (bcom_buffer_done(s->bcom_task)) { | |
79 | bcom_retrieve_buffer(s->bcom_task, NULL, NULL); | |
89dd0842 | 80 | |
8f159d72 | 81 | s->period_current = (s->period_current+1) % s->runtime->periods; |
c4878274 | 82 | s->period_count++; |
dbcc3475 JS |
83 | |
84 | psc_dma_bcom_enqueue_next_buffer(s); | |
89dd0842 | 85 | } |
dbcc3475 | 86 | spin_unlock(&s->psc_dma->lock); |
89dd0842 | 87 | |
dbcc3475 JS |
88 | /* If the stream is active, then also inform the PCM middle layer |
89 | * of the period finished event. */ | |
90 | if (s->active) | |
91 | snd_pcm_period_elapsed(s->stream); | |
92 | ||
93 | return IRQ_HANDLED; | |
89dd0842 JS |
94 | } |
95 | ||
dbcc3475 | 96 | static int psc_dma_hw_free(struct snd_pcm_substream *substream) |
89dd0842 JS |
97 | { |
98 | snd_pcm_set_runtime_buffer(substream, NULL); | |
99 | return 0; | |
100 | } | |
101 | ||
102 | /** | |
cebe7767 | 103 | * psc_dma_trigger: start and stop the DMA transfer. |
89dd0842 JS |
104 | * |
105 | * This function is called by ALSA to start, stop, pause, and resume the DMA | |
106 | * transfer of data. | |
107 | */ | |
dbcc3475 | 108 | static int psc_dma_trigger(struct snd_pcm_substream *substream, int cmd) |
89dd0842 JS |
109 | { |
110 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 111 | struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
89dd0842 | 112 | struct snd_pcm_runtime *runtime = substream->runtime; |
1d8222e8 | 113 | struct psc_dma_stream *s = to_psc_dma_stream(substream, psc_dma); |
cebe7767 | 114 | struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs; |
89dd0842 | 115 | u16 imr; |
89dd0842 | 116 | unsigned long flags; |
dbcc3475 | 117 | int i; |
89dd0842 | 118 | |
89dd0842 JS |
119 | switch (cmd) { |
120 | case SNDRV_PCM_TRIGGER_START: | |
c4878274 GL |
121 | dev_dbg(psc_dma->dev, "START: stream=%i fbits=%u ps=%u #p=%u\n", |
122 | substream->pstr->stream, runtime->frame_bits, | |
123 | (int)runtime->period_size, runtime->periods); | |
89dd0842 JS |
124 | s->period_bytes = frames_to_bytes(runtime, |
125 | runtime->period_size); | |
8f159d72 GL |
126 | s->period_next = 0; |
127 | s->period_current = 0; | |
89dd0842 | 128 | s->active = 1; |
c4878274 | 129 | s->period_count = 0; |
dbcc3475 | 130 | s->runtime = runtime; |
dbcc3475 JS |
131 | |
132 | /* Fill up the bestcomm bd queue and enable DMA. | |
133 | * This will begin filling the PSC's fifo. | |
134 | */ | |
135 | spin_lock_irqsave(&psc_dma->lock, flags); | |
136 | ||
d56b6eb6 | 137 | if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE) |
dbcc3475 | 138 | bcom_gen_bd_rx_reset(s->bcom_task); |
d56b6eb6 | 139 | else |
dbcc3475 | 140 | bcom_gen_bd_tx_reset(s->bcom_task); |
d56b6eb6 GL |
141 | |
142 | for (i = 0; i < runtime->periods; i++) | |
143 | if (!bcom_queue_full(s->bcom_task)) | |
144 | psc_dma_bcom_enqueue_next_buffer(s); | |
89dd0842 | 145 | |
89dd0842 | 146 | bcom_enable(s->bcom_task); |
cebe7767 | 147 | spin_unlock_irqrestore(&psc_dma->lock, flags); |
89dd0842 | 148 | |
dbcc3475 JS |
149 | out_8(®s->command, MPC52xx_PSC_RST_ERR_STAT); |
150 | ||
89dd0842 JS |
151 | break; |
152 | ||
153 | case SNDRV_PCM_TRIGGER_STOP: | |
c4878274 GL |
154 | dev_dbg(psc_dma->dev, "STOP: stream=%i periods_count=%i\n", |
155 | substream->pstr->stream, s->period_count); | |
89dd0842 | 156 | s->active = 0; |
89dd0842 | 157 | |
dbcc3475 | 158 | spin_lock_irqsave(&psc_dma->lock, flags); |
89dd0842 | 159 | bcom_disable(s->bcom_task); |
dbcc3475 JS |
160 | if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE) |
161 | bcom_gen_bd_rx_reset(s->bcom_task); | |
162 | else | |
163 | bcom_gen_bd_tx_reset(s->bcom_task); | |
164 | spin_unlock_irqrestore(&psc_dma->lock, flags); | |
89dd0842 JS |
165 | |
166 | break; | |
167 | ||
168 | default: | |
c4878274 GL |
169 | dev_dbg(psc_dma->dev, "unhandled trigger: stream=%i cmd=%i\n", |
170 | substream->pstr->stream, cmd); | |
89dd0842 JS |
171 | return -EINVAL; |
172 | } | |
173 | ||
174 | /* Update interrupt enable settings */ | |
175 | imr = 0; | |
cebe7767 | 176 | if (psc_dma->playback.active) |
89dd0842 | 177 | imr |= MPC52xx_PSC_IMR_TXEMP; |
cebe7767 | 178 | if (psc_dma->capture.active) |
89dd0842 | 179 | imr |= MPC52xx_PSC_IMR_ORERR; |
dbcc3475 | 180 | out_be16(®s->isr_imr.imr, psc_dma->imr | imr); |
89dd0842 JS |
181 | |
182 | return 0; | |
183 | } | |
184 | ||
89dd0842 JS |
185 | |
186 | /* --------------------------------------------------------------------- | |
187 | * The PSC DMA 'ASoC platform' driver | |
188 | * | |
189 | * Can be referenced by an 'ASoC machine' driver | |
190 | * This driver only deals with the audio bus; it doesn't have any | |
191 | * interaction with the attached codec | |
192 | */ | |
193 | ||
dbcc3475 | 194 | static const struct snd_pcm_hardware psc_dma_hardware = { |
89dd0842 JS |
195 | .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID | |
196 | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
197 | SNDRV_PCM_INFO_BATCH, | |
198 | .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | | |
dbcc3475 | 199 | SNDRV_PCM_FMTBIT_S24_BE | SNDRV_PCM_FMTBIT_S32_BE, |
89dd0842 JS |
200 | .rate_min = 8000, |
201 | .rate_max = 48000, | |
dbcc3475 | 202 | .channels_min = 1, |
89dd0842 JS |
203 | .channels_max = 2, |
204 | .period_bytes_max = 1024 * 1024, | |
205 | .period_bytes_min = 32, | |
206 | .periods_min = 2, | |
207 | .periods_max = 256, | |
208 | .buffer_bytes_max = 2 * 1024 * 1024, | |
dbcc3475 | 209 | .fifo_size = 512, |
89dd0842 JS |
210 | }; |
211 | ||
dbcc3475 | 212 | static int psc_dma_open(struct snd_pcm_substream *substream) |
89dd0842 | 213 | { |
dbcc3475 | 214 | struct snd_pcm_runtime *runtime = substream->runtime; |
89dd0842 | 215 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
f0fba2ad | 216 | struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
cebe7767 | 217 | struct psc_dma_stream *s; |
dbcc3475 | 218 | int rc; |
89dd0842 | 219 | |
dbcc3475 | 220 | dev_dbg(psc_dma->dev, "psc_dma_open(substream=%p)\n", substream); |
89dd0842 JS |
221 | |
222 | if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE) | |
cebe7767 | 223 | s = &psc_dma->capture; |
89dd0842 | 224 | else |
cebe7767 | 225 | s = &psc_dma->playback; |
89dd0842 | 226 | |
dbcc3475 JS |
227 | snd_soc_set_runtime_hwparams(substream, &psc_dma_hardware); |
228 | ||
229 | rc = snd_pcm_hw_constraint_integer(runtime, | |
230 | SNDRV_PCM_HW_PARAM_PERIODS); | |
231 | if (rc < 0) { | |
232 | dev_err(substream->pcm->card->dev, "invalid buffer size\n"); | |
233 | return rc; | |
234 | } | |
89dd0842 JS |
235 | |
236 | s->stream = substream; | |
237 | return 0; | |
238 | } | |
239 | ||
dbcc3475 | 240 | static int psc_dma_close(struct snd_pcm_substream *substream) |
89dd0842 JS |
241 | { |
242 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 243 | struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
cebe7767 | 244 | struct psc_dma_stream *s; |
89dd0842 | 245 | |
dbcc3475 | 246 | dev_dbg(psc_dma->dev, "psc_dma_close(substream=%p)\n", substream); |
89dd0842 JS |
247 | |
248 | if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE) | |
cebe7767 | 249 | s = &psc_dma->capture; |
89dd0842 | 250 | else |
cebe7767 | 251 | s = &psc_dma->playback; |
89dd0842 | 252 | |
dbcc3475 JS |
253 | if (!psc_dma->playback.active && |
254 | !psc_dma->capture.active) { | |
255 | ||
256 | /* Disable all interrupts and reset the PSC */ | |
257 | out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr); | |
258 | out_8(&psc_dma->psc_regs->command, 4 << 4); /* reset error */ | |
259 | } | |
89dd0842 JS |
260 | s->stream = NULL; |
261 | return 0; | |
262 | } | |
263 | ||
264 | static snd_pcm_uframes_t | |
dbcc3475 | 265 | psc_dma_pointer(struct snd_pcm_substream *substream) |
89dd0842 JS |
266 | { |
267 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 268 | struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
cebe7767 | 269 | struct psc_dma_stream *s; |
89dd0842 JS |
270 | dma_addr_t count; |
271 | ||
272 | if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE) | |
cebe7767 | 273 | s = &psc_dma->capture; |
89dd0842 | 274 | else |
cebe7767 | 275 | s = &psc_dma->playback; |
89dd0842 | 276 | |
8f159d72 | 277 | count = s->period_current * s->period_bytes; |
89dd0842 JS |
278 | |
279 | return bytes_to_frames(substream->runtime, count); | |
280 | } | |
281 | ||
dbcc3475 JS |
282 | static int |
283 | psc_dma_hw_params(struct snd_pcm_substream *substream, | |
284 | struct snd_pcm_hw_params *params) | |
285 | { | |
286 | snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); | |
287 | ||
288 | return 0; | |
289 | } | |
290 | ||
291 | static struct snd_pcm_ops psc_dma_ops = { | |
292 | .open = psc_dma_open, | |
293 | .close = psc_dma_close, | |
294 | .hw_free = psc_dma_hw_free, | |
89dd0842 | 295 | .ioctl = snd_pcm_lib_ioctl, |
dbcc3475 JS |
296 | .pointer = psc_dma_pointer, |
297 | .trigger = psc_dma_trigger, | |
298 | .hw_params = psc_dma_hw_params, | |
89dd0842 JS |
299 | }; |
300 | ||
dbcc3475 JS |
301 | static u64 psc_dma_dmamask = 0xffffffff; |
302 | static int psc_dma_new(struct snd_card *card, struct snd_soc_dai *dai, | |
89dd0842 JS |
303 | struct snd_pcm *pcm) |
304 | { | |
305 | struct snd_soc_pcm_runtime *rtd = pcm->private_data; | |
f0fba2ad | 306 | struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
dbcc3475 | 307 | size_t size = psc_dma_hardware.buffer_bytes_max; |
89dd0842 JS |
308 | int rc = 0; |
309 | ||
f0fba2ad | 310 | dev_dbg(rtd->platform->dev, "psc_dma_new(card=%p, dai=%p, pcm=%p)\n", |
89dd0842 JS |
311 | card, dai, pcm); |
312 | ||
313 | if (!card->dev->dma_mask) | |
dbcc3475 | 314 | card->dev->dma_mask = &psc_dma_dmamask; |
89dd0842 JS |
315 | if (!card->dev->coherent_dma_mask) |
316 | card->dev->coherent_dma_mask = 0xffffffff; | |
317 | ||
318 | if (pcm->streams[0].substream) { | |
dbcc3475 JS |
319 | rc = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->card->dev, |
320 | size, &pcm->streams[0].substream->dma_buffer); | |
89dd0842 JS |
321 | if (rc) |
322 | goto playback_alloc_err; | |
323 | } | |
324 | ||
325 | if (pcm->streams[1].substream) { | |
dbcc3475 JS |
326 | rc = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->card->dev, |
327 | size, &pcm->streams[1].substream->dma_buffer); | |
89dd0842 JS |
328 | if (rc) |
329 | goto capture_alloc_err; | |
330 | } | |
331 | ||
f0fba2ad LG |
332 | if (rtd->codec->ac97) |
333 | rtd->codec->ac97->private_data = psc_dma; | |
dbcc3475 | 334 | |
89dd0842 JS |
335 | return 0; |
336 | ||
337 | capture_alloc_err: | |
338 | if (pcm->streams[0].substream) | |
339 | snd_dma_free_pages(&pcm->streams[0].substream->dma_buffer); | |
dbcc3475 | 340 | |
89dd0842 JS |
341 | playback_alloc_err: |
342 | dev_err(card->dev, "Cannot allocate buffer(s)\n"); | |
dbcc3475 | 343 | |
89dd0842 JS |
344 | return -ENOMEM; |
345 | } | |
346 | ||
dbcc3475 | 347 | static void psc_dma_free(struct snd_pcm *pcm) |
89dd0842 JS |
348 | { |
349 | struct snd_soc_pcm_runtime *rtd = pcm->private_data; | |
350 | struct snd_pcm_substream *substream; | |
351 | int stream; | |
352 | ||
f0fba2ad | 353 | dev_dbg(rtd->platform->dev, "psc_dma_free(pcm=%p)\n", pcm); |
89dd0842 JS |
354 | |
355 | for (stream = 0; stream < 2; stream++) { | |
356 | substream = pcm->streams[stream].substream; | |
357 | if (substream) { | |
358 | snd_dma_free_pages(&substream->dma_buffer); | |
359 | substream->dma_buffer.area = NULL; | |
360 | substream->dma_buffer.addr = 0; | |
361 | } | |
362 | } | |
363 | } | |
364 | ||
f0fba2ad LG |
365 | static struct snd_soc_platform_driver mpc5200_audio_dma_platform = { |
366 | .ops = &psc_dma_ops, | |
dbcc3475 JS |
367 | .pcm_new = &psc_dma_new, |
368 | .pcm_free = &psc_dma_free, | |
89dd0842 | 369 | }; |
dbcc3475 | 370 | |
f07eb223 | 371 | static int mpc5200_hpcd_probe(struct of_device *op) |
dbcc3475 JS |
372 | { |
373 | phys_addr_t fifo; | |
374 | struct psc_dma *psc_dma; | |
375 | struct resource res; | |
376 | int size, irq, rc; | |
377 | const __be32 *prop; | |
378 | void __iomem *regs; | |
33d7f778 | 379 | int ret; |
dbcc3475 JS |
380 | |
381 | /* Fetch the registers and IRQ of the PSC */ | |
61c7a080 GL |
382 | irq = irq_of_parse_and_map(op->dev.of_node, 0); |
383 | if (of_address_to_resource(op->dev.of_node, 0, &res)) { | |
dbcc3475 JS |
384 | dev_err(&op->dev, "Missing reg property\n"); |
385 | return -ENODEV; | |
386 | } | |
28f65c11 | 387 | regs = ioremap(res.start, resource_size(&res)); |
dbcc3475 JS |
388 | if (!regs) { |
389 | dev_err(&op->dev, "Could not map registers\n"); | |
390 | return -ENODEV; | |
391 | } | |
392 | ||
393 | /* Allocate and initialize the driver private data */ | |
394 | psc_dma = kzalloc(sizeof *psc_dma, GFP_KERNEL); | |
395 | if (!psc_dma) { | |
33d7f778 JL |
396 | ret = -ENOMEM; |
397 | goto out_unmap; | |
dbcc3475 JS |
398 | } |
399 | ||
400 | /* Get the PSC ID */ | |
61c7a080 | 401 | prop = of_get_property(op->dev.of_node, "cell-index", &size); |
33d7f778 JL |
402 | if (!prop || size < sizeof *prop) { |
403 | ret = -ENODEV; | |
404 | goto out_free; | |
405 | } | |
dbcc3475 JS |
406 | |
407 | spin_lock_init(&psc_dma->lock); | |
0827d6ba | 408 | mutex_init(&psc_dma->mutex); |
dbcc3475 JS |
409 | psc_dma->id = be32_to_cpu(*prop); |
410 | psc_dma->irq = irq; | |
411 | psc_dma->psc_regs = regs; | |
412 | psc_dma->fifo_regs = regs + sizeof *psc_dma->psc_regs; | |
413 | psc_dma->dev = &op->dev; | |
414 | psc_dma->playback.psc_dma = psc_dma; | |
415 | psc_dma->capture.psc_dma = psc_dma; | |
416 | snprintf(psc_dma->name, sizeof psc_dma->name, "PSC%u", psc_dma->id); | |
417 | ||
418 | /* Find the address of the fifo data registers and setup the | |
419 | * DMA tasks */ | |
420 | fifo = res.start + offsetof(struct mpc52xx_psc, buffer.buffer_32); | |
421 | psc_dma->capture.bcom_task = | |
422 | bcom_psc_gen_bd_rx_init(psc_dma->id, 10, fifo, 512); | |
423 | psc_dma->playback.bcom_task = | |
424 | bcom_psc_gen_bd_tx_init(psc_dma->id, 10, fifo); | |
425 | if (!psc_dma->capture.bcom_task || | |
426 | !psc_dma->playback.bcom_task) { | |
427 | dev_err(&op->dev, "Could not allocate bestcomm tasks\n"); | |
33d7f778 JL |
428 | ret = -ENODEV; |
429 | goto out_free; | |
dbcc3475 JS |
430 | } |
431 | ||
432 | /* Disable all interrupts and reset the PSC */ | |
433 | out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr); | |
434 | /* reset receiver */ | |
435 | out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_RX); | |
436 | /* reset transmitter */ | |
437 | out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_TX); | |
438 | /* reset error */ | |
439 | out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_ERR_STAT); | |
440 | /* reset mode */ | |
441 | out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_SEL_MODE_REG_1); | |
442 | ||
443 | /* Set up mode register; | |
444 | * First write: RxRdy (FIFO Alarm) generates rx FIFO irq | |
445 | * Second write: register Normal mode for non loopback | |
446 | */ | |
447 | out_8(&psc_dma->psc_regs->mode, 0); | |
448 | out_8(&psc_dma->psc_regs->mode, 0); | |
449 | ||
450 | /* Set the TX and RX fifo alarm thresholds */ | |
451 | out_be16(&psc_dma->fifo_regs->rfalarm, 0x100); | |
452 | out_8(&psc_dma->fifo_regs->rfcntl, 0x4); | |
453 | out_be16(&psc_dma->fifo_regs->tfalarm, 0x100); | |
454 | out_8(&psc_dma->fifo_regs->tfcntl, 0x7); | |
455 | ||
456 | /* Lookup the IRQ numbers */ | |
457 | psc_dma->playback.irq = | |
458 | bcom_get_task_irq(psc_dma->playback.bcom_task); | |
459 | psc_dma->capture.irq = | |
460 | bcom_get_task_irq(psc_dma->capture.bcom_task); | |
461 | ||
462 | rc = request_irq(psc_dma->irq, &psc_dma_status_irq, IRQF_SHARED, | |
463 | "psc-dma-status", psc_dma); | |
a68cc8da | 464 | rc |= request_irq(psc_dma->capture.irq, &psc_dma_bcom_irq, IRQF_SHARED, |
dbcc3475 | 465 | "psc-dma-capture", &psc_dma->capture); |
a68cc8da | 466 | rc |= request_irq(psc_dma->playback.irq, &psc_dma_bcom_irq, IRQF_SHARED, |
dbcc3475 JS |
467 | "psc-dma-playback", &psc_dma->playback); |
468 | if (rc) { | |
33d7f778 JL |
469 | ret = -ENODEV; |
470 | goto out_irq; | |
dbcc3475 | 471 | } |
89dd0842 | 472 | |
dbcc3475 JS |
473 | /* Save what we've done so it can be found again later */ |
474 | dev_set_drvdata(&op->dev, psc_dma); | |
475 | ||
476 | /* Tell the ASoC OF helpers about it */ | |
f0fba2ad | 477 | return snd_soc_register_platform(&op->dev, &mpc5200_audio_dma_platform); |
33d7f778 JL |
478 | out_irq: |
479 | free_irq(psc_dma->irq, psc_dma); | |
480 | free_irq(psc_dma->capture.irq, &psc_dma->capture); | |
481 | free_irq(psc_dma->playback.irq, &psc_dma->playback); | |
482 | out_free: | |
483 | kfree(psc_dma); | |
484 | out_unmap: | |
485 | iounmap(regs); | |
486 | return ret; | |
dbcc3475 | 487 | } |
dbcc3475 | 488 | |
f0fba2ad | 489 | static int mpc5200_hpcd_remove(struct of_device *op) |
dbcc3475 JS |
490 | { |
491 | struct psc_dma *psc_dma = dev_get_drvdata(&op->dev); | |
492 | ||
493 | dev_dbg(&op->dev, "mpc5200_audio_dma_destroy()\n"); | |
494 | ||
f0fba2ad | 495 | snd_soc_unregister_platform(&op->dev); |
dbcc3475 JS |
496 | |
497 | bcom_gen_bd_rx_release(psc_dma->capture.bcom_task); | |
498 | bcom_gen_bd_tx_release(psc_dma->playback.bcom_task); | |
499 | ||
500 | /* Release irqs */ | |
501 | free_irq(psc_dma->irq, psc_dma); | |
502 | free_irq(psc_dma->capture.irq, &psc_dma->capture); | |
503 | free_irq(psc_dma->playback.irq, &psc_dma->playback); | |
504 | ||
505 | iounmap(psc_dma->psc_regs); | |
506 | kfree(psc_dma); | |
507 | dev_set_drvdata(&op->dev, NULL); | |
508 | ||
509 | return 0; | |
510 | } | |
f0fba2ad LG |
511 | |
512 | static struct of_device_id mpc5200_hpcd_match[] = { | |
f07eb223 | 513 | { .compatible = "fsl,mpc5200-pcm", }, |
f0fba2ad LG |
514 | {} |
515 | }; | |
516 | MODULE_DEVICE_TABLE(of, mpc5200_hpcd_match); | |
517 | ||
f07eb223 | 518 | static struct platform_driver mpc5200_hpcd_of_driver = { |
f0fba2ad LG |
519 | .probe = mpc5200_hpcd_probe, |
520 | .remove = mpc5200_hpcd_remove, | |
f07eb223 GL |
521 | .dev = { |
522 | .owner = THIS_MODULE, | |
523 | .name = "mpc5200-pcm-audio", | |
524 | .of_match_table = mpc5200_hpcd_match, | |
525 | } | |
f0fba2ad LG |
526 | }; |
527 | ||
528 | static int __init mpc5200_hpcd_init(void) | |
529 | { | |
f07eb223 | 530 | return platform_driver_register(&mpc5200_hpcd_of_driver); |
f0fba2ad | 531 | } |
f07eb223 | 532 | module_init(mpc5200_hpcd_init); |
f0fba2ad LG |
533 | |
534 | static void __exit mpc5200_hpcd_exit(void) | |
535 | { | |
f07eb223 | 536 | platform_driver_unregister(&mpc5200_hpcd_of_driver); |
f0fba2ad | 537 | } |
f0fba2ad | 538 | module_exit(mpc5200_hpcd_exit); |
dbcc3475 JS |
539 | |
540 | MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>"); | |
541 | MODULE_DESCRIPTION("Freescale MPC5200 PSC in DMA mode ASoC Driver"); | |
542 | MODULE_LICENSE("GPL"); |