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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / wm_hubs.c
CommitLineData
a2342ae3
MB		 1/*
2 * wm_hubs.c -- WM8993/4 common code
3 *
656baaeb 4 * Copyright 2009-12 Wolfson Microelectronics plc
a2342ae3
MB		 5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
79ef0abc 20#include <linux/mfd/wm8994/registers.h>
a2342ae3
MB		 21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/soc.h>
a2342ae3
MB		 25#include <sound/initval.h>
26#include <sound/tlv.h>
27
28#include "wm8993.h"
29#include "wm_hubs.h"
30
31const DECLARE_TLV_DB_SCALE(wm_hubs_spkmix_tlv, -300, 300, 0);
32EXPORT_SYMBOL_GPL(wm_hubs_spkmix_tlv);
33
34static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1650, 150, 0);
35static const DECLARE_TLV_DB_SCALE(inmix_sw_tlv, 0, 3000, 0);
36static const DECLARE_TLV_DB_SCALE(inmix_tlv, -1500, 300, 1);
37static const DECLARE_TLV_DB_SCALE(earpiece_tlv, -600, 600, 0);
38static const DECLARE_TLV_DB_SCALE(outmix_tlv, -2100, 300, 0);
39static const DECLARE_TLV_DB_SCALE(spkmixout_tlv, -1800, 600, 1);
40static const DECLARE_TLV_DB_SCALE(outpga_tlv, -5700, 100, 0);
41static const unsigned int spkboost_tlv[] = {
028aa634 42 TLV_DB_RANGE_HEAD(2),
a2342ae3
MB		 43 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
44 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0),
45};
46static const DECLARE_TLV_DB_SCALE(line_tlv, -600, 600, 0);
47
48static const char *speaker_ref_text[] = {
49 "SPKVDD/2",
50 "VMID",
51};
52
53static const struct soc_enum speaker_ref =
54 SOC_ENUM_SINGLE(WM8993_SPEAKER_MIXER, 8, 2, speaker_ref_text);
55
56static const char *speaker_mode_text[] = {
57 "Class D",
58 "Class AB",
59};
60
61static const struct soc_enum speaker_mode =
62 SOC_ENUM_SINGLE(WM8993_SPKMIXR_ATTENUATION, 8, 2, speaker_mode_text);
63
4dcc93d0 64static void wait_for_dc_servo(struct snd_soc_codec *codec, unsigned int op)
a2342ae3 65{
d96ca3cd 66 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
a2342ae3
MB		 67 unsigned int reg;
68 int count = 0;
1479c3fb 69 int timeout;
4dcc93d0
MB		 70 unsigned int val;
71
72 val = op | WM8993_DCS_ENA_CHAN_0 | WM8993_DCS_ENA_CHAN_1;
73
74 /* Trigger the command */
75 snd_soc_write(codec, WM8993_DC_SERVO_0, val);
a2342ae3
MB		 76
77 dev_dbg(codec->dev, "Waiting for DC servo...\n");
3ed7074c 78
1479c3fb
MB		 79 if (hubs->dcs_done_irq)
80 timeout = 4;
81 else
82 timeout = 400;
d96ca3cd 83
1479c3fb
MB		 84 do {
85 count++;
86
87 if (hubs->dcs_done_irq)
88 wait_for_completion_timeout(&hubs->dcs_done,
89 msecs_to_jiffies(250));
90 else
d96ca3cd 91 msleep(1);
1479c3fb
MB		 92
93 reg = snd_soc_read(codec, WM8993_DC_SERVO_0);
94 dev_dbg(codec->dev, "DC servo: %x\n", reg);
95 } while (reg & op && count < timeout);
a2342ae3 96
4dcc93d0 97 if (reg & op)
5a9f91ca
MB		 98 dev_err(codec->dev, "Timed out waiting for DC Servo %x\n",
99 op);
a2342ae3
MB		 100}
101
d96ca3cd
MB		 102irqreturn_t wm_hubs_dcs_done(int irq, void *data)
103{
104 struct wm_hubs_data *hubs = data;
105
106 complete(&hubs->dcs_done);
107
108 return IRQ_HANDLED;
109}
110EXPORT_SYMBOL_GPL(wm_hubs_dcs_done);
111
af31a227
MB		 112static bool wm_hubs_dac_hp_direct(struct snd_soc_codec *codec)
113{
114 int reg;
115
116 /* If we're going via the mixer we'll need to do additional checks */
117 reg = snd_soc_read(codec, WM8993_OUTPUT_MIXER1);
118 if (!(reg & WM8993_DACL_TO_HPOUT1L)) {
119 if (reg & ~WM8993_DACL_TO_MIXOUTL) {
120 dev_vdbg(codec->dev, "Analogue paths connected: %x\n",
121 reg & ~WM8993_DACL_TO_HPOUT1L);
122 return false;
123 } else {
124 dev_vdbg(codec->dev, "HPL connected to mixer\n");
af31a227
MB		 125 }
126 } else {
127 dev_vdbg(codec->dev, "HPL connected to DAC\n");
128 }
129
130 reg = snd_soc_read(codec, WM8993_OUTPUT_MIXER2);
131 if (!(reg & WM8993_DACR_TO_HPOUT1R)) {
132 if (reg & ~WM8993_DACR_TO_MIXOUTR) {
133 dev_vdbg(codec->dev, "Analogue paths connected: %x\n",
134 reg & ~WM8993_DACR_TO_HPOUT1R);
135 return false;
136 } else {
137 dev_vdbg(codec->dev, "HPR connected to mixer\n");
af31a227
MB		 138 }
139 } else {
140 dev_vdbg(codec->dev, "HPR connected to DAC\n");
141 }
142
143 return true;
144}
145
94aa733a
MB		 146struct wm_hubs_dcs_cache {
147 struct list_head list;
148 unsigned int left;
149 unsigned int right;
150 u16 dcs_cfg;
151};
152
153static bool wm_hubs_dcs_cache_get(struct snd_soc_codec *codec,
154 struct wm_hubs_dcs_cache **entry)
155{
156 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
157 struct wm_hubs_dcs_cache *cache;
158 unsigned int left, right;
159
160 left = snd_soc_read(codec, WM8993_LEFT_OUTPUT_VOLUME);
161 left &= WM8993_HPOUT1L_VOL_MASK;
162
163 right = snd_soc_read(codec, WM8993_RIGHT_OUTPUT_VOLUME);
164 right &= WM8993_HPOUT1R_VOL_MASK;
165
166 list_for_each_entry(cache, &hubs->dcs_cache, list) {
167 if (cache->left != left || cache->right != right)
168 continue;
169
170 *entry = cache;
171 return true;
172 }
173
174 return false;
175}
176
177static void wm_hubs_dcs_cache_set(struct snd_soc_codec *codec, u16 dcs_cfg)
178{
179 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
180 struct wm_hubs_dcs_cache *cache;
181
182 if (hubs->no_cache_dac_hp_direct)
183 return;
184
185 cache = devm_kzalloc(codec->dev, sizeof(*cache), GFP_KERNEL);
186 if (!cache) {
187 dev_err(codec->dev, "Failed to allocate DCS cache entry\n");
188 return;
189 }
190
191 cache->left = snd_soc_read(codec, WM8993_LEFT_OUTPUT_VOLUME);
192 cache->left &= WM8993_HPOUT1L_VOL_MASK;
193
194 cache->right = snd_soc_read(codec, WM8993_RIGHT_OUTPUT_VOLUME);
195 cache->right &= WM8993_HPOUT1R_VOL_MASK;
196
197 cache->dcs_cfg = dcs_cfg;
198
199 list_add_tail(&cache->list, &hubs->dcs_cache);
200}
201
1f5353e7 202static int wm_hubs_read_dc_servo(struct snd_soc_codec *codec,
fae4efa2
MB		 203 u16 *reg_l, u16 *reg_r)
204{
205 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
206 u16 dcs_reg, reg;
1f5353e7 207 int ret = 0;
fae4efa2
MB		 208
209 switch (hubs->dcs_readback_mode) {
210 case 2:
211 dcs_reg = WM8994_DC_SERVO_4E;
212 break;
213 case 1:
214 dcs_reg = WM8994_DC_SERVO_READBACK;
215 break;
216 default:
217 dcs_reg = WM8993_DC_SERVO_3;
218 break;
219 }
220
221 /* Different chips in the family support different readback
222 * methods.
223 */
224 switch (hubs->dcs_readback_mode) {
225 case 0:
226 *reg_l = snd_soc_read(codec, WM8993_DC_SERVO_READBACK_1)
227 & WM8993_DCS_INTEG_CHAN_0_MASK;
228 *reg_r = snd_soc_read(codec, WM8993_DC_SERVO_READBACK_2)
229 & WM8993_DCS_INTEG_CHAN_1_MASK;
230 break;
231 case 2:
232 case 1:
233 reg = snd_soc_read(codec, dcs_reg);
234 *reg_r = (reg & WM8993_DCS_DAC_WR_VAL_1_MASK)
235 >> WM8993_DCS_DAC_WR_VAL_1_SHIFT;
236 *reg_l = reg & WM8993_DCS_DAC_WR_VAL_0_MASK;
237 break;
238 default:
239 WARN(1, "Unknown DCS readback method\n");
1f5353e7 240 ret = -1;
fae4efa2 241 }
1f5353e7 242 return ret;
fae4efa2
MB		 243}
244
3ed7074c
MB		 245/*
246 * Startup calibration of the DC servo
247 */
a7892c35 248static void enable_dc_servo(struct snd_soc_codec *codec)
3ed7074c 249{
b2c812e2 250 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
94aa733a 251 struct wm_hubs_dcs_cache *cache;
20a4e7fc 252 s8 offset;
fae4efa2 253 u16 reg_l, reg_r, dcs_cfg, dcs_reg;
79ef0abc
MB		 254
255 switch (hubs->dcs_readback_mode) {
256 case 2:
257 dcs_reg = WM8994_DC_SERVO_4E;
258 break;
259 default:
260 dcs_reg = WM8993_DC_SERVO_3;
261 break;
262 }
3ed7074c 263
fec6dd83
MB		 264 /* If we're using a digital only path and have a previously
265 * callibrated DC servo offset stored then use that. */
94aa733a
MB		 266 if (wm_hubs_dac_hp_direct(codec) &&
267 wm_hubs_dcs_cache_get(codec, &cache)) {
268 dev_dbg(codec->dev, "Using cached DCS offset %x for %d,%d\n",
269 cache->dcs_cfg, cache->left, cache->right);
270 snd_soc_write(codec, dcs_reg, cache->dcs_cfg);
fec6dd83
MB		 271 wait_for_dc_servo(codec,
272 WM8993_DCS_TRIG_DAC_WR_0 |
273 WM8993_DCS_TRIG_DAC_WR_1);
274 return;
275 }
276
f9acf9fe 277 if (hubs->series_startup) {
11cef5f0
MB		 278 /* Set for 32 series updates */
279 snd_soc_update_bits(codec, WM8993_DC_SERVO_1,
280 WM8993_DCS_SERIES_NO_01_MASK,
281 32 << WM8993_DCS_SERIES_NO_01_SHIFT);
282 wait_for_dc_servo(codec,
283 WM8993_DCS_TRIG_SERIES_0 |
284 WM8993_DCS_TRIG_SERIES_1);
285 } else {
286 wait_for_dc_servo(codec,
287 WM8993_DCS_TRIG_STARTUP_0 |
288 WM8993_DCS_TRIG_STARTUP_1);
289 }
3ed7074c 290
1f5353e7
TG		 291 if (wm_hubs_read_dc_servo(codec, &reg_l, &reg_r) < 0)
292 return;
fec6dd83
MB		 293
294 dev_dbg(codec->dev, "DCS input: %x %x\n", reg_l, reg_r);
295
3ed7074c 296 /* Apply correction to DC servo result */
4537c4e7
MB		 297 if (hubs->dcs_codes_l || hubs->dcs_codes_r) {
298 dev_dbg(codec->dev,
299 "Applying %d/%d code DC servo correction\n",
300 hubs->dcs_codes_l, hubs->dcs_codes_r);
3ed7074c 301
d5b040c9 302 /* HPOUT1R */
363947d7 303 offset = (s8)reg_r;
20bac1f3
MB		 304 dev_dbg(codec->dev, "DCS right %d->%d\n", offset,
305 offset + hubs->dcs_codes_r);
4537c4e7 306 offset += hubs->dcs_codes_r;
20a4e7fc 307 dcs_cfg = (u8)offset << WM8993_DCS_DAC_WR_VAL_1_SHIFT;
3ed7074c 308
d5b040c9 309 /* HPOUT1L */
363947d7 310 offset = (s8)reg_l;
20bac1f3
MB		 311 dev_dbg(codec->dev, "DCS left %d->%d\n", offset,
312 offset + hubs->dcs_codes_l);
4537c4e7 313 offset += hubs->dcs_codes_l;
20a4e7fc 314 dcs_cfg |= (u8)offset;
3ed7074c 315
3254d285
MB		 316 dev_dbg(codec->dev, "DCS result: %x\n", dcs_cfg);
317
3ed7074c 318 /* Do it */
79ef0abc 319 snd_soc_write(codec, dcs_reg, dcs_cfg);
4dcc93d0
MB		 320 wait_for_dc_servo(codec,
321 WM8993_DCS_TRIG_DAC_WR_0 |
322 WM8993_DCS_TRIG_DAC_WR_1);
fec6dd83 323 } else {
d5b040c9
MB		 324 dcs_cfg = reg_r << WM8993_DCS_DAC_WR_VAL_1_SHIFT;
325 dcs_cfg |= reg_l;
3ed7074c 326 }
fec6dd83
MB		 327
328 /* Save the callibrated offset if we're in class W mode and
329 * therefore don't have any analogue signal mixed in. */
94aa733a
MB		 330 if (wm_hubs_dac_hp_direct(codec))
331 wm_hubs_dcs_cache_set(codec, dcs_cfg);
3ed7074c
MB		 332}
333
a2342ae3
MB		 334/*
335 * Update the DC servo calibration on gain changes
336 */
337static int wm8993_put_dc_servo(struct snd_kcontrol *kcontrol,
3ed7074c 338 struct snd_ctl_elem_value *ucontrol)
a2342ae3
MB		 339{
340 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 341 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
a2342ae3
MB		 342 int ret;
343
c4671a95 344 ret = snd_soc_put_volsw(kcontrol, ucontrol);
a2342ae3 345
ae9d8607
MB		 346 /* If we're applying an offset correction then updating the
347 * callibration would be likely to introduce further offsets. */
4537c4e7 348 if (hubs->dcs_codes_l || hubs->dcs_codes_r || hubs->no_series_update)
ae9d8607
MB		 349 return ret;
350
a2342ae3
MB		 351 /* Only need to do this if the outputs are active */
352 if (snd_soc_read(codec, WM8993_POWER_MANAGEMENT_1)
353 & (WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA))
354 snd_soc_update_bits(codec,
355 WM8993_DC_SERVO_0,
356 WM8993_DCS_TRIG_SINGLE_0 |
357 WM8993_DCS_TRIG_SINGLE_1,
358 WM8993_DCS_TRIG_SINGLE_0 |
359 WM8993_DCS_TRIG_SINGLE_1);
360
361 return ret;
362}
363
364static const struct snd_kcontrol_new analogue_snd_controls[] = {
365SOC_SINGLE_TLV("IN1L Volume", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 0, 31, 0,
366 inpga_tlv),
367SOC_SINGLE("IN1L Switch", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 7, 1, 1),
ea02c63d 368SOC_SINGLE("IN1L ZC Switch", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 6, 1, 0),
a2342ae3
MB		 369
370SOC_SINGLE_TLV("IN1R Volume", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 0, 31, 0,
371 inpga_tlv),
372SOC_SINGLE("IN1R Switch", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 7, 1, 1),
ea02c63d 373SOC_SINGLE("IN1R ZC Switch", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 6, 1, 0),
a2342ae3
MB		 374
375
376SOC_SINGLE_TLV("IN2L Volume", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 0, 31, 0,
377 inpga_tlv),
378SOC_SINGLE("IN2L Switch", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 7, 1, 1),
ea02c63d 379SOC_SINGLE("IN2L ZC Switch", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 6, 1, 0),
a2342ae3
MB		 380
381SOC_SINGLE_TLV("IN2R Volume", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 0, 31, 0,
382 inpga_tlv),
383SOC_SINGLE("IN2R Switch", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 7, 1, 1),
ea02c63d 384SOC_SINGLE("IN2R ZC Switch", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 6, 1, 0),
a2342ae3
MB		 385
386SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8993_INPUT_MIXER3, 7, 1, 0,
387 inmix_sw_tlv),
388SOC_SINGLE_TLV("MIXINL IN1L Volume", WM8993_INPUT_MIXER3, 4, 1, 0,
389 inmix_sw_tlv),
390SOC_SINGLE_TLV("MIXINL Output Record Volume", WM8993_INPUT_MIXER3, 0, 7, 0,
391 inmix_tlv),
392SOC_SINGLE_TLV("MIXINL IN1LP Volume", WM8993_INPUT_MIXER5, 6, 7, 0, inmix_tlv),
393SOC_SINGLE_TLV("MIXINL Direct Voice Volume", WM8993_INPUT_MIXER5, 0, 6, 0,
394 inmix_tlv),
395
396SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8993_INPUT_MIXER4, 7, 1, 0,
397 inmix_sw_tlv),
398SOC_SINGLE_TLV("MIXINR IN1R Volume", WM8993_INPUT_MIXER4, 4, 1, 0,
399 inmix_sw_tlv),
400SOC_SINGLE_TLV("MIXINR Output Record Volume", WM8993_INPUT_MIXER4, 0, 7, 0,
401 inmix_tlv),
402SOC_SINGLE_TLV("MIXINR IN1RP Volume", WM8993_INPUT_MIXER6, 6, 7, 0, inmix_tlv),
403SOC_SINGLE_TLV("MIXINR Direct Voice Volume", WM8993_INPUT_MIXER6, 0, 6, 0,
404 inmix_tlv),
405
406SOC_SINGLE_TLV("Left Output Mixer IN2RN Volume", WM8993_OUTPUT_MIXER5, 6, 7, 1,
407 outmix_tlv),
408SOC_SINGLE_TLV("Left Output Mixer IN2LN Volume", WM8993_OUTPUT_MIXER3, 6, 7, 1,
409 outmix_tlv),
410SOC_SINGLE_TLV("Left Output Mixer IN2LP Volume", WM8993_OUTPUT_MIXER3, 9, 7, 1,
411 outmix_tlv),
412SOC_SINGLE_TLV("Left Output Mixer IN1L Volume", WM8993_OUTPUT_MIXER3, 0, 7, 1,
413 outmix_tlv),
414SOC_SINGLE_TLV("Left Output Mixer IN1R Volume", WM8993_OUTPUT_MIXER3, 3, 7, 1,
415 outmix_tlv),
416SOC_SINGLE_TLV("Left Output Mixer Right Input Volume",
417 WM8993_OUTPUT_MIXER5, 3, 7, 1, outmix_tlv),
418SOC_SINGLE_TLV("Left Output Mixer Left Input Volume",
419 WM8993_OUTPUT_MIXER5, 0, 7, 1, outmix_tlv),
420SOC_SINGLE_TLV("Left Output Mixer DAC Volume", WM8993_OUTPUT_MIXER5, 9, 7, 1,
421 outmix_tlv),
422
423SOC_SINGLE_TLV("Right Output Mixer IN2LN Volume",
424 WM8993_OUTPUT_MIXER6, 6, 7, 1, outmix_tlv),
425SOC_SINGLE_TLV("Right Output Mixer IN2RN Volume",
426 WM8993_OUTPUT_MIXER4, 6, 7, 1, outmix_tlv),
427SOC_SINGLE_TLV("Right Output Mixer IN1L Volume",
428 WM8993_OUTPUT_MIXER4, 3, 7, 1, outmix_tlv),
429SOC_SINGLE_TLV("Right Output Mixer IN1R Volume",
430 WM8993_OUTPUT_MIXER4, 0, 7, 1, outmix_tlv),
431SOC_SINGLE_TLV("Right Output Mixer IN2RP Volume",
432 WM8993_OUTPUT_MIXER4, 9, 7, 1, outmix_tlv),
433SOC_SINGLE_TLV("Right Output Mixer Left Input Volume",
434 WM8993_OUTPUT_MIXER6, 3, 7, 1, outmix_tlv),
435SOC_SINGLE_TLV("Right Output Mixer Right Input Volume",
436 WM8993_OUTPUT_MIXER6, 6, 7, 1, outmix_tlv),
437SOC_SINGLE_TLV("Right Output Mixer DAC Volume",
438 WM8993_OUTPUT_MIXER6, 9, 7, 1, outmix_tlv),
439
440SOC_DOUBLE_R_TLV("Output Volume", WM8993_LEFT_OPGA_VOLUME,
441 WM8993_RIGHT_OPGA_VOLUME, 0, 63, 0, outpga_tlv),
442SOC_DOUBLE_R("Output Switch", WM8993_LEFT_OPGA_VOLUME,
443 WM8993_RIGHT_OPGA_VOLUME, 6, 1, 0),
444SOC_DOUBLE_R("Output ZC Switch", WM8993_LEFT_OPGA_VOLUME,
445 WM8993_RIGHT_OPGA_VOLUME, 7, 1, 0),
446
447SOC_SINGLE("Earpiece Switch", WM8993_HPOUT2_VOLUME, 5, 1, 1),
448SOC_SINGLE_TLV("Earpiece Volume", WM8993_HPOUT2_VOLUME, 4, 1, 1, earpiece_tlv),
449
450SOC_SINGLE_TLV("SPKL Input Volume", WM8993_SPKMIXL_ATTENUATION,
451 5, 1, 1, wm_hubs_spkmix_tlv),
452SOC_SINGLE_TLV("SPKL IN1LP Volume", WM8993_SPKMIXL_ATTENUATION,
453 4, 1, 1, wm_hubs_spkmix_tlv),
454SOC_SINGLE_TLV("SPKL Output Volume", WM8993_SPKMIXL_ATTENUATION,
455 3, 1, 1, wm_hubs_spkmix_tlv),
456
457SOC_SINGLE_TLV("SPKR Input Volume", WM8993_SPKMIXR_ATTENUATION,
458 5, 1, 1, wm_hubs_spkmix_tlv),
459SOC_SINGLE_TLV("SPKR IN1RP Volume", WM8993_SPKMIXR_ATTENUATION,
460 4, 1, 1, wm_hubs_spkmix_tlv),
461SOC_SINGLE_TLV("SPKR Output Volume", WM8993_SPKMIXR_ATTENUATION,
462 3, 1, 1, wm_hubs_spkmix_tlv),
463
464SOC_DOUBLE_R_TLV("Speaker Mixer Volume",
465 WM8993_SPKMIXL_ATTENUATION, WM8993_SPKMIXR_ATTENUATION,
466 0, 3, 1, spkmixout_tlv),
467SOC_DOUBLE_R_TLV("Speaker Volume",
468 WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
469 0, 63, 0, outpga_tlv),
470SOC_DOUBLE_R("Speaker Switch",
471 WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
472 6, 1, 0),
473SOC_DOUBLE_R("Speaker ZC Switch",
474 WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
475 7, 1, 0),
ed8cc471 476SOC_DOUBLE_TLV("Speaker Boost Volume", WM8993_SPKOUT_BOOST, 3, 0, 7, 0,
a2342ae3
MB		 477 spkboost_tlv),
478SOC_ENUM("Speaker Reference", speaker_ref),
479SOC_ENUM("Speaker Mode", speaker_mode),
480
0f9887d1
PU		 481SOC_DOUBLE_R_EXT_TLV("Headphone Volume",
482 WM8993_LEFT_OUTPUT_VOLUME, WM8993_RIGHT_OUTPUT_VOLUME,
c4671a95 483 0, 63, 0, snd_soc_get_volsw, wm8993_put_dc_servo,
0f9887d1
PU		 484 outpga_tlv),
485
a2342ae3
MB		 486SOC_DOUBLE_R("Headphone Switch", WM8993_LEFT_OUTPUT_VOLUME,
487 WM8993_RIGHT_OUTPUT_VOLUME, 6, 1, 0),
488SOC_DOUBLE_R("Headphone ZC Switch", WM8993_LEFT_OUTPUT_VOLUME,
489 WM8993_RIGHT_OUTPUT_VOLUME, 7, 1, 0),
490
491SOC_SINGLE("LINEOUT1N Switch", WM8993_LINE_OUTPUTS_VOLUME, 6, 1, 1),
492SOC_SINGLE("LINEOUT1P Switch", WM8993_LINE_OUTPUTS_VOLUME, 5, 1, 1),
493SOC_SINGLE_TLV("LINEOUT1 Volume", WM8993_LINE_OUTPUTS_VOLUME, 4, 1, 1,
494 line_tlv),
495
496SOC_SINGLE("LINEOUT2N Switch", WM8993_LINE_OUTPUTS_VOLUME, 2, 1, 1),
497SOC_SINGLE("LINEOUT2P Switch", WM8993_LINE_OUTPUTS_VOLUME, 1, 1, 1),
498SOC_SINGLE_TLV("LINEOUT2 Volume", WM8993_LINE_OUTPUTS_VOLUME, 0, 1, 1,
499 line_tlv),
500};
501
3ed7074c
MB		 502static int hp_supply_event(struct snd_soc_dapm_widget *w,
503 struct snd_kcontrol *kcontrol, int event)
504{
505 struct snd_soc_codec *codec = w->codec;
b2c812e2 506 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
3ed7074c
MB		 507
508 switch (event) {
509 case SND_SOC_DAPM_PRE_PMU:
510 switch (hubs->hp_startup_mode) {
511 case 0:
512 break;
513 case 1:
514 /* Enable the headphone amp */
515 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
516 WM8993_HPOUT1L_ENA |
517 WM8993_HPOUT1R_ENA,
518 WM8993_HPOUT1L_ENA |
519 WM8993_HPOUT1R_ENA);
520
521 /* Enable the second stage */
522 snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
523 WM8993_HPOUT1L_DLY |
524 WM8993_HPOUT1R_DLY,
525 WM8993_HPOUT1L_DLY |
526 WM8993_HPOUT1R_DLY);
527 break;
528 default:
529 dev_err(codec->dev, "Unknown HP startup mode %d\n",
530 hubs->hp_startup_mode);
531 break;
532 }
0492665d 533 break;
3ed7074c
MB		 534
535 case SND_SOC_DAPM_PRE_PMD:
536 snd_soc_update_bits(codec, WM8993_CHARGE_PUMP_1,
537 WM8993_CP_ENA, 0);
538 break;
539 }
540
541 return 0;
542}
543
a2342ae3
MB		 544static int hp_event(struct snd_soc_dapm_widget *w,
545 struct snd_kcontrol *kcontrol, int event)
546{
547 struct snd_soc_codec *codec = w->codec;
548 unsigned int reg = snd_soc_read(codec, WM8993_ANALOGUE_HP_0);
549
550 switch (event) {
551 case SND_SOC_DAPM_POST_PMU:
552 snd_soc_update_bits(codec, WM8993_CHARGE_PUMP_1,
553 WM8993_CP_ENA, WM8993_CP_ENA);
554
555 msleep(5);
556
557 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
558 WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA,
559 WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA);
560
561 reg |= WM8993_HPOUT1L_DLY | WM8993_HPOUT1R_DLY;
562 snd_soc_write(codec, WM8993_ANALOGUE_HP_0, reg);
563
3ed7074c 564 snd_soc_update_bits(codec, WM8993_DC_SERVO_1,
f9925d44 565 WM8993_DCS_TIMER_PERIOD_01_MASK, 0);
3ed7074c 566
a7892c35 567 enable_dc_servo(codec);
a2342ae3
MB		 568
569 reg |= WM8993_HPOUT1R_OUTP | WM8993_HPOUT1R_RMV_SHORT |
570 WM8993_HPOUT1L_OUTP | WM8993_HPOUT1L_RMV_SHORT;
571 snd_soc_write(codec, WM8993_ANALOGUE_HP_0, reg);
572 break;
573
574 case SND_SOC_DAPM_PRE_PMD:
3ed7074c 575 snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
6adb26bd
MB		 576 WM8993_HPOUT1L_OUTP |
577 WM8993_HPOUT1R_OUTP |
3ed7074c
MB		 578 WM8993_HPOUT1L_RMV_SHORT |
579 WM8993_HPOUT1R_RMV_SHORT, 0);
a2342ae3 580
3ed7074c 581 snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
6adb26bd
MB		 582 WM8993_HPOUT1L_DLY |
583 WM8993_HPOUT1R_DLY, 0);
a2342ae3 584
395e4b73
MB		 585 snd_soc_write(codec, WM8993_DC_SERVO_0, 0);
586
a2342ae3
MB		 587 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
588 WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA,
589 0);
a2342ae3
MB		 590 break;
591 }
592
593 return 0;
594}
595
596static int earpiece_event(struct snd_soc_dapm_widget *w,
597 struct snd_kcontrol *control, int event)
598{
599 struct snd_soc_codec *codec = w->codec;
600 u16 reg = snd_soc_read(codec, WM8993_ANTIPOP1) & ~WM8993_HPOUT2_IN_ENA;
601
602 switch (event) {
603 case SND_SOC_DAPM_PRE_PMU:
604 reg |= WM8993_HPOUT2_IN_ENA;
605 snd_soc_write(codec, WM8993_ANTIPOP1, reg);
606 udelay(50);
607 break;
608
609 case SND_SOC_DAPM_POST_PMD:
610 snd_soc_write(codec, WM8993_ANTIPOP1, reg);
611 break;
612
613 default:
614 BUG();
615 break;
616 }
617
618 return 0;
619}
620
5f2f3890
MB		 621static int lineout_event(struct snd_soc_dapm_widget *w,
622 struct snd_kcontrol *control, int event)
623{
624 struct snd_soc_codec *codec = w->codec;
625 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
626 bool *flag;
627
628 switch (w->shift) {
629 case WM8993_LINEOUT1N_ENA_SHIFT:
630 flag = &hubs->lineout1n_ena;
631 break;
632 case WM8993_LINEOUT1P_ENA_SHIFT:
633 flag = &hubs->lineout1p_ena;
634 break;
635 case WM8993_LINEOUT2N_ENA_SHIFT:
636 flag = &hubs->lineout2n_ena;
637 break;
638 case WM8993_LINEOUT2P_ENA_SHIFT:
639 flag = &hubs->lineout2p_ena;
640 break;
641 default:
642 WARN(1, "Unknown line output");
643 return -EINVAL;
644 }
645
646 *flag = SND_SOC_DAPM_EVENT_ON(event);
647
648 return 0;
649}
650
02e79476
MB		 651static int micbias_event(struct snd_soc_dapm_widget *w,
652 struct snd_kcontrol *kcontrol, int event)
653{
654 struct snd_soc_codec *codec = w->codec;
655 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
656
657 switch (w->shift) {
658 case WM8993_MICB1_ENA_SHIFT:
659 if (hubs->micb1_delay)
660 msleep(hubs->micb1_delay);
661 break;
662 case WM8993_MICB2_ENA_SHIFT:
663 if (hubs->micb2_delay)
664 msleep(hubs->micb2_delay);
665 break;
666 default:
667 return -EINVAL;
668 }
669
670 return 0;
671}
672
c340304d
MB		 673void wm_hubs_update_class_w(struct snd_soc_codec *codec)
674{
675 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
676 int enable = WM8993_CP_DYN_V | WM8993_CP_DYN_FREQ;
677
678 if (!wm_hubs_dac_hp_direct(codec))
679 enable = false;
680
681 if (hubs->check_class_w_digital && !hubs->check_class_w_digital(codec))
682 enable = false;
683
684 dev_vdbg(codec->dev, "Class W %s\n", enable ? "enabled" : "disabled");
685
686 snd_soc_update_bits(codec, WM8993_CLASS_W_0,
687 WM8993_CP_DYN_V | WM8993_CP_DYN_FREQ, enable);
eb4d5fc1
MB		 688
689 snd_soc_write(codec, WM8993_LEFT_OUTPUT_VOLUME,
690 snd_soc_read(codec, WM8993_LEFT_OUTPUT_VOLUME));
691 snd_soc_write(codec, WM8993_RIGHT_OUTPUT_VOLUME,
692 snd_soc_read(codec, WM8993_RIGHT_OUTPUT_VOLUME));
c340304d
MB		 693}
694EXPORT_SYMBOL_GPL(wm_hubs_update_class_w);
695
04de57c1
MB		 696#define WM_HUBS_SINGLE_W(xname, reg, shift, max, invert) \
697{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
698 .info = snd_soc_info_volsw, \
699 .get = snd_soc_dapm_get_volsw, .put = class_w_put_volsw, \
700 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
701
702static int class_w_put_volsw(struct snd_kcontrol *kcontrol,
703 struct snd_ctl_elem_value *ucontrol)
704{
705 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
706 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
707 struct snd_soc_codec *codec = widget->codec;
708 int ret;
709
710 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
711
712 wm_hubs_update_class_w(codec);
713
714 return ret;
715}
716
c340304d
MB		 717#define WM_HUBS_ENUM_W(xname, xenum) \
718{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
719 .info = snd_soc_info_enum_double, \
720 .get = snd_soc_dapm_get_enum_double, \
04de57c1 721 .put = class_w_put_double, \
c340304d
MB		 722 .private_value = (unsigned long)&xenum }
723
04de57c1
MB		 724static int class_w_put_double(struct snd_kcontrol *kcontrol,
725 struct snd_ctl_elem_value *ucontrol)
c340304d
MB		 726{
727 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
728 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
729 struct snd_soc_codec *codec = widget->codec;
730 int ret;
731
732 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
733
734 wm_hubs_update_class_w(codec);
735
736 return ret;
737}
738
739static const char *hp_mux_text[] = {
740 "Mixer",
741 "DAC",
742};
743
744static const struct soc_enum hpl_enum =
745 SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER1, 8, 2, hp_mux_text);
746
747const struct snd_kcontrol_new wm_hubs_hpl_mux =
748 WM_HUBS_ENUM_W("Left Headphone Mux", hpl_enum);
749EXPORT_SYMBOL_GPL(wm_hubs_hpl_mux);
750
751static const struct soc_enum hpr_enum =
752 SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER2, 8, 2, hp_mux_text);
753
754const struct snd_kcontrol_new wm_hubs_hpr_mux =
755 WM_HUBS_ENUM_W("Right Headphone Mux", hpr_enum);
756EXPORT_SYMBOL_GPL(wm_hubs_hpr_mux);
757
a2342ae3
MB		 758static const struct snd_kcontrol_new in1l_pga[] = {
759SOC_DAPM_SINGLE("IN1LP Switch", WM8993_INPUT_MIXER2, 5, 1, 0),
760SOC_DAPM_SINGLE("IN1LN Switch", WM8993_INPUT_MIXER2, 4, 1, 0),
761};
762
763static const struct snd_kcontrol_new in1r_pga[] = {
764SOC_DAPM_SINGLE("IN1RP Switch", WM8993_INPUT_MIXER2, 1, 1, 0),
765SOC_DAPM_SINGLE("IN1RN Switch", WM8993_INPUT_MIXER2, 0, 1, 0),
766};
767
768static const struct snd_kcontrol_new in2l_pga[] = {
769SOC_DAPM_SINGLE("IN2LP Switch", WM8993_INPUT_MIXER2, 7, 1, 0),
770SOC_DAPM_SINGLE("IN2LN Switch", WM8993_INPUT_MIXER2, 6, 1, 0),
771};
772
773static const struct snd_kcontrol_new in2r_pga[] = {
774SOC_DAPM_SINGLE("IN2RP Switch", WM8993_INPUT_MIXER2, 3, 1, 0),
775SOC_DAPM_SINGLE("IN2RN Switch", WM8993_INPUT_MIXER2, 2, 1, 0),
776};
777
778static const struct snd_kcontrol_new mixinl[] = {
779SOC_DAPM_SINGLE("IN2L Switch", WM8993_INPUT_MIXER3, 8, 1, 0),
780SOC_DAPM_SINGLE("IN1L Switch", WM8993_INPUT_MIXER3, 5, 1, 0),
781};
782
783static const struct snd_kcontrol_new mixinr[] = {
784SOC_DAPM_SINGLE("IN2R Switch", WM8993_INPUT_MIXER4, 8, 1, 0),
785SOC_DAPM_SINGLE("IN1R Switch", WM8993_INPUT_MIXER4, 5, 1, 0),
786};
787
788static const struct snd_kcontrol_new left_output_mixer[] = {
04de57c1
MB		 789WM_HUBS_SINGLE_W("Right Input Switch", WM8993_OUTPUT_MIXER1, 7, 1, 0),
790WM_HUBS_SINGLE_W("Left Input Switch", WM8993_OUTPUT_MIXER1, 6, 1, 0),
791WM_HUBS_SINGLE_W("IN2RN Switch", WM8993_OUTPUT_MIXER1, 5, 1, 0),
792WM_HUBS_SINGLE_W("IN2LN Switch", WM8993_OUTPUT_MIXER1, 4, 1, 0),
793WM_HUBS_SINGLE_W("IN2LP Switch", WM8993_OUTPUT_MIXER1, 1, 1, 0),
794WM_HUBS_SINGLE_W("IN1R Switch", WM8993_OUTPUT_MIXER1, 3, 1, 0),
795WM_HUBS_SINGLE_W("IN1L Switch", WM8993_OUTPUT_MIXER1, 2, 1, 0),
796WM_HUBS_SINGLE_W("DAC Switch", WM8993_OUTPUT_MIXER1, 0, 1, 0),
a2342ae3
MB		 797};
798
799static const struct snd_kcontrol_new right_output_mixer[] = {
04de57c1
MB		 800WM_HUBS_SINGLE_W("Left Input Switch", WM8993_OUTPUT_MIXER2, 7, 1, 0),
801WM_HUBS_SINGLE_W("Right Input Switch", WM8993_OUTPUT_MIXER2, 6, 1, 0),
802WM_HUBS_SINGLE_W("IN2LN Switch", WM8993_OUTPUT_MIXER2, 5, 1, 0),
803WM_HUBS_SINGLE_W("IN2RN Switch", WM8993_OUTPUT_MIXER2, 4, 1, 0),
804WM_HUBS_SINGLE_W("IN1L Switch", WM8993_OUTPUT_MIXER2, 3, 1, 0),
805WM_HUBS_SINGLE_W("IN1R Switch", WM8993_OUTPUT_MIXER2, 2, 1, 0),
806WM_HUBS_SINGLE_W("IN2RP Switch", WM8993_OUTPUT_MIXER2, 1, 1, 0),
807WM_HUBS_SINGLE_W("DAC Switch", WM8993_OUTPUT_MIXER2, 0, 1, 0),
a2342ae3
MB		 808};
809
810static const struct snd_kcontrol_new earpiece_mixer[] = {
811SOC_DAPM_SINGLE("Direct Voice Switch", WM8993_HPOUT2_MIXER, 5, 1, 0),
812SOC_DAPM_SINGLE("Left Output Switch", WM8993_HPOUT2_MIXER, 4, 1, 0),
813SOC_DAPM_SINGLE("Right Output Switch", WM8993_HPOUT2_MIXER, 3, 1, 0),
814};
815
816static const struct snd_kcontrol_new left_speaker_boost[] = {
817SOC_DAPM_SINGLE("Direct Voice Switch", WM8993_SPKOUT_MIXERS, 5, 1, 0),
818SOC_DAPM_SINGLE("SPKL Switch", WM8993_SPKOUT_MIXERS, 4, 1, 0),
819SOC_DAPM_SINGLE("SPKR Switch", WM8993_SPKOUT_MIXERS, 3, 1, 0),
820};
821
822static const struct snd_kcontrol_new right_speaker_boost[] = {
823SOC_DAPM_SINGLE("Direct Voice Switch", WM8993_SPKOUT_MIXERS, 2, 1, 0),
824SOC_DAPM_SINGLE("SPKL Switch", WM8993_SPKOUT_MIXERS, 1, 1, 0),
825SOC_DAPM_SINGLE("SPKR Switch", WM8993_SPKOUT_MIXERS, 0, 1, 0),
826};
827
828static const struct snd_kcontrol_new line1_mix[] = {
829SOC_DAPM_SINGLE("IN1R Switch", WM8993_LINE_MIXER1, 2, 1, 0),
830SOC_DAPM_SINGLE("IN1L Switch", WM8993_LINE_MIXER1, 1, 1, 0),
831SOC_DAPM_SINGLE("Output Switch", WM8993_LINE_MIXER1, 0, 1, 0),
832};
833
834static const struct snd_kcontrol_new line1n_mix[] = {
835SOC_DAPM_SINGLE("Left Output Switch", WM8993_LINE_MIXER1, 6, 1, 0),
836SOC_DAPM_SINGLE("Right Output Switch", WM8993_LINE_MIXER1, 5, 1, 0),
837};
838
839static const struct snd_kcontrol_new line1p_mix[] = {
840SOC_DAPM_SINGLE("Left Output Switch", WM8993_LINE_MIXER1, 0, 1, 0),
841};
842
843static const struct snd_kcontrol_new line2_mix[] = {
43b6cec2
MB		 844SOC_DAPM_SINGLE("IN1L Switch", WM8993_LINE_MIXER2, 2, 1, 0),
845SOC_DAPM_SINGLE("IN1R Switch", WM8993_LINE_MIXER2, 1, 1, 0),
a2342ae3
MB		 846SOC_DAPM_SINGLE("Output Switch", WM8993_LINE_MIXER2, 0, 1, 0),
847};
848
849static const struct snd_kcontrol_new line2n_mix[] = {
114395c6
UK		 850SOC_DAPM_SINGLE("Left Output Switch", WM8993_LINE_MIXER2, 5, 1, 0),
851SOC_DAPM_SINGLE("Right Output Switch", WM8993_LINE_MIXER2, 6, 1, 0),
a2342ae3
MB		 852};
853
854static const struct snd_kcontrol_new line2p_mix[] = {
855SOC_DAPM_SINGLE("Right Output Switch", WM8993_LINE_MIXER2, 0, 1, 0),
856};
857
858static const struct snd_soc_dapm_widget analogue_dapm_widgets[] = {
859SND_SOC_DAPM_INPUT("IN1LN"),
860SND_SOC_DAPM_INPUT("IN1LP"),
861SND_SOC_DAPM_INPUT("IN2LN"),
34825948 862SND_SOC_DAPM_INPUT("IN2LP:VXRN"),
a2342ae3
MB		 863SND_SOC_DAPM_INPUT("IN1RN"),
864SND_SOC_DAPM_INPUT("IN1RP"),
865SND_SOC_DAPM_INPUT("IN2RN"),
34825948 866SND_SOC_DAPM_INPUT("IN2RP:VXRP"),
a2342ae3 867
02e79476
MB		 868SND_SOC_DAPM_SUPPLY("MICBIAS2", WM8993_POWER_MANAGEMENT_1, 5, 0,
869 micbias_event, SND_SOC_DAPM_POST_PMU),
870SND_SOC_DAPM_SUPPLY("MICBIAS1", WM8993_POWER_MANAGEMENT_1, 4, 0,
871 micbias_event, SND_SOC_DAPM_POST_PMU),
a2342ae3
MB		 872
873SND_SOC_DAPM_MIXER("IN1L PGA", WM8993_POWER_MANAGEMENT_2, 6, 0,
874 in1l_pga, ARRAY_SIZE(in1l_pga)),
875SND_SOC_DAPM_MIXER("IN1R PGA", WM8993_POWER_MANAGEMENT_2, 4, 0,
876 in1r_pga, ARRAY_SIZE(in1r_pga)),
877
878SND_SOC_DAPM_MIXER("IN2L PGA", WM8993_POWER_MANAGEMENT_2, 7, 0,
879 in2l_pga, ARRAY_SIZE(in2l_pga)),
880SND_SOC_DAPM_MIXER("IN2R PGA", WM8993_POWER_MANAGEMENT_2, 5, 0,
881 in2r_pga, ARRAY_SIZE(in2r_pga)),
882
a2342ae3
MB		 883SND_SOC_DAPM_MIXER("MIXINL", WM8993_POWER_MANAGEMENT_2, 9, 0,
884 mixinl, ARRAY_SIZE(mixinl)),
885SND_SOC_DAPM_MIXER("MIXINR", WM8993_POWER_MANAGEMENT_2, 8, 0,
886 mixinr, ARRAY_SIZE(mixinr)),
887
a2342ae3
MB		 888SND_SOC_DAPM_MIXER("Left Output Mixer", WM8993_POWER_MANAGEMENT_3, 5, 0,
889 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
890SND_SOC_DAPM_MIXER("Right Output Mixer", WM8993_POWER_MANAGEMENT_3, 4, 0,
891 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
892
893SND_SOC_DAPM_PGA("Left Output PGA", WM8993_POWER_MANAGEMENT_3, 7, 0, NULL, 0),
894SND_SOC_DAPM_PGA("Right Output PGA", WM8993_POWER_MANAGEMENT_3, 6, 0, NULL, 0),
895
3ed7074c
MB		 896SND_SOC_DAPM_SUPPLY("Headphone Supply", SND_SOC_NOPM, 0, 0, hp_supply_event,
897 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
26422625
MB		 898SND_SOC_DAPM_OUT_DRV_E("Headphone PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
899 hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
a2342ae3
MB		 900
901SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
902 earpiece_mixer, ARRAY_SIZE(earpiece_mixer)),
903SND_SOC_DAPM_PGA_E("Earpiece Driver", WM8993_POWER_MANAGEMENT_1, 11, 0,
904 NULL, 0, earpiece_event,
905 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
906
907SND_SOC_DAPM_MIXER("SPKL Boost", SND_SOC_NOPM, 0, 0,
908 left_speaker_boost, ARRAY_SIZE(left_speaker_boost)),
909SND_SOC_DAPM_MIXER("SPKR Boost", SND_SOC_NOPM, 0, 0,
910 right_speaker_boost, ARRAY_SIZE(right_speaker_boost)),
911
03431972 912SND_SOC_DAPM_SUPPLY("TSHUT", WM8993_POWER_MANAGEMENT_2, 14, 0, NULL, 0),
dc9c7454
MB		 913SND_SOC_DAPM_OUT_DRV("SPKL Driver", WM8993_POWER_MANAGEMENT_1, 12, 0,
914 NULL, 0),
915SND_SOC_DAPM_OUT_DRV("SPKR Driver", WM8993_POWER_MANAGEMENT_1, 13, 0,
916 NULL, 0),
a2342ae3
MB		 917
918SND_SOC_DAPM_MIXER("LINEOUT1 Mixer", SND_SOC_NOPM, 0, 0,
919 line1_mix, ARRAY_SIZE(line1_mix)),
920SND_SOC_DAPM_MIXER("LINEOUT2 Mixer", SND_SOC_NOPM, 0, 0,
921 line2_mix, ARRAY_SIZE(line2_mix)),
922
923SND_SOC_DAPM_MIXER("LINEOUT1N Mixer", SND_SOC_NOPM, 0, 0,
924 line1n_mix, ARRAY_SIZE(line1n_mix)),
925SND_SOC_DAPM_MIXER("LINEOUT1P Mixer", SND_SOC_NOPM, 0, 0,
926 line1p_mix, ARRAY_SIZE(line1p_mix)),
927SND_SOC_DAPM_MIXER("LINEOUT2N Mixer", SND_SOC_NOPM, 0, 0,
928 line2n_mix, ARRAY_SIZE(line2n_mix)),
929SND_SOC_DAPM_MIXER("LINEOUT2P Mixer", SND_SOC_NOPM, 0, 0,
930 line2p_mix, ARRAY_SIZE(line2p_mix)),
931
5f2f3890
MB		 932SND_SOC_DAPM_OUT_DRV_E("LINEOUT1N Driver", WM8993_POWER_MANAGEMENT_3, 13, 0,
933 NULL, 0, lineout_event,
934 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
935SND_SOC_DAPM_OUT_DRV_E("LINEOUT1P Driver", WM8993_POWER_MANAGEMENT_3, 12, 0,
936 NULL, 0, lineout_event,
937 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
938SND_SOC_DAPM_OUT_DRV_E("LINEOUT2N Driver", WM8993_POWER_MANAGEMENT_3, 11, 0,
939 NULL, 0, lineout_event,
940 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
941SND_SOC_DAPM_OUT_DRV_E("LINEOUT2P Driver", WM8993_POWER_MANAGEMENT_3, 10, 0,
942 NULL, 0, lineout_event,
943 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
a2342ae3
MB		 944
945SND_SOC_DAPM_OUTPUT("SPKOUTLP"),
946SND_SOC_DAPM_OUTPUT("SPKOUTLN"),
947SND_SOC_DAPM_OUTPUT("SPKOUTRP"),
948SND_SOC_DAPM_OUTPUT("SPKOUTRN"),
949SND_SOC_DAPM_OUTPUT("HPOUT1L"),
950SND_SOC_DAPM_OUTPUT("HPOUT1R"),
951SND_SOC_DAPM_OUTPUT("HPOUT2P"),
952SND_SOC_DAPM_OUTPUT("HPOUT2N"),
953SND_SOC_DAPM_OUTPUT("LINEOUT1P"),
954SND_SOC_DAPM_OUTPUT("LINEOUT1N"),
955SND_SOC_DAPM_OUTPUT("LINEOUT2P"),
956SND_SOC_DAPM_OUTPUT("LINEOUT2N"),
957};
958
959static const struct snd_soc_dapm_route analogue_routes[] = {
4baafdd7
MB		 960 { "MICBIAS1", NULL, "CLK_SYS" },
961 { "MICBIAS2", NULL, "CLK_SYS" },
962
a2342ae3
MB		 963 { "IN1L PGA", "IN1LP Switch", "IN1LP" },
964 { "IN1L PGA", "IN1LN Switch", "IN1LN" },
965
4e04adaf
MB		 966 { "IN1L PGA", NULL, "VMID" },
967 { "IN1R PGA", NULL, "VMID" },
968 { "IN2L PGA", NULL, "VMID" },
969 { "IN2R PGA", NULL, "VMID" },
970
a2342ae3
MB		 971 { "IN1R PGA", "IN1RP Switch", "IN1RP" },
972 { "IN1R PGA", "IN1RN Switch", "IN1RN" },
973
34825948 974 { "IN2L PGA", "IN2LP Switch", "IN2LP:VXRN" },
a2342ae3
MB		 975 { "IN2L PGA", "IN2LN Switch", "IN2LN" },
976
34825948 977 { "IN2R PGA", "IN2RP Switch", "IN2RP:VXRP" },
a2342ae3
MB		 978 { "IN2R PGA", "IN2RN Switch", "IN2RN" },
979
34825948
JS		 980 { "Direct Voice", NULL, "IN2LP:VXRN" },
981 { "Direct Voice", NULL, "IN2RP:VXRP" },
a2342ae3
MB		 982
983 { "MIXINL", "IN1L Switch", "IN1L PGA" },
984 { "MIXINL", "IN2L Switch", "IN2L PGA" },
985 { "MIXINL", NULL, "Direct Voice" },
986 { "MIXINL", NULL, "IN1LP" },
987 { "MIXINL", NULL, "Left Output Mixer" },
4e04adaf 988 { "MIXINL", NULL, "VMID" },
a2342ae3
MB		 989
990 { "MIXINR", "IN1R Switch", "IN1R PGA" },
991 { "MIXINR", "IN2R Switch", "IN2R PGA" },
992 { "MIXINR", NULL, "Direct Voice" },
993 { "MIXINR", NULL, "IN1RP" },
994 { "MIXINR", NULL, "Right Output Mixer" },
4e04adaf 995 { "MIXINR", NULL, "VMID" },
a2342ae3
MB		 996
997 { "ADCL", NULL, "MIXINL" },
998 { "ADCR", NULL, "MIXINR" },
999
1000 { "Left Output Mixer", "Left Input Switch", "MIXINL" },
1001 { "Left Output Mixer", "Right Input Switch", "MIXINR" },
1002 { "Left Output Mixer", "IN2RN Switch", "IN2RN" },
1003 { "Left Output Mixer", "IN2LN Switch", "IN2LN" },
34825948 1004 { "Left Output Mixer", "IN2LP Switch", "IN2LP:VXRN" },
a2342ae3
MB		 1005 { "Left Output Mixer", "IN1L Switch", "IN1L PGA" },
1006 { "Left Output Mixer", "IN1R Switch", "IN1R PGA" },
1007
1008 { "Right Output Mixer", "Left Input Switch", "MIXINL" },
1009 { "Right Output Mixer", "Right Input Switch", "MIXINR" },
1010 { "Right Output Mixer", "IN2LN Switch", "IN2LN" },
1011 { "Right Output Mixer", "IN2RN Switch", "IN2RN" },
34825948 1012 { "Right Output Mixer", "IN2RP Switch", "IN2RP:VXRP" },
a2342ae3
MB		 1013 { "Right Output Mixer", "IN1L Switch", "IN1L PGA" },
1014 { "Right Output Mixer", "IN1R Switch", "IN1R PGA" },
1015
1016 { "Left Output PGA", NULL, "Left Output Mixer" },
1017 { "Left Output PGA", NULL, "TOCLK" },
1018
1019 { "Right Output PGA", NULL, "Right Output Mixer" },
1020 { "Right Output PGA", NULL, "TOCLK" },
1021
1022 { "Earpiece Mixer", "Direct Voice Switch", "Direct Voice" },
1023 { "Earpiece Mixer", "Left Output Switch", "Left Output PGA" },
1024 { "Earpiece Mixer", "Right Output Switch", "Right Output PGA" },
1025
4e04adaf 1026 { "Earpiece Driver", NULL, "VMID" },
a2342ae3
MB		 1027 { "Earpiece Driver", NULL, "Earpiece Mixer" },
1028 { "HPOUT2N", NULL, "Earpiece Driver" },
1029 { "HPOUT2P", NULL, "Earpiece Driver" },
1030
1031 { "SPKL", "Input Switch", "MIXINL" },
1032 { "SPKL", "IN1LP Switch", "IN1LP" },
39cca168 1033 { "SPKL", "Output Switch", "Left Output PGA" },
a2342ae3
MB		 1034 { "SPKL", NULL, "TOCLK" },
1035
1036 { "SPKR", "Input Switch", "MIXINR" },
1037 { "SPKR", "IN1RP Switch", "IN1RP" },
39cca168 1038 { "SPKR", "Output Switch", "Right Output PGA" },
a2342ae3
MB		 1039 { "SPKR", NULL, "TOCLK" },
1040
1041 { "SPKL Boost", "Direct Voice Switch", "Direct Voice" },
1042 { "SPKL Boost", "SPKL Switch", "SPKL" },
1043 { "SPKL Boost", "SPKR Switch", "SPKR" },
1044
1045 { "SPKR Boost", "Direct Voice Switch", "Direct Voice" },
1046 { "SPKR Boost", "SPKR Switch", "SPKR" },
1047 { "SPKR Boost", "SPKL Switch", "SPKL" },
1048
4e04adaf 1049 { "SPKL Driver", NULL, "VMID" },
a2342ae3
MB		 1050 { "SPKL Driver", NULL, "SPKL Boost" },
1051 { "SPKL Driver", NULL, "CLK_SYS" },
03431972 1052 { "SPKL Driver", NULL, "TSHUT" },
a2342ae3 1053
4e04adaf 1054 { "SPKR Driver", NULL, "VMID" },
a2342ae3
MB		 1055 { "SPKR Driver", NULL, "SPKR Boost" },
1056 { "SPKR Driver", NULL, "CLK_SYS" },
03431972 1057 { "SPKR Driver", NULL, "TSHUT" },
a2342ae3
MB		 1058
1059 { "SPKOUTLP", NULL, "SPKL Driver" },
1060 { "SPKOUTLN", NULL, "SPKL Driver" },
1061 { "SPKOUTRP", NULL, "SPKR Driver" },
1062 { "SPKOUTRN", NULL, "SPKR Driver" },
1063
39cca168
MB		 1064 { "Left Headphone Mux", "Mixer", "Left Output PGA" },
1065 { "Right Headphone Mux", "Mixer", "Right Output PGA" },
a2342ae3
MB		 1066
1067 { "Headphone PGA", NULL, "Left Headphone Mux" },
1068 { "Headphone PGA", NULL, "Right Headphone Mux" },
4e04adaf 1069 { "Headphone PGA", NULL, "VMID" },
a2342ae3 1070 { "Headphone PGA", NULL, "CLK_SYS" },
3ed7074c 1071 { "Headphone PGA", NULL, "Headphone Supply" },
a2342ae3
MB		 1072
1073 { "HPOUT1L", NULL, "Headphone PGA" },
1074 { "HPOUT1R", NULL, "Headphone PGA" },
1075
4e04adaf
MB		 1076 { "LINEOUT1N Driver", NULL, "VMID" },
1077 { "LINEOUT1P Driver", NULL, "VMID" },
1078 { "LINEOUT2N Driver", NULL, "VMID" },
1079 { "LINEOUT2P Driver", NULL, "VMID" },
1080
a2342ae3
MB		 1081 { "LINEOUT1N", NULL, "LINEOUT1N Driver" },
1082 { "LINEOUT1P", NULL, "LINEOUT1P Driver" },
1083 { "LINEOUT2N", NULL, "LINEOUT2N Driver" },
1084 { "LINEOUT2P", NULL, "LINEOUT2P Driver" },
1085};
1086
1087static const struct snd_soc_dapm_route lineout1_diff_routes[] = {
1088 { "LINEOUT1 Mixer", "IN1L Switch", "IN1L PGA" },
1089 { "LINEOUT1 Mixer", "IN1R Switch", "IN1R PGA" },
d0b48af6 1090 { "LINEOUT1 Mixer", "Output Switch", "Left Output PGA" },
a2342ae3
MB		 1091
1092 { "LINEOUT1N Driver", NULL, "LINEOUT1 Mixer" },
1093 { "LINEOUT1P Driver", NULL, "LINEOUT1 Mixer" },
1094};
1095
1096static const struct snd_soc_dapm_route lineout1_se_routes[] = {
d0b48af6
MB		 1097 { "LINEOUT1N Mixer", "Left Output Switch", "Left Output PGA" },
1098 { "LINEOUT1N Mixer", "Right Output Switch", "Right Output PGA" },
a2342ae3 1099
d0b48af6 1100 { "LINEOUT1P Mixer", "Left Output Switch", "Left Output PGA" },
a2342ae3
MB		 1101
1102 { "LINEOUT1N Driver", NULL, "LINEOUT1N Mixer" },
1103 { "LINEOUT1P Driver", NULL, "LINEOUT1P Mixer" },
1104};
1105
1106static const struct snd_soc_dapm_route lineout2_diff_routes[] = {
ee76744c
MB		 1107 { "LINEOUT2 Mixer", "IN1L Switch", "IN1L PGA" },
1108 { "LINEOUT2 Mixer", "IN1R Switch", "IN1R PGA" },
d0b48af6 1109 { "LINEOUT2 Mixer", "Output Switch", "Right Output PGA" },
a2342ae3
MB		 1110
1111 { "LINEOUT2N Driver", NULL, "LINEOUT2 Mixer" },
1112 { "LINEOUT2P Driver", NULL, "LINEOUT2 Mixer" },
1113};
1114
1115static const struct snd_soc_dapm_route lineout2_se_routes[] = {
d0b48af6
MB		 1116 { "LINEOUT2N Mixer", "Left Output Switch", "Left Output PGA" },
1117 { "LINEOUT2N Mixer", "Right Output Switch", "Right Output PGA" },
a2342ae3 1118
d0b48af6 1119 { "LINEOUT2P Mixer", "Right Output Switch", "Right Output PGA" },
a2342ae3
MB		 1120
1121 { "LINEOUT2N Driver", NULL, "LINEOUT2N Mixer" },
1122 { "LINEOUT2P Driver", NULL, "LINEOUT2P Mixer" },
1123};
1124
1125int wm_hubs_add_analogue_controls(struct snd_soc_codec *codec)
1126{
ce6120cc
LG		 1127 struct snd_soc_dapm_context *dapm = &codec->dapm;
1128
a2342ae3
MB		 1129 /* Latch volume update bits & default ZC on */
1130 snd_soc_update_bits(codec, WM8993_LEFT_LINE_INPUT_1_2_VOLUME,
1131 WM8993_IN1_VU, WM8993_IN1_VU);
1132 snd_soc_update_bits(codec, WM8993_RIGHT_LINE_INPUT_1_2_VOLUME,
1133 WM8993_IN1_VU, WM8993_IN1_VU);
1134 snd_soc_update_bits(codec, WM8993_LEFT_LINE_INPUT_3_4_VOLUME,
1135 WM8993_IN2_VU, WM8993_IN2_VU);
1136 snd_soc_update_bits(codec, WM8993_RIGHT_LINE_INPUT_3_4_VOLUME,
1137 WM8993_IN2_VU, WM8993_IN2_VU);
1138
fb5af53d
MB		 1139 snd_soc_update_bits(codec, WM8993_SPEAKER_VOLUME_LEFT,
1140 WM8993_SPKOUT_VU, WM8993_SPKOUT_VU);
a2342ae3
MB		 1141 snd_soc_update_bits(codec, WM8993_SPEAKER_VOLUME_RIGHT,
1142 WM8993_SPKOUT_VU, WM8993_SPKOUT_VU);
1143
1144 snd_soc_update_bits(codec, WM8993_LEFT_OUTPUT_VOLUME,
fb5af53d
MB		 1145 WM8993_HPOUT1_VU | WM8993_HPOUT1L_ZC,
1146 WM8993_HPOUT1_VU | WM8993_HPOUT1L_ZC);
a2342ae3
MB		 1147 snd_soc_update_bits(codec, WM8993_RIGHT_OUTPUT_VOLUME,
1148 WM8993_HPOUT1_VU | WM8993_HPOUT1R_ZC,
1149 WM8993_HPOUT1_VU | WM8993_HPOUT1R_ZC);
1150
1151 snd_soc_update_bits(codec, WM8993_LEFT_OPGA_VOLUME,
fb5af53d
MB		 1152 WM8993_MIXOUTL_ZC | WM8993_MIXOUT_VU,
1153 WM8993_MIXOUTL_ZC | WM8993_MIXOUT_VU);
a2342ae3
MB		 1154 snd_soc_update_bits(codec, WM8993_RIGHT_OPGA_VOLUME,
1155 WM8993_MIXOUTR_ZC | WM8993_MIXOUT_VU,
1156 WM8993_MIXOUTR_ZC | WM8993_MIXOUT_VU);
1157
022658be 1158 snd_soc_add_codec_controls(codec, analogue_snd_controls,
a2342ae3
MB		 1159 ARRAY_SIZE(analogue_snd_controls));
1160
ce6120cc 1161 snd_soc_dapm_new_controls(dapm, analogue_dapm_widgets,
a2342ae3
MB		 1162 ARRAY_SIZE(analogue_dapm_widgets));
1163 return 0;
1164}
1165EXPORT_SYMBOL_GPL(wm_hubs_add_analogue_controls);
1166
1167int wm_hubs_add_analogue_routes(struct snd_soc_codec *codec,
1168 int lineout1_diff, int lineout2_diff)
1169{
d96ca3cd 1170 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
ce6120cc
LG		 1171 struct snd_soc_dapm_context *dapm = &codec->dapm;
1172
8cb8e83b
MB		 1173 hubs->codec = codec;
1174
94aa733a 1175 INIT_LIST_HEAD(&hubs->dcs_cache);
d96ca3cd
MB		 1176 init_completion(&hubs->dcs_done);
1177
ce6120cc 1178 snd_soc_dapm_add_routes(dapm, analogue_routes,
a2342ae3
MB		 1179 ARRAY_SIZE(analogue_routes));
1180
1181 if (lineout1_diff)
ce6120cc 1182 snd_soc_dapm_add_routes(dapm,
a2342ae3
MB		 1183 lineout1_diff_routes,
1184 ARRAY_SIZE(lineout1_diff_routes));
1185 else
ce6120cc 1186 snd_soc_dapm_add_routes(dapm,
a2342ae3
MB		 1187 lineout1_se_routes,
1188 ARRAY_SIZE(lineout1_se_routes));
1189
1190 if (lineout2_diff)
ce6120cc 1191 snd_soc_dapm_add_routes(dapm,
a2342ae3
MB		 1192 lineout2_diff_routes,
1193 ARRAY_SIZE(lineout2_diff_routes));
1194 else
ce6120cc 1195 snd_soc_dapm_add_routes(dapm,
a2342ae3
MB		 1196 lineout2_se_routes,
1197 ARRAY_SIZE(lineout2_se_routes));
1198
1199 return 0;
1200}
1201EXPORT_SYMBOL_GPL(wm_hubs_add_analogue_routes);
1202
aa983d9d
MB		 1203int wm_hubs_handle_analogue_pdata(struct snd_soc_codec *codec,
1204 int lineout1_diff, int lineout2_diff,
1205 int lineout1fb, int lineout2fb,
02e79476
MB		 1206 int jd_scthr, int jd_thr,
1207 int micbias1_delay, int micbias2_delay,
1208 int micbias1_lvl, int micbias2_lvl)
aa983d9d 1209{
5f2f3890
MB		 1210 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
1211
1212 hubs->lineout1_se = !lineout1_diff;
1213 hubs->lineout2_se = !lineout2_diff;
02e79476
MB		 1214 hubs->micb1_delay = micbias1_delay;
1215 hubs->micb2_delay = micbias2_delay;
5f2f3890 1216
aa983d9d
MB		 1217 if (!lineout1_diff)
1218 snd_soc_update_bits(codec, WM8993_LINE_MIXER1,
1219 WM8993_LINEOUT1_MODE,
1220 WM8993_LINEOUT1_MODE);
1221 if (!lineout2_diff)
1222 snd_soc_update_bits(codec, WM8993_LINE_MIXER2,
1223 WM8993_LINEOUT2_MODE,
1224 WM8993_LINEOUT2_MODE);
1225
5472bbc9
MB		 1226 if (!lineout1_diff && !lineout2_diff)
1227 snd_soc_update_bits(codec, WM8993_ANTIPOP1,
1228 WM8993_LINEOUT_VMID_BUF_ENA,
1229 WM8993_LINEOUT_VMID_BUF_ENA);
1230
aa983d9d
MB		 1231 if (lineout1fb)
1232 snd_soc_update_bits(codec, WM8993_ADDITIONAL_CONTROL,
1233 WM8993_LINEOUT1_FB, WM8993_LINEOUT1_FB);
1234
1235 if (lineout2fb)
1236 snd_soc_update_bits(codec, WM8993_ADDITIONAL_CONTROL,
1237 WM8993_LINEOUT2_FB, WM8993_LINEOUT2_FB);
1238
1239 snd_soc_update_bits(codec, WM8993_MICBIAS,
1240 WM8993_JD_SCTHR_MASK | WM8993_JD_THR_MASK |
1241 WM8993_MICB1_LVL | WM8993_MICB2_LVL,
1242 jd_scthr << WM8993_JD_SCTHR_SHIFT |
1243 jd_thr << WM8993_JD_THR_SHIFT |
1244 micbias1_lvl |
1245 micbias2_lvl << WM8993_MICB2_LVL_SHIFT);
1246
1247 return 0;
1248}
1249EXPORT_SYMBOL_GPL(wm_hubs_handle_analogue_pdata);
1250
5f2f3890
MB		 1251void wm_hubs_vmid_ena(struct snd_soc_codec *codec)
1252{
1253 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
1254 int val = 0;
1255
1256 if (hubs->lineout1_se)
1257 val |= WM8993_LINEOUT1N_ENA | WM8993_LINEOUT1P_ENA;
1258
1259 if (hubs->lineout2_se)
1260 val |= WM8993_LINEOUT2N_ENA | WM8993_LINEOUT2P_ENA;
1261
1262 /* Enable the line outputs while we power up */
1263 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_3, val, val);
1264}
1265EXPORT_SYMBOL_GPL(wm_hubs_vmid_ena);
1266
1267void wm_hubs_set_bias_level(struct snd_soc_codec *codec,
1268 enum snd_soc_bias_level level)
1269{
1270 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
de050aca 1271 int mask, val;
5f2f3890
MB		 1272
1273 switch (level) {
d60d6c3b
MB		 1274 case SND_SOC_BIAS_STANDBY:
1275 /* Clamp the inputs to VMID while we ramp to charge caps */
1276 snd_soc_update_bits(codec, WM8993_INPUTS_CLAMP_REG,
1277 WM8993_INPUTS_CLAMP, WM8993_INPUTS_CLAMP);
1278 break;
1279
5f2f3890
MB		 1280 case SND_SOC_BIAS_ON:
1281 /* Turn off any unneded single ended outputs */
1282 val = 0;
de050aca
MB		 1283 mask = 0;
1284
1285 if (hubs->lineout1_se)
1286 mask |= WM8993_LINEOUT1N_ENA | WM8993_LINEOUT1P_ENA;
1287
1288 if (hubs->lineout2_se)
1289 mask |= WM8993_LINEOUT2N_ENA | WM8993_LINEOUT2P_ENA;
5f2f3890
MB		 1290
1291 if (hubs->lineout1_se && hubs->lineout1n_ena)
1292 val |= WM8993_LINEOUT1N_ENA;
1293
1294 if (hubs->lineout1_se && hubs->lineout1p_ena)
1295 val |= WM8993_LINEOUT1P_ENA;
1296
1297 if (hubs->lineout2_se && hubs->lineout2n_ena)
1298 val |= WM8993_LINEOUT2N_ENA;
1299
1300 if (hubs->lineout2_se && hubs->lineout2p_ena)
1301 val |= WM8993_LINEOUT2P_ENA;
1302
1303 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_3,
de050aca 1304 mask, val);
5f2f3890 1305
d60d6c3b
MB		 1306 /* Remove the input clamps */
1307 snd_soc_update_bits(codec, WM8993_INPUTS_CLAMP_REG,
1308 WM8993_INPUTS_CLAMP, 0);
5f2f3890
MB		 1309 break;
1310
1311 default:
1312 break;
1313 }
1314}
1315EXPORT_SYMBOL_GPL(wm_hubs_set_bias_level);
1316
a2342ae3
MB		 1317MODULE_DESCRIPTION("Shared support for Wolfson hubs products");
1318MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1319MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)