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ASoC: wm8994: VMID management improvements
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / wm8994.c
CommitLineData
9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
39fb51a1 21#include <linux/pm_runtime.h>
9e6e96a1 22#include <linux/regulator/consumer.h>
5a0e3ad6 23#include <linux/slab.h>
9e6e96a1 24#include <sound/core.h>
821edd2f 25#include <sound/jack.h>
9e6e96a1
MB		 26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
9e6e96a1
MB		 29#include <sound/initval.h>
30#include <sound/tlv.h>
2bbb5d66 31#include <trace/events/asoc.h>
9e6e96a1
MB		 32
33#include <linux/mfd/wm8994/core.h>
34#include <linux/mfd/wm8994/registers.h>
35#include <linux/mfd/wm8994/pdata.h>
36#include <linux/mfd/wm8994/gpio.h>
37
38#include "wm8994.h"
39#include "wm_hubs.h"
40
af6b6fe4
MB		 41#define WM1811_JACKDET_MODE_NONE 0x0000
42#define WM1811_JACKDET_MODE_JACK 0x0100
43#define WM1811_JACKDET_MODE_MIC 0x0080
44#define WM1811_JACKDET_MODE_AUDIO 0x0180
45
9e6e96a1
MB		 46#define WM8994_NUM_DRC 3
47#define WM8994_NUM_EQ 3
48
49static int wm8994_drc_base[] = {
50 WM8994_AIF1_DRC1_1,
51 WM8994_AIF1_DRC2_1,
52 WM8994_AIF2_DRC_1,
53};
54
55static int wm8994_retune_mobile_base[] = {
56 WM8994_AIF1_DAC1_EQ_GAINS_1,
57 WM8994_AIF1_DAC2_EQ_GAINS_1,
58 WM8994_AIF2_EQ_GAINS_1,
59};
60
b00adf76
MB		 61static void wm8958_default_micdet(u16 status, void *data);
62
af6b6fe4 63static const struct wm8958_micd_rate micdet_rates[] = {
b00adf76
MB		 64 { 32768, true, 1, 4 },
65 { 32768, false, 1, 1 },
604533de
MB		 66 { 44100 * 256, true, 7, 10 },
67 { 44100 * 256, false, 7, 10 },
b00adf76
MB		 68};
69
af6b6fe4
MB		 70static const struct wm8958_micd_rate jackdet_rates[] = {
71 { 32768, true, 0, 1 },
72 { 32768, false, 0, 1 },
73 { 44100 * 256, true, 7, 10 },
74 { 44100 * 256, false, 7, 10 },
75};
76
b00adf76
MB		 77static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
78{
79 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
80 int best, i, sysclk, val;
81 bool idle;
af6b6fe4
MB		 82 const struct wm8958_micd_rate *rates;
83 int num_rates;
b00adf76
MB		 84
85 if (wm8994->jack_cb != wm8958_default_micdet)
86 return;
87
88 idle = !wm8994->jack_mic;
89
90 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
91 if (sysclk & WM8994_SYSCLK_SRC)
92 sysclk = wm8994->aifclk[1];
93 else
94 sysclk = wm8994->aifclk[0];
95
cd1707a9
MB		 96 if (wm8994->pdata && wm8994->pdata->micd_rates) {
97 rates = wm8994->pdata->micd_rates;
98 num_rates = wm8994->pdata->num_micd_rates;
99 } else if (wm8994->jackdet) {
af6b6fe4
MB		 100 rates = jackdet_rates;
101 num_rates = ARRAY_SIZE(jackdet_rates);
102 } else {
103 rates = micdet_rates;
104 num_rates = ARRAY_SIZE(micdet_rates);
105 }
106
b00adf76 107 best = 0;
af6b6fe4
MB		 108 for (i = 0; i < num_rates; i++) {
109 if (rates[i].idle != idle)
b00adf76 110 continue;
af6b6fe4
MB		 111 if (abs(rates[i].sysclk - sysclk) <
112 abs(rates[best].sysclk - sysclk))
b00adf76 113 best = i;
af6b6fe4 114 else if (rates[best].idle != idle)
b00adf76
MB		 115 best = i;
116 }
117
af6b6fe4
MB		 118 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
119 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
b00adf76
MB		 120
121 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
122 WM8958_MICD_BIAS_STARTTIME_MASK |
123 WM8958_MICD_RATE_MASK, val);
124}
125
9e6e96a1
MB		 126static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
127{
b2c812e2 128 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 129 int rate;
130 int reg1 = 0;
131 int offset;
132
133 if (aif)
134 offset = 4;
135 else
136 offset = 0;
137
138 switch (wm8994->sysclk[aif]) {
139 case WM8994_SYSCLK_MCLK1:
140 rate = wm8994->mclk[0];
141 break;
142
143 case WM8994_SYSCLK_MCLK2:
144 reg1 |= 0x8;
145 rate = wm8994->mclk[1];
146 break;
147
148 case WM8994_SYSCLK_FLL1:
149 reg1 |= 0x10;
150 rate = wm8994->fll[0].out;
151 break;
152
153 case WM8994_SYSCLK_FLL2:
154 reg1 |= 0x18;
155 rate = wm8994->fll[1].out;
156 break;
157
158 default:
159 return -EINVAL;
160 }
161
162 if (rate >= 13500000) {
163 rate /= 2;
164 reg1 |= WM8994_AIF1CLK_DIV;
165
166 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
167 aif + 1, rate);
168 }
5e5e2bef 169
9e6e96a1
MB		 170 wm8994->aifclk[aif] = rate;
171
172 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
173 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
174 reg1);
175
176 return 0;
177}
178
179static int configure_clock(struct snd_soc_codec *codec)
180{
b2c812e2 181 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
04f45c49 182 int change, new;
9e6e96a1
MB		 183
184 /* Bring up the AIF clocks first */
185 configure_aif_clock(codec, 0);
186 configure_aif_clock(codec, 1);
187
188 /* Then switch CLK_SYS over to the higher of them; a change
189 * can only happen as a result of a clocking change which can
190 * only be made outside of DAPM so we can safely redo the
191 * clocking.
192 */
193
194 /* If they're equal it doesn't matter which is used */
b00adf76
MB		 195 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
196 wm8958_micd_set_rate(codec);
9e6e96a1 197 return 0;
b00adf76 198 }
9e6e96a1
MB		 199
200 if (wm8994->aifclk[0] < wm8994->aifclk[1])
201 new = WM8994_SYSCLK_SRC;
202 else
203 new = 0;
204
04f45c49
AL		 205 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
206 WM8994_SYSCLK_SRC, new);
52ac7ab2
MB		 207 if (change)
208 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1 209
b00adf76
MB		 210 wm8958_micd_set_rate(codec);
211
9e6e96a1
MB		 212 return 0;
213}
214
215static int check_clk_sys(struct snd_soc_dapm_widget *source,
216 struct snd_soc_dapm_widget *sink)
217{
218 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
219 const char *clk;
220
221 /* Check what we're currently using for CLK_SYS */
222 if (reg & WM8994_SYSCLK_SRC)
223 clk = "AIF2CLK";
224 else
225 clk = "AIF1CLK";
226
227 return strcmp(source->name, clk) == 0;
228}
229
230static const char *sidetone_hpf_text[] = {
231 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
232};
233
234static const struct soc_enum sidetone_hpf =
235 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
236
146fd574
UK		 237static const char *adc_hpf_text[] = {
238 "HiFi", "Voice 1", "Voice 2", "Voice 3"
239};
240
241static const struct soc_enum aif1adc1_hpf =
242 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
243
244static const struct soc_enum aif1adc2_hpf =
245 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
246
247static const struct soc_enum aif2adc_hpf =
248 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
249
9e6e96a1
MB		 250static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
251static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
252static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
253static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
254static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1ddc07d0 255static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
81204c84 256static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
9e6e96a1
MB		 257
258#define WM8994_DRC_SWITCH(xname, reg, shift) \
259{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
260 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
261 .put = wm8994_put_drc_sw, \
262 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
263
264static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
265 struct snd_ctl_elem_value *ucontrol)
266{
267 struct soc_mixer_control *mc =
268 (struct soc_mixer_control *)kcontrol->private_value;
269 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
270 int mask, ret;
271
272 /* Can't enable both ADC and DAC paths simultaneously */
273 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
274 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
275 WM8994_AIF1ADC1R_DRC_ENA_MASK;
276 else
277 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
278
279 ret = snd_soc_read(codec, mc->reg);
280 if (ret < 0)
281 return ret;
282 if (ret & mask)
283 return -EINVAL;
284
285 return snd_soc_put_volsw(kcontrol, ucontrol);
286}
287
9e6e96a1
MB		 288static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
289{
b2c812e2 290 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 291 struct wm8994_pdata *pdata = wm8994->pdata;
292 int base = wm8994_drc_base[drc];
293 int cfg = wm8994->drc_cfg[drc];
294 int save, i;
295
296 /* Save any enables; the configuration should clear them. */
297 save = snd_soc_read(codec, base);
298 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
299 WM8994_AIF1ADC1R_DRC_ENA;
300
301 for (i = 0; i < WM8994_DRC_REGS; i++)
302 snd_soc_update_bits(codec, base + i, 0xffff,
303 pdata->drc_cfgs[cfg].regs[i]);
304
305 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
306 WM8994_AIF1ADC1L_DRC_ENA |
307 WM8994_AIF1ADC1R_DRC_ENA, save);
308}
309
310/* Icky as hell but saves code duplication */
311static int wm8994_get_drc(const char *name)
312{
313 if (strcmp(name, "AIF1DRC1 Mode") == 0)
314 return 0;
315 if (strcmp(name, "AIF1DRC2 Mode") == 0)
316 return 1;
317 if (strcmp(name, "AIF2DRC Mode") == 0)
318 return 2;
319 return -EINVAL;
320}
321
322static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
323 struct snd_ctl_elem_value *ucontrol)
324{
325 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 326 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 327 struct wm8994_pdata *pdata = wm8994->pdata;
328 int drc = wm8994_get_drc(kcontrol->id.name);
329 int value = ucontrol->value.integer.value[0];
330
331 if (drc < 0)
332 return drc;
333
334 if (value >= pdata->num_drc_cfgs)
335 return -EINVAL;
336
337 wm8994->drc_cfg[drc] = value;
338
339 wm8994_set_drc(codec, drc);
340
341 return 0;
342}
343
344static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
345 struct snd_ctl_elem_value *ucontrol)
346{
347 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 348 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 349 int drc = wm8994_get_drc(kcontrol->id.name);
350
351 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
352
353 return 0;
354}
355
356static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
357{
b2c812e2 358 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 359 struct wm8994_pdata *pdata = wm8994->pdata;
360 int base = wm8994_retune_mobile_base[block];
361 int iface, best, best_val, save, i, cfg;
362
363 if (!pdata || !wm8994->num_retune_mobile_texts)
364 return;
365
366 switch (block) {
367 case 0:
368 case 1:
369 iface = 0;
370 break;
371 case 2:
372 iface = 1;
373 break;
374 default:
375 return;
376 }
377
378 /* Find the version of the currently selected configuration
379 * with the nearest sample rate. */
380 cfg = wm8994->retune_mobile_cfg[block];
381 best = 0;
382 best_val = INT_MAX;
383 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
384 if (strcmp(pdata->retune_mobile_cfgs[i].name,
385 wm8994->retune_mobile_texts[cfg]) == 0 &&
386 abs(pdata->retune_mobile_cfgs[i].rate
387 - wm8994->dac_rates[iface]) < best_val) {
388 best = i;
389 best_val = abs(pdata->retune_mobile_cfgs[i].rate
390 - wm8994->dac_rates[iface]);
391 }
392 }
393
394 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
395 block,
396 pdata->retune_mobile_cfgs[best].name,
397 pdata->retune_mobile_cfgs[best].rate,
398 wm8994->dac_rates[iface]);
399
400 /* The EQ will be disabled while reconfiguring it, remember the
401 * current configuration.
402 */
403 save = snd_soc_read(codec, base);
404 save &= WM8994_AIF1DAC1_EQ_ENA;
405
406 for (i = 0; i < WM8994_EQ_REGS; i++)
407 snd_soc_update_bits(codec, base + i, 0xffff,
408 pdata->retune_mobile_cfgs[best].regs[i]);
409
410 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
411}
412
413/* Icky as hell but saves code duplication */
414static int wm8994_get_retune_mobile_block(const char *name)
415{
416 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
417 return 0;
418 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
419 return 1;
420 if (strcmp(name, "AIF2 EQ Mode") == 0)
421 return 2;
422 return -EINVAL;
423}
424
425static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
426 struct snd_ctl_elem_value *ucontrol)
427{
428 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 429 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 430 struct wm8994_pdata *pdata = wm8994->pdata;
431 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
432 int value = ucontrol->value.integer.value[0];
433
434 if (block < 0)
435 return block;
436
437 if (value >= pdata->num_retune_mobile_cfgs)
438 return -EINVAL;
439
440 wm8994->retune_mobile_cfg[block] = value;
441
442 wm8994_set_retune_mobile(codec, block);
443
444 return 0;
445}
446
447static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
448 struct snd_ctl_elem_value *ucontrol)
449{
450 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
4a8d929d 451 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 452 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
453
454 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
455
456 return 0;
457}
458
96b101ef 459static const char *aif_chan_src_text[] = {
f554885f
MB		 460 "Left", "Right"
461};
462
96b101ef
MB		 463static const struct soc_enum aif1adcl_src =
464 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
465
466static const struct soc_enum aif1adcr_src =
467 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
468
469static const struct soc_enum aif2adcl_src =
470 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
471
472static const struct soc_enum aif2adcr_src =
473 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
474
f554885f 475static const struct soc_enum aif1dacl_src =
96b101ef 476 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 477
478static const struct soc_enum aif1dacr_src =
96b101ef 479 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f
MB		 480
481static const struct soc_enum aif2dacl_src =
96b101ef 482 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 483
484static const struct soc_enum aif2dacr_src =
96b101ef 485 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 486
154b26aa
MB		 487static const char *osr_text[] = {
488 "Low Power", "High Performance",
489};
490
491static const struct soc_enum dac_osr =
492 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
493
494static const struct soc_enum adc_osr =
495 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
496
9e6e96a1
MB		 497static const struct snd_kcontrol_new wm8994_snd_controls[] = {
498SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
499 WM8994_AIF1_ADC1_RIGHT_VOLUME,
500 1, 119, 0, digital_tlv),
501SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
502 WM8994_AIF1_ADC2_RIGHT_VOLUME,
503 1, 119, 0, digital_tlv),
504SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
505 WM8994_AIF2_ADC_RIGHT_VOLUME,
506 1, 119, 0, digital_tlv),
507
96b101ef
MB		 508SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
509SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
49db7e7b
MB		 510SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
511SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
96b101ef 512
f554885f
MB		 513SOC_ENUM("AIF1DACL Source", aif1dacl_src),
514SOC_ENUM("AIF1DACR Source", aif1dacr_src),
49db7e7b
MB		 515SOC_ENUM("AIF2DACL Source", aif2dacl_src),
516SOC_ENUM("AIF2DACR Source", aif2dacr_src),
f554885f 517
9e6e96a1
MB		 518SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
519 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
520SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
521 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
522SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
523 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
524
525SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
526SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
527
528SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
529SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
530SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
531
532WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
533WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
534WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
535
536WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
537WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
538WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
539
540WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
541WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
542WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
543
544SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
545 5, 12, 0, st_tlv),
546SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
547 0, 12, 0, st_tlv),
548SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
549 5, 12, 0, st_tlv),
550SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
551 0, 12, 0, st_tlv),
552SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
553SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
554
146fd574
UK		 555SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
556SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
557
558SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
559SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
560
561SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
562SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
563
154b26aa
MB		 564SOC_ENUM("ADC OSR", adc_osr),
565SOC_ENUM("DAC OSR", dac_osr),
566
9e6e96a1
MB		 567SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
568 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
569SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
570 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
571
572SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
573 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
574SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
575 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
576
577SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
578 6, 1, 1, wm_hubs_spkmix_tlv),
579SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
580 2, 1, 1, wm_hubs_spkmix_tlv),
581
582SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
583 6, 1, 1, wm_hubs_spkmix_tlv),
584SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
585 2, 1, 1, wm_hubs_spkmix_tlv),
586
587SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
588 10, 15, 0, wm8994_3d_tlv),
458350b3 589SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
9e6e96a1
MB		 590 8, 1, 0),
591SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
592 10, 15, 0, wm8994_3d_tlv),
593SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
594 8, 1, 0),
458350b3 595SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1 596 10, 15, 0, wm8994_3d_tlv),
458350b3 597SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1
MB		 598 8, 1, 0),
599};
600
601static const struct snd_kcontrol_new wm8994_eq_controls[] = {
602SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
603 eq_tlv),
604SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
605 eq_tlv),
606SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
607 eq_tlv),
608SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
609 eq_tlv),
610SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
611 eq_tlv),
612
613SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
614 eq_tlv),
615SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
616 eq_tlv),
617SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
618 eq_tlv),
619SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
620 eq_tlv),
621SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
622 eq_tlv),
623
624SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
625 eq_tlv),
626SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
627 eq_tlv),
628SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
629 eq_tlv),
630SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
631 eq_tlv),
632SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
633 eq_tlv),
634};
635
1ddc07d0
MB		 636static const char *wm8958_ng_text[] = {
637 "30ms", "125ms", "250ms", "500ms",
638};
639
640static const struct soc_enum wm8958_aif1dac1_ng_hold =
641 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
642 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
643
644static const struct soc_enum wm8958_aif1dac2_ng_hold =
645 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
646 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
647
648static const struct soc_enum wm8958_aif2dac_ng_hold =
649 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
650 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
651
c4431df0
MB		 652static const struct snd_kcontrol_new wm8958_snd_controls[] = {
653SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
1ddc07d0
MB		 654
655SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
656 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
657SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
658SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
659 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
660 7, 1, ng_tlv),
661
662SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
663 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
664SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
665SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
666 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
667 7, 1, ng_tlv),
668
669SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
670 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
671SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
672SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
673 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
674 7, 1, ng_tlv),
c4431df0
MB		 675};
676
81204c84
MB		 677static const struct snd_kcontrol_new wm1811_snd_controls[] = {
678SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
679 mixin_boost_tlv),
680SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
681 mixin_boost_tlv),
682};
683
af6b6fe4
MB		 684/* We run all mode setting through a function to enforce audio mode */
685static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
686{
687 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
688
689 if (wm8994->active_refcount)
690 mode = WM1811_JACKDET_MODE_AUDIO;
691
692 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
693 WM1811_JACKDET_MODE_MASK, mode);
694
695 if (mode == WM1811_JACKDET_MODE_MIC)
696 msleep(2);
697}
698
699static void active_reference(struct snd_soc_codec *codec)
700{
701 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
702
703 mutex_lock(&wm8994->accdet_lock);
704
705 wm8994->active_refcount++;
706
707 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
708 wm8994->active_refcount);
709
710 if (wm8994->active_refcount == 1) {
711 /* If we're using jack detection go into audio mode */
712 if (wm8994->jackdet && wm8994->jack_cb) {
713 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
714 WM1811_JACKDET_MODE_MASK,
715 WM1811_JACKDET_MODE_AUDIO);
716 msleep(2);
717 }
718 }
719
720 mutex_unlock(&wm8994->accdet_lock);
721}
722
723static void active_dereference(struct snd_soc_codec *codec)
724{
725 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
726 u16 mode;
727
728 mutex_lock(&wm8994->accdet_lock);
729
730 wm8994->active_refcount--;
731
732 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
733 wm8994->active_refcount);
734
735 if (wm8994->active_refcount == 0) {
736 /* Go into appropriate detection only mode */
737 if (wm8994->jackdet && wm8994->jack_cb) {
738 if (wm8994->jack_mic || wm8994->mic_detecting)
739 mode = WM1811_JACKDET_MODE_MIC;
740 else
741 mode = WM1811_JACKDET_MODE_JACK;
742
743 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
744 WM1811_JACKDET_MODE_MASK,
745 mode);
746 }
747 }
748
749 mutex_unlock(&wm8994->accdet_lock);
750}
751
9e6e96a1
MB		 752static int clk_sys_event(struct snd_soc_dapm_widget *w,
753 struct snd_kcontrol *kcontrol, int event)
754{
755 struct snd_soc_codec *codec = w->codec;
756
757 switch (event) {
758 case SND_SOC_DAPM_PRE_PMU:
759 return configure_clock(codec);
760
761 case SND_SOC_DAPM_POST_PMD:
762 configure_clock(codec);
763 break;
764 }
765
766 return 0;
767}
768
4b7ed83a
MB		 769static void vmid_reference(struct snd_soc_codec *codec)
770{
771 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
772
db966f8a
MB		 773 pm_runtime_get_sync(codec->dev);
774
4b7ed83a
MB		 775 wm8994->vmid_refcount++;
776
777 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
778 wm8994->vmid_refcount);
779
780 if (wm8994->vmid_refcount == 1) {
cc6d5a8c
MB		 781 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
782 WM8994_LINEOUT_VMID_BUF_ENA |
783 WM8994_LINEOUT1_DISCH |
784 WM8994_LINEOUT2_DISCH,
785 WM8994_LINEOUT_VMID_BUF_ENA);
786
4b7ed83a
MB		 787 /* Startup bias, VMID ramp & buffer */
788 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
cc6d5a8c
MB		 789 WM8994_BIAS_SRC |
790 WM8994_VMID_DISCH |
4b7ed83a
MB		 791 WM8994_STARTUP_BIAS_ENA |
792 WM8994_VMID_BUF_ENA |
793 WM8994_VMID_RAMP_MASK,
cc6d5a8c 794 WM8994_BIAS_SRC |
4b7ed83a
MB		 795 WM8994_STARTUP_BIAS_ENA |
796 WM8994_VMID_BUF_ENA |
f647e152 797 (0x3 << WM8994_VMID_RAMP_SHIFT));
4b7ed83a 798
5f2f3890
MB		 799 wm_hubs_vmid_ena(codec);
800
4b7ed83a
MB		 801 /* Main bias enable, VMID=2x40k */
802 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
803 WM8994_BIAS_ENA |
804 WM8994_VMID_SEL_MASK,
805 WM8994_BIAS_ENA | 0x2);
806
cc6d5a8c
MB		 807 msleep(50);
808
809 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
810 WM8994_VMID_RAMP_MASK | WM8994_BIAS_SRC,
811 0);
4b7ed83a
MB		 812 }
813}
814
815static void vmid_dereference(struct snd_soc_codec *codec)
816{
817 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
818
819 wm8994->vmid_refcount--;
820
821 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
822 wm8994->vmid_refcount);
823
824 if (wm8994->vmid_refcount == 0) {
825 /* Switch over to startup biases */
826 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
827 WM8994_BIAS_SRC |
828 WM8994_STARTUP_BIAS_ENA |
829 WM8994_VMID_BUF_ENA |
830 WM8994_VMID_RAMP_MASK,
831 WM8994_BIAS_SRC |
832 WM8994_STARTUP_BIAS_ENA |
833 WM8994_VMID_BUF_ENA |
834 (1 << WM8994_VMID_RAMP_SHIFT));
835
836 /* Disable main biases */
837 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
838 WM8994_BIAS_ENA |
839 WM8994_VMID_SEL_MASK, 0);
840
841 /* Discharge line */
842 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
843 WM8994_LINEOUT1_DISCH |
844 WM8994_LINEOUT2_DISCH,
845 WM8994_LINEOUT1_DISCH |
846 WM8994_LINEOUT2_DISCH);
847
848 msleep(5);
849
850 /* Switch off startup biases */
851 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
852 WM8994_BIAS_SRC |
853 WM8994_STARTUP_BIAS_ENA |
854 WM8994_VMID_BUF_ENA |
855 WM8994_VMID_RAMP_MASK, 0);
856 }
db966f8a
MB		 857
858 pm_runtime_put(codec->dev);
4b7ed83a
MB		 859}
860
861static int vmid_event(struct snd_soc_dapm_widget *w,
862 struct snd_kcontrol *kcontrol, int event)
863{
864 struct snd_soc_codec *codec = w->codec;
865
866 switch (event) {
867 case SND_SOC_DAPM_PRE_PMU:
868 vmid_reference(codec);
869 break;
870
871 case SND_SOC_DAPM_POST_PMD:
872 vmid_dereference(codec);
873 break;
874 }
875
876 return 0;
877}
878
9e6e96a1
MB		 879static void wm8994_update_class_w(struct snd_soc_codec *codec)
880{
fec6dd83 881 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 882 int enable = 1;
883 int source = 0; /* GCC flow analysis can't track enable */
884 int reg, reg_r;
885
886 /* Only support direct DAC->headphone paths */
887 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
888 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
ee839a21 889 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
9e6e96a1
MB		 890 enable = 0;
891 }
892
893 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
894 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
ee839a21 895 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
9e6e96a1
MB		 896 enable = 0;
897 }
898
899 /* We also need the same setting for L/R and only one path */
900 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
901 switch (reg) {
902 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 903 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 904 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
905 break;
906 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 907 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 908 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
909 break;
910 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 911 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 912 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
913 break;
914 default:
ee839a21 915 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
9e6e96a1
MB		 916 enable = 0;
917 break;
918 }
919
920 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
921 if (reg_r != reg) {
ee839a21 922 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
9e6e96a1
MB		 923 enable = 0;
924 }
925
926 if (enable) {
927 dev_dbg(codec->dev, "Class W enabled\n");
928 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
929 WM8994_CP_DYN_PWR |
930 WM8994_CP_DYN_SRC_SEL_MASK,
931 source | WM8994_CP_DYN_PWR);
fec6dd83 932 wm8994->hubs.class_w = true;
9e6e96a1
MB		 933
934 } else {
935 dev_dbg(codec->dev, "Class W disabled\n");
936 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
937 WM8994_CP_DYN_PWR, 0);
fec6dd83 938 wm8994->hubs.class_w = false;
9e6e96a1
MB		 939 }
940}
941
173efa09
DP		 942static int late_enable_ev(struct snd_soc_dapm_widget *w,
943 struct snd_kcontrol *kcontrol, int event)
944{
945 struct snd_soc_codec *codec = w->codec;
946 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
947
948 switch (event) {
949 case SND_SOC_DAPM_PRE_PMU:
a3cff81a 950 if (wm8994->aif1clk_enable) {
173efa09
DP		 951 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
952 WM8994_AIF1CLK_ENA_MASK,
953 WM8994_AIF1CLK_ENA);
a3cff81a
DP		 954 wm8994->aif1clk_enable = 0;
955 }
956 if (wm8994->aif2clk_enable) {
173efa09
DP		 957 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
958 WM8994_AIF2CLK_ENA_MASK,
959 WM8994_AIF2CLK_ENA);
a3cff81a
DP		 960 wm8994->aif2clk_enable = 0;
961 }
173efa09
DP		 962 break;
963 }
964
c6b7b570
MB		 965 /* We may also have postponed startup of DSP, handle that. */
966 wm8958_aif_ev(w, kcontrol, event);
967
173efa09
DP		 968 return 0;
969}
970
971static int late_disable_ev(struct snd_soc_dapm_widget *w,
972 struct snd_kcontrol *kcontrol, int event)
973{
974 struct snd_soc_codec *codec = w->codec;
975 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
976
977 switch (event) {
978 case SND_SOC_DAPM_POST_PMD:
a3cff81a 979 if (wm8994->aif1clk_disable) {
173efa09
DP		 980 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
981 WM8994_AIF1CLK_ENA_MASK, 0);
a3cff81a 982 wm8994->aif1clk_disable = 0;
173efa09 983 }
a3cff81a 984 if (wm8994->aif2clk_disable) {
173efa09
DP		 985 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
986 WM8994_AIF2CLK_ENA_MASK, 0);
a3cff81a 987 wm8994->aif2clk_disable = 0;
173efa09
DP		 988 }
989 break;
990 }
991
992 return 0;
993}
994
995static int aif1clk_ev(struct snd_soc_dapm_widget *w,
996 struct snd_kcontrol *kcontrol, int event)
997{
998 struct snd_soc_codec *codec = w->codec;
999 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1000
1001 switch (event) {
1002 case SND_SOC_DAPM_PRE_PMU:
1003 wm8994->aif1clk_enable = 1;
1004 break;
a3cff81a
DP		 1005 case SND_SOC_DAPM_POST_PMD:
1006 wm8994->aif1clk_disable = 1;
1007 break;
173efa09
DP		 1008 }
1009
1010 return 0;
1011}
1012
1013static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1014 struct snd_kcontrol *kcontrol, int event)
1015{
1016 struct snd_soc_codec *codec = w->codec;
1017 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1018
1019 switch (event) {
1020 case SND_SOC_DAPM_PRE_PMU:
1021 wm8994->aif2clk_enable = 1;
1022 break;
a3cff81a
DP		 1023 case SND_SOC_DAPM_POST_PMD:
1024 wm8994->aif2clk_disable = 1;
1025 break;
173efa09
DP		 1026 }
1027
1028 return 0;
1029}
1030
04d28681
DP		 1031static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1032 struct snd_kcontrol *kcontrol, int event)
1033{
1034 late_enable_ev(w, kcontrol, event);
1035 return 0;
1036}
1037
b462c6e6
DP		 1038static int micbias_ev(struct snd_soc_dapm_widget *w,
1039 struct snd_kcontrol *kcontrol, int event)
1040{
1041 late_enable_ev(w, kcontrol, event);
1042 return 0;
1043}
1044
c52fd021
DP		 1045static int dac_ev(struct snd_soc_dapm_widget *w,
1046 struct snd_kcontrol *kcontrol, int event)
1047{
1048 struct snd_soc_codec *codec = w->codec;
1049 unsigned int mask = 1 << w->shift;
1050
1051 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1052 mask, mask);
1053 return 0;
1054}
1055
9e6e96a1
MB		 1056static const char *hp_mux_text[] = {
1057 "Mixer",
1058 "DAC",
1059};
1060
1061#define WM8994_HP_ENUM(xname, xenum) \
1062{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1063 .info = snd_soc_info_enum_double, \
1064 .get = snd_soc_dapm_get_enum_double, \
1065 .put = wm8994_put_hp_enum, \
1066 .private_value = (unsigned long)&xenum }
1067
1068static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1069 struct snd_ctl_elem_value *ucontrol)
1070{
9d03545d
JN		 1071 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1072 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1073 struct snd_soc_codec *codec = w->codec;
1074 int ret;
1075
1076 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1077
1078 wm8994_update_class_w(codec);
1079
1080 return ret;
1081}
1082
1083static const struct soc_enum hpl_enum =
1084 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1085
1086static const struct snd_kcontrol_new hpl_mux =
1087 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1088
1089static const struct soc_enum hpr_enum =
1090 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1091
1092static const struct snd_kcontrol_new hpr_mux =
1093 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1094
1095static const char *adc_mux_text[] = {
1096 "ADC",
1097 "DMIC",
1098};
1099
1100static const struct soc_enum adc_enum =
1101 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1102
1103static const struct snd_kcontrol_new adcl_mux =
1104 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1105
1106static const struct snd_kcontrol_new adcr_mux =
1107 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1108
1109static const struct snd_kcontrol_new left_speaker_mixer[] = {
1110SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1111SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1112SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1113SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1114SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1115};
1116
1117static const struct snd_kcontrol_new right_speaker_mixer[] = {
1118SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1119SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1120SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1121SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1122SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1123};
1124
1125/* Debugging; dump chip status after DAPM transitions */
1126static int post_ev(struct snd_soc_dapm_widget *w,
1127 struct snd_kcontrol *kcontrol, int event)
1128{
1129 struct snd_soc_codec *codec = w->codec;
1130 dev_dbg(codec->dev, "SRC status: %x\n",
1131 snd_soc_read(codec,
1132 WM8994_RATE_STATUS));
1133 return 0;
1134}
1135
1136static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1137SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1138 1, 1, 0),
1139SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1140 0, 1, 0),
1141};
1142
1143static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1144SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1145 1, 1, 0),
1146SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1147 0, 1, 0),
1148};
1149
a3257ba8
MB		 1150static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1151SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1152 1, 1, 0),
1153SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1154 0, 1, 0),
1155};
1156
1157static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1158SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1159 1, 1, 0),
1160SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1161 0, 1, 0),
1162};
1163
9e6e96a1
MB		 1164static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1165SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1166 5, 1, 0),
1167SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1168 4, 1, 0),
1169SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1170 2, 1, 0),
1171SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1172 1, 1, 0),
1173SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1174 0, 1, 0),
1175};
1176
1177static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1178SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1179 5, 1, 0),
1180SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1181 4, 1, 0),
1182SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1183 2, 1, 0),
1184SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1185 1, 1, 0),
1186SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1187 0, 1, 0),
1188};
1189
1190#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1191{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1192 .info = snd_soc_info_volsw, \
1193 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1194 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1195
1196static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1197 struct snd_ctl_elem_value *ucontrol)
1198{
9d03545d
JN		 1199 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1200 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1201 struct snd_soc_codec *codec = w->codec;
1202 int ret;
1203
1204 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1205
1206 wm8994_update_class_w(codec);
1207
1208 return ret;
1209}
1210
1211static const struct snd_kcontrol_new dac1l_mix[] = {
1212WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1213 5, 1, 0),
1214WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1215 4, 1, 0),
1216WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1217 2, 1, 0),
1218WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1219 1, 1, 0),
1220WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1221 0, 1, 0),
1222};
1223
1224static const struct snd_kcontrol_new dac1r_mix[] = {
1225WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1226 5, 1, 0),
1227WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1228 4, 1, 0),
1229WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1230 2, 1, 0),
1231WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1232 1, 1, 0),
1233WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1234 0, 1, 0),
1235};
1236
1237static const char *sidetone_text[] = {
1238 "ADC/DMIC1", "DMIC2",
1239};
1240
1241static const struct soc_enum sidetone1_enum =
1242 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1243
1244static const struct snd_kcontrol_new sidetone1_mux =
1245 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1246
1247static const struct soc_enum sidetone2_enum =
1248 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1249
1250static const struct snd_kcontrol_new sidetone2_mux =
1251 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1252
1253static const char *aif1dac_text[] = {
1254 "AIF1DACDAT", "AIF3DACDAT",
1255};
1256
1257static const struct soc_enum aif1dac_enum =
1258 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1259
1260static const struct snd_kcontrol_new aif1dac_mux =
1261 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1262
1263static const char *aif2dac_text[] = {
1264 "AIF2DACDAT", "AIF3DACDAT",
1265};
1266
1267static const struct soc_enum aif2dac_enum =
1268 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1269
1270static const struct snd_kcontrol_new aif2dac_mux =
1271 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1272
1273static const char *aif2adc_text[] = {
1274 "AIF2ADCDAT", "AIF3DACDAT",
1275};
1276
1277static const struct soc_enum aif2adc_enum =
1278 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1279
1280static const struct snd_kcontrol_new aif2adc_mux =
1281 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1282
1283static const char *aif3adc_text[] = {
c4431df0 1284 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB		 1285};
1286
c4431df0 1287static const struct soc_enum wm8994_aif3adc_enum =
9e6e96a1
MB		 1288 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1289
c4431df0
MB		 1290static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1291 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1292
1293static const struct soc_enum wm8958_aif3adc_enum =
1294 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1295
1296static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1297 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1298
1299static const char *mono_pcm_out_text[] = {
1300 "None", "AIF2ADCL", "AIF2ADCR",
1301};
1302
1303static const struct soc_enum mono_pcm_out_enum =
1304 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1305
1306static const struct snd_kcontrol_new mono_pcm_out_mux =
1307 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1308
1309static const char *aif2dac_src_text[] = {
1310 "AIF2", "AIF3",
1311};
1312
1313/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1314static const struct soc_enum aif2dacl_src_enum =
1315 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1316
1317static const struct snd_kcontrol_new aif2dacl_src_mux =
1318 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1319
1320static const struct soc_enum aif2dacr_src_enum =
1321 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1322
1323static const struct snd_kcontrol_new aif2dacr_src_mux =
1324 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1 1325
173efa09
DP		 1326static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1327SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1328 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1329SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1330 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1331
1332SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1333 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1334SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1335 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1336SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1337 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1338SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1339 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
b70a51ba
MB		 1340SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1341 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1342
1343SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1344 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1345 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1346SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1347 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1348 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1349SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1350 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1351SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1352 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
173efa09
DP		 1353
1354SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1355};
1356
1357static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1358SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
b70a51ba
MB		 1359SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1360SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1361SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1362 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1363SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1364 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1365SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1366SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
173efa09
DP		 1367};
1368
c52fd021
DP		 1369static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1370SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1371 dac_ev, SND_SOC_DAPM_PRE_PMU),
1372SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1373 dac_ev, SND_SOC_DAPM_PRE_PMU),
1374SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1375 dac_ev, SND_SOC_DAPM_PRE_PMU),
1376SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1377 dac_ev, SND_SOC_DAPM_PRE_PMU),
1378};
1379
1380static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1381SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
0627bd25 1382SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
c52fd021
DP		 1383SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1384SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1385};
1386
04d28681 1387static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
87b86ade
MB		 1388SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1389 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1390SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1391 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
04d28681
DP		 1392};
1393
1394static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
87b86ade
MB		 1395SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1396SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
04d28681
DP		 1397};
1398
9e6e96a1
MB		 1399static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1400SND_SOC_DAPM_INPUT("DMIC1DAT"),
1401SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1402SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1 1403
b462c6e6
DP		 1404SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1405 SND_SOC_DAPM_PRE_PMU),
4b7ed83a
MB		 1406SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1407 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
b462c6e6 1408
9e6e96a1
MB		 1409SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1410 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1411
1412SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1413SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1414SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1415
7f94de48 1416SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
9e6e96a1 1417 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
7f94de48 1418SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
9e6e96a1 1419 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
d6addcc9
MB		 1420SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1421 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
b2822a8c 1422 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1423SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1424 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
b2822a8c 1425 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1 1426
7f94de48 1427SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
9e6e96a1 1428 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
7f94de48 1429SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
9e6e96a1 1430 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
d6addcc9
MB		 1431SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1432 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
b2822a8c 1433 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1434SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1435 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
b2822a8c 1436 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1
MB		 1437
1438SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1439 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1440SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1441 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1442
a3257ba8
MB		 1443SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1444 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1445SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1446 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1447
9e6e96a1
MB		 1448SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1449 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1450SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1451 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1452
1453SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1454SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1455
1456SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1457 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1458SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1459 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1460
1461SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1462 WM8994_POWER_MANAGEMENT_4, 13, 0),
1463SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1464 WM8994_POWER_MANAGEMENT_4, 12, 0),
d6addcc9
MB		 1465SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1466 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1467 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1468SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1469 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1470 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1
MB		 1471
1472SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1473SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
7f94de48 1474SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1475SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1476
1477SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1478SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1479SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1
MB		 1480
1481SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
35024f49 1482SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1483
1484SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1485
1486SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1487SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1488SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1489SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1490
1491/* Power is done with the muxes since the ADC power also controls the
1492 * downsampling chain, the chip will automatically manage the analogue
1493 * specific portions.
1494 */
1495SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1496SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1497
9e6e96a1
MB		 1498SND_SOC_DAPM_POST("Debug log", post_ev),
1499};
1500
c4431df0
MB		 1501static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1502SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1503};
9e6e96a1 1504
c4431df0
MB		 1505static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1506SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1507SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1508SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1509SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1510};
1511
1512static const struct snd_soc_dapm_route intercon[] = {
9e6e96a1
MB		 1513 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1514 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1515
1516 { "DSP1CLK", NULL, "CLK_SYS" },
1517 { "DSP2CLK", NULL, "CLK_SYS" },
1518 { "DSPINTCLK", NULL, "CLK_SYS" },
1519
1520 { "AIF1ADC1L", NULL, "AIF1CLK" },
1521 { "AIF1ADC1L", NULL, "DSP1CLK" },
1522 { "AIF1ADC1R", NULL, "AIF1CLK" },
1523 { "AIF1ADC1R", NULL, "DSP1CLK" },
1524 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1525
1526 { "AIF1DAC1L", NULL, "AIF1CLK" },
1527 { "AIF1DAC1L", NULL, "DSP1CLK" },
1528 { "AIF1DAC1R", NULL, "AIF1CLK" },
1529 { "AIF1DAC1R", NULL, "DSP1CLK" },
1530 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1531
1532 { "AIF1ADC2L", NULL, "AIF1CLK" },
1533 { "AIF1ADC2L", NULL, "DSP1CLK" },
1534 { "AIF1ADC2R", NULL, "AIF1CLK" },
1535 { "AIF1ADC2R", NULL, "DSP1CLK" },
1536 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1537
1538 { "AIF1DAC2L", NULL, "AIF1CLK" },
1539 { "AIF1DAC2L", NULL, "DSP1CLK" },
1540 { "AIF1DAC2R", NULL, "AIF1CLK" },
1541 { "AIF1DAC2R", NULL, "DSP1CLK" },
1542 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1543
1544 { "AIF2ADCL", NULL, "AIF2CLK" },
1545 { "AIF2ADCL", NULL, "DSP2CLK" },
1546 { "AIF2ADCR", NULL, "AIF2CLK" },
1547 { "AIF2ADCR", NULL, "DSP2CLK" },
1548 { "AIF2ADCR", NULL, "DSPINTCLK" },
1549
1550 { "AIF2DACL", NULL, "AIF2CLK" },
1551 { "AIF2DACL", NULL, "DSP2CLK" },
1552 { "AIF2DACR", NULL, "AIF2CLK" },
1553 { "AIF2DACR", NULL, "DSP2CLK" },
1554 { "AIF2DACR", NULL, "DSPINTCLK" },
1555
1556 { "DMIC1L", NULL, "DMIC1DAT" },
1557 { "DMIC1L", NULL, "CLK_SYS" },
1558 { "DMIC1R", NULL, "DMIC1DAT" },
1559 { "DMIC1R", NULL, "CLK_SYS" },
1560 { "DMIC2L", NULL, "DMIC2DAT" },
1561 { "DMIC2L", NULL, "CLK_SYS" },
1562 { "DMIC2R", NULL, "DMIC2DAT" },
1563 { "DMIC2R", NULL, "CLK_SYS" },
1564
1565 { "ADCL", NULL, "AIF1CLK" },
1566 { "ADCL", NULL, "DSP1CLK" },
1567 { "ADCL", NULL, "DSPINTCLK" },
1568
1569 { "ADCR", NULL, "AIF1CLK" },
1570 { "ADCR", NULL, "DSP1CLK" },
1571 { "ADCR", NULL, "DSPINTCLK" },
1572
1573 { "ADCL Mux", "ADC", "ADCL" },
1574 { "ADCL Mux", "DMIC", "DMIC1L" },
1575 { "ADCR Mux", "ADC", "ADCR" },
1576 { "ADCR Mux", "DMIC", "DMIC1R" },
1577
1578 { "DAC1L", NULL, "AIF1CLK" },
1579 { "DAC1L", NULL, "DSP1CLK" },
1580 { "DAC1L", NULL, "DSPINTCLK" },
1581
1582 { "DAC1R", NULL, "AIF1CLK" },
1583 { "DAC1R", NULL, "DSP1CLK" },
1584 { "DAC1R", NULL, "DSPINTCLK" },
1585
1586 { "DAC2L", NULL, "AIF2CLK" },
1587 { "DAC2L", NULL, "DSP2CLK" },
1588 { "DAC2L", NULL, "DSPINTCLK" },
1589
1590 { "DAC2R", NULL, "AIF2DACR" },
1591 { "DAC2R", NULL, "AIF2CLK" },
1592 { "DAC2R", NULL, "DSP2CLK" },
1593 { "DAC2R", NULL, "DSPINTCLK" },
1594
1595 { "TOCLK", NULL, "CLK_SYS" },
1596
1597 /* AIF1 outputs */
1598 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1599 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1600 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1601
1602 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1603 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1604 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1605
a3257ba8
MB		 1606 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1607 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1608 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1609
1610 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1611 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1612 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1613
9e6e96a1
MB		 1614 /* Pin level routing for AIF3 */
1615 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1616 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1617 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1618 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1619
9e6e96a1
MB		 1620 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1621 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1622 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1623 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1624 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1625 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1626 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1627
1628 /* DAC1 inputs */
9e6e96a1
MB		 1629 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1630 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1631 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1632 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1633 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1634
9e6e96a1
MB		 1635 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1636 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1637 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1638 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1639 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1640
1641 /* DAC2/AIF2 outputs */
1642 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
9e6e96a1
MB		 1643 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1644 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1645 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1646 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1647 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1648
1649 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
9e6e96a1
MB		 1650 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1651 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1652 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1653 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1654 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1655
7f94de48
MB		 1656 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1657 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1658 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1659 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1660
9e6e96a1
MB		 1661 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1662
1663 /* AIF3 output */
1664 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1665 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1666 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1667 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1668 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1669 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1670 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1671 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1672
1673 /* Sidetone */
1674 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1675 { "Left Sidetone", "DMIC2", "DMIC2L" },
1676 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1677 { "Right Sidetone", "DMIC2", "DMIC2R" },
1678
1679 /* Output stages */
1680 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1681 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1682
1683 { "SPKL", "DAC1 Switch", "DAC1L" },
1684 { "SPKL", "DAC2 Switch", "DAC2L" },
1685
1686 { "SPKR", "DAC1 Switch", "DAC1R" },
1687 { "SPKR", "DAC2 Switch", "DAC2R" },
1688
1689 { "Left Headphone Mux", "DAC", "DAC1L" },
1690 { "Right Headphone Mux", "DAC", "DAC1R" },
1691};
1692
173efa09
DP		 1693static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1694 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1695 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1696 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1697 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1698 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1699 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1700 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1701 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1702};
1703
1704static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1705 { "DAC1L", NULL, "DAC1L Mixer" },
1706 { "DAC1R", NULL, "DAC1R Mixer" },
1707 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1708 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1709};
1710
6ed8f148
MB		 1711static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1712 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1713 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1714 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1715 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
b793eb60
MB		 1716 { "MICBIAS1", NULL, "CLK_SYS" },
1717 { "MICBIAS1", NULL, "MICBIAS Supply" },
1718 { "MICBIAS2", NULL, "CLK_SYS" },
1719 { "MICBIAS2", NULL, "MICBIAS Supply" },
6ed8f148
MB		 1720};
1721
c4431df0
MB		 1722static const struct snd_soc_dapm_route wm8994_intercon[] = {
1723 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1724 { "AIF2DACR", NULL, "AIF2DAC Mux" },
4e04adaf
MB		 1725 { "MICBIAS1", NULL, "VMID" },
1726 { "MICBIAS2", NULL, "VMID" },
c4431df0
MB		 1727};
1728
1729static const struct snd_soc_dapm_route wm8958_intercon[] = {
1730 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1731 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1732
1733 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1734 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1735 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1736 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1737
1738 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1739 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1740
1741 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1742};
1743
9e6e96a1
MB		 1744/* The size in bits of the FLL divide multiplied by 10
1745 * to allow rounding later */
1746#define FIXED_FLL_SIZE ((1 << 16) * 10)
1747
1748struct fll_div {
1749 u16 outdiv;
1750 u16 n;
1751 u16 k;
1752 u16 clk_ref_div;
1753 u16 fll_fratio;
1754};
1755
1756static int wm8994_get_fll_config(struct fll_div *fll,
1757 int freq_in, int freq_out)
1758{
1759 u64 Kpart;
1760 unsigned int K, Ndiv, Nmod;
1761
1762 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1763
1764 /* Scale the input frequency down to <= 13.5MHz */
1765 fll->clk_ref_div = 0;
1766 while (freq_in > 13500000) {
1767 fll->clk_ref_div++;
1768 freq_in /= 2;
1769
1770 if (fll->clk_ref_div > 3)
1771 return -EINVAL;
1772 }
1773 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1774
1775 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1776 fll->outdiv = 3;
1777 while (freq_out * (fll->outdiv + 1) < 90000000) {
1778 fll->outdiv++;
1779 if (fll->outdiv > 63)
1780 return -EINVAL;
1781 }
1782 freq_out *= fll->outdiv + 1;
1783 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1784
1785 if (freq_in > 1000000) {
1786 fll->fll_fratio = 0;
7d48a6ac
MB		 1787 } else if (freq_in > 256000) {
1788 fll->fll_fratio = 1;
1789 freq_in *= 2;
1790 } else if (freq_in > 128000) {
1791 fll->fll_fratio = 2;
1792 freq_in *= 4;
1793 } else if (freq_in > 64000) {
9e6e96a1
MB		 1794 fll->fll_fratio = 3;
1795 freq_in *= 8;
7d48a6ac
MB		 1796 } else {
1797 fll->fll_fratio = 4;
1798 freq_in *= 16;
9e6e96a1
MB		 1799 }
1800 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1801
1802 /* Now, calculate N.K */
1803 Ndiv = freq_out / freq_in;
1804
1805 fll->n = Ndiv;
1806 Nmod = freq_out % freq_in;
1807 pr_debug("Nmod=%d\n", Nmod);
1808
1809 /* Calculate fractional part - scale up so we can round. */
1810 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1811
1812 do_div(Kpart, freq_in);
1813
1814 K = Kpart & 0xFFFFFFFF;
1815
1816 if ((K % 10) >= 5)
1817 K += 5;
1818
1819 /* Move down to proper range now rounding is done */
1820 fll->k = K / 10;
1821
1822 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1823
1824 return 0;
1825}
1826
f0fba2ad 1827static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 1828 unsigned int freq_in, unsigned int freq_out)
1829{
b2c812e2 1830 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 1831 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 1832 int reg_offset, ret;
1833 struct fll_div fll;
1834 u16 reg, aif1, aif2;
c7ebf932 1835 unsigned long timeout;
4b7ed83a 1836 bool was_enabled;
9e6e96a1
MB		 1837
1838 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1839 & WM8994_AIF1CLK_ENA;
1840
1841 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1842 & WM8994_AIF2CLK_ENA;
1843
1844 switch (id) {
1845 case WM8994_FLL1:
1846 reg_offset = 0;
1847 id = 0;
1848 break;
1849 case WM8994_FLL2:
1850 reg_offset = 0x20;
1851 id = 1;
1852 break;
1853 default:
1854 return -EINVAL;
1855 }
1856
4b7ed83a
MB		 1857 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
1858 was_enabled = reg & WM8994_FLL1_ENA;
1859
136ff2a2 1860 switch (src) {
7add84aa
MB		 1861 case 0:
1862 /* Allow no source specification when stopping */
1863 if (freq_out)
1864 return -EINVAL;
4514e899 1865 src = wm8994->fll[id].src;
7add84aa 1866 break;
136ff2a2
MB		 1867 case WM8994_FLL_SRC_MCLK1:
1868 case WM8994_FLL_SRC_MCLK2:
1869 case WM8994_FLL_SRC_LRCLK:
1870 case WM8994_FLL_SRC_BCLK:
1871 break;
1872 default:
1873 return -EINVAL;
1874 }
1875
9e6e96a1
MB		 1876 /* Are we changing anything? */
1877 if (wm8994->fll[id].src == src &&
1878 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1879 return 0;
1880
1881 /* If we're stopping the FLL redo the old config - no
1882 * registers will actually be written but we avoid GCC flow
1883 * analysis bugs spewing warnings.
1884 */
1885 if (freq_out)
1886 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1887 else
1888 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1889 wm8994->fll[id].out);
1890 if (ret < 0)
1891 return ret;
1892
1893 /* Gate the AIF clocks while we reclock */
1894 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1895 WM8994_AIF1CLK_ENA, 0);
1896 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1897 WM8994_AIF2CLK_ENA, 0);
1898
1899 /* We always need to disable the FLL while reconfiguring */
1900 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1901 WM8994_FLL1_ENA, 0);
1902
1903 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1904 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1905 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1906 WM8994_FLL1_OUTDIV_MASK |
1907 WM8994_FLL1_FRATIO_MASK, reg);
1908
1909 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1910
1911 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1912 WM8994_FLL1_N_MASK,
1913 fll.n << WM8994_FLL1_N_SHIFT);
1914
1915 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
136ff2a2
MB		 1916 WM8994_FLL1_REFCLK_DIV_MASK |
1917 WM8994_FLL1_REFCLK_SRC_MASK,
1918 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1919 (src - 1));
9e6e96a1 1920
f0f5039c
MB		 1921 /* Clear any pending completion from a previous failure */
1922 try_wait_for_completion(&wm8994->fll_locked[id]);
1923
9e6e96a1
MB		 1924 /* Enable (with fractional mode if required) */
1925 if (freq_out) {
4b7ed83a
MB		 1926 /* Enable VMID if we need it */
1927 if (!was_enabled) {
af6b6fe4
MB		 1928 active_reference(codec);
1929
4b7ed83a
MB		 1930 switch (control->type) {
1931 case WM8994:
1932 vmid_reference(codec);
1933 break;
1934 case WM8958:
1935 if (wm8994->revision < 1)
1936 vmid_reference(codec);
1937 break;
1938 default:
1939 break;
1940 }
1941 }
1942
9e6e96a1
MB		 1943 if (fll.k)
1944 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1945 else
1946 reg = WM8994_FLL1_ENA;
1947 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1948 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1949 reg);
8e9ddf81 1950
c7ebf932
MB		 1951 if (wm8994->fll_locked_irq) {
1952 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
1953 msecs_to_jiffies(10));
1954 if (timeout == 0)
1955 dev_warn(codec->dev,
1956 "Timed out waiting for FLL lock\n");
1957 } else {
1958 msleep(5);
1959 }
4b7ed83a
MB		 1960 } else {
1961 if (was_enabled) {
1962 switch (control->type) {
1963 case WM8994:
1964 vmid_dereference(codec);
1965 break;
1966 case WM8958:
1967 if (wm8994->revision < 1)
1968 vmid_dereference(codec);
1969 break;
1970 default:
1971 break;
1972 }
af6b6fe4
MB		 1973
1974 active_dereference(codec);
4b7ed83a 1975 }
9e6e96a1
MB		 1976 }
1977
1978 wm8994->fll[id].in = freq_in;
1979 wm8994->fll[id].out = freq_out;
136ff2a2 1980 wm8994->fll[id].src = src;
9e6e96a1
MB		 1981
1982 /* Enable any gated AIF clocks */
1983 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1984 WM8994_AIF1CLK_ENA, aif1);
1985 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1986 WM8994_AIF2CLK_ENA, aif2);
1987
1988 configure_clock(codec);
1989
1990 return 0;
1991}
1992
c7ebf932
MB		 1993static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
1994{
1995 struct completion *completion = data;
1996
1997 complete(completion);
1998
1999 return IRQ_HANDLED;
2000}
f0fba2ad 2001
66b47fdb
MB		 2002static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2003
f0fba2ad
LG		 2004static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2005 unsigned int freq_in, unsigned int freq_out)
2006{
2007 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2008}
2009
9e6e96a1
MB		 2010static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2011 int clk_id, unsigned int freq, int dir)
2012{
2013 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2014 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 2015 int i;
9e6e96a1
MB		 2016
2017 switch (dai->id) {
2018 case 1:
2019 case 2:
2020 break;
2021
2022 default:
2023 /* AIF3 shares clocking with AIF1/2 */
2024 return -EINVAL;
2025 }
2026
2027 switch (clk_id) {
2028 case WM8994_SYSCLK_MCLK1:
2029 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2030 wm8994->mclk[0] = freq;
2031 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2032 dai->id, freq);
2033 break;
2034
2035 case WM8994_SYSCLK_MCLK2:
2036 /* TODO: Set GPIO AF */
2037 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2038 wm8994->mclk[1] = freq;
2039 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2040 dai->id, freq);
2041 break;
2042
2043 case WM8994_SYSCLK_FLL1:
2044 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2045 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2046 break;
2047
2048 case WM8994_SYSCLK_FLL2:
2049 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2050 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2051 break;
2052
66b47fdb
MB		 2053 case WM8994_SYSCLK_OPCLK:
2054 /* Special case - a division (times 10) is given and
2055 * no effect on main clocking.
2056 */
2057 if (freq) {
2058 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2059 if (opclk_divs[i] == freq)
2060 break;
2061 if (i == ARRAY_SIZE(opclk_divs))
2062 return -EINVAL;
2063 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2064 WM8994_OPCLK_DIV_MASK, i);
2065 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2066 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2067 } else {
2068 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2069 WM8994_OPCLK_ENA, 0);
2070 }
2071
9e6e96a1
MB		 2072 default:
2073 return -EINVAL;
2074 }
2075
2076 configure_clock(codec);
2077
2078 return 0;
2079}
2080
2081static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2082 enum snd_soc_bias_level level)
2083{
b6b05691 2084 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2085 struct wm8994 *control = wm8994->wm8994;
b6b05691 2086
5f2f3890
MB		 2087 wm_hubs_set_bias_level(codec, level);
2088
9e6e96a1
MB		 2089 switch (level) {
2090 case SND_SOC_BIAS_ON:
2091 break;
2092
2093 case SND_SOC_BIAS_PREPARE:
500fa30e
MB		 2094 /* MICBIAS into regulating mode */
2095 switch (control->type) {
2096 case WM8958:
2097 case WM1811:
2098 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2099 WM8958_MICB1_MODE, 0);
2100 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2101 WM8958_MICB2_MODE, 0);
2102 break;
2103 default:
2104 break;
2105 }
af6b6fe4
MB		 2106
2107 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2108 active_reference(codec);
9e6e96a1
MB		 2109 break;
2110
2111 case SND_SOC_BIAS_STANDBY:
ce6120cc 2112 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8bc3c2c2
MB		 2113 switch (control->type) {
2114 case WM8994:
2115 if (wm8994->revision < 4) {
2116 /* Tweak DC servo and DSP
2117 * configuration for improved
2118 * performance. */
2119 snd_soc_write(codec, 0x102, 0x3);
2120 snd_soc_write(codec, 0x56, 0x3);
2121 snd_soc_write(codec, 0x817, 0);
2122 snd_soc_write(codec, 0x102, 0);
2123 }
2124 break;
2125
2126 case WM8958:
2127 if (wm8994->revision == 0) {
2128 /* Optimise performance for rev A */
2129 snd_soc_write(codec, 0x102, 0x3);
2130 snd_soc_write(codec, 0xcb, 0x81);
2131 snd_soc_write(codec, 0x817, 0);
2132 snd_soc_write(codec, 0x102, 0);
2133
2134 snd_soc_update_bits(codec,
2135 WM8958_CHARGE_PUMP_2,
2136 WM8958_CP_DISCH,
2137 WM8958_CP_DISCH);
2138 }
2139 break;
81204c84
MB		 2140
2141 case WM1811:
2142 if (wm8994->revision < 2) {
2143 snd_soc_write(codec, 0x102, 0x3);
2144 snd_soc_write(codec, 0x5d, 0x7e);
2145 snd_soc_write(codec, 0x5e, 0x0);
2146 snd_soc_write(codec, 0x102, 0x0);
2147 }
2148 break;
b6b05691 2149 }
9e6e96a1
MB		 2150
2151 /* Discharge LINEOUT1 & 2 */
2152 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2153 WM8994_LINEOUT1_DISCH |
2154 WM8994_LINEOUT2_DISCH,
2155 WM8994_LINEOUT1_DISCH |
2156 WM8994_LINEOUT2_DISCH);
9e6e96a1
MB		 2157 }
2158
af6b6fe4
MB		 2159 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2160 active_dereference(codec);
2161
500fa30e
MB		 2162 /* MICBIAS into bypass mode on newer devices */
2163 switch (control->type) {
2164 case WM8958:
2165 case WM1811:
2166 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2167 WM8958_MICB1_MODE,
2168 WM8958_MICB1_MODE);
2169 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2170 WM8958_MICB2_MODE,
2171 WM8958_MICB2_MODE);
2172 break;
2173 default:
2174 break;
2175 }
9e6e96a1
MB		 2176 break;
2177
2178 case SND_SOC_BIAS_OFF:
4105ab84 2179 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
fbbf5920 2180 wm8994->cur_fw = NULL;
9e6e96a1
MB		 2181 break;
2182 }
5f2f3890 2183
ce6120cc 2184 codec->dapm.bias_level = level;
af6b6fe4 2185
9e6e96a1
MB		 2186 return 0;
2187}
2188
2189static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2190{
2191 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2192 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2193 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2194 int ms_reg;
2195 int aif1_reg;
2196 int ms = 0;
2197 int aif1 = 0;
2198
2199 switch (dai->id) {
2200 case 1:
2201 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2202 aif1_reg = WM8994_AIF1_CONTROL_1;
2203 break;
2204 case 2:
2205 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2206 aif1_reg = WM8994_AIF2_CONTROL_1;
2207 break;
2208 default:
2209 return -EINVAL;
2210 }
2211
2212 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2213 case SND_SOC_DAIFMT_CBS_CFS:
2214 break;
2215 case SND_SOC_DAIFMT_CBM_CFM:
2216 ms = WM8994_AIF1_MSTR;
2217 break;
2218 default:
2219 return -EINVAL;
2220 }
2221
2222 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2223 case SND_SOC_DAIFMT_DSP_B:
2224 aif1 |= WM8994_AIF1_LRCLK_INV;
2225 case SND_SOC_DAIFMT_DSP_A:
2226 aif1 |= 0x18;
2227 break;
2228 case SND_SOC_DAIFMT_I2S:
2229 aif1 |= 0x10;
2230 break;
2231 case SND_SOC_DAIFMT_RIGHT_J:
2232 break;
2233 case SND_SOC_DAIFMT_LEFT_J:
2234 aif1 |= 0x8;
2235 break;
2236 default:
2237 return -EINVAL;
2238 }
2239
2240 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2241 case SND_SOC_DAIFMT_DSP_A:
2242 case SND_SOC_DAIFMT_DSP_B:
2243 /* frame inversion not valid for DSP modes */
2244 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2245 case SND_SOC_DAIFMT_NB_NF:
2246 break;
2247 case SND_SOC_DAIFMT_IB_NF:
2248 aif1 |= WM8994_AIF1_BCLK_INV;
2249 break;
2250 default:
2251 return -EINVAL;
2252 }
2253 break;
2254
2255 case SND_SOC_DAIFMT_I2S:
2256 case SND_SOC_DAIFMT_RIGHT_J:
2257 case SND_SOC_DAIFMT_LEFT_J:
2258 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2259 case SND_SOC_DAIFMT_NB_NF:
2260 break;
2261 case SND_SOC_DAIFMT_IB_IF:
2262 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2263 break;
2264 case SND_SOC_DAIFMT_IB_NF:
2265 aif1 |= WM8994_AIF1_BCLK_INV;
2266 break;
2267 case SND_SOC_DAIFMT_NB_IF:
2268 aif1 |= WM8994_AIF1_LRCLK_INV;
2269 break;
2270 default:
2271 return -EINVAL;
2272 }
2273 break;
2274 default:
2275 return -EINVAL;
2276 }
2277
c4431df0
MB		 2278 /* The AIF2 format configuration needs to be mirrored to AIF3
2279 * on WM8958 if it's in use so just do it all the time. */
81204c84
MB		 2280 switch (control->type) {
2281 case WM1811:
2282 case WM8958:
2283 if (dai->id == 2)
2284 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2285 WM8994_AIF1_LRCLK_INV |
2286 WM8958_AIF3_FMT_MASK, aif1);
2287 break;
2288
2289 default:
2290 break;
2291 }
c4431df0 2292
9e6e96a1
MB		 2293 snd_soc_update_bits(codec, aif1_reg,
2294 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2295 WM8994_AIF1_FMT_MASK,
2296 aif1);
2297 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2298 ms);
2299
2300 return 0;
2301}
2302
2303static struct {
2304 int val, rate;
2305} srs[] = {
2306 { 0, 8000 },
2307 { 1, 11025 },
2308 { 2, 12000 },
2309 { 3, 16000 },
2310 { 4, 22050 },
2311 { 5, 24000 },
2312 { 6, 32000 },
2313 { 7, 44100 },
2314 { 8, 48000 },
2315 { 9, 88200 },
2316 { 10, 96000 },
2317};
2318
2319static int fs_ratios[] = {
2320 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2321};
2322
2323static int bclk_divs[] = {
2324 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2325 640, 880, 960, 1280, 1760, 1920
2326};
2327
2328static int wm8994_hw_params(struct snd_pcm_substream *substream,
2329 struct snd_pcm_hw_params *params,
2330 struct snd_soc_dai *dai)
2331{
2332 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2333 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1 2334 int aif1_reg;
b1e43d93 2335 int aif2_reg;
9e6e96a1
MB		 2336 int bclk_reg;
2337 int lrclk_reg;
2338 int rate_reg;
2339 int aif1 = 0;
b1e43d93 2340 int aif2 = 0;
9e6e96a1
MB		 2341 int bclk = 0;
2342 int lrclk = 0;
2343 int rate_val = 0;
2344 int id = dai->id - 1;
2345
2346 int i, cur_val, best_val, bclk_rate, best;
2347
2348 switch (dai->id) {
2349 case 1:
2350 aif1_reg = WM8994_AIF1_CONTROL_1;
b1e43d93 2351 aif2_reg = WM8994_AIF1_CONTROL_2;
9e6e96a1
MB		 2352 bclk_reg = WM8994_AIF1_BCLK;
2353 rate_reg = WM8994_AIF1_RATE;
2354 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2355 wm8994->lrclk_shared[0]) {
9e6e96a1 2356 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 2357 } else {
9e6e96a1 2358 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 2359 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2360 }
9e6e96a1
MB		 2361 break;
2362 case 2:
2363 aif1_reg = WM8994_AIF2_CONTROL_1;
b1e43d93 2364 aif2_reg = WM8994_AIF2_CONTROL_2;
9e6e96a1
MB		 2365 bclk_reg = WM8994_AIF2_BCLK;
2366 rate_reg = WM8994_AIF2_RATE;
2367 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2368 wm8994->lrclk_shared[1]) {
9e6e96a1 2369 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 2370 } else {
9e6e96a1 2371 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 2372 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2373 }
9e6e96a1
MB		 2374 break;
2375 default:
2376 return -EINVAL;
2377 }
2378
2379 bclk_rate = params_rate(params) * 2;
2380 switch (params_format(params)) {
2381 case SNDRV_PCM_FORMAT_S16_LE:
2382 bclk_rate *= 16;
2383 break;
2384 case SNDRV_PCM_FORMAT_S20_3LE:
2385 bclk_rate *= 20;
2386 aif1 |= 0x20;
2387 break;
2388 case SNDRV_PCM_FORMAT_S24_LE:
2389 bclk_rate *= 24;
2390 aif1 |= 0x40;
2391 break;
2392 case SNDRV_PCM_FORMAT_S32_LE:
2393 bclk_rate *= 32;
2394 aif1 |= 0x60;
2395 break;
2396 default:
2397 return -EINVAL;
2398 }
2399
2400 /* Try to find an appropriate sample rate; look for an exact match. */
2401 for (i = 0; i < ARRAY_SIZE(srs); i++)
2402 if (srs[i].rate == params_rate(params))
2403 break;
2404 if (i == ARRAY_SIZE(srs))
2405 return -EINVAL;
2406 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2407
2408 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2409 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2410 dai->id, wm8994->aifclk[id], bclk_rate);
2411
b1e43d93
MB		 2412 if (params_channels(params) == 1 &&
2413 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2414 aif2 |= WM8994_AIF1_MONO;
2415
9e6e96a1
MB		 2416 if (wm8994->aifclk[id] == 0) {
2417 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2418 return -EINVAL;
2419 }
2420
2421 /* AIFCLK/fs ratio; look for a close match in either direction */
2422 best = 0;
2423 best_val = abs((fs_ratios[0] * params_rate(params))
2424 - wm8994->aifclk[id]);
2425 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2426 cur_val = abs((fs_ratios[i] * params_rate(params))
2427 - wm8994->aifclk[id]);
2428 if (cur_val >= best_val)
2429 continue;
2430 best = i;
2431 best_val = cur_val;
2432 }
2433 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2434 dai->id, fs_ratios[best]);
2435 rate_val |= best;
2436
2437 /* We may not get quite the right frequency if using
2438 * approximate clocks so look for the closest match that is
2439 * higher than the target (we need to ensure that there enough
2440 * BCLKs to clock out the samples).
2441 */
2442 best = 0;
2443 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 2444 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 2445 if (cur_val < 0) /* BCLK table is sorted */
2446 break;
2447 best = i;
2448 }
07cd8ada 2449 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 2450 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2451 bclk_divs[best], bclk_rate);
2452 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2453
2454 lrclk = bclk_rate / params_rate(params);
fc07ecd8
MB		 2455 if (!lrclk) {
2456 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2457 bclk_rate);
2458 return -EINVAL;
2459 }
9e6e96a1
MB		 2460 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2461 lrclk, bclk_rate / lrclk);
2462
2463 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
b1e43d93 2464 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
9e6e96a1
MB		 2465 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2466 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2467 lrclk);
2468 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2469 WM8994_AIF1CLK_RATE_MASK, rate_val);
2470
2471 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2472 switch (dai->id) {
2473 case 1:
2474 wm8994->dac_rates[0] = params_rate(params);
2475 wm8994_set_retune_mobile(codec, 0);
2476 wm8994_set_retune_mobile(codec, 1);
2477 break;
2478 case 2:
2479 wm8994->dac_rates[1] = params_rate(params);
2480 wm8994_set_retune_mobile(codec, 2);
2481 break;
2482 }
2483 }
2484
2485 return 0;
2486}
2487
c4431df0
MB		 2488static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2489 struct snd_pcm_hw_params *params,
2490 struct snd_soc_dai *dai)
2491{
2492 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2493 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2494 struct wm8994 *control = wm8994->wm8994;
c4431df0
MB		 2495 int aif1_reg;
2496 int aif1 = 0;
2497
2498 switch (dai->id) {
2499 case 3:
2500 switch (control->type) {
81204c84 2501 case WM1811:
c4431df0
MB		 2502 case WM8958:
2503 aif1_reg = WM8958_AIF3_CONTROL_1;
2504 break;
2505 default:
2506 return 0;
2507 }
2508 default:
2509 return 0;
2510 }
2511
2512 switch (params_format(params)) {
2513 case SNDRV_PCM_FORMAT_S16_LE:
2514 break;
2515 case SNDRV_PCM_FORMAT_S20_3LE:
2516 aif1 |= 0x20;
2517 break;
2518 case SNDRV_PCM_FORMAT_S24_LE:
2519 aif1 |= 0x40;
2520 break;
2521 case SNDRV_PCM_FORMAT_S32_LE:
2522 aif1 |= 0x60;
2523 break;
2524 default:
2525 return -EINVAL;
2526 }
2527
2528 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2529}
2530
7d02173c
MB		 2531static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2532 struct snd_soc_dai *dai)
2533{
2534 struct snd_soc_codec *codec = dai->codec;
2535 int rate_reg = 0;
2536
2537 switch (dai->id) {
2538 case 1:
2539 rate_reg = WM8994_AIF1_RATE;
2540 break;
2541 case 2:
c527e6aa 2542 rate_reg = WM8994_AIF2_RATE;
7d02173c
MB		 2543 break;
2544 default:
2545 break;
2546 }
2547
2548 /* If the DAI is idle then configure the divider tree for the
2549 * lowest output rate to save a little power if the clock is
2550 * still active (eg, because it is system clock).
2551 */
2552 if (rate_reg && !dai->playback_active && !dai->capture_active)
2553 snd_soc_update_bits(codec, rate_reg,
2554 WM8994_AIF1_SR_MASK |
2555 WM8994_AIF1CLK_RATE_MASK, 0x9);
2556}
2557
9e6e96a1
MB		 2558static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2559{
2560 struct snd_soc_codec *codec = codec_dai->codec;
2561 int mute_reg;
2562 int reg;
2563
2564 switch (codec_dai->id) {
2565 case 1:
2566 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2567 break;
2568 case 2:
2569 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2570 break;
2571 default:
2572 return -EINVAL;
2573 }
2574
2575 if (mute)
2576 reg = WM8994_AIF1DAC1_MUTE;
2577 else
2578 reg = 0;
2579
2580 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2581
2582 return 0;
2583}
2584
778a76e2
MB		 2585static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2586{
2587 struct snd_soc_codec *codec = codec_dai->codec;
2588 int reg, val, mask;
2589
2590 switch (codec_dai->id) {
2591 case 1:
2592 reg = WM8994_AIF1_MASTER_SLAVE;
2593 mask = WM8994_AIF1_TRI;
2594 break;
2595 case 2:
2596 reg = WM8994_AIF2_MASTER_SLAVE;
2597 mask = WM8994_AIF2_TRI;
2598 break;
2599 case 3:
2600 reg = WM8994_POWER_MANAGEMENT_6;
2601 mask = WM8994_AIF3_TRI;
2602 break;
2603 default:
2604 return -EINVAL;
2605 }
2606
2607 if (tristate)
2608 val = mask;
2609 else
2610 val = 0;
2611
78b3fb46 2612 return snd_soc_update_bits(codec, reg, mask, val);
778a76e2
MB		 2613}
2614
d09f3ecf
MB		 2615static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2616{
2617 struct snd_soc_codec *codec = dai->codec;
2618
2619 /* Disable the pulls on the AIF if we're using it to save power. */
2620 snd_soc_update_bits(codec, WM8994_GPIO_3,
2621 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2622 snd_soc_update_bits(codec, WM8994_GPIO_4,
2623 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2624 snd_soc_update_bits(codec, WM8994_GPIO_5,
2625 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2626
2627 return 0;
2628}
2629
9e6e96a1
MB		 2630#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2631
2632#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 2633 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1 2634
85e7652d 2635static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
9e6e96a1
MB		 2636 .set_sysclk = wm8994_set_dai_sysclk,
2637 .set_fmt = wm8994_set_dai_fmt,
2638 .hw_params = wm8994_hw_params,
7d02173c 2639 .shutdown = wm8994_aif_shutdown,
9e6e96a1
MB		 2640 .digital_mute = wm8994_aif_mute,
2641 .set_pll = wm8994_set_fll,
778a76e2 2642 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2643};
2644
85e7652d 2645static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
9e6e96a1
MB		 2646 .set_sysclk = wm8994_set_dai_sysclk,
2647 .set_fmt = wm8994_set_dai_fmt,
2648 .hw_params = wm8994_hw_params,
7d02173c 2649 .shutdown = wm8994_aif_shutdown,
9e6e96a1
MB		 2650 .digital_mute = wm8994_aif_mute,
2651 .set_pll = wm8994_set_fll,
778a76e2
MB		 2652 .set_tristate = wm8994_set_tristate,
2653};
2654
85e7652d 2655static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 2656 .hw_params = wm8994_aif3_hw_params,
778a76e2 2657 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2658};
2659
f0fba2ad 2660static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 2661 {
f0fba2ad 2662 .name = "wm8994-aif1",
8c7f78b3 2663 .id = 1,
9e6e96a1
MB		 2664 .playback = {
2665 .stream_name = "AIF1 Playback",
b1e43d93 2666 .channels_min = 1,
9e6e96a1
MB		 2667 .channels_max = 2,
2668 .rates = WM8994_RATES,
2669 .formats = WM8994_FORMATS,
99b0292d 2670 .sig_bits = 24,
9e6e96a1
MB		 2671 },
2672 .capture = {
2673 .stream_name = "AIF1 Capture",
b1e43d93 2674 .channels_min = 1,
9e6e96a1
MB		 2675 .channels_max = 2,
2676 .rates = WM8994_RATES,
2677 .formats = WM8994_FORMATS,
99b0292d 2678 .sig_bits = 24,
9e6e96a1
MB		 2679 },
2680 .ops = &wm8994_aif1_dai_ops,
2681 },
2682 {
f0fba2ad 2683 .name = "wm8994-aif2",
8c7f78b3 2684 .id = 2,
9e6e96a1
MB		 2685 .playback = {
2686 .stream_name = "AIF2 Playback",
b1e43d93 2687 .channels_min = 1,
9e6e96a1
MB		 2688 .channels_max = 2,
2689 .rates = WM8994_RATES,
2690 .formats = WM8994_FORMATS,
99b0292d 2691 .sig_bits = 24,
9e6e96a1
MB		 2692 },
2693 .capture = {
2694 .stream_name = "AIF2 Capture",
b1e43d93 2695 .channels_min = 1,
9e6e96a1
MB		 2696 .channels_max = 2,
2697 .rates = WM8994_RATES,
2698 .formats = WM8994_FORMATS,
99b0292d 2699 .sig_bits = 24,
9e6e96a1 2700 },
d09f3ecf 2701 .probe = wm8994_aif2_probe,
9e6e96a1
MB		 2702 .ops = &wm8994_aif2_dai_ops,
2703 },
2704 {
f0fba2ad 2705 .name = "wm8994-aif3",
8c7f78b3 2706 .id = 3,
9e6e96a1
MB		 2707 .playback = {
2708 .stream_name = "AIF3 Playback",
b1e43d93 2709 .channels_min = 1,
9e6e96a1
MB		 2710 .channels_max = 2,
2711 .rates = WM8994_RATES,
2712 .formats = WM8994_FORMATS,
99b0292d 2713 .sig_bits = 24,
9e6e96a1 2714 },
a8462bde 2715 .capture = {
9e6e96a1 2716 .stream_name = "AIF3 Capture",
b1e43d93 2717 .channels_min = 1,
9e6e96a1
MB		 2718 .channels_max = 2,
2719 .rates = WM8994_RATES,
2720 .formats = WM8994_FORMATS,
99b0292d
MB		 2721 .sig_bits = 24,
2722 },
778a76e2 2723 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 2724 }
2725};
9e6e96a1
MB		 2726
2727#ifdef CONFIG_PM
84b315ee 2728static int wm8994_suspend(struct snd_soc_codec *codec)
9e6e96a1 2729{
b2c812e2 2730 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2731 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2732 int i, ret;
2733
ca629928
MB		 2734 switch (control->type) {
2735 case WM8994:
2736 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2737 break;
81204c84 2738 case WM1811:
af6b6fe4
MB		 2739 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2740 WM1811_JACKDET_MODE_MASK, 0);
2741 /* Fall through */
ca629928
MB		 2742 case WM8958:
2743 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2744 WM8958_MICD_ENA, 0);
2745 break;
2746 }
2747
9e6e96a1
MB		 2748 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2749 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
f701a2e5 2750 sizeof(struct wm8994_fll_config));
f0fba2ad 2751 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 2752 if (ret < 0)
2753 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2754 i + 1, ret);
2755 }
2756
2757 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2758
2759 return 0;
2760}
2761
f0fba2ad 2762static int wm8994_resume(struct snd_soc_codec *codec)
9e6e96a1 2763{
b2c812e2 2764 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2765 struct wm8994 *control = wm8994->wm8994;
9e6e96a1 2766 int i, ret;
c52fd021
DP		 2767 unsigned int val, mask;
2768
2769 if (wm8994->revision < 4) {
2770 /* force a HW read */
d9a7666f
MB		 2771 ret = regmap_read(control->regmap,
2772 WM8994_POWER_MANAGEMENT_5, &val);
c52fd021
DP		 2773
2774 /* modify the cache only */
2775 codec->cache_only = 1;
2776 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2777 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2778 val &= mask;
2779 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2780 mask, val);
2781 codec->cache_only = 0;
2782 }
9e6e96a1 2783
9e6e96a1 2784 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 2785 if (!wm8994->fll_suspend[i].out)
2786 continue;
2787
f0fba2ad 2788 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 2789 wm8994->fll_suspend[i].src,
2790 wm8994->fll_suspend[i].in,
2791 wm8994->fll_suspend[i].out);
2792 if (ret < 0)
2793 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2794 i + 1, ret);
2795 }
2796
ca629928
MB		 2797 switch (control->type) {
2798 case WM8994:
2799 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2800 snd_soc_update_bits(codec, WM8994_MICBIAS,
2801 WM8994_MICD_ENA, WM8994_MICD_ENA);
2802 break;
81204c84 2803 case WM1811:
af6b6fe4
MB		 2804 if (wm8994->jackdet && wm8994->jack_cb) {
2805 /* Restart from idle */
2806 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2807 WM1811_JACKDET_MODE_MASK,
2808 WM1811_JACKDET_MODE_JACK);
2809 break;
2810 }
ca629928
MB		 2811 case WM8958:
2812 if (wm8994->jack_cb)
2813 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2814 WM8958_MICD_ENA, WM8958_MICD_ENA);
2815 break;
2816 }
2817
9e6e96a1
MB		 2818 return 0;
2819}
2820#else
2821#define wm8994_suspend NULL
2822#define wm8994_resume NULL
2823#endif
2824
2825static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2826{
f0fba2ad 2827 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2828 struct wm8994_pdata *pdata = wm8994->pdata;
2829 struct snd_kcontrol_new controls[] = {
2830 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2831 wm8994->retune_mobile_enum,
2832 wm8994_get_retune_mobile_enum,
2833 wm8994_put_retune_mobile_enum),
2834 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2835 wm8994->retune_mobile_enum,
2836 wm8994_get_retune_mobile_enum,
2837 wm8994_put_retune_mobile_enum),
2838 SOC_ENUM_EXT("AIF2 EQ Mode",
2839 wm8994->retune_mobile_enum,
2840 wm8994_get_retune_mobile_enum,
2841 wm8994_put_retune_mobile_enum),
2842 };
2843 int ret, i, j;
2844 const char **t;
2845
2846 /* We need an array of texts for the enum API but the number
2847 * of texts is likely to be less than the number of
2848 * configurations due to the sample rate dependency of the
2849 * configurations. */
2850 wm8994->num_retune_mobile_texts = 0;
2851 wm8994->retune_mobile_texts = NULL;
2852 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2853 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2854 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2855 wm8994->retune_mobile_texts[j]) == 0)
2856 break;
2857 }
2858
2859 if (j != wm8994->num_retune_mobile_texts)
2860 continue;
2861
2862 /* Expand the array... */
2863 t = krealloc(wm8994->retune_mobile_texts,
2864 sizeof(char *) *
2865 (wm8994->num_retune_mobile_texts + 1),
2866 GFP_KERNEL);
2867 if (t == NULL)
2868 continue;
2869
2870 /* ...store the new entry... */
2871 t[wm8994->num_retune_mobile_texts] =
2872 pdata->retune_mobile_cfgs[i].name;
2873
2874 /* ...and remember the new version. */
2875 wm8994->num_retune_mobile_texts++;
2876 wm8994->retune_mobile_texts = t;
2877 }
2878
2879 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2880 wm8994->num_retune_mobile_texts);
2881
2882 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2883 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2884
022658be 2885 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
9e6e96a1
MB		 2886 ARRAY_SIZE(controls));
2887 if (ret != 0)
f0fba2ad 2888 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2889 "Failed to add ReTune Mobile controls: %d\n", ret);
2890}
2891
2892static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2893{
f0fba2ad 2894 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2895 struct wm8994_pdata *pdata = wm8994->pdata;
2896 int ret, i;
2897
2898 if (!pdata)
2899 return;
2900
2901 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2902 pdata->lineout2_diff,
2903 pdata->lineout1fb,
2904 pdata->lineout2fb,
2905 pdata->jd_scthr,
2906 pdata->jd_thr,
2907 pdata->micbias1_lvl,
2908 pdata->micbias2_lvl);
2909
2910 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2911
2912 if (pdata->num_drc_cfgs) {
2913 struct snd_kcontrol_new controls[] = {
2914 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2915 wm8994_get_drc_enum, wm8994_put_drc_enum),
2916 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2917 wm8994_get_drc_enum, wm8994_put_drc_enum),
2918 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2919 wm8994_get_drc_enum, wm8994_put_drc_enum),
2920 };
2921
2922 /* We need an array of texts for the enum API */
7270cebe
MB		 2923 wm8994->drc_texts = devm_kzalloc(wm8994->codec->dev,
2924 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
9e6e96a1 2925 if (!wm8994->drc_texts) {
f0fba2ad 2926 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2927 "Failed to allocate %d DRC config texts\n",
2928 pdata->num_drc_cfgs);
2929 return;
2930 }
2931
2932 for (i = 0; i < pdata->num_drc_cfgs; i++)
2933 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2934
2935 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2936 wm8994->drc_enum.texts = wm8994->drc_texts;
2937
022658be 2938 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
9e6e96a1
MB		 2939 ARRAY_SIZE(controls));
2940 if (ret != 0)
f0fba2ad 2941 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2942 "Failed to add DRC mode controls: %d\n", ret);
2943
2944 for (i = 0; i < WM8994_NUM_DRC; i++)
2945 wm8994_set_drc(codec, i);
2946 }
2947
2948 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2949 pdata->num_retune_mobile_cfgs);
2950
2951 if (pdata->num_retune_mobile_cfgs)
2952 wm8994_handle_retune_mobile_pdata(wm8994);
2953 else
022658be 2954 snd_soc_add_codec_controls(wm8994->codec, wm8994_eq_controls,
9e6e96a1 2955 ARRAY_SIZE(wm8994_eq_controls));
48e028ec
MB		 2956
2957 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2958 if (pdata->micbias[i]) {
2959 snd_soc_write(codec, WM8958_MICBIAS1 + i,
2960 pdata->micbias[i] & 0xffff);
2961 }
2962 }
9e6e96a1
MB		 2963}
2964
88766984
MB		 2965/**
2966 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2967 *
2968 * @codec: WM8994 codec
2969 * @jack: jack to report detection events on
2970 * @micbias: microphone bias to detect on
88766984
MB		 2971 *
2972 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2973 * being used to bring out signals to the processor then only platform
5ab230a7 2974 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 2975 * be configured using snd_soc_jack_add_gpios() instead.
2976 *
2977 * Configuration of detection levels is available via the micbias1_lvl
2978 * and micbias2_lvl platform data members.
2979 */
2980int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
87092e3c 2981 int micbias)
88766984 2982{
b2c812e2 2983 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 2984 struct wm8994_micdet *micdet;
2a8a856d 2985 struct wm8994 *control = wm8994->wm8994;
87092e3c 2986 int reg, ret;
88766984 2987
87092e3c
MB		 2988 if (control->type != WM8994) {
2989 dev_warn(codec->dev, "Not a WM8994\n");
3a423157 2990 return -EINVAL;
87092e3c 2991 }
3a423157 2992
88766984
MB		 2993 switch (micbias) {
2994 case 1:
2995 micdet = &wm8994->micdet[0];
87092e3c
MB		 2996 if (jack)
2997 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
2998 "MICBIAS1");
2999 else
3000 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3001 "MICBIAS1");
88766984
MB		 3002 break;
3003 case 2:
3004 micdet = &wm8994->micdet[1];
87092e3c
MB		 3005 if (jack)
3006 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3007 "MICBIAS1");
3008 else
3009 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3010 "MICBIAS1");
88766984
MB		 3011 break;
3012 default:
87092e3c 3013 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
88766984 3014 return -EINVAL;
87092e3c 3015 }
88766984 3016
87092e3c
MB		 3017 if (ret != 0)
3018 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3019 micbias, ret);
3020
3021 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3022 micbias, jack);
88766984
MB		 3023
3024 /* Store the configuration */
3025 micdet->jack = jack;
87092e3c 3026 micdet->detecting = true;
88766984
MB		 3027
3028 /* If either of the jacks is set up then enable detection */
3029 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3030 reg = WM8994_MICD_ENA;
87092e3c 3031 else
88766984
MB		 3032 reg = 0;
3033
3034 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3035
87092e3c
MB		 3036 snd_soc_dapm_sync(&codec->dapm);
3037
88766984
MB		 3038 return 0;
3039}
3040EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3041
3042static irqreturn_t wm8994_mic_irq(int irq, void *data)
3043{
3044 struct wm8994_priv *priv = data;
f0fba2ad 3045 struct snd_soc_codec *codec = priv->codec;
88766984
MB		 3046 int reg;
3047 int report;
3048
7116f452 3049#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3050 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3051#endif
2bbb5d66 3052
88766984
MB		 3053 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3054 if (reg < 0) {
3055 dev_err(codec->dev, "Failed to read microphone status: %d\n",
3056 reg);
3057 return IRQ_HANDLED;
3058 }
3059
3060 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
3061
3062 report = 0;
87092e3c
MB		 3063 if (reg & WM8994_MIC1_DET_STS) {
3064 if (priv->micdet[0].detecting)
3065 report = SND_JACK_HEADSET;
3066 }
3067 if (reg & WM8994_MIC1_SHRT_STS) {
3068 if (priv->micdet[0].detecting)
3069 report = SND_JACK_HEADPHONE;
3070 else
3071 report |= SND_JACK_BTN_0;
3072 }
3073 if (report)
3074 priv->micdet[0].detecting = false;
3075 else
3076 priv->micdet[0].detecting = true;
3077
88766984 3078 snd_soc_jack_report(priv->micdet[0].jack, report,
87092e3c 3079 SND_JACK_HEADSET | SND_JACK_BTN_0);
88766984
MB		 3080
3081 report = 0;
87092e3c
MB		 3082 if (reg & WM8994_MIC2_DET_STS) {
3083 if (priv->micdet[1].detecting)
3084 report = SND_JACK_HEADSET;
3085 }
3086 if (reg & WM8994_MIC2_SHRT_STS) {
3087 if (priv->micdet[1].detecting)
3088 report = SND_JACK_HEADPHONE;
3089 else
3090 report |= SND_JACK_BTN_0;
3091 }
3092 if (report)
3093 priv->micdet[1].detecting = false;
3094 else
3095 priv->micdet[1].detecting = true;
3096
88766984 3097 snd_soc_jack_report(priv->micdet[1].jack, report,
87092e3c 3098 SND_JACK_HEADSET | SND_JACK_BTN_0);
88766984
MB		 3099
3100 return IRQ_HANDLED;
3101}
3102
821edd2f
MB		 3103/* Default microphone detection handler for WM8958 - the user can
3104 * override this if they wish.
3105 */
3106static void wm8958_default_micdet(u16 status, void *data)
3107{
3108 struct snd_soc_codec *codec = data;
3109 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4585790d 3110 int report;
821edd2f 3111
a1691343
MB		 3112 dev_dbg(codec->dev, "MICDET %x\n", status);
3113
af6b6fe4 3114 /* Either nothing present or just starting detection */
b00adf76 3115 if (!(status & WM8958_MICD_STS)) {
af6b6fe4
MB		 3116 if (!wm8994->jackdet) {
3117 /* If nothing present then clear our statuses */
3118 dev_dbg(codec->dev, "Detected open circuit\n");
3119 wm8994->jack_mic = false;
3120 wm8994->mic_detecting = true;
b00adf76 3121
af6b6fe4 3122 wm8958_micd_set_rate(codec);
b00adf76 3123
af6b6fe4
MB		 3124 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3125 wm8994->btn_mask |
3126 SND_JACK_HEADSET);
3127 }
b00adf76
MB		 3128 return;
3129 }
821edd2f 3130
b00adf76
MB		 3131 /* If the measurement is showing a high impedence we've got a
3132 * microphone.
3133 */
157a75e6 3134 if (wm8994->mic_detecting && (status & 0x600)) {
b00adf76
MB		 3135 dev_dbg(codec->dev, "Detected microphone\n");
3136
157a75e6 3137 wm8994->mic_detecting = false;
b00adf76
MB		 3138 wm8994->jack_mic = true;
3139
3140 wm8958_micd_set_rate(codec);
3141
3142 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3143 SND_JACK_HEADSET);
3144 }
821edd2f 3145
b00adf76 3146
7c08b51f 3147 if (wm8994->mic_detecting && status & 0xfc) {
b00adf76 3148 dev_dbg(codec->dev, "Detected headphone\n");
157a75e6 3149 wm8994->mic_detecting = false;
b00adf76
MB		 3150
3151 wm8958_micd_set_rate(codec);
3152
3153 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3154 SND_JACK_HEADSET);
af6b6fe4
MB		 3155
3156 /* If we have jackdet that will detect removal */
3157 if (wm8994->jackdet) {
3158 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3159 WM8958_MICD_ENA, 0);
3160
3161 wm1811_jackdet_set_mode(codec,
3162 WM1811_JACKDET_MODE_JACK);
3163 }
b00adf76
MB		 3164 }
3165
3166 /* Report short circuit as a button */
3167 if (wm8994->jack_mic) {
4585790d 3168 report = 0;
b00adf76 3169 if (status & 0x4)
4585790d
MB		 3170 report |= SND_JACK_BTN_0;
3171
3172 if (status & 0x8)
3173 report |= SND_JACK_BTN_1;
3174
3175 if (status & 0x10)
3176 report |= SND_JACK_BTN_2;
3177
3178 if (status & 0x20)
3179 report |= SND_JACK_BTN_3;
3180
3181 if (status & 0x40)
3182 report |= SND_JACK_BTN_4;
3183
3184 if (status & 0x80)
3185 report |= SND_JACK_BTN_5;
3186
3187 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3188 wm8994->btn_mask);
b00adf76 3189 }
821edd2f
MB		 3190}
3191
af6b6fe4
MB		 3192static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3193{
3194 struct wm8994_priv *wm8994 = data;
3195 struct snd_soc_codec *codec = wm8994->codec;
3196 int reg;
3197
3198 mutex_lock(&wm8994->accdet_lock);
3199
3200 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3201 if (reg < 0) {
3202 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3203 mutex_unlock(&wm8994->accdet_lock);
3204 return IRQ_NONE;
3205 }
3206
3207 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3208
3209 if (reg & WM1811_JACKDET_LVL) {
3210 dev_dbg(codec->dev, "Jack detected\n");
3211
3212 snd_soc_jack_report(wm8994->micdet[0].jack,
3213 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3214
3215 /*
3216 * Start off measument of microphone impedence to find
3217 * out what's actually there.
3218 */
3219 wm8994->mic_detecting = true;
3220 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3221 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3222 WM8958_MICD_ENA, WM8958_MICD_ENA);
3223 } else {
3224 dev_dbg(codec->dev, "Jack not detected\n");
3225
3226 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3227 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3228 wm8994->btn_mask);
3229
3230 wm8994->mic_detecting = false;
3231 wm8994->jack_mic = false;
3232 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3233 WM8958_MICD_ENA, 0);
3234 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3235 }
3236
3237 mutex_unlock(&wm8994->accdet_lock);
3238
3239 return IRQ_HANDLED;
3240}
3241
821edd2f
MB		 3242/**
3243 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3244 *
3245 * @codec: WM8958 codec
3246 * @jack: jack to report detection events on
3247 *
3248 * Enable microphone detection functionality for the WM8958. By
3249 * default simple detection which supports the detection of up to 6
3250 * buttons plus video and microphone functionality is supported.
3251 *
3252 * The WM8958 has an advanced jack detection facility which is able to
3253 * support complex accessory detection, especially when used in
3254 * conjunction with external circuitry. In order to provide maximum
3255 * flexiblity a callback is provided which allows a completely custom
3256 * detection algorithm.
3257 */
3258int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3259 wm8958_micdet_cb cb, void *cb_data)
3260{
3261 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3262 struct wm8994 *control = wm8994->wm8994;
4585790d 3263 u16 micd_lvl_sel;
821edd2f 3264
81204c84
MB		 3265 switch (control->type) {
3266 case WM1811:
3267 case WM8958:
3268 break;
3269 default:
821edd2f 3270 return -EINVAL;
81204c84 3271 }
821edd2f
MB		 3272
3273 if (jack) {
3274 if (!cb) {
3275 dev_dbg(codec->dev, "Using default micdet callback\n");
3276 cb = wm8958_default_micdet;
3277 cb_data = codec;
3278 }
3279
4cdf5e49
MB		 3280 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3281
821edd2f
MB		 3282 wm8994->micdet[0].jack = jack;
3283 wm8994->jack_cb = cb;
3284 wm8994->jack_cb_data = cb_data;
3285
157a75e6 3286 wm8994->mic_detecting = true;
b00adf76
MB		 3287 wm8994->jack_mic = false;
3288
3289 wm8958_micd_set_rate(codec);
3290
4585790d
MB		 3291 /* Detect microphones and short circuits by default */
3292 if (wm8994->pdata->micd_lvl_sel)
3293 micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3294 else
3295 micd_lvl_sel = 0x41;
3296
3297 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3298 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3299 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3300
b00adf76 3301 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
4585790d 3302 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
b00adf76 3303
af6b6fe4
MB		 3304 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3305
3306 /*
3307 * If we can use jack detection start off with that,
3308 * otherwise jump straight to microphone detection.
3309 */
3310 if (wm8994->jackdet) {
3311 snd_soc_update_bits(codec, WM8994_LDO_1,
3312 WM8994_LDO1_DISCH, 0);
3313 wm1811_jackdet_set_mode(codec,
3314 WM1811_JACKDET_MODE_JACK);
3315 } else {
3316 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3317 WM8958_MICD_ENA, WM8958_MICD_ENA);
3318 }
3319
821edd2f
MB		 3320 } else {
3321 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3322 WM8958_MICD_ENA, 0);
4cdf5e49 3323 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
821edd2f
MB		 3324 }
3325
3326 return 0;
3327}
3328EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3329
3330static irqreturn_t wm8958_mic_irq(int irq, void *data)
3331{
3332 struct wm8994_priv *wm8994 = data;
3333 struct snd_soc_codec *codec = wm8994->codec;
19940b3d 3334 int reg, count;
821edd2f 3335
af6b6fe4
MB		 3336 mutex_lock(&wm8994->accdet_lock);
3337
3338 /*
3339 * Jack detection may have detected a removal simulataneously
3340 * with an update of the MICDET status; if so it will have
3341 * stopped detection and we can ignore this interrupt.
3342 */
3343 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA)) {
3344 mutex_unlock(&wm8994->accdet_lock);
3345 return IRQ_HANDLED;
3346 }
3347
19940b3d
MB		 3348 /* We may occasionally read a detection without an impedence
3349 * range being provided - if that happens loop again.
3350 */
3351 count = 10;
3352 do {
3353 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3354 if (reg < 0) {
af6b6fe4 3355 mutex_unlock(&wm8994->accdet_lock);
19940b3d
MB		 3356 dev_err(codec->dev,
3357 "Failed to read mic detect status: %d\n",
3358 reg);
3359 return IRQ_NONE;
3360 }
821edd2f 3361
19940b3d
MB		 3362 if (!(reg & WM8958_MICD_VALID)) {
3363 dev_dbg(codec->dev, "Mic detect data not valid\n");
3364 goto out;
3365 }
3366
3367 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3368 break;
3369
3370 msleep(1);
3371 } while (count--);
3372
3373 if (count == 0)
3374 dev_warn(codec->dev, "No impedence range reported for jack\n");
821edd2f 3375
7116f452 3376#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3377 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3378#endif
2bbb5d66 3379
821edd2f
MB		 3380 if (wm8994->jack_cb)
3381 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3382 else
3383 dev_warn(codec->dev, "Accessory detection with no callback\n");
3384
3385out:
af6b6fe4
MB		 3386 mutex_unlock(&wm8994->accdet_lock);
3387
821edd2f
MB		 3388 return IRQ_HANDLED;
3389}
3390
3b1af3f8
MB		 3391static irqreturn_t wm8994_fifo_error(int irq, void *data)
3392{
3393 struct snd_soc_codec *codec = data;
3394
3395 dev_err(codec->dev, "FIFO error\n");
3396
3397 return IRQ_HANDLED;
3398}
3399
f0b182b0
MB		 3400static irqreturn_t wm8994_temp_warn(int irq, void *data)
3401{
3402 struct snd_soc_codec *codec = data;
3403
3404 dev_err(codec->dev, "Thermal warning\n");
3405
3406 return IRQ_HANDLED;
3407}
3408
3409static irqreturn_t wm8994_temp_shut(int irq, void *data)
3410{
3411 struct snd_soc_codec *codec = data;
3412
3413 dev_crit(codec->dev, "Thermal shutdown\n");
3414
3415 return IRQ_HANDLED;
3416}
3417
f0fba2ad 3418static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 3419{
d9a7666f 3420 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
9e6e96a1 3421 struct wm8994_priv *wm8994;
ce6120cc 3422 struct snd_soc_dapm_context *dapm = &codec->dapm;
d9a7666f 3423 unsigned int reg;
ec62dbd7 3424 int ret, i;
9e6e96a1 3425
d9a7666f 3426 codec->control_data = control->regmap;
9e6e96a1 3427
7270cebe
MB		 3428 wm8994 = devm_kzalloc(codec->dev, sizeof(struct wm8994_priv),
3429 GFP_KERNEL);
f0fba2ad 3430 if (wm8994 == NULL)
9e6e96a1 3431 return -ENOMEM;
b2c812e2 3432 snd_soc_codec_set_drvdata(codec, wm8994);
f0fba2ad 3433
d9a7666f 3434 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
2a8a856d
MB		 3435
3436 wm8994->wm8994 = dev_get_drvdata(codec->dev->parent);
f0fba2ad
LG		 3437 wm8994->pdata = dev_get_platdata(codec->dev->parent);
3438 wm8994->codec = codec;
9e6e96a1 3439
af6b6fe4
MB		 3440 mutex_init(&wm8994->accdet_lock);
3441
c7ebf932
MB		 3442 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3443 init_completion(&wm8994->fll_locked[i]);
3444
9b7c525d
MB		 3445 if (wm8994->pdata && wm8994->pdata->micdet_irq)
3446 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3447 else if (wm8994->pdata && wm8994->pdata->irq_base)
3448 wm8994->micdet_irq = wm8994->pdata->irq_base +
3449 WM8994_IRQ_MIC1_DET;
3450
39fb51a1 3451 pm_runtime_enable(codec->dev);
5fab5174 3452 pm_runtime_idle(codec->dev);
39fb51a1 3453
f959dee9
MB		 3454 /* By default use idle_bias_off, will override for WM8994 */
3455 codec->dapm.idle_bias_off = 1;
3456
9e6e96a1 3457 /* Set revision-specific configuration */
b6b05691 3458 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3a423157
MB		 3459 switch (control->type) {
3460 case WM8994:
f959dee9
MB		 3461 /* Single ended line outputs should have VMID on. */
3462 if (!wm8994->pdata->lineout1_diff ||
3463 !wm8994->pdata->lineout2_diff)
3464 codec->dapm.idle_bias_off = 0;
3465
3a423157
MB		 3466 switch (wm8994->revision) {
3467 case 2:
3468 case 3:
4537c4e7
MB		 3469 wm8994->hubs.dcs_codes_l = -5;
3470 wm8994->hubs.dcs_codes_r = -5;
3a423157
MB		 3471 wm8994->hubs.hp_startup_mode = 1;
3472 wm8994->hubs.dcs_readback_mode = 1;
f9acf9fe 3473 wm8994->hubs.series_startup = 1;
3a423157
MB		 3474 break;
3475 default:
79ef0abc 3476 wm8994->hubs.dcs_readback_mode = 2;
3a423157
MB		 3477 break;
3478 }
280ec8b7 3479 break;
3a423157
MB		 3480
3481 case WM8958:
8437f700 3482 wm8994->hubs.dcs_readback_mode = 1;
9e6e96a1 3483 break;
3a423157 3484
81204c84
MB		 3485 case WM1811:
3486 wm8994->hubs.dcs_readback_mode = 2;
3487 wm8994->hubs.no_series_update = 1;
3488
3489 switch (wm8994->revision) {
3490 case 0:
3491 case 1:
fc8e6e86
MB		 3492 case 2:
3493 case 3:
6473a148
MB		 3494 wm8994->hubs.dcs_codes_l = -9;
3495 wm8994->hubs.dcs_codes_r = -5;
81204c84
MB		 3496 break;
3497 default:
3498 break;
3499 }
3500
3501 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3502 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3503 break;
3504
9e6e96a1
MB		 3505 default:
3506 break;
3507 }
9e6e96a1 3508
2a8a856d 3509 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3b1af3f8 3510 wm8994_fifo_error, "FIFO error", codec);
2a8a856d 3511 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
f0b182b0 3512 wm8994_temp_warn, "Thermal warning", codec);
2a8a856d 3513 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
f0b182b0 3514 wm8994_temp_shut, "Thermal shutdown", codec);
3b1af3f8 3515
2a8a856d 3516 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f
MB		 3517 wm_hubs_dcs_done, "DC servo done",
3518 &wm8994->hubs);
3519 if (ret == 0)
3520 wm8994->hubs.dcs_done_irq = true;
3521
3a423157
MB		 3522 switch (control->type) {
3523 case WM8994:
9b7c525d
MB		 3524 if (wm8994->micdet_irq) {
3525 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3526 wm8994_mic_irq,
3527 IRQF_TRIGGER_RISING,
3528 "Mic1 detect",
3529 wm8994);
3530 if (ret != 0)
3531 dev_warn(codec->dev,
3532 "Failed to request Mic1 detect IRQ: %d\n",
3533 ret);
3534 }
3a423157 3535
2a8a856d 3536 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3537 WM8994_IRQ_MIC1_SHRT,
3538 wm8994_mic_irq, "Mic 1 short",
3539 wm8994);
3540 if (ret != 0)
3541 dev_warn(codec->dev,
3542 "Failed to request Mic1 short IRQ: %d\n",
3543 ret);
3544
2a8a856d 3545 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3546 WM8994_IRQ_MIC2_DET,
3547 wm8994_mic_irq, "Mic 2 detect",
3548 wm8994);
3549 if (ret != 0)
3550 dev_warn(codec->dev,
3551 "Failed to request Mic2 detect IRQ: %d\n",
3552 ret);
3553
2a8a856d 3554 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3555 WM8994_IRQ_MIC2_SHRT,
3556 wm8994_mic_irq, "Mic 2 short",
3557 wm8994);
3558 if (ret != 0)
3559 dev_warn(codec->dev,
3560 "Failed to request Mic2 short IRQ: %d\n",
3561 ret);
3562 break;
821edd2f
MB		 3563
3564 case WM8958:
81204c84 3565 case WM1811:
9b7c525d
MB		 3566 if (wm8994->micdet_irq) {
3567 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3568 wm8958_mic_irq,
3569 IRQF_TRIGGER_RISING,
3570 "Mic detect",
3571 wm8994);
3572 if (ret != 0)
3573 dev_warn(codec->dev,
3574 "Failed to request Mic detect IRQ: %d\n",
3575 ret);
3576 }
3a423157 3577 }
88766984 3578
af6b6fe4
MB		 3579 switch (control->type) {
3580 case WM1811:
3581 if (wm8994->revision > 1) {
3582 ret = wm8994_request_irq(wm8994->wm8994,
3583 WM8994_IRQ_GPIO(6),
3584 wm1811_jackdet_irq, "JACKDET",
3585 wm8994);
3586 if (ret == 0)
3587 wm8994->jackdet = true;
3588 }
3589 break;
3590 default:
3591 break;
3592 }
3593
c7ebf932
MB		 3594 wm8994->fll_locked_irq = true;
3595 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
2a8a856d 3596 ret = wm8994_request_irq(wm8994->wm8994,
c7ebf932
MB		 3597 WM8994_IRQ_FLL1_LOCK + i,
3598 wm8994_fll_locked_irq, "FLL lock",
3599 &wm8994->fll_locked[i]);
3600 if (ret != 0)
3601 wm8994->fll_locked_irq = false;
3602 }
3603
27060b3c
MB		 3604 /* Make sure we can read from the GPIOs if they're inputs */
3605 pm_runtime_get_sync(codec->dev);
3606
9e6e96a1
MB		 3607 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3608 * configured on init - if a system wants to do this dynamically
3609 * at runtime we can deal with that then.
3610 */
d9a7666f 3611 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
9e6e96a1
MB		 3612 if (ret < 0) {
3613 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 3614 goto err_irq;
9e6e96a1 3615 }
d9a7666f 3616 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 3617 wm8994->lrclk_shared[0] = 1;
3618 wm8994_dai[0].symmetric_rates = 1;
3619 } else {
3620 wm8994->lrclk_shared[0] = 0;
3621 }
3622
d9a7666f 3623 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
9e6e96a1
MB		 3624 if (ret < 0) {
3625 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 3626 goto err_irq;
9e6e96a1 3627 }
d9a7666f 3628 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 3629 wm8994->lrclk_shared[1] = 1;
3630 wm8994_dai[1].symmetric_rates = 1;
3631 } else {
3632 wm8994->lrclk_shared[1] = 0;
3633 }
3634
27060b3c
MB		 3635 pm_runtime_put(codec->dev);
3636
9e6e96a1 3637 /* Latch volume updates (right only; we always do left then right). */
baa81603
MB		 3638 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3639 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
9e6e96a1
MB		 3640 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3641 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
baa81603
MB		 3642 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3643 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
9e6e96a1
MB		 3644 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3645 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
baa81603
MB		 3646 snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3647 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
9e6e96a1
MB		 3648 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3649 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
baa81603
MB		 3650 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3651 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
9e6e96a1
MB		 3652 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3653 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
baa81603
MB		 3654 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3655 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
9e6e96a1
MB		 3656 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3657 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
baa81603
MB		 3658 snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3659 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
9e6e96a1
MB		 3660 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3661 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
baa81603
MB		 3662 snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3663 WM8994_DAC1_VU, WM8994_DAC1_VU);
9e6e96a1
MB		 3664 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3665 WM8994_DAC1_VU, WM8994_DAC1_VU);
baa81603
MB		 3666 snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3667 WM8994_DAC2_VU, WM8994_DAC2_VU);
9e6e96a1
MB		 3668 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3669 WM8994_DAC2_VU, WM8994_DAC2_VU);
3670
3671 /* Set the low bit of the 3D stereo depth so TLV matches */
3672 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3673 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3674 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3675 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3676 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3677 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3678 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3679 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3680 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3681
5b739670
MB		 3682 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3683 * use this; it only affects behaviour on idle TDM clock
3684 * cycles. */
3685 switch (control->type) {
3686 case WM8994:
3687 case WM8958:
3688 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3689 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3690 break;
3691 default:
3692 break;
3693 }
d1ce6b20 3694
500fa30e
MB		 3695 /* Put MICBIAS into bypass mode by default on newer devices */
3696 switch (control->type) {
3697 case WM8958:
3698 case WM1811:
3699 snd_soc_update_bits(codec, WM8958_MICBIAS1,
3700 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
3701 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3702 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
3703 break;
3704 default:
3705 break;
3706 }
3707
9e6e96a1
MB		 3708 wm8994_update_class_w(codec);
3709
f0fba2ad 3710 wm8994_handle_pdata(wm8994);
9e6e96a1 3711
f0fba2ad 3712 wm_hubs_add_analogue_controls(codec);
022658be 3713 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
f0fba2ad 3714 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 3715 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 3716 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB		 3717
3718 switch (control->type) {
3719 case WM8994:
3720 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3721 ARRAY_SIZE(wm8994_specific_dapm_widgets));
c52fd021 3722 if (wm8994->revision < 4) {
173efa09
DP		 3723 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3724 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
04d28681
DP		 3725 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3726 ARRAY_SIZE(wm8994_adc_revd_widgets));
c52fd021
DP		 3727 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3728 ARRAY_SIZE(wm8994_dac_revd_widgets));
3729 } else {
173efa09
DP		 3730 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3731 ARRAY_SIZE(wm8994_lateclk_widgets));
04d28681
DP		 3732 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3733 ARRAY_SIZE(wm8994_adc_widgets));
c52fd021
DP		 3734 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3735 ARRAY_SIZE(wm8994_dac_widgets));
3736 }
c4431df0
MB		 3737 break;
3738 case WM8958:
022658be 3739 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
c4431df0
MB		 3740 ARRAY_SIZE(wm8958_snd_controls));
3741 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3742 ARRAY_SIZE(wm8958_dapm_widgets));
780e2806
MB		 3743 if (wm8994->revision < 1) {
3744 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3745 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3746 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3747 ARRAY_SIZE(wm8994_adc_revd_widgets));
3748 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3749 ARRAY_SIZE(wm8994_dac_revd_widgets));
3750 } else {
3751 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3752 ARRAY_SIZE(wm8994_lateclk_widgets));
3753 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3754 ARRAY_SIZE(wm8994_adc_widgets));
3755 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3756 ARRAY_SIZE(wm8994_dac_widgets));
3757 }
c4431df0 3758 break;
81204c84
MB		 3759
3760 case WM1811:
022658be 3761 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
81204c84
MB		 3762 ARRAY_SIZE(wm8958_snd_controls));
3763 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3764 ARRAY_SIZE(wm8958_dapm_widgets));
3765 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3766 ARRAY_SIZE(wm8994_lateclk_widgets));
3767 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3768 ARRAY_SIZE(wm8994_adc_widgets));
3769 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3770 ARRAY_SIZE(wm8994_dac_widgets));
3771 break;
c4431df0
MB		 3772 }
3773
3774
f0fba2ad 3775 wm_hubs_add_analogue_routes(codec, 0, 0);
ce6120cc 3776 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 3777
c4431df0
MB		 3778 switch (control->type) {
3779 case WM8994:
3780 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3781 ARRAY_SIZE(wm8994_intercon));
6ed8f148 3782
173efa09 3783 if (wm8994->revision < 4) {
6ed8f148
MB		 3784 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3785 ARRAY_SIZE(wm8994_revd_intercon));
173efa09
DP		 3786 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3787 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3788 } else {
3789 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3790 ARRAY_SIZE(wm8994_lateclk_intercon));
3791 }
c4431df0
MB		 3792 break;
3793 case WM8958:
780e2806
MB		 3794 if (wm8994->revision < 1) {
3795 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3796 ARRAY_SIZE(wm8994_revd_intercon));
3797 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3798 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3799 } else {
3800 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3801 ARRAY_SIZE(wm8994_lateclk_intercon));
3802 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3803 ARRAY_SIZE(wm8958_intercon));
3804 }
f701a2e5
MB		 3805
3806 wm8958_dsp2_init(codec);
c4431df0 3807 break;
81204c84
MB		 3808 case WM1811:
3809 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3810 ARRAY_SIZE(wm8994_lateclk_intercon));
3811 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3812 ARRAY_SIZE(wm8958_intercon));
3813 break;
c4431df0
MB		 3814 }
3815
9e6e96a1
MB		 3816 return 0;
3817
88766984 3818err_irq:
af6b6fe4
MB		 3819 if (wm8994->jackdet)
3820 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
2a8a856d
MB		 3821 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
3822 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
3823 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
9b7c525d
MB		 3824 if (wm8994->micdet_irq)
3825 free_irq(wm8994->micdet_irq, wm8994);
c7ebf932 3826 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 3827 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932 3828 &wm8994->fll_locked[i]);
2a8a856d 3829 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 3830 &wm8994->hubs);
2a8a856d
MB		 3831 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3832 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3833 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
a421a0e4 3834
9e6e96a1
MB		 3835 return ret;
3836}
3837
f0fba2ad 3838static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 3839{
f0fba2ad 3840 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3841 struct wm8994 *control = wm8994->wm8994;
c7ebf932 3842 int i;
9e6e96a1
MB		 3843
3844 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 3845
39fb51a1
MB		 3846 pm_runtime_disable(codec->dev);
3847
c7ebf932 3848 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 3849 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932
MB		 3850 &wm8994->fll_locked[i]);
3851
2a8a856d 3852 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 3853 &wm8994->hubs);
2a8a856d
MB		 3854 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3855 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3856 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
b30ead5f 3857
af6b6fe4
MB		 3858 if (wm8994->jackdet)
3859 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
3860
3a423157
MB		 3861 switch (control->type) {
3862 case WM8994:
9b7c525d
MB		 3863 if (wm8994->micdet_irq)
3864 free_irq(wm8994->micdet_irq, wm8994);
2a8a856d 3865 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3a423157 3866 wm8994);
2a8a856d 3867 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3a423157 3868 wm8994);
2a8a856d 3869 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3a423157
MB		 3870 wm8994);
3871 break;
821edd2f 3872
81204c84 3873 case WM1811:
821edd2f 3874 case WM8958:
9b7c525d
MB		 3875 if (wm8994->micdet_irq)
3876 free_irq(wm8994->micdet_irq, wm8994);
821edd2f 3877 break;
3a423157 3878 }
fbbf5920
MB		 3879 if (wm8994->mbc)
3880 release_firmware(wm8994->mbc);
09e10d7f
MB		 3881 if (wm8994->mbc_vss)
3882 release_firmware(wm8994->mbc_vss);
31215871
MB		 3883 if (wm8994->enh_eq)
3884 release_firmware(wm8994->enh_eq);
24fb2b11 3885 kfree(wm8994->retune_mobile_texts);
9e6e96a1
MB		 3886
3887 return 0;
3888}
3889
1b39bf34
MB		 3890static int wm8994_soc_volatile(struct snd_soc_codec *codec,
3891 unsigned int reg)
3892{
3893 return true;
3894}
3895
f0fba2ad
LG		 3896static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3897 .probe = wm8994_codec_probe,
3898 .remove = wm8994_codec_remove,
3899 .suspend = wm8994_suspend,
3900 .resume = wm8994_resume,
f0fba2ad 3901 .set_bias_level = wm8994_set_bias_level,
1b39bf34
MB		 3902 .reg_cache_size = WM8994_MAX_REGISTER,
3903 .volatile_register = wm8994_soc_volatile,
f0fba2ad
LG		 3904};
3905
3906static int __devinit wm8994_probe(struct platform_device *pdev)
3907{
3908 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3909 wm8994_dai, ARRAY_SIZE(wm8994_dai));
3910}
3911
3912static int __devexit wm8994_remove(struct platform_device *pdev)
3913{
3914 snd_soc_unregister_codec(&pdev->dev);
3915 return 0;
3916}
3917
9e6e96a1
MB		 3918static struct platform_driver wm8994_codec_driver = {
3919 .driver = {
3920 .name = "wm8994-codec",
3921 .owner = THIS_MODULE,
3922 },
f0fba2ad
LG		 3923 .probe = wm8994_probe,
3924 .remove = __devexit_p(wm8994_remove),
9e6e96a1
MB		 3925};
3926
5bbcc3c0 3927module_platform_driver(wm8994_codec_driver);
9e6e96a1
MB		 3928
3929MODULE_DESCRIPTION("ASoC WM8994 driver");
3930MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3931MODULE_LICENSE("GPL");
3932MODULE_ALIAS("platform:wm8994-codec");
kernel source for telekom puls (alcatel/mediatek)