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Merge branch 'for-2.6.34' into for-2.6.35
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / wm8993.c
CommitLineData
942c435b
MB		 1/*
2 * wm8993.c -- WM8993 ALSA SoC audio driver
3 *
be587ef4 4 * Copyright 2009, 2010 Wolfson Microelectronics plc
942c435b
MB		 5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/i2c.h>
b37e399b 19#include <linux/regulator/consumer.h>
942c435b
MB		 20#include <linux/spi/spi.h>
21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/tlv.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/wm8993.h>
29
30#include "wm8993.h"
a2342ae3 31#include "wm_hubs.h"
942c435b 32
b37e399b
MB		 33#define WM8993_NUM_SUPPLIES 6
34static const char *wm8993_supply_names[WM8993_NUM_SUPPLIES] = {
35 "DCVDD",
36 "DBVDD",
37 "AVDD1",
38 "AVDD2",
39 "CPVDD",
40 "SPKVDD",
41};
42
942c435b
MB		 43static u16 wm8993_reg_defaults[WM8993_REGISTER_COUNT] = {
44 0x8993, /* R0 - Software Reset */
45 0x0000, /* R1 - Power Management (1) */
46 0x6000, /* R2 - Power Management (2) */
47 0x0000, /* R3 - Power Management (3) */
48 0x4050, /* R4 - Audio Interface (1) */
49 0x4000, /* R5 - Audio Interface (2) */
50 0x01C8, /* R6 - Clocking 1 */
51 0x0000, /* R7 - Clocking 2 */
52 0x0000, /* R8 - Audio Interface (3) */
53 0x0040, /* R9 - Audio Interface (4) */
54 0x0004, /* R10 - DAC CTRL */
55 0x00C0, /* R11 - Left DAC Digital Volume */
56 0x00C0, /* R12 - Right DAC Digital Volume */
57 0x0000, /* R13 - Digital Side Tone */
58 0x0300, /* R14 - ADC CTRL */
59 0x00C0, /* R15 - Left ADC Digital Volume */
60 0x00C0, /* R16 - Right ADC Digital Volume */
61 0x0000, /* R17 */
62 0x0000, /* R18 - GPIO CTRL 1 */
63 0x0010, /* R19 - GPIO1 */
64 0x0000, /* R20 - IRQ_DEBOUNCE */
65 0x0000, /* R21 */
66 0x8000, /* R22 - GPIOCTRL 2 */
67 0x0800, /* R23 - GPIO_POL */
68 0x008B, /* R24 - Left Line Input 1&2 Volume */
69 0x008B, /* R25 - Left Line Input 3&4 Volume */
70 0x008B, /* R26 - Right Line Input 1&2 Volume */
71 0x008B, /* R27 - Right Line Input 3&4 Volume */
72 0x006D, /* R28 - Left Output Volume */
73 0x006D, /* R29 - Right Output Volume */
74 0x0066, /* R30 - Line Outputs Volume */
75 0x0020, /* R31 - HPOUT2 Volume */
76 0x0079, /* R32 - Left OPGA Volume */
77 0x0079, /* R33 - Right OPGA Volume */
78 0x0003, /* R34 - SPKMIXL Attenuation */
79 0x0003, /* R35 - SPKMIXR Attenuation */
80 0x0011, /* R36 - SPKOUT Mixers */
81 0x0100, /* R37 - SPKOUT Boost */
82 0x0079, /* R38 - Speaker Volume Left */
83 0x0079, /* R39 - Speaker Volume Right */
84 0x0000, /* R40 - Input Mixer2 */
85 0x0000, /* R41 - Input Mixer3 */
86 0x0000, /* R42 - Input Mixer4 */
87 0x0000, /* R43 - Input Mixer5 */
88 0x0000, /* R44 - Input Mixer6 */
89 0x0000, /* R45 - Output Mixer1 */
90 0x0000, /* R46 - Output Mixer2 */
91 0x0000, /* R47 - Output Mixer3 */
92 0x0000, /* R48 - Output Mixer4 */
93 0x0000, /* R49 - Output Mixer5 */
94 0x0000, /* R50 - Output Mixer6 */
95 0x0000, /* R51 - HPOUT2 Mixer */
96 0x0000, /* R52 - Line Mixer1 */
97 0x0000, /* R53 - Line Mixer2 */
98 0x0000, /* R54 - Speaker Mixer */
99 0x0000, /* R55 - Additional Control */
100 0x0000, /* R56 - AntiPOP1 */
101 0x0000, /* R57 - AntiPOP2 */
102 0x0000, /* R58 - MICBIAS */
103 0x0000, /* R59 */
104 0x0000, /* R60 - FLL Control 1 */
105 0x0000, /* R61 - FLL Control 2 */
106 0x0000, /* R62 - FLL Control 3 */
107 0x2EE0, /* R63 - FLL Control 4 */
108 0x0002, /* R64 - FLL Control 5 */
109 0x2287, /* R65 - Clocking 3 */
110 0x025F, /* R66 - Clocking 4 */
111 0x0000, /* R67 - MW Slave Control */
112 0x0000, /* R68 */
113 0x0002, /* R69 - Bus Control 1 */
114 0x0000, /* R70 - Write Sequencer 0 */
115 0x0000, /* R71 - Write Sequencer 1 */
116 0x0000, /* R72 - Write Sequencer 2 */
117 0x0000, /* R73 - Write Sequencer 3 */
118 0x0000, /* R74 - Write Sequencer 4 */
119 0x0000, /* R75 - Write Sequencer 5 */
120 0x1F25, /* R76 - Charge Pump 1 */
121 0x0000, /* R77 */
122 0x0000, /* R78 */
123 0x0000, /* R79 */
124 0x0000, /* R80 */
125 0x0000, /* R81 - Class W 0 */
126 0x0000, /* R82 */
127 0x0000, /* R83 */
128 0x0000, /* R84 - DC Servo 0 */
129 0x054A, /* R85 - DC Servo 1 */
130 0x0000, /* R86 */
131 0x0000, /* R87 - DC Servo 3 */
132 0x0000, /* R88 - DC Servo Readback 0 */
133 0x0000, /* R89 - DC Servo Readback 1 */
134 0x0000, /* R90 - DC Servo Readback 2 */
135 0x0000, /* R91 */
136 0x0000, /* R92 */
137 0x0000, /* R93 */
138 0x0000, /* R94 */
139 0x0000, /* R95 */
140 0x0100, /* R96 - Analogue HP 0 */
141 0x0000, /* R97 */
142 0x0000, /* R98 - EQ1 */
143 0x000C, /* R99 - EQ2 */
144 0x000C, /* R100 - EQ3 */
145 0x000C, /* R101 - EQ4 */
146 0x000C, /* R102 - EQ5 */
147 0x000C, /* R103 - EQ6 */
148 0x0FCA, /* R104 - EQ7 */
149 0x0400, /* R105 - EQ8 */
150 0x00D8, /* R106 - EQ9 */
151 0x1EB5, /* R107 - EQ10 */
152 0xF145, /* R108 - EQ11 */
153 0x0B75, /* R109 - EQ12 */
154 0x01C5, /* R110 - EQ13 */
155 0x1C58, /* R111 - EQ14 */
156 0xF373, /* R112 - EQ15 */
157 0x0A54, /* R113 - EQ16 */
158 0x0558, /* R114 - EQ17 */
159 0x168E, /* R115 - EQ18 */
160 0xF829, /* R116 - EQ19 */
161 0x07AD, /* R117 - EQ20 */
162 0x1103, /* R118 - EQ21 */
163 0x0564, /* R119 - EQ22 */
164 0x0559, /* R120 - EQ23 */
165 0x4000, /* R121 - EQ24 */
166 0x0000, /* R122 - Digital Pulls */
167 0x0F08, /* R123 - DRC Control 1 */
168 0x0000, /* R124 - DRC Control 2 */
169 0x0080, /* R125 - DRC Control 3 */
170 0x0000, /* R126 - DRC Control 4 */
171};
172
173static struct {
174 int ratio;
175 int clk_sys_rate;
176} clk_sys_rates[] = {
177 { 64, 0 },
178 { 128, 1 },
179 { 192, 2 },
180 { 256, 3 },
181 { 384, 4 },
182 { 512, 5 },
183 { 768, 6 },
184 { 1024, 7 },
185 { 1408, 8 },
186 { 1536, 9 },
187};
188
189static struct {
190 int rate;
191 int sample_rate;
192} sample_rates[] = {
193 { 8000, 0 },
194 { 11025, 1 },
195 { 12000, 1 },
196 { 16000, 2 },
197 { 22050, 3 },
198 { 24000, 3 },
199 { 32000, 4 },
200 { 44100, 5 },
201 { 48000, 5 },
202};
203
204static struct {
205 int div; /* *10 due to .5s */
206 int bclk_div;
207} bclk_divs[] = {
208 { 10, 0 },
209 { 15, 1 },
210 { 20, 2 },
211 { 30, 3 },
212 { 40, 4 },
213 { 55, 5 },
214 { 60, 6 },
215 { 80, 7 },
216 { 110, 8 },
217 { 120, 9 },
218 { 160, 10 },
219 { 220, 11 },
220 { 240, 12 },
221 { 320, 13 },
222 { 440, 14 },
223 { 480, 15 },
224};
225
226struct wm8993_priv {
3ed7074c 227 struct wm_hubs_data hubs_data;
942c435b 228 u16 reg_cache[WM8993_REGISTER_COUNT];
b37e399b 229 struct regulator_bulk_data supplies[WM8993_NUM_SUPPLIES];
942c435b
MB		 230 struct wm8993_platform_data pdata;
231 struct snd_soc_codec codec;
232 int master;
233 int sysclk_source;
d3c9e9a1
MB		 234 int tdm_slots;
235 int tdm_width;
942c435b
MB		 236 unsigned int mclk_rate;
237 unsigned int sysclk_rate;
238 unsigned int fs;
239 unsigned int bclk;
240 int class_w_users;
241 unsigned int fll_fref;
242 unsigned int fll_fout;
53242c68 243 int fll_src;
942c435b
MB		 244};
245
942c435b
MB		 246static int wm8993_volatile(unsigned int reg)
247{
248 switch (reg) {
249 case WM8993_SOFTWARE_RESET:
250 case WM8993_DC_SERVO_0:
251 case WM8993_DC_SERVO_READBACK_0:
252 case WM8993_DC_SERVO_READBACK_1:
253 case WM8993_DC_SERVO_READBACK_2:
254 return 1;
255 default:
256 return 0;
257 }
258}
259
942c435b
MB		 260struct _fll_div {
261 u16 fll_fratio;
262 u16 fll_outdiv;
263 u16 fll_clk_ref_div;
264 u16 n;
265 u16 k;
266};
267
268/* The size in bits of the FLL divide multiplied by 10
269 * to allow rounding later */
270#define FIXED_FLL_SIZE ((1 << 16) * 10)
271
272static struct {
273 unsigned int min;
274 unsigned int max;
275 u16 fll_fratio;
276 int ratio;
277} fll_fratios[] = {
278 { 0, 64000, 4, 16 },
279 { 64000, 128000, 3, 8 },
280 { 128000, 256000, 2, 4 },
281 { 256000, 1000000, 1, 2 },
282 { 1000000, 13500000, 0, 1 },
283};
284
285static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
286 unsigned int Fout)
287{
288 u64 Kpart;
289 unsigned int K, Ndiv, Nmod, target;
290 unsigned int div;
291 int i;
292
293 /* Fref must be <=13.5MHz */
294 div = 1;
0c11f655 295 fll_div->fll_clk_ref_div = 0;
942c435b
MB		 296 while ((Fref / div) > 13500000) {
297 div *= 2;
0c11f655 298 fll_div->fll_clk_ref_div++;
942c435b
MB		 299
300 if (div > 8) {
301 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
302 Fref);
303 return -EINVAL;
304 }
305 }
306
307 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
308
309 /* Apply the division for our remaining calculations */
310 Fref /= div;
311
312 /* Fvco should be 90-100MHz; don't check the upper bound */
313 div = 0;
314 target = Fout * 2;
315 while (target < 90000000) {
316 div++;
317 target *= 2;
318 if (div > 7) {
319 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
320 Fout);
321 return -EINVAL;
322 }
323 }
324 fll_div->fll_outdiv = div;
325
326 pr_debug("Fvco=%dHz\n", target);
327
328 /* Find an appropraite FLL_FRATIO and factor it out of the target */
329 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
330 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
331 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
332 target /= fll_fratios[i].ratio;
333 break;
334 }
335 }
336 if (i == ARRAY_SIZE(fll_fratios)) {
337 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
338 return -EINVAL;
339 }
340
341 /* Now, calculate N.K */
342 Ndiv = target / Fref;
343
344 fll_div->n = Ndiv;
345 Nmod = target % Fref;
346 pr_debug("Nmod=%d\n", Nmod);
347
348 /* Calculate fractional part - scale up so we can round. */
349 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
350
351 do_div(Kpart, Fref);
352
353 K = Kpart & 0xFFFFFFFF;
354
355 if ((K % 10) >= 5)
356 K += 5;
357
358 /* Move down to proper range now rounding is done */
359 fll_div->k = K / 10;
360
361 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
362 fll_div->n, fll_div->k,
363 fll_div->fll_fratio, fll_div->fll_outdiv,
364 fll_div->fll_clk_ref_div);
365
366 return 0;
367}
368
85488037 369static int wm8993_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
942c435b
MB		 370 unsigned int Fref, unsigned int Fout)
371{
372 struct snd_soc_codec *codec = dai->codec;
373 struct wm8993_priv *wm8993 = codec->private_data;
374 u16 reg1, reg4, reg5;
375 struct _fll_div fll_div;
376 int ret;
377
378 /* Any change? */
379 if (Fref == wm8993->fll_fref && Fout == wm8993->fll_fout)
380 return 0;
381
382 /* Disable the FLL */
383 if (Fout == 0) {
384 dev_dbg(codec->dev, "FLL disabled\n");
385 wm8993->fll_fref = 0;
386 wm8993->fll_fout = 0;
387
3bf6e421 388 reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1);
942c435b 389 reg1 &= ~WM8993_FLL_ENA;
3bf6e421 390 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1);
942c435b
MB		 391
392 return 0;
393 }
394
395 ret = fll_factors(&fll_div, Fref, Fout);
396 if (ret != 0)
397 return ret;
398
3bf6e421 399 reg5 = snd_soc_read(codec, WM8993_FLL_CONTROL_5);
942c435b
MB		 400 reg5 &= ~WM8993_FLL_CLK_SRC_MASK;
401
402 switch (fll_id) {
403 case WM8993_FLL_MCLK:
404 break;
405
406 case WM8993_FLL_LRCLK:
407 reg5 |= 1;
408 break;
409
410 case WM8993_FLL_BCLK:
411 reg5 |= 2;
412 break;
413
414 default:
415 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
416 return -EINVAL;
417 }
418
419 /* Any FLL configuration change requires that the FLL be
420 * disabled first. */
3bf6e421 421 reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1);
942c435b 422 reg1 &= ~WM8993_FLL_ENA;
3bf6e421 423 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1);
942c435b
MB		 424
425 /* Apply the configuration */
426 if (fll_div.k)
427 reg1 |= WM8993_FLL_FRAC_MASK;
428 else
429 reg1 &= ~WM8993_FLL_FRAC_MASK;
3bf6e421 430 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1);
942c435b 431
3bf6e421
MB		 432 snd_soc_write(codec, WM8993_FLL_CONTROL_2,
433 (fll_div.fll_outdiv << WM8993_FLL_OUTDIV_SHIFT) |
434 (fll_div.fll_fratio << WM8993_FLL_FRATIO_SHIFT));
435 snd_soc_write(codec, WM8993_FLL_CONTROL_3, fll_div.k);
942c435b 436
3bf6e421 437 reg4 = snd_soc_read(codec, WM8993_FLL_CONTROL_4);
942c435b
MB		 438 reg4 &= ~WM8993_FLL_N_MASK;
439 reg4 |= fll_div.n << WM8993_FLL_N_SHIFT;
3bf6e421 440 snd_soc_write(codec, WM8993_FLL_CONTROL_4, reg4);
942c435b
MB		 441
442 reg5 &= ~WM8993_FLL_CLK_REF_DIV_MASK;
443 reg5 |= fll_div.fll_clk_ref_div << WM8993_FLL_CLK_REF_DIV_SHIFT;
3bf6e421 444 snd_soc_write(codec, WM8993_FLL_CONTROL_5, reg5);
942c435b
MB		 445
446 /* Enable the FLL */
3bf6e421 447 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1 | WM8993_FLL_ENA);
942c435b
MB		 448
449 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
450
451 wm8993->fll_fref = Fref;
452 wm8993->fll_fout = Fout;
53242c68 453 wm8993->fll_src = source;
942c435b
MB		 454
455 return 0;
456}
457
458static int configure_clock(struct snd_soc_codec *codec)
459{
460 struct wm8993_priv *wm8993 = codec->private_data;
461 unsigned int reg;
462
463 /* This should be done on init() for bypass paths */
464 switch (wm8993->sysclk_source) {
465 case WM8993_SYSCLK_MCLK:
466 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8993->mclk_rate);
467
3bf6e421 468 reg = snd_soc_read(codec, WM8993_CLOCKING_2);
0182dcc5 469 reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC);
942c435b
MB		 470 if (wm8993->mclk_rate > 13500000) {
471 reg |= WM8993_MCLK_DIV;
472 wm8993->sysclk_rate = wm8993->mclk_rate / 2;
473 } else {
474 reg &= ~WM8993_MCLK_DIV;
475 wm8993->sysclk_rate = wm8993->mclk_rate;
476 }
3bf6e421 477 snd_soc_write(codec, WM8993_CLOCKING_2, reg);
942c435b
MB		 478 break;
479
480 case WM8993_SYSCLK_FLL:
481 dev_dbg(codec->dev, "Using %dHz FLL clock\n",
482 wm8993->fll_fout);
483
3bf6e421 484 reg = snd_soc_read(codec, WM8993_CLOCKING_2);
942c435b
MB		 485 reg |= WM8993_SYSCLK_SRC;
486 if (wm8993->fll_fout > 13500000) {
487 reg |= WM8993_MCLK_DIV;
488 wm8993->sysclk_rate = wm8993->fll_fout / 2;
489 } else {
490 reg &= ~WM8993_MCLK_DIV;
491 wm8993->sysclk_rate = wm8993->fll_fout;
492 }
3bf6e421 493 snd_soc_write(codec, WM8993_CLOCKING_2, reg);
942c435b
MB		 494 break;
495
496 default:
497 dev_err(codec->dev, "System clock not configured\n");
498 return -EINVAL;
499 }
500
501 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8993->sysclk_rate);
502
503 return 0;
504}
505
942c435b
MB		 506static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
507static const DECLARE_TLV_DB_SCALE(drc_comp_threash, -4500, 75, 0);
508static const DECLARE_TLV_DB_SCALE(drc_comp_amp, -2250, 75, 0);
509static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
510static const unsigned int drc_max_tlv[] = {
511 TLV_DB_RANGE_HEAD(4),
512 0, 2, TLV_DB_SCALE_ITEM(1200, 600, 0),
513 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
514};
515static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
516static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -1800, 300, 0);
517static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
518static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
519static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
942c435b
MB		 520
521static const char *dac_deemph_text[] = {
522 "None",
523 "32kHz",
524 "44.1kHz",
525 "48kHz",
526};
527
528static const struct soc_enum dac_deemph =
529 SOC_ENUM_SINGLE(WM8993_DAC_CTRL, 4, 4, dac_deemph_text);
530
531static const char *adc_hpf_text[] = {
532 "Hi-Fi",
533 "Voice 1",
534 "Voice 2",
535 "Voice 3",
536};
537
538static const struct soc_enum adc_hpf =
539 SOC_ENUM_SINGLE(WM8993_ADC_CTRL, 5, 4, adc_hpf_text);
540
541static const char *drc_path_text[] = {
542 "ADC",
543 "DAC"
544};
545
546static const struct soc_enum drc_path =
547 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 14, 2, drc_path_text);
548
549static const char *drc_r0_text[] = {
550 "1",
551 "1/2",
552 "1/4",
553 "1/8",
554 "1/16",
555 "0",
556};
557
558static const struct soc_enum drc_r0 =
559 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 8, 6, drc_r0_text);
560
561static const char *drc_r1_text[] = {
562 "1",
563 "1/2",
564 "1/4",
565 "1/8",
566 "0",
567};
568
569static const struct soc_enum drc_r1 =
570 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_4, 13, 5, drc_r1_text);
571
572static const char *drc_attack_text[] = {
573 "Reserved",
574 "181us",
575 "363us",
576 "726us",
577 "1.45ms",
578 "2.9ms",
579 "5.8ms",
580 "11.6ms",
581 "23.2ms",
582 "46.4ms",
583 "92.8ms",
584 "185.6ms",
585};
586
587static const struct soc_enum drc_attack =
588 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 12, 12, drc_attack_text);
589
590static const char *drc_decay_text[] = {
591 "186ms",
592 "372ms",
593 "743ms",
594 "1.49s",
595 "2.97ms",
596 "5.94ms",
597 "11.89ms",
598 "23.78ms",
599 "47.56ms",
600};
601
602static const struct soc_enum drc_decay =
603 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 8, 9, drc_decay_text);
604
605static const char *drc_ff_text[] = {
606 "5 samples",
607 "9 samples",
608};
609
610static const struct soc_enum drc_ff =
611 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 7, 2, drc_ff_text);
612
613static const char *drc_qr_rate_text[] = {
614 "0.725ms",
615 "1.45ms",
616 "5.8ms",
617};
618
619static const struct soc_enum drc_qr_rate =
620 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 0, 3, drc_qr_rate_text);
621
622static const char *drc_smooth_text[] = {
623 "Low",
624 "Medium",
625 "High",
626};
627
628static const struct soc_enum drc_smooth =
629 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 4, 3, drc_smooth_text);
630
942c435b 631static const struct snd_kcontrol_new wm8993_snd_controls[] = {
942c435b
MB		 632SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8993_DIGITAL_SIDE_TONE,
633 5, 9, 12, 0, sidetone_tlv),
634
635SOC_SINGLE("DRC Switch", WM8993_DRC_CONTROL_1, 15, 1, 0),
636SOC_ENUM("DRC Path", drc_path),
af901ca1 637SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8993_DRC_CONTROL_2,
942c435b
MB		 638 2, 60, 1, drc_comp_threash),
639SOC_SINGLE_TLV("DRC Compressor Amplitude Volume", WM8993_DRC_CONTROL_3,
640 11, 30, 1, drc_comp_amp),
641SOC_ENUM("DRC R0", drc_r0),
642SOC_ENUM("DRC R1", drc_r1),
643SOC_SINGLE_TLV("DRC Minimum Volume", WM8993_DRC_CONTROL_1, 2, 3, 1,
644 drc_min_tlv),
645SOC_SINGLE_TLV("DRC Maximum Volume", WM8993_DRC_CONTROL_1, 0, 3, 0,
646 drc_max_tlv),
647SOC_ENUM("DRC Attack Rate", drc_attack),
648SOC_ENUM("DRC Decay Rate", drc_decay),
649SOC_ENUM("DRC FF Delay", drc_ff),
650SOC_SINGLE("DRC Anti-clip Switch", WM8993_DRC_CONTROL_1, 9, 1, 0),
651SOC_SINGLE("DRC Quick Release Switch", WM8993_DRC_CONTROL_1, 10, 1, 0),
652SOC_SINGLE_TLV("DRC Quick Release Volume", WM8993_DRC_CONTROL_3, 2, 3, 0,
653 drc_qr_tlv),
654SOC_ENUM("DRC Quick Release Rate", drc_qr_rate),
655SOC_SINGLE("DRC Smoothing Switch", WM8993_DRC_CONTROL_1, 11, 1, 0),
656SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8993_DRC_CONTROL_1, 8, 1, 0),
af901ca1 657SOC_ENUM("DRC Smoothing Hysteresis Threshold", drc_smooth),
942c435b
MB		 658SOC_SINGLE_TLV("DRC Startup Volume", WM8993_DRC_CONTROL_4, 8, 18, 0,
659 drc_startup_tlv),
660
661SOC_SINGLE("EQ Switch", WM8993_EQ1, 0, 1, 0),
662
663SOC_DOUBLE_R_TLV("Capture Volume", WM8993_LEFT_ADC_DIGITAL_VOLUME,
664 WM8993_RIGHT_ADC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
665SOC_SINGLE("ADC High Pass Filter Switch", WM8993_ADC_CTRL, 8, 1, 0),
666SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
667
668SOC_DOUBLE_R_TLV("Playback Volume", WM8993_LEFT_DAC_DIGITAL_VOLUME,
669 WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
670SOC_SINGLE_TLV("Playback Boost Volume", WM8993_AUDIO_INTERFACE_2, 10, 3, 0,
671 dac_boost_tlv),
672SOC_ENUM("DAC Deemphasis", dac_deemph),
673
942c435b 674SOC_SINGLE_TLV("SPKL DAC Volume", WM8993_SPKMIXL_ATTENUATION,
a2342ae3 675 2, 1, 1, wm_hubs_spkmix_tlv),
942c435b 676
a2342ae3
MB		 677SOC_SINGLE_TLV("SPKR DAC Volume", WM8993_SPKMIXR_ATTENUATION,
678 2, 1, 1, wm_hubs_spkmix_tlv),
942c435b
MB		 679};
680
681static const struct snd_kcontrol_new wm8993_eq_controls[] = {
682SOC_SINGLE_TLV("EQ1 Volume", WM8993_EQ2, 0, 24, 0, eq_tlv),
683SOC_SINGLE_TLV("EQ2 Volume", WM8993_EQ3, 0, 24, 0, eq_tlv),
684SOC_SINGLE_TLV("EQ3 Volume", WM8993_EQ4, 0, 24, 0, eq_tlv),
685SOC_SINGLE_TLV("EQ4 Volume", WM8993_EQ5, 0, 24, 0, eq_tlv),
686SOC_SINGLE_TLV("EQ5 Volume", WM8993_EQ6, 0, 24, 0, eq_tlv),
687};
688
942c435b
MB		 689static int clk_sys_event(struct snd_soc_dapm_widget *w,
690 struct snd_kcontrol *kcontrol, int event)
691{
692 struct snd_soc_codec *codec = w->codec;
693
694 switch (event) {
695 case SND_SOC_DAPM_PRE_PMU:
696 return configure_clock(codec);
697
698 case SND_SOC_DAPM_POST_PMD:
699 break;
700 }
701
702 return 0;
703}
704
705/*
706 * When used with DAC outputs only the WM8993 charge pump supports
707 * operation in class W mode, providing very low power consumption
708 * when used with digital sources. Enable and disable this mode
709 * automatically depending on the mixer configuration.
710 *
711 * Currently the only supported paths are the direct DAC->headphone
712 * paths (which provide minimum power consumption anyway).
713 */
a2342ae3
MB		 714static int class_w_put(struct snd_kcontrol *kcontrol,
715 struct snd_ctl_elem_value *ucontrol)
942c435b
MB		 716{
717 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
718 struct snd_soc_codec *codec = widget->codec;
719 struct wm8993_priv *wm8993 = codec->private_data;
720 int ret;
721
722 /* Turn it off if we're using the main output mixer */
723 if (ucontrol->value.integer.value[0] == 0) {
724 if (wm8993->class_w_users == 0) {
725 dev_dbg(codec->dev, "Disabling Class W\n");
726 snd_soc_update_bits(codec, WM8993_CLASS_W_0,
727 WM8993_CP_DYN_FREQ |
728 WM8993_CP_DYN_V,
729 0);
730 }
731 wm8993->class_w_users++;
732 }
733
734 /* Implement the change */
735 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
736
737 /* Enable it if we're using the direct DAC path */
738 if (ucontrol->value.integer.value[0] == 1) {
739 if (wm8993->class_w_users == 1) {
740 dev_dbg(codec->dev, "Enabling Class W\n");
741 snd_soc_update_bits(codec, WM8993_CLASS_W_0,
742 WM8993_CP_DYN_FREQ |
743 WM8993_CP_DYN_V,
744 WM8993_CP_DYN_FREQ |
745 WM8993_CP_DYN_V);
746 }
747 wm8993->class_w_users--;
748 }
749
750 dev_dbg(codec->dev, "Indirect DAC use count now %d\n",
751 wm8993->class_w_users);
752
753 return ret;
754}
755
756#define SOC_DAPM_ENUM_W(xname, xenum) \
757{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
758 .info = snd_soc_info_enum_double, \
759 .get = snd_soc_dapm_get_enum_double, \
a2342ae3 760 .put = class_w_put, \
942c435b
MB		 761 .private_value = (unsigned long)&xenum }
762
942c435b
MB		 763static const char *hp_mux_text[] = {
764 "Mixer",
765 "DAC",
766};
767
768static const struct soc_enum hpl_enum =
769 SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER1, 8, 2, hp_mux_text);
770
771static const struct snd_kcontrol_new hpl_mux =
772 SOC_DAPM_ENUM_W("Left Headphone Mux", hpl_enum);
773
774static const struct soc_enum hpr_enum =
775 SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER2, 8, 2, hp_mux_text);
776
777static const struct snd_kcontrol_new hpr_mux =
778 SOC_DAPM_ENUM_W("Right Headphone Mux", hpr_enum);
779
a2342ae3
MB		 780static const struct snd_kcontrol_new left_speaker_mixer[] = {
781SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 7, 1, 0),
782SOC_DAPM_SINGLE("IN1LP Switch", WM8993_SPEAKER_MIXER, 5, 1, 0),
783SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 3, 1, 0),
784SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
942c435b
MB		 785};
786
a2342ae3
MB		 787static const struct snd_kcontrol_new right_speaker_mixer[] = {
788SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
789SOC_DAPM_SINGLE("IN1RP Switch", WM8993_SPEAKER_MIXER, 4, 1, 0),
790SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 2, 1, 0),
791SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 0, 1, 0),
942c435b
MB		 792};
793
59ae07a5
MB		 794static const char *aif_text[] = {
795 "Left", "Right"
796};
797
798static const struct soc_enum aifoutl_enum =
799 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_1, 15, 2, aif_text);
800
801static const struct snd_kcontrol_new aifoutl_mux =
802 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
803
804static const struct soc_enum aifoutr_enum =
805 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_1, 14, 2, aif_text);
806
807static const struct snd_kcontrol_new aifoutr_mux =
808 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
809
810static const struct soc_enum aifinl_enum =
811 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_2, 15, 2, aif_text);
812
813static const struct snd_kcontrol_new aifinl_mux =
814 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
815
816static const struct soc_enum aifinr_enum =
817 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_2, 14, 2, aif_text);
818
819static const struct snd_kcontrol_new aifinr_mux =
820 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
821
822static const char *sidetone_text[] = {
823 "None", "Left", "Right"
824};
825
826static const struct soc_enum sidetonel_enum =
827 SOC_ENUM_SINGLE(WM8993_DIGITAL_SIDE_TONE, 2, 3, sidetone_text);
828
829static const struct snd_kcontrol_new sidetonel_mux =
830 SOC_DAPM_ENUM("Left Sidetone", sidetonel_enum);
831
832static const struct soc_enum sidetoner_enum =
833 SOC_ENUM_SINGLE(WM8993_DIGITAL_SIDE_TONE, 0, 3, sidetone_text);
834
835static const struct snd_kcontrol_new sidetoner_mux =
836 SOC_DAPM_ENUM("Right Sidetone", sidetoner_enum);
837
942c435b 838static const struct snd_soc_dapm_widget wm8993_dapm_widgets[] = {
942c435b
MB		 839SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8993_BUS_CONTROL_1, 1, 0, clk_sys_event,
840 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
841SND_SOC_DAPM_SUPPLY("TOCLK", WM8993_CLOCKING_1, 14, 0, NULL, 0),
842SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8993_CLOCKING_3, 0, 0, NULL, 0),
843
59ae07a5
MB		 844SND_SOC_DAPM_ADC("ADCL", NULL, WM8993_POWER_MANAGEMENT_2, 1, 0),
845SND_SOC_DAPM_ADC("ADCR", NULL, WM8993_POWER_MANAGEMENT_2, 0, 0),
846
847SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
848SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
849
850SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
851SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
942c435b 852
59ae07a5
MB		 853SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
854SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
942c435b 855
59ae07a5
MB		 856SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
857SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
858
859SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &sidetonel_mux),
860SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &sidetoner_mux),
861
862SND_SOC_DAPM_DAC("DACL", NULL, WM8993_POWER_MANAGEMENT_3, 1, 0),
863SND_SOC_DAPM_DAC("DACR", NULL, WM8993_POWER_MANAGEMENT_3, 0, 0),
942c435b 864
a2342ae3
MB		 865SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
866SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
942c435b
MB		 867
868SND_SOC_DAPM_MIXER("SPKL", WM8993_POWER_MANAGEMENT_3, 8, 0,
869 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
870SND_SOC_DAPM_MIXER("SPKR", WM8993_POWER_MANAGEMENT_3, 9, 0,
871 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
872
942c435b
MB		 873};
874
875static const struct snd_soc_dapm_route routes[] = {
942c435b
MB		 876 { "ADCL", NULL, "CLK_SYS" },
877 { "ADCL", NULL, "CLK_DSP" },
942c435b
MB		 878 { "ADCR", NULL, "CLK_SYS" },
879 { "ADCR", NULL, "CLK_DSP" },
880
59ae07a5
MB		 881 { "AIFOUTL Mux", "Left", "ADCL" },
882 { "AIFOUTL Mux", "Right", "ADCR" },
883 { "AIFOUTR Mux", "Left", "ADCL" },
884 { "AIFOUTR Mux", "Right", "ADCR" },
885
886 { "AIFOUTL", NULL, "AIFOUTL Mux" },
887 { "AIFOUTR", NULL, "AIFOUTR Mux" },
888
889 { "DACL Mux", "Left", "AIFINL" },
890 { "DACL Mux", "Right", "AIFINR" },
891 { "DACR Mux", "Left", "AIFINL" },
892 { "DACR Mux", "Right", "AIFINR" },
893
894 { "DACL Sidetone", "Left", "ADCL" },
895 { "DACL Sidetone", "Right", "ADCR" },
896 { "DACR Sidetone", "Left", "ADCL" },
897 { "DACR Sidetone", "Right", "ADCR" },
898
942c435b
MB		 899 { "DACL", NULL, "CLK_SYS" },
900 { "DACL", NULL, "CLK_DSP" },
59ae07a5
MB		 901 { "DACL", NULL, "DACL Mux" },
902 { "DACL", NULL, "DACL Sidetone" },
942c435b
MB		 903 { "DACR", NULL, "CLK_SYS" },
904 { "DACR", NULL, "CLK_DSP" },
59ae07a5
MB		 905 { "DACR", NULL, "DACR Mux" },
906 { "DACR", NULL, "DACR Sidetone" },
942c435b 907
942c435b
MB		 908 { "Left Output Mixer", "DAC Switch", "DACL" },
909
942c435b
MB		 910 { "Right Output Mixer", "DAC Switch", "DACR" },
911
942c435b 912 { "Left Output PGA", NULL, "CLK_SYS" },
942c435b 913
942c435b 914 { "Right Output PGA", NULL, "CLK_SYS" },
942c435b 915
942c435b
MB		 916 { "SPKL", "DAC Switch", "DACL" },
917 { "SPKL", NULL, "CLK_SYS" },
942c435b 918
942c435b
MB		 919 { "SPKR", "DAC Switch", "DACR" },
920 { "SPKR", NULL, "CLK_SYS" },
942c435b
MB		 921
922 { "Left Headphone Mux", "DAC", "DACL" },
942c435b 923 { "Right Headphone Mux", "DAC", "DACR" },
942c435b
MB		 924};
925
cf56f627
MB		 926static void wm8993_cache_restore(struct snd_soc_codec *codec)
927{
928 u16 *cache = codec->reg_cache;
929 int i;
930
931 if (!codec->cache_sync)
932 return;
933
934 /* Reenable hardware writes */
935 codec->cache_only = 0;
936
937 /* Restore the register settings */
938 for (i = 1; i < WM8993_MAX_REGISTER; i++) {
939 if (cache[i] == wm8993_reg_defaults[i])
940 continue;
941 snd_soc_write(codec, i, cache[i]);
942 }
943
944 /* We're in sync again */
945 codec->cache_sync = 0;
946}
947
942c435b
MB		 948static int wm8993_set_bias_level(struct snd_soc_codec *codec,
949 enum snd_soc_bias_level level)
950{
951 struct wm8993_priv *wm8993 = codec->private_data;
cf56f627 952 int ret;
942c435b
MB		 953
954 switch (level) {
955 case SND_SOC_BIAS_ON:
956 case SND_SOC_BIAS_PREPARE:
957 /* VMID=2*40k */
958 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
959 WM8993_VMID_SEL_MASK, 0x2);
960 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2,
961 WM8993_TSHUT_ENA, WM8993_TSHUT_ENA);
962 break;
963
964 case SND_SOC_BIAS_STANDBY:
965 if (codec->bias_level == SND_SOC_BIAS_OFF) {
cf56f627
MB		 966 ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
967 wm8993->supplies);
968 if (ret != 0)
969 return ret;
970
971 wm8993_cache_restore(codec);
972
3ed7074c
MB		 973 /* Tune DC servo configuration */
974 snd_soc_write(codec, 0x44, 3);
975 snd_soc_write(codec, 0x56, 3);
976 snd_soc_write(codec, 0x44, 0);
977
942c435b
MB		 978 /* Bring up VMID with fast soft start */
979 snd_soc_update_bits(codec, WM8993_ANTIPOP2,
980 WM8993_STARTUP_BIAS_ENA |
981 WM8993_VMID_BUF_ENA |
982 WM8993_VMID_RAMP_MASK |
983 WM8993_BIAS_SRC,
984 WM8993_STARTUP_BIAS_ENA |
985 WM8993_VMID_BUF_ENA |
986 WM8993_VMID_RAMP_MASK |
987 WM8993_BIAS_SRC);
988
989 /* If either line output is single ended we
990 * need the VMID buffer */
991 if (!wm8993->pdata.lineout1_diff ||
992 !wm8993->pdata.lineout2_diff)
993 snd_soc_update_bits(codec, WM8993_ANTIPOP1,
994 WM8993_LINEOUT_VMID_BUF_ENA,
995 WM8993_LINEOUT_VMID_BUF_ENA);
996
997 /* VMID=2*40k */
998 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
999 WM8993_VMID_SEL_MASK |
1000 WM8993_BIAS_ENA,
1001 WM8993_BIAS_ENA | 0x2);
1002 msleep(32);
1003
1004 /* Switch to normal bias */
1005 snd_soc_update_bits(codec, WM8993_ANTIPOP2,
1006 WM8993_BIAS_SRC |
1007 WM8993_STARTUP_BIAS_ENA, 0);
1008 }
1009
1010 /* VMID=2*240k */
1011 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1012 WM8993_VMID_SEL_MASK, 0x4);
1013
1014 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2,
1015 WM8993_TSHUT_ENA, 0);
1016 break;
1017
1018 case SND_SOC_BIAS_OFF:
1019 snd_soc_update_bits(codec, WM8993_ANTIPOP1,
1020 WM8993_LINEOUT_VMID_BUF_ENA, 0);
1021
1022 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1023 WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA,
1024 0);
cf56f627
MB		 1025
1026#ifdef CONFIG_REGULATOR
1027 /* Post 2.6.34 we will be able to get a callback when
1028 * the regulators are disabled which we can use but
1029 * for now just assume that the power will be cut if
1030 * the regulator API is in use.
1031 */
1032 codec->cache_sync = 1;
1033#endif
1034
1035 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies),
1036 wm8993->supplies);
942c435b
MB		 1037 break;
1038 }
1039
1040 codec->bias_level = level;
1041
1042 return 0;
1043}
1044
1045static int wm8993_set_sysclk(struct snd_soc_dai *codec_dai,
1046 int clk_id, unsigned int freq, int dir)
1047{
1048 struct snd_soc_codec *codec = codec_dai->codec;
1049 struct wm8993_priv *wm8993 = codec->private_data;
1050
1051 switch (clk_id) {
1052 case WM8993_SYSCLK_MCLK:
1053 wm8993->mclk_rate = freq;
1054 case WM8993_SYSCLK_FLL:
1055 wm8993->sysclk_source = clk_id;
1056 break;
1057
1058 default:
1059 return -EINVAL;
1060 }
1061
1062 return 0;
1063}
1064
1065static int wm8993_set_dai_fmt(struct snd_soc_dai *dai,
1066 unsigned int fmt)
1067{
1068 struct snd_soc_codec *codec = dai->codec;
1069 struct wm8993_priv *wm8993 = codec->private_data;
3bf6e421
MB		 1070 unsigned int aif1 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_1);
1071 unsigned int aif4 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_4);
942c435b
MB		 1072
1073 aif1 &= ~(WM8993_BCLK_DIR | WM8993_AIF_BCLK_INV |
1074 WM8993_AIF_LRCLK_INV | WM8993_AIF_FMT_MASK);
1075 aif4 &= ~WM8993_LRCLK_DIR;
1076
1077 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1078 case SND_SOC_DAIFMT_CBS_CFS:
1079 wm8993->master = 0;
1080 break;
1081 case SND_SOC_DAIFMT_CBS_CFM:
1082 aif4 |= WM8993_LRCLK_DIR;
1083 wm8993->master = 1;
1084 break;
1085 case SND_SOC_DAIFMT_CBM_CFS:
1086 aif1 |= WM8993_BCLK_DIR;
1087 wm8993->master = 1;
1088 break;
1089 case SND_SOC_DAIFMT_CBM_CFM:
1090 aif1 |= WM8993_BCLK_DIR;
1091 aif4 |= WM8993_LRCLK_DIR;
1092 wm8993->master = 1;
1093 break;
1094 default:
1095 return -EINVAL;
1096 }
1097
1098 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1099 case SND_SOC_DAIFMT_DSP_B:
1100 aif1 |= WM8993_AIF_LRCLK_INV;
1101 case SND_SOC_DAIFMT_DSP_A:
1102 aif1 |= 0x18;
1103 break;
1104 case SND_SOC_DAIFMT_I2S:
1105 aif1 |= 0x10;
1106 break;
1107 case SND_SOC_DAIFMT_RIGHT_J:
1108 break;
1109 case SND_SOC_DAIFMT_LEFT_J:
1110 aif1 |= 0x8;
1111 break;
1112 default:
1113 return -EINVAL;
1114 }
1115
1116 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1117 case SND_SOC_DAIFMT_DSP_A:
1118 case SND_SOC_DAIFMT_DSP_B:
1119 /* frame inversion not valid for DSP modes */
1120 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1121 case SND_SOC_DAIFMT_NB_NF:
1122 break;
1123 case SND_SOC_DAIFMT_IB_NF:
1124 aif1 |= WM8993_AIF_BCLK_INV;
1125 break;
1126 default:
1127 return -EINVAL;
1128 }
1129 break;
1130
1131 case SND_SOC_DAIFMT_I2S:
1132 case SND_SOC_DAIFMT_RIGHT_J:
1133 case SND_SOC_DAIFMT_LEFT_J:
1134 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1135 case SND_SOC_DAIFMT_NB_NF:
1136 break;
1137 case SND_SOC_DAIFMT_IB_IF:
1138 aif1 |= WM8993_AIF_BCLK_INV | WM8993_AIF_LRCLK_INV;
1139 break;
1140 case SND_SOC_DAIFMT_IB_NF:
1141 aif1 |= WM8993_AIF_BCLK_INV;
1142 break;
1143 case SND_SOC_DAIFMT_NB_IF:
1144 aif1 |= WM8993_AIF_LRCLK_INV;
1145 break;
1146 default:
1147 return -EINVAL;
1148 }
1149 break;
1150 default:
1151 return -EINVAL;
1152 }
1153
3bf6e421
MB		 1154 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_1, aif1);
1155 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_4, aif4);
942c435b
MB		 1156
1157 return 0;
1158}
1159
1160static int wm8993_hw_params(struct snd_pcm_substream *substream,
1161 struct snd_pcm_hw_params *params,
1162 struct snd_soc_dai *dai)
1163{
1164 struct snd_soc_codec *codec = dai->codec;
1165 struct wm8993_priv *wm8993 = codec->private_data;
1166 int ret, i, best, best_val, cur_val;
1167 unsigned int clocking1, clocking3, aif1, aif4;
1168
3bf6e421 1169 clocking1 = snd_soc_read(codec, WM8993_CLOCKING_1);
942c435b
MB		 1170 clocking1 &= ~WM8993_BCLK_DIV_MASK;
1171
3bf6e421 1172 clocking3 = snd_soc_read(codec, WM8993_CLOCKING_3);
942c435b
MB		 1173 clocking3 &= ~(WM8993_CLK_SYS_RATE_MASK | WM8993_SAMPLE_RATE_MASK);
1174
3bf6e421 1175 aif1 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_1);
942c435b
MB		 1176 aif1 &= ~WM8993_AIF_WL_MASK;
1177
3bf6e421 1178 aif4 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_4);
942c435b
MB		 1179 aif4 &= ~WM8993_LRCLK_RATE_MASK;
1180
1181 /* What BCLK do we need? */
1182 wm8993->fs = params_rate(params);
1183 wm8993->bclk = 2 * wm8993->fs;
d3c9e9a1
MB		 1184 if (wm8993->tdm_slots) {
1185 dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n",
1186 wm8993->tdm_slots, wm8993->tdm_width);
1187 wm8993->bclk *= wm8993->tdm_width * wm8993->tdm_slots;
1188 } else {
1189 switch (params_format(params)) {
1190 case SNDRV_PCM_FORMAT_S16_LE:
1191 wm8993->bclk *= 16;
1192 break;
1193 case SNDRV_PCM_FORMAT_S20_3LE:
1194 wm8993->bclk *= 20;
1195 aif1 |= 0x8;
1196 break;
1197 case SNDRV_PCM_FORMAT_S24_LE:
1198 wm8993->bclk *= 24;
1199 aif1 |= 0x10;
1200 break;
1201 case SNDRV_PCM_FORMAT_S32_LE:
1202 wm8993->bclk *= 32;
1203 aif1 |= 0x18;
1204 break;
1205 default:
1206 return -EINVAL;
1207 }
942c435b
MB		 1208 }
1209
1210 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8993->bclk);
1211
1212 ret = configure_clock(codec);
1213 if (ret != 0)
1214 return ret;
1215
1216 /* Select nearest CLK_SYS_RATE */
1217 best = 0;
1218 best_val = abs((wm8993->sysclk_rate / clk_sys_rates[0].ratio)
1219 - wm8993->fs);
1220 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1221 cur_val = abs((wm8993->sysclk_rate /
1222 clk_sys_rates[i].ratio) - wm8993->fs);;
1223 if (cur_val < best_val) {
1224 best = i;
1225 best_val = cur_val;
1226 }
1227 }
1228 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1229 clk_sys_rates[best].ratio);
1230 clocking3 |= (clk_sys_rates[best].clk_sys_rate
1231 << WM8993_CLK_SYS_RATE_SHIFT);
1232
1233 /* SAMPLE_RATE */
1234 best = 0;
1235 best_val = abs(wm8993->fs - sample_rates[0].rate);
1236 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1237 /* Closest match */
1238 cur_val = abs(wm8993->fs - sample_rates[i].rate);
1239 if (cur_val < best_val) {
1240 best = i;
1241 best_val = cur_val;
1242 }
1243 }
1244 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1245 sample_rates[best].rate);
e465d544
MB		 1246 clocking3 |= (sample_rates[best].sample_rate
1247 << WM8993_SAMPLE_RATE_SHIFT);
942c435b
MB		 1248
1249 /* BCLK_DIV */
1250 best = 0;
1251 best_val = INT_MAX;
1252 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1253 cur_val = ((wm8993->sysclk_rate * 10) / bclk_divs[i].div)
1254 - wm8993->bclk;
1255 if (cur_val < 0) /* Table is sorted */
1256 break;
1257 if (cur_val < best_val) {
1258 best = i;
1259 best_val = cur_val;
1260 }
1261 }
1262 wm8993->bclk = (wm8993->sysclk_rate * 10) / bclk_divs[best].div;
1263 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1264 bclk_divs[best].div, wm8993->bclk);
1265 clocking1 |= bclk_divs[best].bclk_div << WM8993_BCLK_DIV_SHIFT;
1266
1267 /* LRCLK is a simple fraction of BCLK */
1268 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8993->bclk / wm8993->fs);
1269 aif4 |= wm8993->bclk / wm8993->fs;
1270
3bf6e421
MB		 1271 snd_soc_write(codec, WM8993_CLOCKING_1, clocking1);
1272 snd_soc_write(codec, WM8993_CLOCKING_3, clocking3);
1273 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_1, aif1);
1274 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_4, aif4);
942c435b
MB		 1275
1276 /* ReTune Mobile? */
1277 if (wm8993->pdata.num_retune_configs) {
3bf6e421 1278 u16 eq1 = snd_soc_read(codec, WM8993_EQ1);
942c435b
MB		 1279 struct wm8993_retune_mobile_setting *s;
1280
1281 best = 0;
1282 best_val = abs(wm8993->pdata.retune_configs[0].rate
1283 - wm8993->fs);
1284 for (i = 0; i < wm8993->pdata.num_retune_configs; i++) {
1285 cur_val = abs(wm8993->pdata.retune_configs[i].rate
1286 - wm8993->fs);
1287 if (cur_val < best_val) {
1288 best_val = cur_val;
1289 best = i;
1290 }
1291 }
1292 s = &wm8993->pdata.retune_configs[best];
1293
1294 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
1295 s->name, s->rate);
1296
1297 /* Disable EQ while we reconfigure */
1298 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, 0);
1299
1300 for (i = 1; i < ARRAY_SIZE(s->config); i++)
3bf6e421 1301 snd_soc_write(codec, WM8993_EQ1 + i, s->config[i]);
942c435b
MB		 1302
1303 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, eq1);
1304 }
1305
1306 return 0;
1307}
1308
1309static int wm8993_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1310{
1311 struct snd_soc_codec *codec = codec_dai->codec;
1312 unsigned int reg;
1313
3bf6e421 1314 reg = snd_soc_read(codec, WM8993_DAC_CTRL);
942c435b
MB		 1315
1316 if (mute)
1317 reg |= WM8993_DAC_MUTE;
1318 else
1319 reg &= ~WM8993_DAC_MUTE;
1320
3bf6e421 1321 snd_soc_write(codec, WM8993_DAC_CTRL, reg);
942c435b
MB		 1322
1323 return 0;
1324}
1325
d3c9e9a1
MB		 1326static int wm8993_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1327 unsigned int rx_mask, int slots, int slot_width)
1328{
1329 struct snd_soc_codec *codec = dai->codec;
1330 struct wm8993_priv *wm8993 = codec->private_data;
1331 int aif1 = 0;
1332 int aif2 = 0;
1333
1334 /* Don't need to validate anything if we're turning off TDM */
1335 if (slots == 0) {
1336 wm8993->tdm_slots = 0;
1337 goto out;
1338 }
1339
1340 /* Note that we allow configurations we can't handle ourselves -
1341 * for example, we can generate clocks for slots 2 and up even if
1342 * we can't use those slots ourselves.
1343 */
1344 aif1 |= WM8993_AIFADC_TDM;
1345 aif2 |= WM8993_AIFDAC_TDM;
1346
1347 switch (rx_mask) {
1348 case 3:
1349 break;
1350 case 0xc:
1351 aif1 |= WM8993_AIFADC_TDM_CHAN;
1352 break;
1353 default:
1354 return -EINVAL;
1355 }
1356
1357
1358 switch (tx_mask) {
1359 case 3:
1360 break;
1361 case 0xc:
1362 aif2 |= WM8993_AIFDAC_TDM_CHAN;
1363 break;
1364 default:
1365 return -EINVAL;
1366 }
1367
1368out:
1369 wm8993->tdm_width = slot_width;
1370 wm8993->tdm_slots = slots / 2;
1371
1372 snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_1,
1373 WM8993_AIFADC_TDM | WM8993_AIFADC_TDM_CHAN, aif1);
1374 snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_2,
1375 WM8993_AIFDAC_TDM | WM8993_AIFDAC_TDM_CHAN, aif2);
1376
1377 return 0;
1378}
1379
942c435b
MB		 1380static struct snd_soc_dai_ops wm8993_ops = {
1381 .set_sysclk = wm8993_set_sysclk,
1382 .set_fmt = wm8993_set_dai_fmt,
1383 .hw_params = wm8993_hw_params,
1384 .digital_mute = wm8993_digital_mute,
1385 .set_pll = wm8993_set_fll,
d3c9e9a1 1386 .set_tdm_slot = wm8993_set_tdm_slot,
942c435b
MB		 1387};
1388
1389#define WM8993_RATES SNDRV_PCM_RATE_8000_48000
1390
1391#define WM8993_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1392 SNDRV_PCM_FMTBIT_S20_3LE |\
1393 SNDRV_PCM_FMTBIT_S24_LE |\
1394 SNDRV_PCM_FMTBIT_S32_LE)
1395
1396struct snd_soc_dai wm8993_dai = {
1397 .name = "WM8993",
1398 .playback = {
1399 .stream_name = "Playback",
1400 .channels_min = 1,
1401 .channels_max = 2,
1402 .rates = WM8993_RATES,
1403 .formats = WM8993_FORMATS,
1404 },
1405 .capture = {
1406 .stream_name = "Capture",
1407 .channels_min = 1,
1408 .channels_max = 2,
1409 .rates = WM8993_RATES,
1410 .formats = WM8993_FORMATS,
1411 },
1412 .ops = &wm8993_ops,
1413 .symmetric_rates = 1,
1414};
1415EXPORT_SYMBOL_GPL(wm8993_dai);
1416
1417static struct snd_soc_codec *wm8993_codec;
1418
1419static int wm8993_probe(struct platform_device *pdev)
1420{
1421 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1422 struct snd_soc_codec *codec;
1423 struct wm8993_priv *wm8993;
1424 int ret = 0;
1425
1426 if (!wm8993_codec) {
1427 dev_err(&pdev->dev, "I2C device not yet probed\n");
1428 goto err;
1429 }
1430
1431 socdev->card->codec = wm8993_codec;
1432 codec = wm8993_codec;
1433 wm8993 = codec->private_data;
1434
1435 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1436 if (ret < 0) {
1437 dev_err(codec->dev, "failed to create pcms\n");
1438 goto err;
1439 }
1440
1441 snd_soc_add_controls(codec, wm8993_snd_controls,
1442 ARRAY_SIZE(wm8993_snd_controls));
1443 if (wm8993->pdata.num_retune_configs != 0) {
1444 dev_dbg(codec->dev, "Using ReTune Mobile\n");
1445 } else {
1446 dev_dbg(codec->dev, "No ReTune Mobile, using normal EQ\n");
1447 snd_soc_add_controls(codec, wm8993_eq_controls,
1448 ARRAY_SIZE(wm8993_eq_controls));
1449 }
1450
1451 snd_soc_dapm_new_controls(codec, wm8993_dapm_widgets,
1452 ARRAY_SIZE(wm8993_dapm_widgets));
a2342ae3 1453 wm_hubs_add_analogue_controls(codec);
942c435b
MB		 1454
1455 snd_soc_dapm_add_routes(codec, routes, ARRAY_SIZE(routes));
a2342ae3
MB		 1456 wm_hubs_add_analogue_routes(codec, wm8993->pdata.lineout1_diff,
1457 wm8993->pdata.lineout2_diff);
942c435b 1458
942c435b
MB		 1459 return ret;
1460
942c435b
MB		 1461err:
1462 return ret;
1463}
1464
1465static int wm8993_remove(struct platform_device *pdev)
1466{
1467 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1468
1469 snd_soc_free_pcms(socdev);
1470 snd_soc_dapm_free(socdev);
1471
1472 return 0;
1473}
1474
53242c68
MB		 1475#ifdef CONFIG_PM
1476static int wm8993_suspend(struct platform_device *pdev, pm_message_t state)
1477{
1478 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1479 struct snd_soc_codec *codec = socdev->card->codec;
1480 struct wm8993_priv *wm8993 = codec->private_data;
1481 int fll_fout = wm8993->fll_fout;
1482 int fll_fref = wm8993->fll_fref;
1483 int ret;
1484
1485 /* Stop the FLL in an orderly fashion */
1486 ret = wm8993_set_fll(codec->dai, 0, 0, 0, 0);
1487 if (ret != 0) {
1488 dev_err(&pdev->dev, "Failed to stop FLL\n");
1489 return ret;
1490 }
1491
1492 wm8993->fll_fout = fll_fout;
1493 wm8993->fll_fref = fll_fref;
1494
1495 wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF);
1496
1497 return 0;
1498}
1499
1500static int wm8993_resume(struct platform_device *pdev)
1501{
1502 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1503 struct snd_soc_codec *codec = socdev->card->codec;
1504 struct wm8993_priv *wm8993 = codec->private_data;
cf56f627 1505 int ret;
53242c68
MB		 1506
1507 wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1508
1509 /* Restart the FLL? */
1510 if (wm8993->fll_fout) {
1511 int fll_fout = wm8993->fll_fout;
1512 int fll_fref = wm8993->fll_fref;
1513
1514 wm8993->fll_fref = 0;
1515 wm8993->fll_fout = 0;
1516
1517 ret = wm8993_set_fll(codec->dai, 0, wm8993->fll_src,
1518 fll_fref, fll_fout);
1519 if (ret != 0)
1520 dev_err(codec->dev, "Failed to restart FLL\n");
1521 }
1522
1523 return 0;
1524}
1525#else
1526#define wm8993_suspend NULL
1527#define wm8993_resume NULL
1528#endif
1529
942c435b
MB		 1530struct snd_soc_codec_device soc_codec_dev_wm8993 = {
1531 .probe = wm8993_probe,
1532 .remove = wm8993_remove,
53242c68
MB		 1533 .suspend = wm8993_suspend,
1534 .resume = wm8993_resume,
942c435b
MB		 1535};
1536EXPORT_SYMBOL_GPL(soc_codec_dev_wm8993);
1537
1538static int wm8993_i2c_probe(struct i2c_client *i2c,
1539 const struct i2c_device_id *id)
1540{
1541 struct wm8993_priv *wm8993;
1542 struct snd_soc_codec *codec;
1543 unsigned int val;
1544 int ret;
b37e399b 1545 int i;
942c435b
MB		 1546
1547 if (wm8993_codec) {
1548 dev_err(&i2c->dev, "A WM8993 is already registered\n");
1549 return -EINVAL;
1550 }
1551
1552 wm8993 = kzalloc(sizeof(struct wm8993_priv), GFP_KERNEL);
1553 if (wm8993 == NULL)
1554 return -ENOMEM;
1555
1556 codec = &wm8993->codec;
1557 if (i2c->dev.platform_data)
1558 memcpy(&wm8993->pdata, i2c->dev.platform_data,
1559 sizeof(wm8993->pdata));
1560
1561 mutex_init(&codec->mutex);
1562 INIT_LIST_HEAD(&codec->dapm_widgets);
1563 INIT_LIST_HEAD(&codec->dapm_paths);
1564
1565 codec->name = "WM8993";
3bf6e421 1566 codec->volatile_register = wm8993_volatile;
942c435b
MB		 1567 codec->reg_cache = wm8993->reg_cache;
1568 codec->reg_cache_size = ARRAY_SIZE(wm8993->reg_cache);
1569 codec->bias_level = SND_SOC_BIAS_OFF;
1570 codec->set_bias_level = wm8993_set_bias_level;
1571 codec->dai = &wm8993_dai;
1572 codec->num_dai = 1;
1573 codec->private_data = wm8993;
1574
3ed7074c 1575 wm8993->hubs_data.hp_startup_mode = 1;
be587ef4 1576 wm8993->hubs_data.dcs_codes = -2;
3ed7074c 1577
942c435b
MB		 1578 memcpy(wm8993->reg_cache, wm8993_reg_defaults,
1579 sizeof(wm8993->reg_cache));
1580
3bf6e421
MB		 1581 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1582 if (ret != 0) {
1583 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1584 goto err;
1585 }
1586
942c435b
MB		 1587 i2c_set_clientdata(i2c, wm8993);
1588 codec->control_data = i2c;
1589 wm8993_codec = codec;
1590
1591 codec->dev = &i2c->dev;
1592
b37e399b
MB		 1593 for (i = 0; i < ARRAY_SIZE(wm8993->supplies); i++)
1594 wm8993->supplies[i].supply = wm8993_supply_names[i];
1595
1596 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8993->supplies),
1597 wm8993->supplies);
1598 if (ret != 0) {
1599 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1600 goto err;
1601 }
1602
1603 ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
1604 wm8993->supplies);
1605 if (ret != 0) {
1606 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1607 goto err_get;
1608 }
1609
3bf6e421 1610 val = snd_soc_read(codec, WM8993_SOFTWARE_RESET);
942c435b
MB		 1611 if (val != wm8993_reg_defaults[WM8993_SOFTWARE_RESET]) {
1612 dev_err(codec->dev, "Invalid ID register value %x\n", val);
1613 ret = -EINVAL;
b37e399b 1614 goto err_enable;
942c435b
MB		 1615 }
1616
3bf6e421 1617 ret = snd_soc_write(codec, WM8993_SOFTWARE_RESET, 0xffff);
942c435b 1618 if (ret != 0)
b37e399b 1619 goto err_enable;
942c435b 1620
cf56f627
MB		 1621 codec->cache_only = 1;
1622
942c435b
MB		 1623 /* By default we're using the output mixers */
1624 wm8993->class_w_users = 2;
1625
1626 /* Latch volume update bits and default ZC on */
942c435b
MB		 1627 snd_soc_update_bits(codec, WM8993_RIGHT_DAC_DIGITAL_VOLUME,
1628 WM8993_DAC_VU, WM8993_DAC_VU);
1629 snd_soc_update_bits(codec, WM8993_RIGHT_ADC_DIGITAL_VOLUME,
1630 WM8993_ADC_VU, WM8993_ADC_VU);
1631
1632 /* Manualy manage the HPOUT sequencing for independent stereo
1633 * control. */
1634 snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
1635 WM8993_HPOUT1_AUTO_PU, 0);
1636
1637 /* Use automatic clock configuration */
1638 snd_soc_update_bits(codec, WM8993_CLOCKING_4, WM8993_SR_MODE, 0);
1639
aa983d9d
MB		 1640 wm_hubs_handle_analogue_pdata(codec, wm8993->pdata.lineout1_diff,
1641 wm8993->pdata.lineout2_diff,
1642 wm8993->pdata.lineout1fb,
1643 wm8993->pdata.lineout2fb,
1644 wm8993->pdata.jd_scthr,
1645 wm8993->pdata.jd_thr,
1646 wm8993->pdata.micbias1_lvl,
1647 wm8993->pdata.micbias2_lvl);
1648
942c435b
MB		 1649 ret = wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1650 if (ret != 0)
b37e399b 1651 goto err_enable;
942c435b
MB		 1652
1653 wm8993_dai.dev = codec->dev;
1654
1655 ret = snd_soc_register_dai(&wm8993_dai);
1656 if (ret != 0)
1657 goto err_bias;
1658
1659 ret = snd_soc_register_codec(codec);
1660
1661 return 0;
1662
1663err_bias:
1664 wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF);
b37e399b
MB		 1665err_enable:
1666 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1667err_get:
1668 regulator_bulk_free(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
942c435b
MB		 1669err:
1670 wm8993_codec = NULL;
1671 kfree(wm8993);
1672 return ret;
1673}
1674
1675static int wm8993_i2c_remove(struct i2c_client *client)
1676{
1677 struct wm8993_priv *wm8993 = i2c_get_clientdata(client);
1678
1679 snd_soc_unregister_codec(&wm8993->codec);
1680 snd_soc_unregister_dai(&wm8993_dai);
1681
1682 wm8993_set_bias_level(&wm8993->codec, SND_SOC_BIAS_OFF);
b37e399b 1683 regulator_bulk_free(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
942c435b
MB		 1684 kfree(wm8993);
1685
1686 return 0;
1687}
1688
1689static const struct i2c_device_id wm8993_i2c_id[] = {
1690 { "wm8993", 0 },
1691 { }
1692};
1693MODULE_DEVICE_TABLE(i2c, wm8993_i2c_id);
1694
1695static struct i2c_driver wm8993_i2c_driver = {
1696 .driver = {
1697 .name = "WM8993",
1698 .owner = THIS_MODULE,
1699 },
1700 .probe = wm8993_i2c_probe,
1701 .remove = wm8993_i2c_remove,
1702 .id_table = wm8993_i2c_id,
1703};
1704
1705
1706static int __init wm8993_modinit(void)
1707{
1708 int ret;
1709
1710 ret = i2c_add_driver(&wm8993_i2c_driver);
1711 if (ret != 0)
1712 pr_err("WM8993: Unable to register I2C driver: %d\n", ret);
1713
1714 return ret;
1715}
1716module_init(wm8993_modinit);
1717
1718static void __exit wm8993_exit(void)
1719{
1720 i2c_del_driver(&wm8993_i2c_driver);
1721}
1722module_exit(wm8993_exit);
1723
1724
1725MODULE_DESCRIPTION("ASoC WM8993 driver");
1726MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1727MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)