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ASoC: Make I2C usage unconditional in WM8955
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / wm8955.c
CommitLineData
b35a28af
MB		 1/*
2 * wm8955.c -- WM8955 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/i2c.h>
b35a28af 19#include <linux/regulator/consumer.h>
5a0e3ad6 20#include <linux/slab.h>
b35a28af
MB		 21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/soc.h>
b35a28af
MB		 25#include <sound/initval.h>
26#include <sound/tlv.h>
27#include <sound/wm8955.h>
28
29#include "wm8955.h"
30
b35a28af
MB		 31#define WM8955_NUM_SUPPLIES 4
32static const char *wm8955_supply_names[WM8955_NUM_SUPPLIES] = {
33 "DCVDD",
34 "DBVDD",
35 "HPVDD",
36 "AVDD",
37};
38
39/* codec private data */
40struct wm8955_priv {
f0fba2ad 41 enum snd_soc_control_type control_type;
f0fba2ad 42
b35a28af
MB		 43 unsigned int mclk_rate;
44
45 int deemph;
46 int fs;
47
48 struct regulator_bulk_data supplies[WM8955_NUM_SUPPLIES];
b35a28af
MB		 49};
50
51static const u16 wm8955_reg[WM8955_MAX_REGISTER + 1] = {
52 0x0000, /* R0 */
53 0x0000, /* R1 */
54 0x0079, /* R2 - LOUT1 volume */
55 0x0079, /* R3 - ROUT1 volume */
56 0x0000, /* R4 */
57 0x0008, /* R5 - DAC Control */
58 0x0000, /* R6 */
59 0x000A, /* R7 - Audio Interface */
60 0x0000, /* R8 - Sample Rate */
61 0x0000, /* R9 */
62 0x00FF, /* R10 - Left DAC volume */
63 0x00FF, /* R11 - Right DAC volume */
64 0x000F, /* R12 - Bass control */
65 0x000F, /* R13 - Treble control */
66 0x0000, /* R14 */
67 0x0000, /* R15 - Reset */
68 0x0000, /* R16 */
69 0x0000, /* R17 */
70 0x0000, /* R18 */
71 0x0000, /* R19 */
72 0x0000, /* R20 */
73 0x0000, /* R21 */
74 0x0000, /* R22 */
75 0x00C1, /* R23 - Additional control (1) */
76 0x0000, /* R24 - Additional control (2) */
77 0x0000, /* R25 - Power Management (1) */
78 0x0000, /* R26 - Power Management (2) */
79 0x0000, /* R27 - Additional Control (3) */
80 0x0000, /* R28 */
81 0x0000, /* R29 */
82 0x0000, /* R30 */
83 0x0000, /* R31 */
84 0x0000, /* R32 */
85 0x0000, /* R33 */
86 0x0050, /* R34 - Left out Mix (1) */
87 0x0050, /* R35 - Left out Mix (2) */
88 0x0050, /* R36 - Right out Mix (1) */
89 0x0050, /* R37 - Right Out Mix (2) */
90 0x0050, /* R38 - Mono out Mix (1) */
91 0x0050, /* R39 - Mono out Mix (2) */
92 0x0079, /* R40 - LOUT2 volume */
93 0x0079, /* R41 - ROUT2 volume */
94 0x0079, /* R42 - MONOOUT volume */
95 0x0000, /* R43 - Clocking / PLL */
96 0x0103, /* R44 - PLL Control 1 */
97 0x0024, /* R45 - PLL Control 2 */
98 0x01BA, /* R46 - PLL Control 3 */
99 0x0000, /* R47 */
100 0x0000, /* R48 */
101 0x0000, /* R49 */
102 0x0000, /* R50 */
103 0x0000, /* R51 */
104 0x0000, /* R52 */
105 0x0000, /* R53 */
106 0x0000, /* R54 */
107 0x0000, /* R55 */
108 0x0000, /* R56 */
109 0x0000, /* R57 */
110 0x0000, /* R58 */
111 0x0000, /* R59 - PLL Control 4 */
112};
113
114static int wm8955_reset(struct snd_soc_codec *codec)
115{
116 return snd_soc_write(codec, WM8955_RESET, 0);
117}
118
119struct pll_factors {
120 int n;
121 int k;
122 int outdiv;
123};
124
125/* The size in bits of the FLL divide multiplied by 10
126 * to allow rounding later */
127#define FIXED_FLL_SIZE ((1 << 22) * 10)
128
129static int wm8995_pll_factors(struct device *dev,
130 int Fref, int Fout, struct pll_factors *pll)
131{
132 u64 Kpart;
133 unsigned int K, Ndiv, Nmod, target;
134
135 dev_dbg(dev, "Fref=%u Fout=%u\n", Fref, Fout);
136
137 /* The oscilator should run at should be 90-100MHz, and
138 * there's a divide by 4 plus an optional divide by 2 in the
139 * output path to generate the system clock. The clock table
140 * is sortd so we should always generate a suitable target. */
141 target = Fout * 4;
142 if (target < 90000000) {
143 pll->outdiv = 1;
144 target *= 2;
145 } else {
146 pll->outdiv = 0;
147 }
148
149 WARN_ON(target < 90000000 || target > 100000000);
150
151 dev_dbg(dev, "Fvco=%dHz\n", target);
152
153 /* Now, calculate N.K */
154 Ndiv = target / Fref;
155
156 pll->n = Ndiv;
157 Nmod = target % Fref;
158 dev_dbg(dev, "Nmod=%d\n", Nmod);
159
160 /* Calculate fractional part - scale up so we can round. */
161 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
162
163 do_div(Kpart, Fref);
164
165 K = Kpart & 0xFFFFFFFF;
166
167 if ((K % 10) >= 5)
168 K += 5;
169
170 /* Move down to proper range now rounding is done */
171 pll->k = K / 10;
172
173 dev_dbg(dev, "N=%x K=%x OUTDIV=%x\n", pll->n, pll->k, pll->outdiv);
174
175 return 0;
176}
177
25985edc 178/* Lookup table specifying SRATE (table 25 in datasheet); some of the
b35a28af
MB		 179 * output frequencies have been rounded to the standard frequencies
180 * they are intended to match where the error is slight. */
181static struct {
182 int mclk;
183 int fs;
184 int usb;
185 int sr;
186} clock_cfgs[] = {
187 { 18432000, 8000, 0, 3, },
188 { 18432000, 12000, 0, 9, },
189 { 18432000, 16000, 0, 11, },
190 { 18432000, 24000, 0, 29, },
191 { 18432000, 32000, 0, 13, },
192 { 18432000, 48000, 0, 1, },
193 { 18432000, 96000, 0, 15, },
194
195 { 16934400, 8018, 0, 19, },
196 { 16934400, 11025, 0, 25, },
197 { 16934400, 22050, 0, 27, },
198 { 16934400, 44100, 0, 17, },
199 { 16934400, 88200, 0, 31, },
200
201 { 12000000, 8000, 1, 2, },
202 { 12000000, 11025, 1, 25, },
203 { 12000000, 12000, 1, 8, },
204 { 12000000, 16000, 1, 10, },
205 { 12000000, 22050, 1, 27, },
206 { 12000000, 24000, 1, 28, },
207 { 12000000, 32000, 1, 12, },
208 { 12000000, 44100, 1, 17, },
209 { 12000000, 48000, 1, 0, },
210 { 12000000, 88200, 1, 31, },
211 { 12000000, 96000, 1, 14, },
212
213 { 12288000, 8000, 0, 2, },
214 { 12288000, 12000, 0, 8, },
215 { 12288000, 16000, 0, 10, },
216 { 12288000, 24000, 0, 28, },
217 { 12288000, 32000, 0, 12, },
218 { 12288000, 48000, 0, 0, },
219 { 12288000, 96000, 0, 14, },
220
221 { 12289600, 8018, 0, 18, },
222 { 12289600, 11025, 0, 24, },
223 { 12289600, 22050, 0, 26, },
224 { 11289600, 44100, 0, 16, },
225 { 11289600, 88200, 0, 31, },
226};
227
228static int wm8955_configure_clocking(struct snd_soc_codec *codec)
229{
b2c812e2 230 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
b35a28af
MB		 231 int i, ret, val;
232 int clocking = 0;
233 int srate = 0;
234 int sr = -1;
235 struct pll_factors pll;
236
237 /* If we're not running a sample rate currently just pick one */
238 if (wm8955->fs == 0)
239 wm8955->fs = 8000;
240
241 /* Can we generate an exact output? */
242 for (i = 0; i < ARRAY_SIZE(clock_cfgs); i++) {
243 if (wm8955->fs != clock_cfgs[i].fs)
244 continue;
245 sr = i;
246
247 if (wm8955->mclk_rate == clock_cfgs[i].mclk)
248 break;
249 }
250
251 /* We should never get here with an unsupported sample rate */
252 if (sr == -1) {
253 dev_err(codec->dev, "Sample rate %dHz unsupported\n",
254 wm8955->fs);
255 WARN_ON(sr == -1);
256 return -EINVAL;
257 }
258
259 if (i == ARRAY_SIZE(clock_cfgs)) {
260 /* If we can't generate the right clock from MCLK then
261 * we should configure the PLL to supply us with an
262 * appropriate clock.
263 */
264 clocking |= WM8955_MCLKSEL;
265
266 /* Use the last divider configuration we saw for the
267 * sample rate. */
268 ret = wm8995_pll_factors(codec->dev, wm8955->mclk_rate,
269 clock_cfgs[sr].mclk, &pll);
270 if (ret != 0) {
271 dev_err(codec->dev,
272 "Unable to generate %dHz from %dHz MCLK\n",
273 wm8955->fs, wm8955->mclk_rate);
274 return -EINVAL;
275 }
276
277 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_1,
278 WM8955_N_MASK | WM8955_K_21_18_MASK,
279 (pll.n << WM8955_N_SHIFT) |
280 pll.k >> 18);
281 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_2,
282 WM8955_K_17_9_MASK,
283 (pll.k >> 9) & WM8955_K_17_9_MASK);
284 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_2,
285 WM8955_K_8_0_MASK,
286 pll.k & WM8955_K_8_0_MASK);
287 if (pll.k)
288 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_4,
289 WM8955_KEN, WM8955_KEN);
290 else
291 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_4,
292 WM8955_KEN, 0);
293
294 if (pll.outdiv)
295 val = WM8955_PLL_RB | WM8955_PLLOUTDIV2;
296 else
297 val = WM8955_PLL_RB;
298
299 /* Now start the PLL running */
300 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
301 WM8955_PLL_RB | WM8955_PLLOUTDIV2, val);
302 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
303 WM8955_PLLEN, WM8955_PLLEN);
304 }
305
306 srate = clock_cfgs[sr].usb | (clock_cfgs[sr].sr << WM8955_SR_SHIFT);
307
308 snd_soc_update_bits(codec, WM8955_SAMPLE_RATE,
309 WM8955_USB | WM8955_SR_MASK, srate);
310 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
311 WM8955_MCLKSEL, clocking);
312
313 return 0;
314}
315
316static int wm8955_sysclk(struct snd_soc_dapm_widget *w,
317 struct snd_kcontrol *kcontrol, int event)
318{
319 struct snd_soc_codec *codec = w->codec;
320 int ret = 0;
321
322 /* Always disable the clocks - if we're doing reconfiguration this
323 * avoids misclocking.
324 */
325 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
326 WM8955_DIGENB, 0);
327 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
328 WM8955_PLL_RB | WM8955_PLLEN, 0);
329
330 switch (event) {
331 case SND_SOC_DAPM_POST_PMD:
332 break;
333 case SND_SOC_DAPM_PRE_PMU:
334 ret = wm8955_configure_clocking(codec);
335 break;
336 default:
337 ret = -EINVAL;
338 break;
339 }
340
341 return ret;
342}
343
344static int deemph_settings[] = { 0, 32000, 44100, 48000 };
345
346static int wm8955_set_deemph(struct snd_soc_codec *codec)
347{
b2c812e2 348 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
b35a28af
MB		 349 int val, i, best;
350
351 /* If we're using deemphasis select the nearest available sample
352 * rate.
353 */
354 if (wm8955->deemph) {
355 best = 1;
356 for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
357 if (abs(deemph_settings[i] - wm8955->fs) <
358 abs(deemph_settings[best] - wm8955->fs))
359 best = i;
360 }
361
362 val = best << WM8955_DEEMPH_SHIFT;
363 } else {
364 val = 0;
365 }
366
367 dev_dbg(codec->dev, "Set deemphasis %d\n", val);
368
369 return snd_soc_update_bits(codec, WM8955_DAC_CONTROL,
370 WM8955_DEEMPH_MASK, val);
371}
372
373static int wm8955_get_deemph(struct snd_kcontrol *kcontrol,
374 struct snd_ctl_elem_value *ucontrol)
375{
376 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 377 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
b35a28af 378
3f343f85
DA		 379 ucontrol->value.enumerated.item[0] = wm8955->deemph;
380 return 0;
b35a28af
MB		 381}
382
383static int wm8955_put_deemph(struct snd_kcontrol *kcontrol,
384 struct snd_ctl_elem_value *ucontrol)
385{
386 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 387 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
b35a28af
MB		 388 int deemph = ucontrol->value.enumerated.item[0];
389
390 if (deemph > 1)
391 return -EINVAL;
392
393 wm8955->deemph = deemph;
394
395 return wm8955_set_deemph(codec);
396}
397
398static const char *bass_mode_text[] = {
399 "Linear", "Adaptive",
400};
401
402static const struct soc_enum bass_mode =
403 SOC_ENUM_SINGLE(WM8955_BASS_CONTROL, 7, 2, bass_mode_text);
404
405static const char *bass_cutoff_text[] = {
406 "Low", "High"
407};
408
409static const struct soc_enum bass_cutoff =
410 SOC_ENUM_SINGLE(WM8955_BASS_CONTROL, 6, 2, bass_cutoff_text);
411
412static const char *treble_cutoff_text[] = {
413 "High", "Low"
414};
415
416static const struct soc_enum treble_cutoff =
417 SOC_ENUM_SINGLE(WM8955_TREBLE_CONTROL, 6, 2, treble_cutoff_text);
418
419static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
420static const DECLARE_TLV_DB_SCALE(atten_tlv, -600, 600, 0);
421static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
422static const DECLARE_TLV_DB_SCALE(mono_tlv, -2100, 300, 0);
423static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
424static const DECLARE_TLV_DB_SCALE(treble_tlv, -1200, 150, 1);
425
426static const struct snd_kcontrol_new wm8955_snd_controls[] = {
427SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8955_LEFT_DAC_VOLUME,
428 WM8955_RIGHT_DAC_VOLUME, 0, 255, 0, digital_tlv),
429SOC_SINGLE_TLV("Playback Attenuation Volume", WM8955_DAC_CONTROL, 7, 1, 1,
430 atten_tlv),
431SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
432 wm8955_get_deemph, wm8955_put_deemph),
433
434SOC_ENUM("Bass Mode", bass_mode),
435SOC_ENUM("Bass Cutoff", bass_cutoff),
436SOC_SINGLE("Bass Volume", WM8955_BASS_CONTROL, 0, 15, 1),
437
438SOC_ENUM("Treble Cutoff", treble_cutoff),
439SOC_SINGLE_TLV("Treble Volume", WM8955_TREBLE_CONTROL, 0, 14, 1, treble_tlv),
440
441SOC_SINGLE_TLV("Left Bypass Volume", WM8955_LEFT_OUT_MIX_1, 4, 7, 1,
442 bypass_tlv),
443SOC_SINGLE_TLV("Left Mono Volume", WM8955_LEFT_OUT_MIX_2, 4, 7, 1,
444 bypass_tlv),
445
446SOC_SINGLE_TLV("Right Mono Volume", WM8955_RIGHT_OUT_MIX_1, 4, 7, 1,
447 bypass_tlv),
448SOC_SINGLE_TLV("Right Bypass Volume", WM8955_RIGHT_OUT_MIX_2, 4, 7, 1,
449 bypass_tlv),
450
451/* Not a stereo pair so they line up with the DAPM switches */
452SOC_SINGLE_TLV("Mono Left Bypass Volume", WM8955_MONO_OUT_MIX_1, 4, 7, 1,
453 mono_tlv),
454SOC_SINGLE_TLV("Mono Right Bypass Volume", WM8955_MONO_OUT_MIX_2, 4, 7, 1,
455 mono_tlv),
456
457SOC_DOUBLE_R_TLV("Headphone Volume", WM8955_LOUT1_VOLUME,
458 WM8955_ROUT1_VOLUME, 0, 127, 0, out_tlv),
459SOC_DOUBLE_R("Headphone ZC Switch", WM8955_LOUT1_VOLUME,
460 WM8955_ROUT1_VOLUME, 7, 1, 0),
461
462SOC_DOUBLE_R_TLV("Speaker Volume", WM8955_LOUT2_VOLUME,
463 WM8955_ROUT2_VOLUME, 0, 127, 0, out_tlv),
464SOC_DOUBLE_R("Speaker ZC Switch", WM8955_LOUT2_VOLUME,
465 WM8955_ROUT2_VOLUME, 7, 1, 0),
466
467SOC_SINGLE_TLV("Mono Volume", WM8955_MONOOUT_VOLUME, 0, 127, 0, out_tlv),
468SOC_SINGLE("Mono ZC Switch", WM8955_MONOOUT_VOLUME, 7, 1, 0),
469};
470
471static const struct snd_kcontrol_new lmixer[] = {
472SOC_DAPM_SINGLE("Playback Switch", WM8955_LEFT_OUT_MIX_1, 8, 1, 0),
473SOC_DAPM_SINGLE("Bypass Switch", WM8955_LEFT_OUT_MIX_1, 7, 1, 0),
474SOC_DAPM_SINGLE("Right Playback Switch", WM8955_LEFT_OUT_MIX_2, 8, 1, 0),
475SOC_DAPM_SINGLE("Mono Switch", WM8955_LEFT_OUT_MIX_2, 7, 1, 0),
476};
477
478static const struct snd_kcontrol_new rmixer[] = {
479SOC_DAPM_SINGLE("Left Playback Switch", WM8955_RIGHT_OUT_MIX_1, 8, 1, 0),
480SOC_DAPM_SINGLE("Mono Switch", WM8955_RIGHT_OUT_MIX_1, 7, 1, 0),
481SOC_DAPM_SINGLE("Playback Switch", WM8955_RIGHT_OUT_MIX_2, 8, 1, 0),
482SOC_DAPM_SINGLE("Bypass Switch", WM8955_RIGHT_OUT_MIX_2, 7, 1, 0),
483};
484
485static const struct snd_kcontrol_new mmixer[] = {
486SOC_DAPM_SINGLE("Left Playback Switch", WM8955_MONO_OUT_MIX_1, 8, 1, 0),
487SOC_DAPM_SINGLE("Left Bypass Switch", WM8955_MONO_OUT_MIX_1, 7, 1, 0),
488SOC_DAPM_SINGLE("Right Playback Switch", WM8955_MONO_OUT_MIX_2, 8, 1, 0),
489SOC_DAPM_SINGLE("Right Bypass Switch", WM8955_MONO_OUT_MIX_2, 7, 1, 0),
490};
491
492static const struct snd_soc_dapm_widget wm8955_dapm_widgets[] = {
493SND_SOC_DAPM_INPUT("MONOIN-"),
494SND_SOC_DAPM_INPUT("MONOIN+"),
495SND_SOC_DAPM_INPUT("LINEINR"),
496SND_SOC_DAPM_INPUT("LINEINL"),
497
498SND_SOC_DAPM_PGA("Mono Input", SND_SOC_NOPM, 0, 0, NULL, 0),
499
500SND_SOC_DAPM_SUPPLY("SYSCLK", WM8955_POWER_MANAGEMENT_1, 0, 1, wm8955_sysclk,
501 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
502SND_SOC_DAPM_SUPPLY("TSDEN", WM8955_ADDITIONAL_CONTROL_1, 8, 0, NULL, 0),
503
504SND_SOC_DAPM_DAC("DACL", "Playback", WM8955_POWER_MANAGEMENT_2, 8, 0),
505SND_SOC_DAPM_DAC("DACR", "Playback", WM8955_POWER_MANAGEMENT_2, 7, 0),
506
507SND_SOC_DAPM_PGA("LOUT1 PGA", WM8955_POWER_MANAGEMENT_2, 6, 0, NULL, 0),
508SND_SOC_DAPM_PGA("ROUT1 PGA", WM8955_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
509SND_SOC_DAPM_PGA("LOUT2 PGA", WM8955_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
510SND_SOC_DAPM_PGA("ROUT2 PGA", WM8955_POWER_MANAGEMENT_2, 3, 0, NULL, 0),
511SND_SOC_DAPM_PGA("MOUT PGA", WM8955_POWER_MANAGEMENT_2, 2, 0, NULL, 0),
512SND_SOC_DAPM_PGA("OUT3 PGA", WM8955_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
513
514/* The names are chosen to make the control names nice */
515SND_SOC_DAPM_MIXER("Left", SND_SOC_NOPM, 0, 0,
516 lmixer, ARRAY_SIZE(lmixer)),
517SND_SOC_DAPM_MIXER("Right", SND_SOC_NOPM, 0, 0,
518 rmixer, ARRAY_SIZE(rmixer)),
519SND_SOC_DAPM_MIXER("Mono", SND_SOC_NOPM, 0, 0,
520 mmixer, ARRAY_SIZE(mmixer)),
521
522SND_SOC_DAPM_OUTPUT("LOUT1"),
523SND_SOC_DAPM_OUTPUT("ROUT1"),
524SND_SOC_DAPM_OUTPUT("LOUT2"),
525SND_SOC_DAPM_OUTPUT("ROUT2"),
526SND_SOC_DAPM_OUTPUT("MONOOUT"),
527SND_SOC_DAPM_OUTPUT("OUT3"),
528};
529
530static const struct snd_soc_dapm_route wm8955_intercon[] = {
531 { "DACL", NULL, "SYSCLK" },
532 { "DACR", NULL, "SYSCLK" },
533
534 { "Mono Input", NULL, "MONOIN-" },
535 { "Mono Input", NULL, "MONOIN+" },
536
537 { "Left", "Playback Switch", "DACL" },
538 { "Left", "Right Playback Switch", "DACR" },
539 { "Left", "Bypass Switch", "LINEINL" },
540 { "Left", "Mono Switch", "Mono Input" },
541
542 { "Right", "Playback Switch", "DACR" },
543 { "Right", "Left Playback Switch", "DACL" },
544 { "Right", "Bypass Switch", "LINEINR" },
545 { "Right", "Mono Switch", "Mono Input" },
546
547 { "Mono", "Left Playback Switch", "DACL" },
548 { "Mono", "Right Playback Switch", "DACR" },
549 { "Mono", "Left Bypass Switch", "LINEINL" },
550 { "Mono", "Right Bypass Switch", "LINEINR" },
551
552 { "LOUT1 PGA", NULL, "Left" },
553 { "LOUT1", NULL, "TSDEN" },
554 { "LOUT1", NULL, "LOUT1 PGA" },
555
556 { "ROUT1 PGA", NULL, "Right" },
557 { "ROUT1", NULL, "TSDEN" },
558 { "ROUT1", NULL, "ROUT1 PGA" },
559
560 { "LOUT2 PGA", NULL, "Left" },
561 { "LOUT2", NULL, "TSDEN" },
562 { "LOUT2", NULL, "LOUT2 PGA" },
563
564 { "ROUT2 PGA", NULL, "Right" },
565 { "ROUT2", NULL, "TSDEN" },
566 { "ROUT2", NULL, "ROUT2 PGA" },
567
568 { "MOUT PGA", NULL, "Mono" },
569 { "MONOOUT", NULL, "MOUT PGA" },
570
571 /* OUT3 not currently implemented */
572 { "OUT3", NULL, "OUT3 PGA" },
573};
574
575static int wm8955_add_widgets(struct snd_soc_codec *codec)
576{
ce6120cc
LG		 577 struct snd_soc_dapm_context *dapm = &codec->dapm;
578
b35a28af
MB		 579 snd_soc_add_controls(codec, wm8955_snd_controls,
580 ARRAY_SIZE(wm8955_snd_controls));
581
ce6120cc 582 snd_soc_dapm_new_controls(dapm, wm8955_dapm_widgets,
b35a28af 583 ARRAY_SIZE(wm8955_dapm_widgets));
ce6120cc 584 snd_soc_dapm_add_routes(dapm, wm8955_intercon,
b35a28af
MB		 585 ARRAY_SIZE(wm8955_intercon));
586
587 return 0;
588}
589
590static int wm8955_hw_params(struct snd_pcm_substream *substream,
591 struct snd_pcm_hw_params *params,
592 struct snd_soc_dai *dai)
593{
594 struct snd_soc_codec *codec = dai->codec;
b2c812e2 595 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
b35a28af
MB		 596 int ret;
597 int wl;
598
599 switch (params_format(params)) {
600 case SNDRV_PCM_FORMAT_S16_LE:
601 wl = 0;
602 break;
603 case SNDRV_PCM_FORMAT_S20_3LE:
604 wl = 0x4;
605 break;
606 case SNDRV_PCM_FORMAT_S24_LE:
607 wl = 0x8;
608 break;
609 case SNDRV_PCM_FORMAT_S32_LE:
610 wl = 0xc;
611 break;
612 default:
613 return -EINVAL;
614 }
615 snd_soc_update_bits(codec, WM8955_AUDIO_INTERFACE,
616 WM8955_WL_MASK, wl);
617
618 wm8955->fs = params_rate(params);
619 wm8955_set_deemph(codec);
620
621 /* If the chip is clocked then disable the clocks and force a
622 * reconfiguration, otherwise DAPM will power up the
623 * clocks for us later. */
624 ret = snd_soc_read(codec, WM8955_POWER_MANAGEMENT_1);
625 if (ret < 0)
626 return ret;
627 if (ret & WM8955_DIGENB) {
628 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
629 WM8955_DIGENB, 0);
630 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
631 WM8955_PLL_RB | WM8955_PLLEN, 0);
632
633 wm8955_configure_clocking(codec);
634 }
635
636 return 0;
637}
638
639
640static int wm8955_set_sysclk(struct snd_soc_dai *dai, int clk_id,
641 unsigned int freq, int dir)
642{
643 struct snd_soc_codec *codec = dai->codec;
b2c812e2 644 struct wm8955_priv *priv = snd_soc_codec_get_drvdata(codec);
b35a28af
MB		 645 int div;
646
647 switch (clk_id) {
648 case WM8955_CLK_MCLK:
649 if (freq > 15000000) {
650 priv->mclk_rate = freq /= 2;
651 div = WM8955_MCLKDIV2;
652 } else {
653 priv->mclk_rate = freq;
654 div = 0;
655 }
656
657 snd_soc_update_bits(codec, WM8955_SAMPLE_RATE,
658 WM8955_MCLKDIV2, div);
659 break;
660
661 default:
662 return -EINVAL;
663 }
664
665 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
666
667 return 0;
668}
669
670static int wm8955_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
671{
672 struct snd_soc_codec *codec = dai->codec;
673 u16 aif = 0;
674
675 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
676 case SND_SOC_DAIFMT_CBS_CFS:
677 break;
678 case SND_SOC_DAIFMT_CBM_CFM:
679 aif |= WM8955_MS;
680 break;
681 default:
682 return -EINVAL;
683 }
684
685 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
686 case SND_SOC_DAIFMT_DSP_B:
687 aif |= WM8955_LRP;
688 case SND_SOC_DAIFMT_DSP_A:
689 aif |= 0x3;
690 break;
691 case SND_SOC_DAIFMT_I2S:
692 aif |= 0x2;
693 break;
694 case SND_SOC_DAIFMT_RIGHT_J:
695 break;
696 case SND_SOC_DAIFMT_LEFT_J:
697 aif |= 0x1;
698 break;
699 default:
700 return -EINVAL;
701 }
702
703 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
704 case SND_SOC_DAIFMT_DSP_A:
705 case SND_SOC_DAIFMT_DSP_B:
706 /* frame inversion not valid for DSP modes */
707 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
708 case SND_SOC_DAIFMT_NB_NF:
709 break;
710 case SND_SOC_DAIFMT_IB_NF:
711 aif |= WM8955_BCLKINV;
712 break;
713 default:
714 return -EINVAL;
715 }
716 break;
717
718 case SND_SOC_DAIFMT_I2S:
719 case SND_SOC_DAIFMT_RIGHT_J:
720 case SND_SOC_DAIFMT_LEFT_J:
721 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
722 case SND_SOC_DAIFMT_NB_NF:
723 break;
724 case SND_SOC_DAIFMT_IB_IF:
725 aif |= WM8955_BCLKINV | WM8955_LRP;
726 break;
727 case SND_SOC_DAIFMT_IB_NF:
728 aif |= WM8955_BCLKINV;
729 break;
730 case SND_SOC_DAIFMT_NB_IF:
731 aif |= WM8955_LRP;
732 break;
733 default:
734 return -EINVAL;
735 }
736 break;
737 default:
738 return -EINVAL;
739 }
740
741 snd_soc_update_bits(codec, WM8955_AUDIO_INTERFACE,
742 WM8955_MS | WM8955_FORMAT_MASK | WM8955_BCLKINV |
743 WM8955_LRP, aif);
744
745 return 0;
746}
747
748
749static int wm8955_digital_mute(struct snd_soc_dai *codec_dai, int mute)
750{
751 struct snd_soc_codec *codec = codec_dai->codec;
752 int val;
753
754 if (mute)
755 val = WM8955_DACMU;
756 else
757 val = 0;
758
759 snd_soc_update_bits(codec, WM8955_DAC_CONTROL, WM8955_DACMU, val);
760
761 return 0;
762}
763
764static int wm8955_set_bias_level(struct snd_soc_codec *codec,
765 enum snd_soc_bias_level level)
766{
b2c812e2 767 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
715920d0 768 u16 *reg_cache = codec->reg_cache;
b35a28af
MB		 769 int ret, i;
770
771 switch (level) {
772 case SND_SOC_BIAS_ON:
773 break;
774
775 case SND_SOC_BIAS_PREPARE:
776 /* VMID resistance 2*50k */
777 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
778 WM8955_VMIDSEL_MASK,
779 0x1 << WM8955_VMIDSEL_SHIFT);
780
781 /* Default bias current */
782 snd_soc_update_bits(codec, WM8955_ADDITIONAL_CONTROL_1,
783 WM8955_VSEL_MASK,
784 0x2 << WM8955_VSEL_SHIFT);
785 break;
786
787 case SND_SOC_BIAS_STANDBY:
ce6120cc 788 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
b35a28af
MB		 789 ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
790 wm8955->supplies);
791 if (ret != 0) {
792 dev_err(codec->dev,
793 "Failed to enable supplies: %d\n",
794 ret);
795 return ret;
796 }
797
798 /* Sync back cached values if they're
799 * different from the hardware default.
800 */
715920d0 801 for (i = 0; i < codec->driver->reg_cache_size; i++) {
b35a28af
MB		 802 if (i == WM8955_RESET)
803 continue;
804
715920d0 805 if (reg_cache[i] == wm8955_reg[i])
b35a28af
MB		 806 continue;
807
715920d0 808 snd_soc_write(codec, i, reg_cache[i]);
b35a28af
MB		 809 }
810
811 /* Enable VREF and VMID */
812 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
813 WM8955_VREF |
814 WM8955_VMIDSEL_MASK,
815 WM8955_VREF |
816 0x3 << WM8955_VREF_SHIFT);
817
818 /* Let VMID ramp */
819 msleep(500);
820
821 /* High resistance VROI to maintain outputs */
822 snd_soc_update_bits(codec,
823 WM8955_ADDITIONAL_CONTROL_3,
824 WM8955_VROI, WM8955_VROI);
825 }
826
827 /* Maintain VMID with 2*250k */
828 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
829 WM8955_VMIDSEL_MASK,
830 0x2 << WM8955_VMIDSEL_SHIFT);
831
832 /* Minimum bias current */
833 snd_soc_update_bits(codec, WM8955_ADDITIONAL_CONTROL_1,
834 WM8955_VSEL_MASK, 0);
835 break;
836
837 case SND_SOC_BIAS_OFF:
838 /* Low resistance VROI to help discharge */
839 snd_soc_update_bits(codec,
840 WM8955_ADDITIONAL_CONTROL_3,
841 WM8955_VROI, 0);
842
843 /* Turn off VMID and VREF */
844 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
845 WM8955_VREF |
846 WM8955_VMIDSEL_MASK, 0);
847
848 regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies),
849 wm8955->supplies);
850 break;
851 }
ce6120cc 852 codec->dapm.bias_level = level;
b35a28af
MB		 853 return 0;
854}
855
856#define WM8955_RATES SNDRV_PCM_RATE_8000_96000
857
858#define WM8955_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
859 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
860
85e7652d 861static const struct snd_soc_dai_ops wm8955_dai_ops = {
b35a28af
MB		 862 .set_sysclk = wm8955_set_sysclk,
863 .set_fmt = wm8955_set_fmt,
864 .hw_params = wm8955_hw_params,
865 .digital_mute = wm8955_digital_mute,
866};
867
f0fba2ad
LG		 868static struct snd_soc_dai_driver wm8955_dai = {
869 .name = "wm8955-hifi",
b35a28af
MB		 870 .playback = {
871 .stream_name = "Playback",
872 .channels_min = 2,
873 .channels_max = 2,
874 .rates = WM8955_RATES,
875 .formats = WM8955_FORMATS,
876 },
877 .ops = &wm8955_dai_ops,
878};
b35a28af
MB		 879
880#ifdef CONFIG_PM
84b315ee 881static int wm8955_suspend(struct snd_soc_codec *codec)
b35a28af 882{
b35a28af
MB		 883 wm8955_set_bias_level(codec, SND_SOC_BIAS_OFF);
884
885 return 0;
886}
887
f0fba2ad 888static int wm8955_resume(struct snd_soc_codec *codec)
b35a28af 889{
b35a28af
MB		 890 wm8955_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
891
892 return 0;
893}
894#else
895#define wm8955_suspend NULL
896#define wm8955_resume NULL
897#endif
898
f0fba2ad 899static int wm8955_probe(struct snd_soc_codec *codec)
b35a28af 900{
f0fba2ad
LG		 901 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
902 struct wm8955_pdata *pdata = dev_get_platdata(codec->dev);
715920d0 903 u16 *reg_cache = codec->reg_cache;
f0fba2ad 904 int ret, i;
b35a28af 905
f0fba2ad 906 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8955->control_type);
b35a28af
MB		 907 if (ret != 0) {
908 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
f0fba2ad 909 return ret;
b35a28af
MB		 910 }
911
912 for (i = 0; i < ARRAY_SIZE(wm8955->supplies); i++)
913 wm8955->supplies[i].supply = wm8955_supply_names[i];
914
915 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8955->supplies),
916 wm8955->supplies);
917 if (ret != 0) {
918 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
f0fba2ad 919 return ret;
b35a28af
MB		 920 }
921
922 ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
923 wm8955->supplies);
924 if (ret != 0) {
925 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
926 goto err_get;
927 }
928
929 ret = wm8955_reset(codec);
930 if (ret < 0) {
931 dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
932 goto err_enable;
933 }
934
b35a28af 935 /* Change some default settings - latch VU and enable ZC */
a1b3b5ee
MB		 936 snd_soc_update_bits(codec, WM8955_LEFT_DAC_VOLUME,
937 WM8955_LDVU, WM8955_LDVU);
938 snd_soc_update_bits(codec, WM8955_RIGHT_DAC_VOLUME,
939 WM8955_RDVU, WM8955_RDVU);
940 snd_soc_update_bits(codec, WM8955_LOUT1_VOLUME,
941 WM8955_LO1VU | WM8955_LO1ZC,
942 WM8955_LO1VU | WM8955_LO1ZC);
943 snd_soc_update_bits(codec, WM8955_ROUT1_VOLUME,
944 WM8955_RO1VU | WM8955_RO1ZC,
945 WM8955_RO1VU | WM8955_RO1ZC);
946 snd_soc_update_bits(codec, WM8955_LOUT2_VOLUME,
947 WM8955_LO2VU | WM8955_LO2ZC,
948 WM8955_LO2VU | WM8955_LO2ZC);
949 snd_soc_update_bits(codec, WM8955_ROUT2_VOLUME,
950 WM8955_RO2VU | WM8955_RO2ZC,
951 WM8955_RO2VU | WM8955_RO2ZC);
952 snd_soc_update_bits(codec, WM8955_MONOOUT_VOLUME,
953 WM8955_MOZC, WM8955_MOZC);
b35a28af
MB		 954
955 /* Also enable adaptive bass boost by default */
a1b3b5ee 956 snd_soc_update_bits(codec, WM8955_BASS_CONTROL, WM8955_BB, WM8955_BB);
b35a28af
MB		 957
958 /* Set platform data values */
f0fba2ad
LG		 959 if (pdata) {
960 if (pdata->out2_speaker)
715920d0 961 reg_cache[WM8955_ADDITIONAL_CONTROL_2]
b35a28af
MB		 962 |= WM8955_ROUT2INV;
963
f0fba2ad 964 if (pdata->monoin_diff)
715920d0 965 reg_cache[WM8955_MONO_OUT_MIX_1]
b35a28af
MB		 966 |= WM8955_DMEN;
967 }
968
969 wm8955_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
970
971 /* Bias level configuration will have done an extra enable */
972 regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
973
f0fba2ad 974 wm8955_add_widgets(codec);
b35a28af
MB		 975 return 0;
976
977err_enable:
978 regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
979err_get:
980 regulator_bulk_free(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
b35a28af
MB		 981 return ret;
982}
983
f0fba2ad 984static int wm8955_remove(struct snd_soc_codec *codec)
b35a28af 985{
f0fba2ad
LG		 986 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
987
988 wm8955_set_bias_level(codec, SND_SOC_BIAS_OFF);
b35a28af 989 regulator_bulk_free(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
f0fba2ad 990 return 0;
b35a28af
MB		 991}
992
f0fba2ad
LG		 993static struct snd_soc_codec_driver soc_codec_dev_wm8955 = {
994 .probe = wm8955_probe,
995 .remove = wm8955_remove,
996 .suspend = wm8955_suspend,
997 .resume = wm8955_resume,
998 .set_bias_level = wm8955_set_bias_level,
999 .reg_cache_size = ARRAY_SIZE(wm8955_reg),
1000 .reg_word_size = sizeof(u16),
1001 .reg_cache_default = wm8955_reg,
1002};
1003
b35a28af
MB		 1004static __devinit int wm8955_i2c_probe(struct i2c_client *i2c,
1005 const struct i2c_device_id *id)
1006{
1007 struct wm8955_priv *wm8955;
f0fba2ad 1008 int ret;
b35a28af
MB		 1009
1010 wm8955 = kzalloc(sizeof(struct wm8955_priv), GFP_KERNEL);
1011 if (wm8955 == NULL)
1012 return -ENOMEM;
1013
b35a28af 1014 i2c_set_clientdata(i2c, wm8955);
7f984b55 1015 wm8955->control_type = SND_SOC_I2C;
b35a28af 1016
f0fba2ad
LG		 1017 ret = snd_soc_register_codec(&i2c->dev,
1018 &soc_codec_dev_wm8955, &wm8955_dai, 1);
1019 if (ret < 0)
1020 kfree(wm8955);
1021 return ret;
b35a28af
MB		 1022}
1023
1024static __devexit int wm8955_i2c_remove(struct i2c_client *client)
1025{
f0fba2ad
LG		 1026 snd_soc_unregister_codec(&client->dev);
1027 kfree(i2c_get_clientdata(client));
b35a28af
MB		 1028 return 0;
1029}
1030
1031static const struct i2c_device_id wm8955_i2c_id[] = {
1032 { "wm8955", 0 },
1033 { }
1034};
1035MODULE_DEVICE_TABLE(i2c, wm8955_i2c_id);
1036
1037static struct i2c_driver wm8955_i2c_driver = {
1038 .driver = {
091edccf 1039 .name = "wm8955",
b35a28af
MB		 1040 .owner = THIS_MODULE,
1041 },
1042 .probe = wm8955_i2c_probe,
1043 .remove = __devexit_p(wm8955_i2c_remove),
1044 .id_table = wm8955_i2c_id,
1045};
b35a28af
MB		 1046
1047static int __init wm8955_modinit(void)
1048{
f0fba2ad 1049 int ret = 0;
b35a28af
MB		 1050 ret = i2c_add_driver(&wm8955_i2c_driver);
1051 if (ret != 0) {
1052 printk(KERN_ERR "Failed to register WM8955 I2C driver: %d\n",
1053 ret);
1054 }
f0fba2ad 1055 return ret;
b35a28af
MB		 1056}
1057module_init(wm8955_modinit);
1058
1059static void __exit wm8955_exit(void)
1060{
b35a28af 1061 i2c_del_driver(&wm8955_i2c_driver);
b35a28af
MB		 1062}
1063module_exit(wm8955_exit);
1064
1065MODULE_DESCRIPTION("ASoC WM8955 driver");
1066MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1067MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)