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Merge branch 'topic/hda' into for-linus
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
7cfe5617 5 * Copyright 2011 NVIDIA, Inc.
f1c0a02f
MB		 6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * TODO:
14 * - TDM mode configuration.
f1c0a02f 15 * - Digital microphone support.
f1c0a02f
MB		 16 */
17
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/init.h>
8abd16a6 21#include <linux/completion.h>
f1c0a02f 22#include <linux/delay.h>
7cfe5617 23#include <linux/gpio.h>
f1c0a02f
MB		 24#include <linux/pm.h>
25#include <linux/i2c.h>
26#include <linux/platform_device.h>
5a0e3ad6 27#include <linux/slab.h>
f1c0a02f 28#include <sound/core.h>
7245387e 29#include <sound/jack.h>
f1c0a02f
MB		 30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/tlv.h>
33#include <sound/soc.h>
f1c0a02f 34#include <sound/initval.h>
8abd16a6 35#include <sound/wm8903.h>
2bbb5d66 36#include <trace/events/asoc.h>
f1c0a02f
MB		 37
38#include "wm8903.h"
39
f1c0a02f
MB		 40/* Register defaults at reset */
41static u16 wm8903_reg_defaults[] = {
42 0x8903, /* R0 - SW Reset and ID */
43 0x0000, /* R1 - Revision Number */
44 0x0000, /* R2 */
45 0x0000, /* R3 */
46 0x0018, /* R4 - Bias Control 0 */
47 0x0000, /* R5 - VMID Control 0 */
48 0x0000, /* R6 - Mic Bias Control 0 */
49 0x0000, /* R7 */
50 0x0001, /* R8 - Analogue DAC 0 */
51 0x0000, /* R9 */
52 0x0001, /* R10 - Analogue ADC 0 */
53 0x0000, /* R11 */
54 0x0000, /* R12 - Power Management 0 */
55 0x0000, /* R13 - Power Management 1 */
56 0x0000, /* R14 - Power Management 2 */
57 0x0000, /* R15 - Power Management 3 */
58 0x0000, /* R16 - Power Management 4 */
59 0x0000, /* R17 - Power Management 5 */
60 0x0000, /* R18 - Power Management 6 */
61 0x0000, /* R19 */
62 0x0400, /* R20 - Clock Rates 0 */
63 0x0D07, /* R21 - Clock Rates 1 */
64 0x0000, /* R22 - Clock Rates 2 */
65 0x0000, /* R23 */
66 0x0050, /* R24 - Audio Interface 0 */
67 0x0242, /* R25 - Audio Interface 1 */
68 0x0008, /* R26 - Audio Interface 2 */
69 0x0022, /* R27 - Audio Interface 3 */
70 0x0000, /* R28 */
71 0x0000, /* R29 */
72 0x00C0, /* R30 - DAC Digital Volume Left */
73 0x00C0, /* R31 - DAC Digital Volume Right */
74 0x0000, /* R32 - DAC Digital 0 */
75 0x0000, /* R33 - DAC Digital 1 */
76 0x0000, /* R34 */
77 0x0000, /* R35 */
78 0x00C0, /* R36 - ADC Digital Volume Left */
79 0x00C0, /* R37 - ADC Digital Volume Right */
80 0x0000, /* R38 - ADC Digital 0 */
81 0x0073, /* R39 - Digital Microphone 0 */
82 0x09BF, /* R40 - DRC 0 */
83 0x3241, /* R41 - DRC 1 */
84 0x0020, /* R42 - DRC 2 */
85 0x0000, /* R43 - DRC 3 */
86 0x0085, /* R44 - Analogue Left Input 0 */
87 0x0085, /* R45 - Analogue Right Input 0 */
88 0x0044, /* R46 - Analogue Left Input 1 */
89 0x0044, /* R47 - Analogue Right Input 1 */
90 0x0000, /* R48 */
91 0x0000, /* R49 */
92 0x0008, /* R50 - Analogue Left Mix 0 */
93 0x0004, /* R51 - Analogue Right Mix 0 */
94 0x0000, /* R52 - Analogue Spk Mix Left 0 */
95 0x0000, /* R53 - Analogue Spk Mix Left 1 */
96 0x0000, /* R54 - Analogue Spk Mix Right 0 */
97 0x0000, /* R55 - Analogue Spk Mix Right 1 */
98 0x0000, /* R56 */
99 0x002D, /* R57 - Analogue OUT1 Left */
100 0x002D, /* R58 - Analogue OUT1 Right */
101 0x0039, /* R59 - Analogue OUT2 Left */
102 0x0039, /* R60 - Analogue OUT2 Right */
103 0x0100, /* R61 */
104 0x0139, /* R62 - Analogue OUT3 Left */
105 0x0139, /* R63 - Analogue OUT3 Right */
106 0x0000, /* R64 */
107 0x0000, /* R65 - Analogue SPK Output Control 0 */
108 0x0000, /* R66 */
109 0x0010, /* R67 - DC Servo 0 */
110 0x0100, /* R68 */
111 0x00A4, /* R69 - DC Servo 2 */
112 0x0807, /* R70 */
113 0x0000, /* R71 */
114 0x0000, /* R72 */
115 0x0000, /* R73 */
116 0x0000, /* R74 */
117 0x0000, /* R75 */
118 0x0000, /* R76 */
119 0x0000, /* R77 */
120 0x0000, /* R78 */
121 0x000E, /* R79 */
122 0x0000, /* R80 */
123 0x0000, /* R81 */
124 0x0000, /* R82 */
125 0x0000, /* R83 */
126 0x0000, /* R84 */
127 0x0000, /* R85 */
128 0x0000, /* R86 */
129 0x0006, /* R87 */
130 0x0000, /* R88 */
131 0x0000, /* R89 */
132 0x0000, /* R90 - Analogue HP 0 */
133 0x0060, /* R91 */
134 0x0000, /* R92 */
135 0x0000, /* R93 */
136 0x0000, /* R94 - Analogue Lineout 0 */
137 0x0060, /* R95 */
138 0x0000, /* R96 */
139 0x0000, /* R97 */
140 0x0000, /* R98 - Charge Pump 0 */
141 0x1F25, /* R99 */
142 0x2B19, /* R100 */
143 0x01C0, /* R101 */
144 0x01EF, /* R102 */
145 0x2B00, /* R103 */
146 0x0000, /* R104 - Class W 0 */
147 0x01C0, /* R105 */
148 0x1C10, /* R106 */
149 0x0000, /* R107 */
150 0x0000, /* R108 - Write Sequencer 0 */
151 0x0000, /* R109 - Write Sequencer 1 */
152 0x0000, /* R110 - Write Sequencer 2 */
153 0x0000, /* R111 - Write Sequencer 3 */
154 0x0000, /* R112 - Write Sequencer 4 */
155 0x0000, /* R113 */
156 0x0000, /* R114 - Control Interface */
157 0x0000, /* R115 */
158 0x00A8, /* R116 - GPIO Control 1 */
159 0x00A8, /* R117 - GPIO Control 2 */
160 0x00A8, /* R118 - GPIO Control 3 */
161 0x0220, /* R119 - GPIO Control 4 */
162 0x01A0, /* R120 - GPIO Control 5 */
163 0x0000, /* R121 - Interrupt Status 1 */
164 0xFFFF, /* R122 - Interrupt Status 1 Mask */
165 0x0000, /* R123 - Interrupt Polarity 1 */
166 0x0000, /* R124 */
167 0x0003, /* R125 */
168 0x0000, /* R126 - Interrupt Control */
169 0x0000, /* R127 */
170 0x0005, /* R128 */
171 0x0000, /* R129 - Control Interface Test 1 */
172 0x0000, /* R130 */
173 0x0000, /* R131 */
174 0x0000, /* R132 */
175 0x0000, /* R133 */
176 0x0000, /* R134 */
177 0x03FF, /* R135 */
178 0x0007, /* R136 */
179 0x0040, /* R137 */
180 0x0000, /* R138 */
181 0x0000, /* R139 */
182 0x0000, /* R140 */
183 0x0000, /* R141 */
184 0x0000, /* R142 */
185 0x0000, /* R143 */
186 0x0000, /* R144 */
187 0x0000, /* R145 */
188 0x0000, /* R146 */
189 0x0000, /* R147 */
190 0x4000, /* R148 */
191 0x6810, /* R149 - Charge Pump Test 1 */
192 0x0004, /* R150 */
193 0x0000, /* R151 */
194 0x0000, /* R152 */
195 0x0000, /* R153 */
196 0x0000, /* R154 */
197 0x0000, /* R155 */
198 0x0000, /* R156 */
199 0x0000, /* R157 */
200 0x0000, /* R158 */
201 0x0000, /* R159 */
202 0x0000, /* R160 */
203 0x0000, /* R161 */
204 0x0000, /* R162 */
205 0x0000, /* R163 */
206 0x0028, /* R164 - Clock Rate Test 4 */
207 0x0004, /* R165 */
208 0x0000, /* R166 */
209 0x0060, /* R167 */
210 0x0000, /* R168 */
211 0x0000, /* R169 */
212 0x0000, /* R170 */
213 0x0000, /* R171 */
214 0x0000, /* R172 - Analogue Output Bias 0 */
215};
216
d58d5d55 217struct wm8903_priv {
7cfe5617 218 struct snd_soc_codec *codec;
f0fba2ad 219
d58d5d55 220 int sysclk;
f0fba2ad 221 int irq;
d58d5d55 222
69fff9bb
MB		 223 int fs;
224 int deemph;
225
c5b6a9fe
MB		 226 int dcs_pending;
227 int dcs_cache[4];
228
f2c1fe09 229 /* Reference count */
d58d5d55 230 int class_w_users;
d58d5d55 231
7245387e
MB		 232 struct snd_soc_jack *mic_jack;
233 int mic_det;
234 int mic_short;
235 int mic_last_report;
236 int mic_delay;
7cfe5617
SW		 237
238#ifdef CONFIG_GPIOLIB
239 struct gpio_chip gpio_chip;
240#endif
d58d5d55
MB		 241};
242
d4754ec9 243static int wm8903_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
f1c0a02f
MB		 244{
245 switch (reg) {
246 case WM8903_SW_RESET_AND_ID:
247 case WM8903_REVISION_NUMBER:
248 case WM8903_INTERRUPT_STATUS_1:
249 case WM8903_WRITE_SEQUENCER_4:
c5b6a9fe
MB		 250 case WM8903_DC_SERVO_READBACK_1:
251 case WM8903_DC_SERVO_READBACK_2:
252 case WM8903_DC_SERVO_READBACK_3:
253 case WM8903_DC_SERVO_READBACK_4:
8d50e447 254 return 1;
f1c0a02f
MB		 255
256 default:
f1c0a02f 257 return 0;
8d50e447 258 }
f1c0a02f
MB		 259}
260
f1c0a02f
MB		 261static void wm8903_reset(struct snd_soc_codec *codec)
262{
8d50e447 263 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
d58d5d55
MB		 264 memcpy(codec->reg_cache, wm8903_reg_defaults,
265 sizeof(wm8903_reg_defaults));
f1c0a02f
MB		 266}
267
42768a12
MB		 268static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
269 struct snd_kcontrol *kcontrol, int event)
270{
271 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
272 mdelay(4);
273
274 return 0;
275}
276
c5b6a9fe
MB		 277static int wm8903_dcs_event(struct snd_soc_dapm_widget *w,
278 struct snd_kcontrol *kcontrol, int event)
279{
280 struct snd_soc_codec *codec = w->codec;
281 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
282
283 switch (event) {
284 case SND_SOC_DAPM_POST_PMU:
285 wm8903->dcs_pending |= 1 << w->shift;
286 break;
287 case SND_SOC_DAPM_PRE_PMD:
288 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
289 1 << w->shift, 0);
290 break;
291 }
292
293 return 0;
294}
295
296#define WM8903_DCS_MODE_WRITE_STOP 0
297#define WM8903_DCS_MODE_START_STOP 2
298
299static void wm8903_seq_notifier(struct snd_soc_dapm_context *dapm,
300 enum snd_soc_dapm_type event, int subseq)
301{
302 struct snd_soc_codec *codec = container_of(dapm,
303 struct snd_soc_codec, dapm);
304 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
305 int dcs_mode = WM8903_DCS_MODE_WRITE_STOP;
306 int i, val;
307
308 /* Complete any pending DC servo starts */
309 if (wm8903->dcs_pending) {
310 dev_dbg(codec->dev, "Starting DC servo for %x\n",
311 wm8903->dcs_pending);
312
313 /* If we've no cached values then we need to do startup */
314 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
315 if (!(wm8903->dcs_pending & (1 << i)))
316 continue;
317
318 if (wm8903->dcs_cache[i]) {
319 dev_dbg(codec->dev,
320 "Restore DC servo %d value %x\n",
321 3 - i, wm8903->dcs_cache[i]);
322
323 snd_soc_write(codec, WM8903_DC_SERVO_4 + i,
324 wm8903->dcs_cache[i] & 0xff);
325 } else {
326 dev_dbg(codec->dev,
327 "Calibrate DC servo %d\n", 3 - i);
328 dcs_mode = WM8903_DCS_MODE_START_STOP;
329 }
330 }
331
332 /* Don't trust the cache for analogue */
333 if (wm8903->class_w_users)
334 dcs_mode = WM8903_DCS_MODE_START_STOP;
335
336 snd_soc_update_bits(codec, WM8903_DC_SERVO_2,
337 WM8903_DCS_MODE_MASK, dcs_mode);
338
339 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
340 WM8903_DCS_ENA_MASK, wm8903->dcs_pending);
341
342 switch (dcs_mode) {
343 case WM8903_DCS_MODE_WRITE_STOP:
344 break;
345
346 case WM8903_DCS_MODE_START_STOP:
347 msleep(270);
348
349 /* Cache the measured offsets for digital */
350 if (wm8903->class_w_users)
351 break;
352
353 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
354 if (!(wm8903->dcs_pending & (1 << i)))
355 continue;
356
357 val = snd_soc_read(codec,
358 WM8903_DC_SERVO_READBACK_1 + i);
359 dev_dbg(codec->dev, "DC servo %d: %x\n",
360 3 - i, val);
361 wm8903->dcs_cache[i] = val;
362 }
363 break;
364
365 default:
366 pr_warn("DCS mode %d delay not set\n", dcs_mode);
367 break;
368 }
369
370 wm8903->dcs_pending = 0;
371 }
372}
373
f1c0a02f
MB		 374/*
375 * When used with DAC outputs only the WM8903 charge pump supports
376 * operation in class W mode, providing very low power consumption
377 * when used with digital sources. Enable and disable this mode
378 * automatically depending on the mixer configuration.
379 *
380 * All the relevant controls are simple switches.
381 */
382static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
383 struct snd_ctl_elem_value *ucontrol)
384{
9d03545d
JN		 385 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
386 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
f1c0a02f 387 struct snd_soc_codec *codec = widget->codec;
b2c812e2 388 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 389 u16 reg;
390 int ret;
391
8d50e447 392 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
f1c0a02f
MB		 393
394 /* Turn it off if we're about to enable bypass */
395 if (ucontrol->value.integer.value[0]) {
396 if (wm8903->class_w_users == 0) {
f0fba2ad 397 dev_dbg(codec->dev, "Disabling Class W\n");
8d50e447 398 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
f1c0a02f
MB		 399 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
400 }
401 wm8903->class_w_users++;
402 }
403
404 /* Implement the change */
405 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
406
407 /* If we've just disabled the last bypass path turn Class W on */
408 if (!ucontrol->value.integer.value[0]) {
409 if (wm8903->class_w_users == 1) {
f0fba2ad 410 dev_dbg(codec->dev, "Enabling Class W\n");
8d50e447 411 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 412 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
413 }
414 wm8903->class_w_users--;
415 }
416
f0fba2ad 417 dev_dbg(codec->dev, "Bypass use count now %d\n",
f1c0a02f
MB		 418 wm8903->class_w_users);
419
420 return ret;
421}
422
423#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
424{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
425 .info = snd_soc_info_volsw, \
426 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
427 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
428
429
69fff9bb
MB		 430static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
431
432static int wm8903_set_deemph(struct snd_soc_codec *codec)
433{
434 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
435 int val, i, best;
436
437 /* If we're using deemphasis select the nearest available sample
438 * rate.
439 */
440 if (wm8903->deemph) {
441 best = 1;
442 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
443 if (abs(wm8903_deemph[i] - wm8903->fs) <
444 abs(wm8903_deemph[best] - wm8903->fs))
445 best = i;
446 }
447
448 val = best << WM8903_DEEMPH_SHIFT;
449 } else {
450 best = 0;
451 val = 0;
452 }
453
454 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n",
455 best, wm8903_deemph[best]);
456
457 return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
458 WM8903_DEEMPH_MASK, val);
459}
460
461static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
462 struct snd_ctl_elem_value *ucontrol)
463{
464 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
465 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
466
467 ucontrol->value.enumerated.item[0] = wm8903->deemph;
468
469 return 0;
470}
471
472static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
473 struct snd_ctl_elem_value *ucontrol)
474{
475 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
476 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
477 int deemph = ucontrol->value.enumerated.item[0];
478 int ret = 0;
479
480 if (deemph > 1)
481 return -EINVAL;
482
483 mutex_lock(&codec->mutex);
484 if (wm8903->deemph != deemph) {
485 wm8903->deemph = deemph;
486
487 wm8903_set_deemph(codec);
488
489 ret = 1;
490 }
491 mutex_unlock(&codec->mutex);
492
493 return ret;
494}
495
f1c0a02f
MB		 496/* ALSA can only do steps of .01dB */
497static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
498
291ce18c 499static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
f1c0a02f
MB		 500static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
501
502static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
503static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
504static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
505static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
506static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
507
460f4aae
MB		 508static const char *hpf_mode_text[] = {
509 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
510};
511
512static const struct soc_enum hpf_mode =
513 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
514
dcf9ada3
MB		 515static const char *osr_text[] = {
516 "Low power", "High performance"
517};
518
519static const struct soc_enum adc_osr =
520 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text);
521
522static const struct soc_enum dac_osr =
523 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text);
524
f1c0a02f
MB		 525static const char *drc_slope_text[] = {
526 "1", "1/2", "1/4", "1/8", "1/16", "0"
527};
528
529static const struct soc_enum drc_slope_r0 =
530 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
531
532static const struct soc_enum drc_slope_r1 =
533 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
534
535static const char *drc_attack_text[] = {
536 "instantaneous",
537 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
538 "46.4ms", "92.8ms", "185.6ms"
539};
540
541static const struct soc_enum drc_attack =
542 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
543
544static const char *drc_decay_text[] = {
545 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
546 "23.87s", "47.56s"
547};
548
549static const struct soc_enum drc_decay =
550 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
551
552static const char *drc_ff_delay_text[] = {
553 "5 samples", "9 samples"
554};
555
556static const struct soc_enum drc_ff_delay =
557 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
558
559static const char *drc_qr_decay_text[] = {
560 "0.725ms", "1.45ms", "5.8ms"
561};
562
563static const struct soc_enum drc_qr_decay =
564 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
565
566static const char *drc_smoothing_text[] = {
567 "Low", "Medium", "High"
568};
569
570static const struct soc_enum drc_smoothing =
571 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
572
573static const char *soft_mute_text[] = {
574 "Fast (fs/2)", "Slow (fs/32)"
575};
576
577static const struct soc_enum soft_mute =
578 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
579
580static const char *mute_mode_text[] = {
581 "Hard", "Soft"
582};
583
584static const struct soc_enum mute_mode =
585 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
586
f1c0a02f
MB		 587static const char *companding_text[] = {
588 "ulaw", "alaw"
589};
590
591static const struct soc_enum dac_companding =
592 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
593
594static const struct soc_enum adc_companding =
595 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
596
597static const char *input_mode_text[] = {
598 "Single-Ended", "Differential Line", "Differential Mic"
599};
600
601static const struct soc_enum linput_mode_enum =
602 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
603
604static const struct soc_enum rinput_mode_enum =
605 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
606
607static const char *linput_mux_text[] = {
608 "IN1L", "IN2L", "IN3L"
609};
610
611static const struct soc_enum linput_enum =
612 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
613
614static const struct soc_enum linput_inv_enum =
615 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
616
617static const char *rinput_mux_text[] = {
618 "IN1R", "IN2R", "IN3R"
619};
620
621static const struct soc_enum rinput_enum =
622 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
623
624static const struct soc_enum rinput_inv_enum =
625 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
626
627
291ce18c
MB		 628static const char *sidetone_text[] = {
629 "None", "Left", "Right"
630};
631
632static const struct soc_enum lsidetone_enum =
633 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
634
635static const struct soc_enum rsidetone_enum =
636 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
637
97945c46
SW		 638static const char *adcinput_text[] = {
639 "ADC", "DMIC"
640};
641
642static const struct soc_enum adcinput_enum =
643 SOC_ENUM_SINGLE(WM8903_CLOCK_RATE_TEST_4, 9, 2, adcinput_text);
644
1e113bf9
MB		 645static const char *aif_text[] = {
646 "Left", "Right"
647};
648
649static const struct soc_enum lcapture_enum =
650 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 7, 2, aif_text);
651
652static const struct soc_enum rcapture_enum =
653 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 6, 2, aif_text);
654
655static const struct soc_enum lplay_enum =
656 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 5, 2, aif_text);
657
658static const struct soc_enum rplay_enum =
659 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 4, 2, aif_text);
660
f1c0a02f
MB		 661static const struct snd_kcontrol_new wm8903_snd_controls[] = {
662
663/* Input PGAs - No TLV since the scale depends on PGA mode */
664SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 665 7, 1, 1),
f1c0a02f
MB		 666SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
667 0, 31, 0),
668SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
669 6, 1, 0),
670
671SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 672 7, 1, 1),
f1c0a02f
MB		 673SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
674 0, 31, 0),
675SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
676 6, 1, 0),
677
678/* ADCs */
dcf9ada3 679SOC_ENUM("ADC OSR", adc_osr),
460f4aae
MB		 680SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
681SOC_ENUM("HPF Mode", hpf_mode),
f1c0a02f
MB		 682SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
683SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
684SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
af901ca1 685SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
f1c0a02f
MB		 686 drc_tlv_thresh),
687SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
688SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
689SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
690SOC_ENUM("DRC Attack Rate", drc_attack),
691SOC_ENUM("DRC Decay Rate", drc_decay),
692SOC_ENUM("DRC FF Delay", drc_ff_delay),
693SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
694SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
af901ca1 695SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
f1c0a02f
MB		 696SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
697SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
698SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
af901ca1 699SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
f1c0a02f
MB		 700SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
701
702SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
61bf35b9 703 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
f1c0a02f
MB		 704SOC_ENUM("ADC Companding Mode", adc_companding),
705SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
706
291ce18c
MB		 707SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
708 12, 0, digital_sidetone_tlv),
709
f1c0a02f 710/* DAC */
dcf9ada3 711SOC_ENUM("DAC OSR", dac_osr),
f1c0a02f
MB		 712SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
713 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
714SOC_ENUM("DAC Soft Mute Rate", soft_mute),
715SOC_ENUM("DAC Mute Mode", mute_mode),
716SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
f1c0a02f
MB		 717SOC_ENUM("DAC Companding Mode", dac_companding),
718SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
69fff9bb
MB		 719SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
720 wm8903_get_deemph, wm8903_put_deemph),
f1c0a02f
MB		 721
722/* Headphones */
723SOC_DOUBLE_R("Headphone Switch",
724 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
725 8, 1, 1),
726SOC_DOUBLE_R("Headphone ZC Switch",
727 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
728 6, 1, 0),
729SOC_DOUBLE_R_TLV("Headphone Volume",
730 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
731 0, 63, 0, out_tlv),
732
733/* Line out */
734SOC_DOUBLE_R("Line Out Switch",
735 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
736 8, 1, 1),
737SOC_DOUBLE_R("Line Out ZC Switch",
738 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
739 6, 1, 0),
740SOC_DOUBLE_R_TLV("Line Out Volume",
741 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
742 0, 63, 0, out_tlv),
743
744/* Speaker */
745SOC_DOUBLE_R("Speaker Switch",
746 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
747SOC_DOUBLE_R("Speaker ZC Switch",
748 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
749SOC_DOUBLE_R_TLV("Speaker Volume",
750 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
751 0, 63, 0, out_tlv),
752};
753
f1c0a02f
MB		 754static const struct snd_kcontrol_new linput_mode_mux =
755 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
756
757static const struct snd_kcontrol_new rinput_mode_mux =
758 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
759
760static const struct snd_kcontrol_new linput_mux =
761 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
762
763static const struct snd_kcontrol_new linput_inv_mux =
764 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
765
766static const struct snd_kcontrol_new rinput_mux =
767 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
768
769static const struct snd_kcontrol_new rinput_inv_mux =
770 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
771
291ce18c
MB		 772static const struct snd_kcontrol_new lsidetone_mux =
773 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
774
775static const struct snd_kcontrol_new rsidetone_mux =
776 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
777
97945c46
SW		 778static const struct snd_kcontrol_new adcinput_mux =
779 SOC_DAPM_ENUM("ADC Input", adcinput_enum);
780
1e113bf9
MB		 781static const struct snd_kcontrol_new lcapture_mux =
782 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum);
783
784static const struct snd_kcontrol_new rcapture_mux =
785 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum);
786
787static const struct snd_kcontrol_new lplay_mux =
788 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum);
789
790static const struct snd_kcontrol_new rplay_mux =
791 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum);
792
f1c0a02f
MB		 793static const struct snd_kcontrol_new left_output_mixer[] = {
794SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
795SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
796SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 797SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 798};
799
800static const struct snd_kcontrol_new right_output_mixer[] = {
801SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
802SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
803SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 804SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 805};
806
807static const struct snd_kcontrol_new left_speaker_mixer[] = {
808SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
809SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
810SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
811SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 812 0, 1, 0),
f1c0a02f
MB		 813};
814
815static const struct snd_kcontrol_new right_speaker_mixer[] = {
816SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
817SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
818SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
819 1, 1, 0),
820SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 821 0, 1, 0),
f1c0a02f
MB		 822};
823
824static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
825SND_SOC_DAPM_INPUT("IN1L"),
826SND_SOC_DAPM_INPUT("IN1R"),
827SND_SOC_DAPM_INPUT("IN2L"),
828SND_SOC_DAPM_INPUT("IN2R"),
829SND_SOC_DAPM_INPUT("IN3L"),
830SND_SOC_DAPM_INPUT("IN3R"),
97945c46 831SND_SOC_DAPM_INPUT("DMICDAT"),
f1c0a02f
MB		 832
833SND_SOC_DAPM_OUTPUT("HPOUTL"),
834SND_SOC_DAPM_OUTPUT("HPOUTR"),
835SND_SOC_DAPM_OUTPUT("LINEOUTL"),
836SND_SOC_DAPM_OUTPUT("LINEOUTR"),
837SND_SOC_DAPM_OUTPUT("LOP"),
838SND_SOC_DAPM_OUTPUT("LON"),
839SND_SOC_DAPM_OUTPUT("ROP"),
840SND_SOC_DAPM_OUTPUT("RON"),
841
842SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
843
844SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
845SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
846 &linput_inv_mux),
847SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
848
849SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
850SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
851 &rinput_inv_mux),
852SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
853
854SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
855SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
856
97945c46
SW		 857SND_SOC_DAPM_MUX("Left ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
858SND_SOC_DAPM_MUX("Right ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
859
1e113bf9
MB		 860SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0),
861SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0),
862
863SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux),
864SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux),
865
866SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
867SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
f1c0a02f 868
291ce18c
MB		 869SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
870SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
871
1e113bf9
MB		 872SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0),
873SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0),
874
875SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux),
876SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux),
877
878SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0),
879SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0),
f1c0a02f
MB		 880
881SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
882 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
883SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
884 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
885
886SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
887 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
888SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
889 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
890
1b877cb5
DL		 891SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
892 1, 0, NULL, 0),
893SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
13a9983e
MB		 894 0, 0, NULL, 0),
895
1b877cb5 896SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 1, 0,
13a9983e 897 NULL, 0),
1b877cb5 898SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 0, 0,
13a9983e
MB		 899 NULL, 0),
900
901SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0),
902SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0),
1b877cb5
DL		 903SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0),
904SND_SOC_DAPM_PGA_S("HPL_ENA", 1, WM8903_ANALOGUE_HP_0, 4, 0, NULL, 0),
13a9983e
MB		 905SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0),
906SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0),
1b877cb5
DL		 907SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0),
908SND_SOC_DAPM_PGA_S("HPR_ENA", 1, WM8903_ANALOGUE_HP_0, 0, 0, NULL, 0),
13a9983e
MB		 909
910SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0,
911 NULL, 0),
912SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0,
913 NULL, 0),
1b877cb5
DL		 914SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 5, 0,
915 NULL, 0),
916SND_SOC_DAPM_PGA_S("LINEOUTL_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 4, 0,
13a9983e
MB		 917 NULL, 0),
918SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0,
919 NULL, 0),
920SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0,
921 NULL, 0),
1b877cb5
DL		 922SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 1, 0,
923 NULL, 0),
924SND_SOC_DAPM_PGA_S("LINEOUTR_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 0, 0,
13a9983e
MB		 925 NULL, 0),
926
c5b6a9fe
MB		 927SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0),
928SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM, 3, 0, wm8903_dcs_event,
929 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
930SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM, 2, 0, wm8903_dcs_event,
931 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
932SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM, 1, 0, wm8903_dcs_event,
933 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
934SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM, 0, 0, wm8903_dcs_event,
935 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 936
937SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
938 NULL, 0),
939SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
940 NULL, 0),
941
42768a12
MB		 942SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
943 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
c2aef4ff 944SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
2c8be5a2 945SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0),
f1c0a02f
MB		 946};
947
ecd01512 948static const struct snd_soc_dapm_route wm8903_intercon[] = {
f1c0a02f 949
2c8be5a2
MB		 950 { "CLK_DSP", NULL, "CLK_SYS" },
951 { "Mic Bias", NULL, "CLK_SYS" },
952 { "HPL_DCS", NULL, "CLK_SYS" },
953 { "HPR_DCS", NULL, "CLK_SYS" },
954 { "LINEOUTL_DCS", NULL, "CLK_SYS" },
955 { "LINEOUTR_DCS", NULL, "CLK_SYS" },
956
f1c0a02f
MB		 957 { "Left Input Mux", "IN1L", "IN1L" },
958 { "Left Input Mux", "IN2L", "IN2L" },
959 { "Left Input Mux", "IN3L", "IN3L" },
960
961 { "Left Input Inverting Mux", "IN1L", "IN1L" },
962 { "Left Input Inverting Mux", "IN2L", "IN2L" },
963 { "Left Input Inverting Mux", "IN3L", "IN3L" },
964
965 { "Right Input Mux", "IN1R", "IN1R" },
966 { "Right Input Mux", "IN2R", "IN2R" },
967 { "Right Input Mux", "IN3R", "IN3R" },
968
969 { "Right Input Inverting Mux", "IN1R", "IN1R" },
970 { "Right Input Inverting Mux", "IN2R", "IN2R" },
971 { "Right Input Inverting Mux", "IN3R", "IN3R" },
972
973 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
974 { "Left Input Mode Mux", "Differential Line",
975 "Left Input Mux" },
976 { "Left Input Mode Mux", "Differential Line",
977 "Left Input Inverting Mux" },
978 { "Left Input Mode Mux", "Differential Mic",
979 "Left Input Mux" },
980 { "Left Input Mode Mux", "Differential Mic",
981 "Left Input Inverting Mux" },
982
983 { "Right Input Mode Mux", "Single-Ended",
984 "Right Input Inverting Mux" },
985 { "Right Input Mode Mux", "Differential Line",
986 "Right Input Mux" },
987 { "Right Input Mode Mux", "Differential Line",
988 "Right Input Inverting Mux" },
989 { "Right Input Mode Mux", "Differential Mic",
990 "Right Input Mux" },
991 { "Right Input Mode Mux", "Differential Mic",
992 "Right Input Inverting Mux" },
993
994 { "Left Input PGA", NULL, "Left Input Mode Mux" },
995 { "Right Input PGA", NULL, "Right Input Mode Mux" },
996
97945c46
SW		 997 { "Left ADC Input", "ADC", "Left Input PGA" },
998 { "Left ADC Input", "DMIC", "DMICDAT" },
999 { "Right ADC Input", "ADC", "Right Input PGA" },
1000 { "Right ADC Input", "DMIC", "DMICDAT" },
1001
1e113bf9
MB		 1002 { "Left Capture Mux", "Left", "ADCL" },
1003 { "Left Capture Mux", "Right", "ADCR" },
1004
1005 { "Right Capture Mux", "Left", "ADCL" },
1006 { "Right Capture Mux", "Right", "ADCR" },
1007
1008 { "AIFTXL", NULL, "Left Capture Mux" },
1009 { "AIFTXR", NULL, "Right Capture Mux" },
1010
97945c46 1011 { "ADCL", NULL, "Left ADC Input" },
c2aef4ff 1012 { "ADCL", NULL, "CLK_DSP" },
97945c46 1013 { "ADCR", NULL, "Right ADC Input" },
c2aef4ff
MB		 1014 { "ADCR", NULL, "CLK_DSP" },
1015
1e113bf9
MB		 1016 { "Left Playback Mux", "Left", "AIFRXL" },
1017 { "Left Playback Mux", "Right", "AIFRXR" },
1018
1019 { "Right Playback Mux", "Left", "AIFRXL" },
1020 { "Right Playback Mux", "Right", "AIFRXR" },
1021
291ce18c
MB		 1022 { "DACL Sidetone", "Left", "ADCL" },
1023 { "DACL Sidetone", "Right", "ADCR" },
1024 { "DACR Sidetone", "Left", "ADCL" },
1025 { "DACR Sidetone", "Right", "ADCR" },
1026
1e113bf9 1027 { "DACL", NULL, "Left Playback Mux" },
291ce18c 1028 { "DACL", NULL, "DACL Sidetone" },
c2aef4ff 1029 { "DACL", NULL, "CLK_DSP" },
1e113bf9
MB		 1030
1031 { "DACR", NULL, "Right Playback Mux" },
291ce18c 1032 { "DACR", NULL, "DACR Sidetone" },
c2aef4ff 1033 { "DACR", NULL, "CLK_DSP" },
f1c0a02f
MB		 1034
1035 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1036 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1037 { "Left Output Mixer", "DACL Switch", "DACL" },
1038 { "Left Output Mixer", "DACR Switch", "DACR" },
1039
1040 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1041 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1042 { "Right Output Mixer", "DACL Switch", "DACL" },
1043 { "Right Output Mixer", "DACR Switch", "DACR" },
1044
1045 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1046 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1047 { "Left Speaker Mixer", "DACL Switch", "DACL" },
1048 { "Left Speaker Mixer", "DACR Switch", "DACR" },
1049
1050 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1051 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1052 { "Right Speaker Mixer", "DACL Switch", "DACL" },
1053 { "Right Speaker Mixer", "DACR Switch", "DACR" },
1054
1055 { "Left Line Output PGA", NULL, "Left Output Mixer" },
1056 { "Right Line Output PGA", NULL, "Right Output Mixer" },
1057
1058 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
1059 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
1060
1061 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
1062 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
1063
1b877cb5
DL		 1064 { "HPL_ENA", NULL, "Left Headphone Output PGA" },
1065 { "HPR_ENA", NULL, "Right Headphone Output PGA" },
1066 { "HPL_ENA_DLY", NULL, "HPL_ENA" },
1067 { "HPR_ENA_DLY", NULL, "HPR_ENA" },
1068 { "LINEOUTL_ENA", NULL, "Left Line Output PGA" },
1069 { "LINEOUTR_ENA", NULL, "Right Line Output PGA" },
1070 { "LINEOUTL_ENA_DLY", NULL, "LINEOUTL_ENA" },
1071 { "LINEOUTR_ENA_DLY", NULL, "LINEOUTR_ENA" },
13a9983e 1072
c5b6a9fe
MB		 1073 { "HPL_DCS", NULL, "DCS Master" },
1074 { "HPR_DCS", NULL, "DCS Master" },
1075 { "LINEOUTL_DCS", NULL, "DCS Master" },
1076 { "LINEOUTR_DCS", NULL, "DCS Master" },
1077
13a9983e
MB		 1078 { "HPL_DCS", NULL, "HPL_ENA_DLY" },
1079 { "HPR_DCS", NULL, "HPR_ENA_DLY" },
1080 { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" },
1081 { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" },
1082
1083 { "HPL_ENA_OUTP", NULL, "HPL_DCS" },
1084 { "HPR_ENA_OUTP", NULL, "HPR_DCS" },
1085 { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" },
1086 { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" },
1087
1088 { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" },
1089 { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" },
1090 { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" },
1091 { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" },
1092
1093 { "HPOUTL", NULL, "HPL_RMV_SHORT" },
1094 { "HPOUTR", NULL, "HPR_RMV_SHORT" },
1095 { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" },
1096 { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" },
f1c0a02f
MB		 1097
1098 { "LOP", NULL, "Left Speaker PGA" },
1099 { "LON", NULL, "Left Speaker PGA" },
1100
1101 { "ROP", NULL, "Right Speaker PGA" },
1102 { "RON", NULL, "Right Speaker PGA" },
42768a12
MB		 1103
1104 { "Left Headphone Output PGA", NULL, "Charge Pump" },
1105 { "Right Headphone Output PGA", NULL, "Charge Pump" },
1106 { "Left Line Output PGA", NULL, "Charge Pump" },
1107 { "Right Line Output PGA", NULL, "Charge Pump" },
f1c0a02f
MB		 1108};
1109
f1c0a02f
MB		 1110static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1111 enum snd_soc_bias_level level)
1112{
f1c0a02f
MB		 1113 switch (level) {
1114 case SND_SOC_BIAS_ON:
66daaa59 1115 break;
22f226dd 1116
f1c0a02f 1117 case SND_SOC_BIAS_PREPARE:
66daaa59
MB		 1118 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1119 WM8903_VMID_RES_MASK,
1120 WM8903_VMID_RES_50K);
f1c0a02f
MB		 1121 break;
1122
1123 case SND_SOC_BIAS_STANDBY:
ce6120cc 1124 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
22f226dd
MB		 1125 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1126 WM8903_POBCTRL | WM8903_ISEL_MASK |
1127 WM8903_STARTUP_BIAS_ENA |
1128 WM8903_BIAS_ENA,
1129 WM8903_POBCTRL |
1130 (2 << WM8903_ISEL_SHIFT) |
1131 WM8903_STARTUP_BIAS_ENA);
1132
1133 snd_soc_update_bits(codec,
1134 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1135 WM8903_SPK_DISCHARGE,
1136 WM8903_SPK_DISCHARGE);
1137
1138 msleep(33);
1139
1140 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
1141 WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1142 WM8903_SPKL_ENA | WM8903_SPKR_ENA);
1143
1144 snd_soc_update_bits(codec,
1145 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1146 WM8903_SPK_DISCHARGE, 0);
1147
1148 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1149 WM8903_VMID_TIE_ENA |
1150 WM8903_BUFIO_ENA |
1151 WM8903_VMID_IO_ENA |
1152 WM8903_VMID_SOFT_MASK |
1153 WM8903_VMID_RES_MASK |
1154 WM8903_VMID_BUF_ENA,
1155 WM8903_VMID_TIE_ENA |
1156 WM8903_BUFIO_ENA |
1157 WM8903_VMID_IO_ENA |
1158 (2 << WM8903_VMID_SOFT_SHIFT) |
1159 WM8903_VMID_RES_250K |
1160 WM8903_VMID_BUF_ENA);
1161
1162 msleep(129);
1163
1164 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
1165 WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1166 0);
1167
1168 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1169 WM8903_VMID_SOFT_MASK, 0);
1170
1171 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1172 WM8903_VMID_RES_MASK,
1173 WM8903_VMID_RES_50K);
1174
1175 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1176 WM8903_BIAS_ENA | WM8903_POBCTRL,
1177 WM8903_BIAS_ENA);
f1c0a02f 1178
f1c0a02f
MB		 1179 /* By default no bypass paths are enabled so
1180 * enable Class W support.
1181 */
f0fba2ad 1182 dev_dbg(codec->dev, "Enabling Class W\n");
524d7692
MB		 1183 snd_soc_update_bits(codec, WM8903_CLASS_W_0,
1184 WM8903_CP_DYN_FREQ |
1185 WM8903_CP_DYN_V,
1186 WM8903_CP_DYN_FREQ |
1187 WM8903_CP_DYN_V);
f1c0a02f
MB		 1188 }
1189
66daaa59
MB		 1190 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1191 WM8903_VMID_RES_MASK,
1192 WM8903_VMID_RES_250K);
f1c0a02f
MB		 1193 break;
1194
1195 case SND_SOC_BIAS_OFF:
b4d06f45
MB		 1196 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1197 WM8903_BIAS_ENA, 0);
1198
1199 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1200 WM8903_VMID_SOFT_MASK,
1201 2 << WM8903_VMID_SOFT_SHIFT);
1202
1203 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1204 WM8903_VMID_BUF_ENA, 0);
1205
1206 msleep(290);
1207
1208 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1209 WM8903_VMID_TIE_ENA | WM8903_BUFIO_ENA |
1210 WM8903_VMID_IO_ENA | WM8903_VMID_RES_MASK |
1211 WM8903_VMID_SOFT_MASK |
1212 WM8903_VMID_BUF_ENA, 0);
1213
1214 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1215 WM8903_STARTUP_BIAS_ENA, 0);
f1c0a02f
MB		 1216 break;
1217 }
1218
ce6120cc 1219 codec->dapm.bias_level = level;
f1c0a02f
MB		 1220
1221 return 0;
1222}
1223
1224static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1225 int clk_id, unsigned int freq, int dir)
1226{
1227 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1228 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1229
1230 wm8903->sysclk = freq;
1231
1232 return 0;
1233}
1234
1235static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1236 unsigned int fmt)
1237{
1238 struct snd_soc_codec *codec = codec_dai->codec;
8d50e447 1239 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
f1c0a02f
MB		 1240
1241 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1242 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1243
1244 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1245 case SND_SOC_DAIFMT_CBS_CFS:
1246 break;
1247 case SND_SOC_DAIFMT_CBS_CFM:
1248 aif1 |= WM8903_LRCLK_DIR;
1249 break;
1250 case SND_SOC_DAIFMT_CBM_CFM:
1251 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1252 break;
1253 case SND_SOC_DAIFMT_CBM_CFS:
1254 aif1 |= WM8903_BCLK_DIR;
1255 break;
1256 default:
1257 return -EINVAL;
1258 }
1259
1260 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1261 case SND_SOC_DAIFMT_DSP_A:
1262 aif1 |= 0x3;
1263 break;
1264 case SND_SOC_DAIFMT_DSP_B:
1265 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1266 break;
1267 case SND_SOC_DAIFMT_I2S:
1268 aif1 |= 0x2;
1269 break;
1270 case SND_SOC_DAIFMT_RIGHT_J:
1271 aif1 |= 0x1;
1272 break;
1273 case SND_SOC_DAIFMT_LEFT_J:
1274 break;
1275 default:
1276 return -EINVAL;
1277 }
1278
1279 /* Clock inversion */
1280 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1281 case SND_SOC_DAIFMT_DSP_A:
1282 case SND_SOC_DAIFMT_DSP_B:
1283 /* frame inversion not valid for DSP modes */
1284 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1285 case SND_SOC_DAIFMT_NB_NF:
1286 break;
1287 case SND_SOC_DAIFMT_IB_NF:
1288 aif1 |= WM8903_AIF_BCLK_INV;
1289 break;
1290 default:
1291 return -EINVAL;
1292 }
1293 break;
1294 case SND_SOC_DAIFMT_I2S:
1295 case SND_SOC_DAIFMT_RIGHT_J:
1296 case SND_SOC_DAIFMT_LEFT_J:
1297 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1298 case SND_SOC_DAIFMT_NB_NF:
1299 break;
1300 case SND_SOC_DAIFMT_IB_IF:
1301 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1302 break;
1303 case SND_SOC_DAIFMT_IB_NF:
1304 aif1 |= WM8903_AIF_BCLK_INV;
1305 break;
1306 case SND_SOC_DAIFMT_NB_IF:
1307 aif1 |= WM8903_AIF_LRCLK_INV;
1308 break;
1309 default:
1310 return -EINVAL;
1311 }
1312 break;
1313 default:
1314 return -EINVAL;
1315 }
1316
8d50e447 1317 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
f1c0a02f
MB		 1318
1319 return 0;
1320}
1321
1322static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1323{
1324 struct snd_soc_codec *codec = codec_dai->codec;
1325 u16 reg;
1326
8d50e447 1327 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1328
1329 if (mute)
1330 reg |= WM8903_DAC_MUTE;
1331 else
1332 reg &= ~WM8903_DAC_MUTE;
1333
8d50e447 1334 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
f1c0a02f
MB		 1335
1336 return 0;
1337}
1338
1339/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1340 * for optimal performance so we list the lower rates first and match
1341 * on the last match we find. */
1342static struct {
1343 int div;
1344 int rate;
1345 int mode;
1346 int mclk_div;
1347} clk_sys_ratios[] = {
1348 { 64, 0x0, 0x0, 1 },
1349 { 68, 0x0, 0x1, 1 },
1350 { 125, 0x0, 0x2, 1 },
1351 { 128, 0x1, 0x0, 1 },
1352 { 136, 0x1, 0x1, 1 },
1353 { 192, 0x2, 0x0, 1 },
1354 { 204, 0x2, 0x1, 1 },
1355
1356 { 64, 0x0, 0x0, 2 },
1357 { 68, 0x0, 0x1, 2 },
1358 { 125, 0x0, 0x2, 2 },
1359 { 128, 0x1, 0x0, 2 },
1360 { 136, 0x1, 0x1, 2 },
1361 { 192, 0x2, 0x0, 2 },
1362 { 204, 0x2, 0x1, 2 },
1363
1364 { 250, 0x2, 0x2, 1 },
1365 { 256, 0x3, 0x0, 1 },
1366 { 272, 0x3, 0x1, 1 },
1367 { 384, 0x4, 0x0, 1 },
1368 { 408, 0x4, 0x1, 1 },
1369 { 375, 0x4, 0x2, 1 },
1370 { 512, 0x5, 0x0, 1 },
1371 { 544, 0x5, 0x1, 1 },
1372 { 500, 0x5, 0x2, 1 },
1373 { 768, 0x6, 0x0, 1 },
1374 { 816, 0x6, 0x1, 1 },
1375 { 750, 0x6, 0x2, 1 },
1376 { 1024, 0x7, 0x0, 1 },
1377 { 1088, 0x7, 0x1, 1 },
1378 { 1000, 0x7, 0x2, 1 },
1379 { 1408, 0x8, 0x0, 1 },
1380 { 1496, 0x8, 0x1, 1 },
1381 { 1536, 0x9, 0x0, 1 },
1382 { 1632, 0x9, 0x1, 1 },
1383 { 1500, 0x9, 0x2, 1 },
1384
1385 { 250, 0x2, 0x2, 2 },
1386 { 256, 0x3, 0x0, 2 },
1387 { 272, 0x3, 0x1, 2 },
1388 { 384, 0x4, 0x0, 2 },
1389 { 408, 0x4, 0x1, 2 },
1390 { 375, 0x4, 0x2, 2 },
1391 { 512, 0x5, 0x0, 2 },
1392 { 544, 0x5, 0x1, 2 },
1393 { 500, 0x5, 0x2, 2 },
1394 { 768, 0x6, 0x0, 2 },
1395 { 816, 0x6, 0x1, 2 },
1396 { 750, 0x6, 0x2, 2 },
1397 { 1024, 0x7, 0x0, 2 },
1398 { 1088, 0x7, 0x1, 2 },
1399 { 1000, 0x7, 0x2, 2 },
1400 { 1408, 0x8, 0x0, 2 },
1401 { 1496, 0x8, 0x1, 2 },
1402 { 1536, 0x9, 0x0, 2 },
1403 { 1632, 0x9, 0x1, 2 },
1404 { 1500, 0x9, 0x2, 2 },
1405};
1406
1407/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1408static struct {
1409 int ratio;
1410 int div;
1411} bclk_divs[] = {
1412 { 10, 0 },
f1c0a02f
MB		 1413 { 20, 2 },
1414 { 30, 3 },
1415 { 40, 4 },
1416 { 50, 5 },
f1c0a02f
MB		 1417 { 60, 7 },
1418 { 80, 8 },
1419 { 100, 9 },
f1c0a02f
MB		 1420 { 120, 11 },
1421 { 160, 12 },
1422 { 200, 13 },
1423 { 220, 14 },
1424 { 240, 15 },
f1c0a02f
MB		 1425 { 300, 17 },
1426 { 320, 18 },
1427 { 440, 19 },
1428 { 480, 20 },
1429};
1430
1431/* Sample rates for DSP */
1432static struct {
1433 int rate;
1434 int value;
1435} sample_rates[] = {
1436 { 8000, 0 },
1437 { 11025, 1 },
1438 { 12000, 2 },
1439 { 16000, 3 },
1440 { 22050, 4 },
1441 { 24000, 5 },
1442 { 32000, 6 },
1443 { 44100, 7 },
1444 { 48000, 8 },
1445 { 88200, 9 },
1446 { 96000, 10 },
1447 { 0, 0 },
1448};
1449
f1c0a02f 1450static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1451 struct snd_pcm_hw_params *params,
1452 struct snd_soc_dai *dai)
f1c0a02f
MB		 1453{
1454 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1455 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 1456 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1457 int fs = params_rate(params);
1458 int bclk;
1459 int bclk_div;
1460 int i;
1461 int dsp_config;
1462 int clk_config;
1463 int best_val;
1464 int cur_val;
1465 int clk_sys;
1466
8d50e447
MB		 1467 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1468 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1469 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1470 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1471 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1472 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1473
9e79261f
MB		 1474 /* Enable sloping stopband filter for low sample rates */
1475 if (fs <= 24000)
1476 dac_digital1 |= WM8903_DAC_SB_FILT;
1477 else
1478 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1479
f1c0a02f
MB		 1480 /* Configure sample rate logic for DSP - choose nearest rate */
1481 dsp_config = 0;
1482 best_val = abs(sample_rates[dsp_config].rate - fs);
1483 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1484 cur_val = abs(sample_rates[i].rate - fs);
1485 if (cur_val <= best_val) {
1486 dsp_config = i;
1487 best_val = cur_val;
1488 }
1489 }
1490
f0fba2ad 1491 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
f1c0a02f
MB		 1492 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1493 clock1 |= sample_rates[dsp_config].value;
1494
1495 aif1 &= ~WM8903_AIF_WL_MASK;
1496 bclk = 2 * fs;
1497 switch (params_format(params)) {
1498 case SNDRV_PCM_FORMAT_S16_LE:
1499 bclk *= 16;
1500 break;
1501 case SNDRV_PCM_FORMAT_S20_3LE:
1502 bclk *= 20;
1503 aif1 |= 0x4;
1504 break;
1505 case SNDRV_PCM_FORMAT_S24_LE:
1506 bclk *= 24;
1507 aif1 |= 0x8;
1508 break;
1509 case SNDRV_PCM_FORMAT_S32_LE:
1510 bclk *= 32;
1511 aif1 |= 0xc;
1512 break;
1513 default:
1514 return -EINVAL;
1515 }
1516
f0fba2ad 1517 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n",
f1c0a02f
MB		 1518 wm8903->sysclk, fs);
1519
1520 /* We may not have an MCLK which allows us to generate exactly
1521 * the clock we want, particularly with USB derived inputs, so
1522 * approximate.
1523 */
1524 clk_config = 0;
1525 best_val = abs((wm8903->sysclk /
1526 (clk_sys_ratios[0].mclk_div *
1527 clk_sys_ratios[0].div)) - fs);
1528 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1529 cur_val = abs((wm8903->sysclk /
1530 (clk_sys_ratios[i].mclk_div *
1531 clk_sys_ratios[i].div)) - fs);
1532
1533 if (cur_val <= best_val) {
1534 clk_config = i;
1535 best_val = cur_val;
1536 }
1537 }
1538
1539 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1540 clock0 |= WM8903_MCLKDIV2;
1541 clk_sys = wm8903->sysclk / 2;
1542 } else {
1543 clock0 &= ~WM8903_MCLKDIV2;
1544 clk_sys = wm8903->sysclk;
1545 }
1546
1547 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1548 WM8903_CLK_SYS_MODE_MASK);
1549 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1550 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1551
f0fba2ad 1552 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
f1c0a02f
MB		 1553 clk_sys_ratios[clk_config].rate,
1554 clk_sys_ratios[clk_config].mode,
1555 clk_sys_ratios[clk_config].div);
1556
f0fba2ad 1557 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
f1c0a02f
MB		 1558
1559 /* We may not get quite the right frequency if using
1560 * approximate clocks so look for the closest match that is
1561 * higher than the target (we need to ensure that there enough
1562 * BCLKs to clock out the samples).
1563 */
1564 bclk_div = 0;
1565 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1566 i = 1;
1567 while (i < ARRAY_SIZE(bclk_divs)) {
1568 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1569 if (cur_val < 0) /* BCLK table is sorted */
1570 break;
1571 bclk_div = i;
1572 best_val = cur_val;
1573 i++;
1574 }
1575
1576 aif2 &= ~WM8903_BCLK_DIV_MASK;
1577 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1578
f0fba2ad 1579 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
f1c0a02f
MB		 1580 bclk_divs[bclk_div].ratio / 10, bclk,
1581 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1582
1583 aif2 |= bclk_divs[bclk_div].div;
1584 aif3 |= bclk / fs;
1585
69fff9bb
MB		 1586 wm8903->fs = params_rate(params);
1587 wm8903_set_deemph(codec);
1588
8d50e447
MB		 1589 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1590 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1591 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1592 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1593 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1594 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
f1c0a02f
MB		 1595
1596 return 0;
1597}
1598
7245387e
MB		 1599/**
1600 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1601 *
1602 * @codec: WM8903 codec
1603 * @jack: jack to report detection events on
1604 * @det: value to report for presence detection
1605 * @shrt: value to report for short detection
1606 *
1607 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1608 * being used to bring out signals to the processor then only platform
1609 * data configuration is needed for WM8903 and processor GPIOs should
1610 * be configured using snd_soc_jack_add_gpios() instead.
1611 *
1612 * The current threasholds for detection should be configured using
1613 * micdet_cfg in the platform data. Using this function will force on
1614 * the microphone bias for the device.
1615 */
1616int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1617 int det, int shrt)
1618{
b2c812e2 1619 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
69266866 1620 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
7245387e
MB		 1621
1622 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1623 det, shrt);
1624
1625 /* Store the configuration */
1626 wm8903->mic_jack = jack;
1627 wm8903->mic_det = det;
1628 wm8903->mic_short = shrt;
1629
1630 /* Enable interrupts we've got a report configured for */
1631 if (det)
1632 irq_mask &= ~WM8903_MICDET_EINT;
1633 if (shrt)
1634 irq_mask &= ~WM8903_MICSHRT_EINT;
1635
1636 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1637 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1638 irq_mask);
1639
3088e3b4 1640 if (det || shrt) {
69266866
MB		 1641 /* Enable mic detection, this may not have been set through
1642 * platform data (eg, if the defaults are OK). */
1643 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1644 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1645 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1646 WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1647 } else {
1648 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1649 WM8903_MICDET_ENA, 0);
1650 }
7245387e
MB		 1651
1652 return 0;
1653}
1654EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1655
8abd16a6
MB		 1656static irqreturn_t wm8903_irq(int irq, void *data)
1657{
f0fba2ad
LG		 1658 struct snd_soc_codec *codec = data;
1659 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
7245387e
MB		 1660 int mic_report;
1661 int int_pol;
1662 int int_val = 0;
1663 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK);
8abd16a6 1664
7245387e 1665 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask;
8abd16a6 1666
7245387e 1667 if (int_val & WM8903_WSEQ_BUSY_EINT) {
b4d06f45 1668 dev_warn(codec->dev, "Write sequencer done\n");
8abd16a6
MB		 1669 }
1670
7245387e
MB		 1671 /*
1672 * The rest is microphone jack detection. We need to manually
1673 * invert the polarity of the interrupt after each event - to
1674 * simplify the code keep track of the last state we reported
1675 * and just invert the relevant bits in both the report and
1676 * the polarity register.
1677 */
1678 mic_report = wm8903->mic_last_report;
1679 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
1680
1435b940 1681#ifndef CONFIG_SND_SOC_WM8903_MODULE
2bbb5d66
MB		 1682 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
1683 trace_snd_soc_jack_irq(dev_name(codec->dev));
1435b940 1684#endif
2bbb5d66 1685
7245387e
MB		 1686 if (int_val & WM8903_MICSHRT_EINT) {
1687 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
1688
1689 mic_report ^= wm8903->mic_short;
1690 int_pol ^= WM8903_MICSHRT_INV;
1691 }
1692
1693 if (int_val & WM8903_MICDET_EINT) {
1694 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol);
1695
1696 mic_report ^= wm8903->mic_det;
1697 int_pol ^= WM8903_MICDET_INV;
1698
1699 msleep(wm8903->mic_delay);
1700 }
1701
1702 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1,
1703 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
1704
1705 snd_soc_jack_report(wm8903->mic_jack, mic_report,
1706 wm8903->mic_short | wm8903->mic_det);
1707
1708 wm8903->mic_last_report = mic_report;
1709
8abd16a6
MB		 1710 return IRQ_HANDLED;
1711}
1712
f1c0a02f
MB		 1713#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1714 SNDRV_PCM_RATE_11025 | \
1715 SNDRV_PCM_RATE_16000 | \
1716 SNDRV_PCM_RATE_22050 | \
1717 SNDRV_PCM_RATE_32000 | \
1718 SNDRV_PCM_RATE_44100 | \
1719 SNDRV_PCM_RATE_48000 | \
1720 SNDRV_PCM_RATE_88200 | \
1721 SNDRV_PCM_RATE_96000)
1722
1723#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1724 SNDRV_PCM_RATE_11025 | \
1725 SNDRV_PCM_RATE_16000 | \
1726 SNDRV_PCM_RATE_22050 | \
1727 SNDRV_PCM_RATE_32000 | \
1728 SNDRV_PCM_RATE_44100 | \
1729 SNDRV_PCM_RATE_48000)
1730
1731#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1732 SNDRV_PCM_FMTBIT_S20_3LE |\
1733 SNDRV_PCM_FMTBIT_S24_LE)
1734
6335d055 1735static struct snd_soc_dai_ops wm8903_dai_ops = {
6335d055
EM		 1736 .hw_params = wm8903_hw_params,
1737 .digital_mute = wm8903_digital_mute,
1738 .set_fmt = wm8903_set_dai_fmt,
1739 .set_sysclk = wm8903_set_dai_sysclk,
1740};
1741
f0fba2ad
LG		 1742static struct snd_soc_dai_driver wm8903_dai = {
1743 .name = "wm8903-hifi",
f1c0a02f
MB		 1744 .playback = {
1745 .stream_name = "Playback",
1746 .channels_min = 2,
1747 .channels_max = 2,
1748 .rates = WM8903_PLAYBACK_RATES,
1749 .formats = WM8903_FORMATS,
1750 },
1751 .capture = {
1752 .stream_name = "Capture",
1753 .channels_min = 2,
1754 .channels_max = 2,
1755 .rates = WM8903_CAPTURE_RATES,
1756 .formats = WM8903_FORMATS,
1757 },
6335d055 1758 .ops = &wm8903_dai_ops,
0d960e88 1759 .symmetric_rates = 1,
f1c0a02f 1760};
f1c0a02f 1761
f0fba2ad 1762static int wm8903_suspend(struct snd_soc_codec *codec, pm_message_t state)
f1c0a02f 1763{
f1c0a02f
MB		 1764 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1765
1766 return 0;
1767}
1768
f0fba2ad 1769static int wm8903_resume(struct snd_soc_codec *codec)
f1c0a02f 1770{
f1c0a02f
MB		 1771 int i;
1772 u16 *reg_cache = codec->reg_cache;
40aa7030 1773 u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults),
f1c0a02f
MB		 1774 GFP_KERNEL);
1775
1776 /* Bring the codec back up to standby first to minimise pop/clicks */
1777 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
f1c0a02f
MB		 1778
1779 /* Sync back everything else */
1780 if (tmp_cache) {
1781 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1782 if (tmp_cache[i] != reg_cache[i])
8d50e447 1783 snd_soc_write(codec, i, tmp_cache[i]);
40aa7030 1784 kfree(tmp_cache);
f1c0a02f 1785 } else {
f0fba2ad 1786 dev_err(codec->dev, "Failed to allocate temporary cache\n");
f1c0a02f
MB		 1787 }
1788
1789 return 0;
1790}
1791
7cfe5617
SW		 1792#ifdef CONFIG_GPIOLIB
1793static inline struct wm8903_priv *gpio_to_wm8903(struct gpio_chip *chip)
1794{
1795 return container_of(chip, struct wm8903_priv, gpio_chip);
1796}
1797
1798static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset)
1799{
1800 if (offset >= WM8903_NUM_GPIO)
1801 return -EINVAL;
1802
1803 return 0;
1804}
1805
1806static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
1807{
1808 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1809 struct snd_soc_codec *codec = wm8903->codec;
1810 unsigned int mask, val;
1811
1812 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK;
1813 val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) |
1814 WM8903_GP1_DIR;
1815
1816 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1817 mask, val);
1818}
1819
1820static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset)
1821{
1822 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1823 struct snd_soc_codec *codec = wm8903->codec;
1824 int reg;
1825
1826 reg = snd_soc_read(codec, WM8903_GPIO_CONTROL_1 + offset);
1827
1828 return (reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT;
1829}
1830
1831static int wm8903_gpio_direction_out(struct gpio_chip *chip,
1832 unsigned offset, int value)
1833{
1834 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1835 struct snd_soc_codec *codec = wm8903->codec;
1836 unsigned int mask, val;
1837
1838 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK;
1839 val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) |
1840 (value << WM8903_GP2_LVL_SHIFT);
1841
1842 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1843 mask, val);
1844}
1845
1846static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1847{
1848 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1849 struct snd_soc_codec *codec = wm8903->codec;
1850
1851 snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
c8059930
MB		 1852 WM8903_GP1_LVL_MASK,
1853 !!value << WM8903_GP1_LVL_SHIFT);
7cfe5617
SW		 1854}
1855
1856static struct gpio_chip wm8903_template_chip = {
1857 .label = "wm8903",
1858 .owner = THIS_MODULE,
1859 .request = wm8903_gpio_request,
1860 .direction_input = wm8903_gpio_direction_in,
1861 .get = wm8903_gpio_get,
1862 .direction_output = wm8903_gpio_direction_out,
1863 .set = wm8903_gpio_set,
1864 .can_sleep = 1,
1865};
1866
1867static void wm8903_init_gpio(struct snd_soc_codec *codec)
1868{
1869 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1870 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1871 int ret;
1872
1873 wm8903->gpio_chip = wm8903_template_chip;
1874 wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO;
1875 wm8903->gpio_chip.dev = codec->dev;
1876
1877 if (pdata && pdata->gpio_base)
1878 wm8903->gpio_chip.base = pdata->gpio_base;
1879 else
1880 wm8903->gpio_chip.base = -1;
1881
1882 ret = gpiochip_add(&wm8903->gpio_chip);
1883 if (ret != 0)
1884 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
1885}
1886
1887static void wm8903_free_gpio(struct snd_soc_codec *codec)
1888{
1889 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1890 int ret;
1891
1892 ret = gpiochip_remove(&wm8903->gpio_chip);
1893 if (ret != 0)
1894 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
1895}
1896#else
1897static void wm8903_init_gpio(struct snd_soc_codec *codec)
1898{
1899}
1900
1901static void wm8903_free_gpio(struct snd_soc_codec *codec)
1902{
1903}
1904#endif
1905
f0fba2ad 1906static int wm8903_probe(struct snd_soc_codec *codec)
f1c0a02f 1907{
f0fba2ad
LG		 1908 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1909 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
73b34ead 1910 int ret, i;
8abd16a6 1911 int trigger, irq_pol;
f1c0a02f
MB		 1912 u16 val;
1913
7cfe5617 1914 wm8903->codec = codec;
d58d5d55 1915
8d50e447
MB		 1916 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1917 if (ret != 0) {
f0fba2ad
LG		 1918 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1919 return ret;
8d50e447
MB		 1920 }
1921
1922 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID);
d58d5d55 1923 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
f0fba2ad 1924 dev_err(codec->dev,
d58d5d55
MB		 1925 "Device with ID register %x is not a WM8903\n", val);
1926 return -ENODEV;
f1c0a02f
MB		 1927 }
1928
8d50e447 1929 val = snd_soc_read(codec, WM8903_REVISION_NUMBER);
1d8d62d6
MB		 1930 dev_info(codec->dev, "WM8903 revision %c\n",
1931 (val & WM8903_CHIP_REV_MASK) + 'A');
f1c0a02f
MB		 1932
1933 wm8903_reset(codec);
1934
37f88e84 1935 /* Set up GPIOs and microphone detection */
73b34ead 1936 if (pdata) {
905f6952
MB		 1937 bool mic_gpio = false;
1938
73b34ead 1939 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
7cfe5617 1940 if (pdata->gpio_cfg[i] == WM8903_GPIO_NO_CONFIG)
73b34ead
MB		 1941 continue;
1942
1943 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i,
1944 pdata->gpio_cfg[i] & 0xffff);
905f6952
MB		 1945
1946 val = (pdata->gpio_cfg[i] & WM8903_GP1_FN_MASK)
1947 >> WM8903_GP1_FN_SHIFT;
1948
1949 switch (val) {
1950 case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT:
1951 case WM8903_GPn_FN_MICBIAS_SHORT_DETECT:
1952 mic_gpio = true;
1953 break;
1954 default:
1955 break;
1956 }
73b34ead 1957 }
37f88e84
MB		 1958
1959 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0,
1960 pdata->micdet_cfg);
1961
1962 /* Microphone detection needs the WSEQ clock */
1963 if (pdata->micdet_cfg)
1964 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1965 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1966
905f6952
MB		 1967 /* If microphone detection is enabled by pdata but
1968 * detected via IRQ then interrupts can be lost before
1969 * the machine driver has set up microphone detection
1970 * IRQs as the IRQs are clear on read. The detection
1971 * will be enabled when the machine driver configures.
1972 */
1973 WARN_ON(!mic_gpio && (pdata->micdet_cfg & WM8903_MICDET_ENA));
1974
37f88e84 1975 wm8903->mic_delay = pdata->micdet_delay;
73b34ead 1976 }
8abd16a6 1977
f0fba2ad 1978 if (wm8903->irq) {
8abd16a6
MB		 1979 if (pdata && pdata->irq_active_low) {
1980 trigger = IRQF_TRIGGER_LOW;
1981 irq_pol = WM8903_IRQ_POL;
1982 } else {
1983 trigger = IRQF_TRIGGER_HIGH;
1984 irq_pol = 0;
1985 }
1986
1987 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL,
1988 WM8903_IRQ_POL, irq_pol);
1989
f0fba2ad 1990 ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq,
8abd16a6 1991 trigger | IRQF_ONESHOT,
f0fba2ad 1992 "wm8903", codec);
8abd16a6 1993 if (ret != 0) {
f0fba2ad 1994 dev_err(codec->dev, "Failed to request IRQ: %d\n",
8abd16a6 1995 ret);
f0fba2ad 1996 return ret;
8abd16a6
MB		 1997 }
1998
1999 /* Enable write sequencer interrupts */
2000 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
2001 WM8903_IM_WSEQ_BUSY_EINT, 0);
2002 }
73b34ead 2003
f1c0a02f
MB		 2004 /* power on device */
2005 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2006
2007 /* Latch volume update bits */
8d50e447 2008 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
f1c0a02f 2009 val |= WM8903_ADCVU;
8d50e447
MB		 2010 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
2011 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 2012
8d50e447 2013 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
f1c0a02f 2014 val |= WM8903_DACVU;
8d50e447
MB		 2015 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
2016 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 2017
8d50e447 2018 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
f1c0a02f 2019 val |= WM8903_HPOUTVU;
8d50e447
MB		 2020 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
2021 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
f1c0a02f 2022
8d50e447 2023 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
f1c0a02f 2024 val |= WM8903_LINEOUTVU;
8d50e447
MB		 2025 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
2026 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
f1c0a02f 2027
8d50e447 2028 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
f1c0a02f 2029 val |= WM8903_SPKVU;
8d50e447
MB		 2030 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
2031 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
f1c0a02f
MB		 2032
2033 /* Enable DAC soft mute by default */
e12adab0
MB		 2034 snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
2035 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE,
2036 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE);
f1c0a02f 2037
f0fba2ad
LG		 2038 snd_soc_add_controls(codec, wm8903_snd_controls,
2039 ARRAY_SIZE(wm8903_snd_controls));
f1c0a02f 2040
7cfe5617
SW		 2041 wm8903_init_gpio(codec);
2042
f1c0a02f
MB		 2043 return ret;
2044}
2045
f0fba2ad
LG		 2046/* power down chip */
2047static int wm8903_remove(struct snd_soc_codec *codec)
f1c0a02f 2048{
7cfe5617 2049 wm8903_free_gpio(codec);
f0fba2ad
LG		 2050 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
2051 return 0;
2052}
f1c0a02f 2053
f0fba2ad
LG		 2054static struct snd_soc_codec_driver soc_codec_dev_wm8903 = {
2055 .probe = wm8903_probe,
2056 .remove = wm8903_remove,
2057 .suspend = wm8903_suspend,
2058 .resume = wm8903_resume,
2059 .set_bias_level = wm8903_set_bias_level,
2060 .reg_cache_size = ARRAY_SIZE(wm8903_reg_defaults),
2061 .reg_word_size = sizeof(u16),
2062 .reg_cache_default = wm8903_reg_defaults,
2063 .volatile_register = wm8903_volatile_register,
c5b6a9fe 2064 .seq_notifier = wm8903_seq_notifier,
ecd01512
MB		 2065 .dapm_widgets = wm8903_dapm_widgets,
2066 .num_dapm_widgets = ARRAY_SIZE(wm8903_dapm_widgets),
2067 .dapm_routes = wm8903_intercon,
2068 .num_dapm_routes = ARRAY_SIZE(wm8903_intercon),
f0fba2ad 2069};
f1c0a02f 2070
f0fba2ad
LG		 2071#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2072static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
2073 const struct i2c_device_id *id)
2074{
2075 struct wm8903_priv *wm8903;
2076 int ret;
f1c0a02f 2077
f0fba2ad
LG		 2078 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
2079 if (wm8903 == NULL)
2080 return -ENOMEM;
8abd16a6 2081
f0fba2ad 2082 i2c_set_clientdata(i2c, wm8903);
f0fba2ad 2083 wm8903->irq = i2c->irq;
d58d5d55 2084
f0fba2ad
LG		 2085 ret = snd_soc_register_codec(&i2c->dev,
2086 &soc_codec_dev_wm8903, &wm8903_dai, 1);
2087 if (ret < 0)
2088 kfree(wm8903);
2089 return ret;
2090}
f1c0a02f 2091
f0fba2ad
LG		 2092static __devexit int wm8903_i2c_remove(struct i2c_client *client)
2093{
2094 snd_soc_unregister_codec(&client->dev);
2095 kfree(i2c_get_clientdata(client));
f1c0a02f
MB		 2096 return 0;
2097}
2098
f1c0a02f 2099static const struct i2c_device_id wm8903_i2c_id[] = {
f0fba2ad
LG		 2100 { "wm8903", 0 },
2101 { }
f1c0a02f
MB		 2102};
2103MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
2104
2105static struct i2c_driver wm8903_i2c_driver = {
2106 .driver = {
4b592c91 2107 .name = "wm8903",
f1c0a02f
MB		 2108 .owner = THIS_MODULE,
2109 },
f0fba2ad
LG		 2110 .probe = wm8903_i2c_probe,
2111 .remove = __devexit_p(wm8903_i2c_remove),
f1c0a02f
MB		 2112 .id_table = wm8903_i2c_id,
2113};
f0fba2ad 2114#endif
f1c0a02f 2115
f0fba2ad 2116static int __init wm8903_modinit(void)
f1c0a02f 2117{
f1c0a02f 2118 int ret = 0;
f0fba2ad
LG		 2119#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2120 ret = i2c_add_driver(&wm8903_i2c_driver);
2121 if (ret != 0) {
2122 printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n",
2123 ret);
f1c0a02f 2124 }
f0fba2ad 2125#endif
f1c0a02f 2126 return ret;
64089b84
MB		 2127}
2128module_init(wm8903_modinit);
2129
2130static void __exit wm8903_exit(void)
2131{
f0fba2ad 2132#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
d58d5d55 2133 i2c_del_driver(&wm8903_i2c_driver);
f0fba2ad 2134#endif
64089b84
MB		 2135}
2136module_exit(wm8903_exit);
2137
f1c0a02f
MB		 2138MODULE_DESCRIPTION("ASoC WM8903 driver");
2139MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
2140MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)