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ALSA: ASoC: Add AK4535 driver
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / wm8750.c
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abadfc92
RP		 1/*
2 * wm8750.c -- WM8750 ALSA SoC audio driver
3 *
4 * Copyright 2005 Openedhand Ltd.
5 *
6 * Author: Richard Purdie <richard@openedhand.com>
7 *
8 * Based on WM8753.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/pm.h>
20#include <linux/i2c.h>
21#include <linux/platform_device.h>
abadfc92
RP		 22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28
29#include "wm8750.h"
30
31#define AUDIO_NAME "WM8750"
4422b606 32#define WM8750_VERSION "0.12"
abadfc92
RP		 33
34/*
35 * Debug
36 */
37
38#define WM8750_DEBUG 0
39
40#ifdef WM8750_DEBUG
41#define dbg(format, arg...) \
42 printk(KERN_DEBUG AUDIO_NAME ": " format "\n" , ## arg)
43#else
44#define dbg(format, arg...) do {} while (0)
45#endif
46#define err(format, arg...) \
47 printk(KERN_ERR AUDIO_NAME ": " format "\n" , ## arg)
48#define info(format, arg...) \
49 printk(KERN_INFO AUDIO_NAME ": " format "\n" , ## arg)
50#define warn(format, arg...) \
51 printk(KERN_WARNING AUDIO_NAME ": " format "\n" , ## arg)
52
4422b606
LG		 53/* codec private data */
54struct wm8750_priv {
55 unsigned int sysclk;
56};
57
abadfc92
RP		 58/*
59 * wm8750 register cache
60 * We can't read the WM8750 register space when we
61 * are using 2 wire for device control, so we cache them instead.
62 */
63static const u16 wm8750_reg[] = {
64 0x0097, 0x0097, 0x0079, 0x0079, /* 0 */
65 0x0000, 0x0008, 0x0000, 0x000a, /* 4 */
66 0x0000, 0x0000, 0x00ff, 0x00ff, /* 8 */
67 0x000f, 0x000f, 0x0000, 0x0000, /* 12 */
68 0x0000, 0x007b, 0x0000, 0x0032, /* 16 */
69 0x0000, 0x00c3, 0x00c3, 0x00c0, /* 20 */
70 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
71 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
72 0x0000, 0x0000, 0x0050, 0x0050, /* 32 */
73 0x0050, 0x0050, 0x0050, 0x0050, /* 36 */
74 0x0079, 0x0079, 0x0079, /* 40 */
75};
76
abadfc92
RP		 77/*
78 * read wm8750 register cache
79 */
80static inline unsigned int wm8750_read_reg_cache(struct snd_soc_codec *codec,
81 unsigned int reg)
82{
83 u16 *cache = codec->reg_cache;
84 if (reg > WM8750_CACHE_REGNUM)
85 return -1;
86 return cache[reg];
87}
88
89/*
90 * write wm8750 register cache
91 */
92static inline void wm8750_write_reg_cache(struct snd_soc_codec *codec,
93 unsigned int reg, unsigned int value)
94{
95 u16 *cache = codec->reg_cache;
96 if (reg > WM8750_CACHE_REGNUM)
97 return;
98 cache[reg] = value;
99}
100
101static int wm8750_write(struct snd_soc_codec *codec, unsigned int reg,
102 unsigned int value)
103{
104 u8 data[2];
105
106 /* data is
107 * D15..D9 WM8753 register offset
108 * D8...D0 register data
109 */
110 data[0] = (reg << 1) | ((value >> 8) & 0x0001);
111 data[1] = value & 0x00ff;
112
42f3030f 113 wm8750_write_reg_cache(codec, reg, value);
abadfc92
RP		 114 if (codec->hw_write(codec->control_data, data, 2) == 2)
115 return 0;
116 else
117 return -EIO;
118}
119
120#define wm8750_reset(c) wm8750_write(c, WM8750_RESET, 0)
121
122/*
123 * WM8750 Controls
124 */
125static const char *wm8750_bass[] = {"Linear Control", "Adaptive Boost"};
126static const char *wm8750_bass_filter[] = { "130Hz @ 48kHz", "200Hz @ 48kHz" };
127static const char *wm8750_treble[] = {"8kHz", "4kHz"};
128static const char *wm8750_3d_lc[] = {"200Hz", "500Hz"};
129static const char *wm8750_3d_uc[] = {"2.2kHz", "1.5kHz"};
130static const char *wm8750_3d_func[] = {"Capture", "Playback"};
131static const char *wm8750_alc_func[] = {"Off", "Right", "Left", "Stereo"};
132static const char *wm8750_ng_type[] = {"Constant PGA Gain",
133 "Mute ADC Output"};
134static const char *wm8750_line_mux[] = {"Line 1", "Line 2", "Line 3", "PGA",
135 "Differential"};
136static const char *wm8750_pga_sel[] = {"Line 1", "Line 2", "Line 3",
137 "Differential"};
138static const char *wm8750_out3[] = {"VREF", "ROUT1 + Vol", "MonoOut",
139 "ROUT1"};
140static const char *wm8750_diff_sel[] = {"Line 1", "Line 2"};
141static const char *wm8750_adcpol[] = {"Normal", "L Invert", "R Invert",
142 "L + R Invert"};
143static const char *wm8750_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
144static const char *wm8750_mono_mux[] = {"Stereo", "Mono (Left)",
145 "Mono (Right)", "Digital Mono"};
146
147static const struct soc_enum wm8750_enum[] = {
148SOC_ENUM_SINGLE(WM8750_BASS, 7, 2, wm8750_bass),
149SOC_ENUM_SINGLE(WM8750_BASS, 6, 2, wm8750_bass_filter),
150SOC_ENUM_SINGLE(WM8750_TREBLE, 6, 2, wm8750_treble),
151SOC_ENUM_SINGLE(WM8750_3D, 5, 2, wm8750_3d_lc),
152SOC_ENUM_SINGLE(WM8750_3D, 6, 2, wm8750_3d_uc),
153SOC_ENUM_SINGLE(WM8750_3D, 7, 2, wm8750_3d_func),
154SOC_ENUM_SINGLE(WM8750_ALC1, 7, 4, wm8750_alc_func),
155SOC_ENUM_SINGLE(WM8750_NGATE, 1, 2, wm8750_ng_type),
156SOC_ENUM_SINGLE(WM8750_LOUTM1, 0, 5, wm8750_line_mux),
157SOC_ENUM_SINGLE(WM8750_ROUTM1, 0, 5, wm8750_line_mux),
158SOC_ENUM_SINGLE(WM8750_LADCIN, 6, 4, wm8750_pga_sel), /* 10 */
159SOC_ENUM_SINGLE(WM8750_RADCIN, 6, 4, wm8750_pga_sel),
160SOC_ENUM_SINGLE(WM8750_ADCTL2, 7, 4, wm8750_out3),
161SOC_ENUM_SINGLE(WM8750_ADCIN, 8, 2, wm8750_diff_sel),
162SOC_ENUM_SINGLE(WM8750_ADCDAC, 5, 4, wm8750_adcpol),
163SOC_ENUM_SINGLE(WM8750_ADCDAC, 1, 4, wm8750_deemph),
164SOC_ENUM_SINGLE(WM8750_ADCIN, 6, 4, wm8750_mono_mux), /* 16 */
165
166};
167
168static const struct snd_kcontrol_new wm8750_snd_controls[] = {
169
170SOC_DOUBLE_R("Capture Volume", WM8750_LINVOL, WM8750_RINVOL, 0, 63, 0),
171SOC_DOUBLE_R("Capture ZC Switch", WM8750_LINVOL, WM8750_RINVOL, 6, 1, 0),
172SOC_DOUBLE_R("Capture Switch", WM8750_LINVOL, WM8750_RINVOL, 7, 1, 1),
173
bd903b6e 174SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8750_LOUT1V,
abadfc92 175 WM8750_ROUT1V, 7, 1, 0),
bd903b6e 176SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8750_LOUT2V,
abadfc92
RP		 177 WM8750_ROUT2V, 7, 1, 0),
178
179SOC_ENUM("Playback De-emphasis", wm8750_enum[15]),
180
181SOC_ENUM("Capture Polarity", wm8750_enum[14]),
182SOC_SINGLE("Playback 6dB Attenuate", WM8750_ADCDAC, 7, 1, 0),
183SOC_SINGLE("Capture 6dB Attenuate", WM8750_ADCDAC, 8, 1, 0),
184
185SOC_DOUBLE_R("PCM Volume", WM8750_LDAC, WM8750_RDAC, 0, 255, 0),
186
187SOC_ENUM("Bass Boost", wm8750_enum[0]),
188SOC_ENUM("Bass Filter", wm8750_enum[1]),
189SOC_SINGLE("Bass Volume", WM8750_BASS, 0, 15, 1),
190
6a7b8cf4 191SOC_SINGLE("Treble Volume", WM8750_TREBLE, 0, 15, 1),
abadfc92
RP		 192SOC_ENUM("Treble Cut-off", wm8750_enum[2]),
193
194SOC_SINGLE("3D Switch", WM8750_3D, 0, 1, 0),
195SOC_SINGLE("3D Volume", WM8750_3D, 1, 15, 0),
196SOC_ENUM("3D Lower Cut-off", wm8750_enum[3]),
197SOC_ENUM("3D Upper Cut-off", wm8750_enum[4]),
198SOC_ENUM("3D Mode", wm8750_enum[5]),
199
200SOC_SINGLE("ALC Capture Target Volume", WM8750_ALC1, 0, 7, 0),
201SOC_SINGLE("ALC Capture Max Volume", WM8750_ALC1, 4, 7, 0),
202SOC_ENUM("ALC Capture Function", wm8750_enum[6]),
203SOC_SINGLE("ALC Capture ZC Switch", WM8750_ALC2, 7, 1, 0),
204SOC_SINGLE("ALC Capture Hold Time", WM8750_ALC2, 0, 15, 0),
205SOC_SINGLE("ALC Capture Decay Time", WM8750_ALC3, 4, 15, 0),
206SOC_SINGLE("ALC Capture Attack Time", WM8750_ALC3, 0, 15, 0),
207SOC_SINGLE("ALC Capture NG Threshold", WM8750_NGATE, 3, 31, 0),
208SOC_ENUM("ALC Capture NG Type", wm8750_enum[4]),
209SOC_SINGLE("ALC Capture NG Switch", WM8750_NGATE, 0, 1, 0),
210
211SOC_SINGLE("Left ADC Capture Volume", WM8750_LADC, 0, 255, 0),
212SOC_SINGLE("Right ADC Capture Volume", WM8750_RADC, 0, 255, 0),
213
214SOC_SINGLE("ZC Timeout Switch", WM8750_ADCTL1, 0, 1, 0),
215SOC_SINGLE("Playback Invert Switch", WM8750_ADCTL1, 1, 1, 0),
216
bd903b6e 217SOC_SINGLE("Right Speaker Playback Invert Switch", WM8750_ADCTL2, 4, 1, 0),
abadfc92
RP		 218
219/* Unimplemented */
220/* ADCDAC Bit 0 - ADCHPD */
221/* ADCDAC Bit 4 - HPOR */
222/* ADCTL1 Bit 2,3 - DATSEL */
223/* ADCTL1 Bit 4,5 - DMONOMIX */
224/* ADCTL1 Bit 6,7 - VSEL */
225/* ADCTL2 Bit 2 - LRCM */
226/* ADCTL2 Bit 3 - TRI */
227/* ADCTL3 Bit 5 - HPFLREN */
228/* ADCTL3 Bit 6 - VROI */
229/* ADCTL3 Bit 7,8 - ADCLRM */
230/* ADCIN Bit 4 - LDCM */
231/* ADCIN Bit 5 - RDCM */
232
233SOC_DOUBLE_R("Mic Boost", WM8750_LADCIN, WM8750_RADCIN, 4, 3, 0),
234
235SOC_DOUBLE_R("Bypass Left Playback Volume", WM8750_LOUTM1,
236 WM8750_LOUTM2, 4, 7, 1),
237SOC_DOUBLE_R("Bypass Right Playback Volume", WM8750_ROUTM1,
238 WM8750_ROUTM2, 4, 7, 1),
239SOC_DOUBLE_R("Bypass Mono Playback Volume", WM8750_MOUTM1,
240 WM8750_MOUTM2, 4, 7, 1),
241
242SOC_SINGLE("Mono Playback ZC Switch", WM8750_MOUTV, 7, 1, 0),
243
bd903b6e
LG		 244SOC_DOUBLE_R("Headphone Playback Volume", WM8750_LOUT1V, WM8750_ROUT1V,
245 0, 127, 0),
246SOC_DOUBLE_R("Speaker Playback Volume", WM8750_LOUT2V, WM8750_ROUT2V,
247 0, 127, 0),
abadfc92
RP		 248
249SOC_SINGLE("Mono Playback Volume", WM8750_MOUTV, 0, 127, 0),
250
251};
252
253/* add non dapm controls */
254static int wm8750_add_controls(struct snd_soc_codec *codec)
255{
256 int err, i;
257
258 for (i = 0; i < ARRAY_SIZE(wm8750_snd_controls); i++) {
259 err = snd_ctl_add(codec->card,
42f3030f
MB		 260 snd_soc_cnew(&wm8750_snd_controls[i],
261 codec, NULL));
abadfc92
RP		 262 if (err < 0)
263 return err;
264 }
265 return 0;
266}
267
268/*
269 * DAPM Controls
270 */
271
272/* Left Mixer */
273static const struct snd_kcontrol_new wm8750_left_mixer_controls[] = {
274SOC_DAPM_SINGLE("Playback Switch", WM8750_LOUTM1, 8, 1, 0),
275SOC_DAPM_SINGLE("Left Bypass Switch", WM8750_LOUTM1, 7, 1, 0),
276SOC_DAPM_SINGLE("Right Playback Switch", WM8750_LOUTM2, 8, 1, 0),
277SOC_DAPM_SINGLE("Right Bypass Switch", WM8750_LOUTM2, 7, 1, 0),
278};
279
280/* Right Mixer */
281static const struct snd_kcontrol_new wm8750_right_mixer_controls[] = {
282SOC_DAPM_SINGLE("Left Playback Switch", WM8750_ROUTM1, 8, 1, 0),
283SOC_DAPM_SINGLE("Left Bypass Switch", WM8750_ROUTM1, 7, 1, 0),
284SOC_DAPM_SINGLE("Playback Switch", WM8750_ROUTM2, 8, 1, 0),
285SOC_DAPM_SINGLE("Right Bypass Switch", WM8750_ROUTM2, 7, 1, 0),
286};
287
288/* Mono Mixer */
289static const struct snd_kcontrol_new wm8750_mono_mixer_controls[] = {
290SOC_DAPM_SINGLE("Left Playback Switch", WM8750_MOUTM1, 8, 1, 0),
291SOC_DAPM_SINGLE("Left Bypass Switch", WM8750_MOUTM1, 7, 1, 0),
292SOC_DAPM_SINGLE("Right Playback Switch", WM8750_MOUTM2, 8, 1, 0),
293SOC_DAPM_SINGLE("Right Bypass Switch", WM8750_MOUTM2, 7, 1, 0),
294};
295
296/* Left Line Mux */
297static const struct snd_kcontrol_new wm8750_left_line_controls =
298SOC_DAPM_ENUM("Route", wm8750_enum[8]);
299
300/* Right Line Mux */
301static const struct snd_kcontrol_new wm8750_right_line_controls =
302SOC_DAPM_ENUM("Route", wm8750_enum[9]);
303
304/* Left PGA Mux */
305static const struct snd_kcontrol_new wm8750_left_pga_controls =
306SOC_DAPM_ENUM("Route", wm8750_enum[10]);
307
308/* Right PGA Mux */
309static const struct snd_kcontrol_new wm8750_right_pga_controls =
310SOC_DAPM_ENUM("Route", wm8750_enum[11]);
311
312/* Out 3 Mux */
313static const struct snd_kcontrol_new wm8750_out3_controls =
314SOC_DAPM_ENUM("Route", wm8750_enum[12]);
315
316/* Differential Mux */
317static const struct snd_kcontrol_new wm8750_diffmux_controls =
318SOC_DAPM_ENUM("Route", wm8750_enum[13]);
319
320/* Mono ADC Mux */
321static const struct snd_kcontrol_new wm8750_monomux_controls =
322SOC_DAPM_ENUM("Route", wm8750_enum[16]);
323
324static const struct snd_soc_dapm_widget wm8750_dapm_widgets[] = {
325 SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
326 &wm8750_left_mixer_controls[0],
327 ARRAY_SIZE(wm8750_left_mixer_controls)),
328 SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
329 &wm8750_right_mixer_controls[0],
330 ARRAY_SIZE(wm8750_right_mixer_controls)),
331 SND_SOC_DAPM_MIXER("Mono Mixer", WM8750_PWR2, 2, 0,
332 &wm8750_mono_mixer_controls[0],
333 ARRAY_SIZE(wm8750_mono_mixer_controls)),
334
335 SND_SOC_DAPM_PGA("Right Out 2", WM8750_PWR2, 3, 0, NULL, 0),
336 SND_SOC_DAPM_PGA("Left Out 2", WM8750_PWR2, 4, 0, NULL, 0),
337 SND_SOC_DAPM_PGA("Right Out 1", WM8750_PWR2, 5, 0, NULL, 0),
338 SND_SOC_DAPM_PGA("Left Out 1", WM8750_PWR2, 6, 0, NULL, 0),
339 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8750_PWR2, 7, 0),
340 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8750_PWR2, 8, 0),
341
342 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8750_PWR1, 1, 0),
343 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8750_PWR1, 2, 0),
344 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8750_PWR1, 3, 0),
345
346 SND_SOC_DAPM_MUX("Left PGA Mux", WM8750_PWR1, 5, 0,
347 &wm8750_left_pga_controls),
348 SND_SOC_DAPM_MUX("Right PGA Mux", WM8750_PWR1, 4, 0,
349 &wm8750_right_pga_controls),
350 SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
351 &wm8750_left_line_controls),
352 SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
353 &wm8750_right_line_controls),
354
355 SND_SOC_DAPM_MUX("Out3 Mux", SND_SOC_NOPM, 0, 0, &wm8750_out3_controls),
356 SND_SOC_DAPM_PGA("Out 3", WM8750_PWR2, 1, 0, NULL, 0),
357 SND_SOC_DAPM_PGA("Mono Out 1", WM8750_PWR2, 2, 0, NULL, 0),
358
359 SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
360 &wm8750_diffmux_controls),
361 SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
362 &wm8750_monomux_controls),
363 SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
364 &wm8750_monomux_controls),
365
366 SND_SOC_DAPM_OUTPUT("LOUT1"),
367 SND_SOC_DAPM_OUTPUT("ROUT1"),
368 SND_SOC_DAPM_OUTPUT("LOUT2"),
369 SND_SOC_DAPM_OUTPUT("ROUT2"),
370 SND_SOC_DAPM_OUTPUT("MONO"),
371 SND_SOC_DAPM_OUTPUT("OUT3"),
372
373 SND_SOC_DAPM_INPUT("LINPUT1"),
374 SND_SOC_DAPM_INPUT("LINPUT2"),
375 SND_SOC_DAPM_INPUT("LINPUT3"),
376 SND_SOC_DAPM_INPUT("RINPUT1"),
377 SND_SOC_DAPM_INPUT("RINPUT2"),
378 SND_SOC_DAPM_INPUT("RINPUT3"),
379};
380
a65f0568 381static const struct snd_soc_dapm_route audio_map[] = {
abadfc92
RP		 382 /* left mixer */
383 {"Left Mixer", "Playback Switch", "Left DAC"},
384 {"Left Mixer", "Left Bypass Switch", "Left Line Mux"},
385 {"Left Mixer", "Right Playback Switch", "Right DAC"},
386 {"Left Mixer", "Right Bypass Switch", "Right Line Mux"},
387
388 /* right mixer */
389 {"Right Mixer", "Left Playback Switch", "Left DAC"},
390 {"Right Mixer", "Left Bypass Switch", "Left Line Mux"},
391 {"Right Mixer", "Playback Switch", "Right DAC"},
392 {"Right Mixer", "Right Bypass Switch", "Right Line Mux"},
393
394 /* left out 1 */
395 {"Left Out 1", NULL, "Left Mixer"},
396 {"LOUT1", NULL, "Left Out 1"},
397
398 /* left out 2 */
399 {"Left Out 2", NULL, "Left Mixer"},
400 {"LOUT2", NULL, "Left Out 2"},
401
402 /* right out 1 */
403 {"Right Out 1", NULL, "Right Mixer"},
404 {"ROUT1", NULL, "Right Out 1"},
405
406 /* right out 2 */
407 {"Right Out 2", NULL, "Right Mixer"},
408 {"ROUT2", NULL, "Right Out 2"},
409
410 /* mono mixer */
411 {"Mono Mixer", "Left Playback Switch", "Left DAC"},
412 {"Mono Mixer", "Left Bypass Switch", "Left Line Mux"},
413 {"Mono Mixer", "Right Playback Switch", "Right DAC"},
414 {"Mono Mixer", "Right Bypass Switch", "Right Line Mux"},
415
416 /* mono out */
417 {"Mono Out 1", NULL, "Mono Mixer"},
418 {"MONO1", NULL, "Mono Out 1"},
419
420 /* out 3 */
421 {"Out3 Mux", "VREF", "VREF"},
422 {"Out3 Mux", "ROUT1 + Vol", "ROUT1"},
423 {"Out3 Mux", "ROUT1", "Right Mixer"},
424 {"Out3 Mux", "MonoOut", "MONO1"},
425 {"Out 3", NULL, "Out3 Mux"},
426 {"OUT3", NULL, "Out 3"},
427
428 /* Left Line Mux */
429 {"Left Line Mux", "Line 1", "LINPUT1"},
430 {"Left Line Mux", "Line 2", "LINPUT2"},
431 {"Left Line Mux", "Line 3", "LINPUT3"},
432 {"Left Line Mux", "PGA", "Left PGA Mux"},
433 {"Left Line Mux", "Differential", "Differential Mux"},
434
435 /* Right Line Mux */
436 {"Right Line Mux", "Line 1", "RINPUT1"},
437 {"Right Line Mux", "Line 2", "RINPUT2"},
438 {"Right Line Mux", "Line 3", "RINPUT3"},
439 {"Right Line Mux", "PGA", "Right PGA Mux"},
440 {"Right Line Mux", "Differential", "Differential Mux"},
441
442 /* Left PGA Mux */
443 {"Left PGA Mux", "Line 1", "LINPUT1"},
444 {"Left PGA Mux", "Line 2", "LINPUT2"},
445 {"Left PGA Mux", "Line 3", "LINPUT3"},
446 {"Left PGA Mux", "Differential", "Differential Mux"},
447
448 /* Right PGA Mux */
449 {"Right PGA Mux", "Line 1", "RINPUT1"},
450 {"Right PGA Mux", "Line 2", "RINPUT2"},
451 {"Right PGA Mux", "Line 3", "RINPUT3"},
452 {"Right PGA Mux", "Differential", "Differential Mux"},
453
454 /* Differential Mux */
455 {"Differential Mux", "Line 1", "LINPUT1"},
456 {"Differential Mux", "Line 1", "RINPUT1"},
457 {"Differential Mux", "Line 2", "LINPUT2"},
458 {"Differential Mux", "Line 2", "RINPUT2"},
459
460 /* Left ADC Mux */
461 {"Left ADC Mux", "Stereo", "Left PGA Mux"},
462 {"Left ADC Mux", "Mono (Left)", "Left PGA Mux"},
463 {"Left ADC Mux", "Digital Mono", "Left PGA Mux"},
464
465 /* Right ADC Mux */
466 {"Right ADC Mux", "Stereo", "Right PGA Mux"},
467 {"Right ADC Mux", "Mono (Right)", "Right PGA Mux"},
468 {"Right ADC Mux", "Digital Mono", "Right PGA Mux"},
469
470 /* ADC */
471 {"Left ADC", NULL, "Left ADC Mux"},
472 {"Right ADC", NULL, "Right ADC Mux"},
abadfc92
RP		 473};
474
475static int wm8750_add_widgets(struct snd_soc_codec *codec)
476{
a65f0568
MB		 477 snd_soc_dapm_new_controls(codec, wm8750_dapm_widgets,
478 ARRAY_SIZE(wm8750_dapm_widgets));
abadfc92 479
a65f0568 480 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
abadfc92
RP		 481
482 snd_soc_dapm_new_widgets(codec);
483 return 0;
484}
485
486struct _coeff_div {
487 u32 mclk;
488 u32 rate;
489 u16 fs;
490 u8 sr:5;
491 u8 usb:1;
492};
493
494/* codec hifi mclk clock divider coefficients */
495static const struct _coeff_div coeff_div[] = {
496 /* 8k */
497 {12288000, 8000, 1536, 0x6, 0x0},
498 {11289600, 8000, 1408, 0x16, 0x0},
499 {18432000, 8000, 2304, 0x7, 0x0},
500 {16934400, 8000, 2112, 0x17, 0x0},
501 {12000000, 8000, 1500, 0x6, 0x1},
502
503 /* 11.025k */
504 {11289600, 11025, 1024, 0x18, 0x0},
505 {16934400, 11025, 1536, 0x19, 0x0},
506 {12000000, 11025, 1088, 0x19, 0x1},
507
508 /* 16k */
509 {12288000, 16000, 768, 0xa, 0x0},
510 {18432000, 16000, 1152, 0xb, 0x0},
511 {12000000, 16000, 750, 0xa, 0x1},
512
513 /* 22.05k */
514 {11289600, 22050, 512, 0x1a, 0x0},
515 {16934400, 22050, 768, 0x1b, 0x0},
516 {12000000, 22050, 544, 0x1b, 0x1},
517
518 /* 32k */
519 {12288000, 32000, 384, 0xc, 0x0},
520 {18432000, 32000, 576, 0xd, 0x0},
521 {12000000, 32000, 375, 0xa, 0x1},
522
523 /* 44.1k */
524 {11289600, 44100, 256, 0x10, 0x0},
525 {16934400, 44100, 384, 0x11, 0x0},
526 {12000000, 44100, 272, 0x11, 0x1},
527
528 /* 48k */
529 {12288000, 48000, 256, 0x0, 0x0},
530 {18432000, 48000, 384, 0x1, 0x0},
531 {12000000, 48000, 250, 0x0, 0x1},
532
533 /* 88.2k */
534 {11289600, 88200, 128, 0x1e, 0x0},
535 {16934400, 88200, 192, 0x1f, 0x0},
536 {12000000, 88200, 136, 0x1f, 0x1},
537
538 /* 96k */
539 {12288000, 96000, 128, 0xe, 0x0},
540 {18432000, 96000, 192, 0xf, 0x0},
541 {12000000, 96000, 125, 0xe, 0x1},
542};
543
544static inline int get_coeff(int mclk, int rate)
545{
546 int i;
547
548 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
549 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
550 return i;
551 }
a71a468a
LG		 552
553 printk(KERN_ERR "wm8750: could not get coeff for mclk %d @ rate %d\n",
554 mclk, rate);
abadfc92
RP		 555 return -EINVAL;
556}
557
4422b606
LG		 558static int wm8750_set_dai_sysclk(struct snd_soc_codec_dai *codec_dai,
559 int clk_id, unsigned int freq, int dir)
abadfc92 560{
4422b606
LG		 561 struct snd_soc_codec *codec = codec_dai->codec;
562 struct wm8750_priv *wm8750 = codec->private_data;
563
564 switch (freq) {
565 case 11289600:
566 case 12000000:
567 case 12288000:
568 case 16934400:
569 case 18432000:
570 wm8750->sysclk = freq;
571 return 0;
572 }
573 return -EINVAL;
abadfc92
RP		 574}
575
4422b606
LG		 576static int wm8750_set_dai_fmt(struct snd_soc_codec_dai *codec_dai,
577 unsigned int fmt)
abadfc92 578{
4422b606
LG		 579 struct snd_soc_codec *codec = codec_dai->codec;
580 u16 iface = 0;
abadfc92
RP		 581
582 /* set master/slave audio interface */
4422b606 583 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
abadfc92
RP		 584 case SND_SOC_DAIFMT_CBM_CFM:
585 iface = 0x0040;
586 break;
587 case SND_SOC_DAIFMT_CBS_CFS:
588 break;
4422b606
LG		 589 default:
590 return -EINVAL;
abadfc92
RP		 591 }
592
593 /* interface format */
4422b606 594 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
abadfc92
RP		 595 case SND_SOC_DAIFMT_I2S:
596 iface |= 0x0002;
597 break;
598 case SND_SOC_DAIFMT_RIGHT_J:
599 break;
600 case SND_SOC_DAIFMT_LEFT_J:
601 iface |= 0x0001;
602 break;
603 case SND_SOC_DAIFMT_DSP_A:
604 iface |= 0x0003;
605 break;
606 case SND_SOC_DAIFMT_DSP_B:
607 iface |= 0x0013;
608 break;
4422b606
LG		 609 default:
610 return -EINVAL;
abadfc92
RP		 611 }
612
613 /* clock inversion */
4422b606 614 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
abadfc92
RP		 615 case SND_SOC_DAIFMT_NB_NF:
616 break;
617 case SND_SOC_DAIFMT_IB_IF:
618 iface |= 0x0090;
619 break;
620 case SND_SOC_DAIFMT_IB_NF:
621 iface |= 0x0080;
622 break;
623 case SND_SOC_DAIFMT_NB_IF:
624 iface |= 0x0010;
625 break;
4422b606
LG		 626 default:
627 return -EINVAL;
abadfc92
RP		 628 }
629
4422b606
LG		 630 wm8750_write(codec, WM8750_IFACE, iface);
631 return 0;
632}
633
634static int wm8750_pcm_hw_params(struct snd_pcm_substream *substream,
635 struct snd_pcm_hw_params *params)
636{
637 struct snd_soc_pcm_runtime *rtd = substream->private_data;
638 struct snd_soc_device *socdev = rtd->socdev;
639 struct snd_soc_codec *codec = socdev->codec;
640 struct wm8750_priv *wm8750 = codec->private_data;
641 u16 iface = wm8750_read_reg_cache(codec, WM8750_IFACE) & 0x1f3;
642 u16 srate = wm8750_read_reg_cache(codec, WM8750_SRATE) & 0x1c0;
643 int coeff = get_coeff(wm8750->sysclk, params_rate(params));
644
645 /* bit size */
646 switch (params_format(params)) {
647 case SNDRV_PCM_FORMAT_S16_LE:
abadfc92 648 break;
4422b606
LG		 649 case SNDRV_PCM_FORMAT_S20_3LE:
650 iface |= 0x0004;
abadfc92 651 break;
4422b606
LG		 652 case SNDRV_PCM_FORMAT_S24_LE:
653 iface |= 0x0008;
abadfc92 654 break;
4422b606
LG		 655 case SNDRV_PCM_FORMAT_S32_LE:
656 iface |= 0x000c;
abadfc92
RP		 657 break;
658 }
659
660 /* set iface & srate */
661 wm8750_write(codec, WM8750_IFACE, iface);
4422b606
LG		 662 if (coeff >= 0)
663 wm8750_write(codec, WM8750_SRATE, srate |
664 (coeff_div[coeff].sr << 1) | coeff_div[coeff].usb);
abadfc92
RP		 665
666 return 0;
667}
668
4422b606 669static int wm8750_mute(struct snd_soc_codec_dai *dai, int mute)
abadfc92 670{
4422b606 671 struct snd_soc_codec *codec = dai->codec;
abadfc92 672 u16 mute_reg = wm8750_read_reg_cache(codec, WM8750_ADCDAC) & 0xfff7;
4422b606 673
abadfc92
RP		 674 if (mute)
675 wm8750_write(codec, WM8750_ADCDAC, mute_reg | 0x8);
676 else
677 wm8750_write(codec, WM8750_ADCDAC, mute_reg);
678 return 0;
679}
680
0be9898a
MB		 681static int wm8750_set_bias_level(struct snd_soc_codec *codec,
682 enum snd_soc_bias_level level)
abadfc92
RP		 683{
684 u16 pwr_reg = wm8750_read_reg_cache(codec, WM8750_PWR1) & 0xfe3e;
685
0be9898a
MB		 686 switch (level) {
687 case SND_SOC_BIAS_ON:
abadfc92
RP		 688 /* set vmid to 50k and unmute dac */
689 wm8750_write(codec, WM8750_PWR1, pwr_reg | 0x00c0);
690 break;
0be9898a 691 case SND_SOC_BIAS_PREPARE:
abadfc92
RP		 692 /* set vmid to 5k for quick power up */
693 wm8750_write(codec, WM8750_PWR1, pwr_reg | 0x01c1);
694 break;
0be9898a 695 case SND_SOC_BIAS_STANDBY:
abadfc92
RP		 696 /* mute dac and set vmid to 500k, enable VREF */
697 wm8750_write(codec, WM8750_PWR1, pwr_reg | 0x0141);
698 break;
0be9898a 699 case SND_SOC_BIAS_OFF:
abadfc92
RP		 700 wm8750_write(codec, WM8750_PWR1, 0x0001);
701 break;
702 }
0be9898a 703 codec->bias_level = level;
abadfc92
RP		 704 return 0;
705}
706
4422b606 707#define WM8750_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
42f3030f
MB		 708 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
709 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
4422b606
LG		 710
711#define WM8750_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
712 SNDRV_PCM_FMTBIT_S24_LE)
713
abadfc92
RP		 714struct snd_soc_codec_dai wm8750_dai = {
715 .name = "WM8750",
716 .playback = {
717 .stream_name = "Playback",
718 .channels_min = 1,
719 .channels_max = 2,
4422b606
LG		 720 .rates = WM8750_RATES,
721 .formats = WM8750_FORMATS,},
abadfc92
RP		 722 .capture = {
723 .stream_name = "Capture",
724 .channels_min = 1,
725 .channels_max = 2,
4422b606
LG		 726 .rates = WM8750_RATES,
727 .formats = WM8750_FORMATS,},
abadfc92 728 .ops = {
4422b606 729 .hw_params = wm8750_pcm_hw_params,
abadfc92 730 },
4422b606
LG		 731 .dai_ops = {
732 .digital_mute = wm8750_mute,
733 .set_fmt = wm8750_set_dai_fmt,
734 .set_sysclk = wm8750_set_dai_sysclk,
abadfc92
RP		 735 },
736};
737EXPORT_SYMBOL_GPL(wm8750_dai);
738
1321b160 739static void wm8750_work(struct work_struct *work)
abadfc92 740{
1321b160
TI		 741 struct snd_soc_codec *codec =
742 container_of(work, struct snd_soc_codec, delayed_work.work);
0be9898a 743 wm8750_set_bias_level(codec, codec->bias_level);
abadfc92
RP		 744}
745
746static int wm8750_suspend(struct platform_device *pdev, pm_message_t state)
747{
748 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
749 struct snd_soc_codec *codec = socdev->codec;
750
0be9898a 751 wm8750_set_bias_level(codec, SND_SOC_BIAS_OFF);
abadfc92
RP		 752 return 0;
753}
754
755static int wm8750_resume(struct platform_device *pdev)
756{
757 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
758 struct snd_soc_codec *codec = socdev->codec;
759 int i;
760 u8 data[2];
761 u16 *cache = codec->reg_cache;
762
763 /* Sync reg_cache with the hardware */
764 for (i = 0; i < ARRAY_SIZE(wm8750_reg); i++) {
765 if (i == WM8750_RESET)
766 continue;
767 data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
768 data[1] = cache[i] & 0x00ff;
769 codec->hw_write(codec->control_data, data, 2);
770 }
771
0be9898a 772 wm8750_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
abadfc92
RP		 773
774 /* charge wm8750 caps */
0be9898a
MB		 775 if (codec->suspend_bias_level == SND_SOC_BIAS_ON) {
776 wm8750_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
777 codec->bias_level = SND_SOC_BIAS_ON;
42f3030f
MB		 778 schedule_delayed_work(&codec->delayed_work,
779 msecs_to_jiffies(1000));
abadfc92
RP		 780 }
781
782 return 0;
783}
784
785/*
786 * initialise the WM8750 driver
787 * register the mixer and dsp interfaces with the kernel
788 */
789static int wm8750_init(struct snd_soc_device *socdev)
790{
791 struct snd_soc_codec *codec = socdev->codec;
792 int reg, ret = 0;
793
794 codec->name = "WM8750";
795 codec->owner = THIS_MODULE;
796 codec->read = wm8750_read_reg_cache;
797 codec->write = wm8750_write;
0be9898a 798 codec->set_bias_level = wm8750_set_bias_level;
abadfc92
RP		 799 codec->dai = &wm8750_dai;
800 codec->num_dai = 1;
d751b233 801 codec->reg_cache_size = ARRAY_SIZE(wm8750_reg);
713fb939 802 codec->reg_cache = kmemdup(wm8750_reg, sizeof(wm8750_reg), GFP_KERNEL);
abadfc92
RP		 803 if (codec->reg_cache == NULL)
804 return -ENOMEM;
abadfc92
RP		 805
806 wm8750_reset(codec);
807
808 /* register pcms */
809 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
810 if (ret < 0) {
e35115a5
LG		 811 printk(KERN_ERR "wm8750: failed to create pcms\n");
812 goto pcm_err;
abadfc92
RP		 813 }
814
815 /* charge output caps */
0be9898a
MB		 816 wm8750_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
817 codec->bias_level = SND_SOC_BIAS_STANDBY;
1321b160 818 schedule_delayed_work(&codec->delayed_work, msecs_to_jiffies(1000));
abadfc92
RP		 819
820 /* set the update bits */
821 reg = wm8750_read_reg_cache(codec, WM8750_LDAC);
822 wm8750_write(codec, WM8750_LDAC, reg | 0x0100);
823 reg = wm8750_read_reg_cache(codec, WM8750_RDAC);
824 wm8750_write(codec, WM8750_RDAC, reg | 0x0100);
825 reg = wm8750_read_reg_cache(codec, WM8750_LOUT1V);
826 wm8750_write(codec, WM8750_LOUT1V, reg | 0x0100);
827 reg = wm8750_read_reg_cache(codec, WM8750_ROUT1V);
828 wm8750_write(codec, WM8750_ROUT1V, reg | 0x0100);
829 reg = wm8750_read_reg_cache(codec, WM8750_LOUT2V);
830 wm8750_write(codec, WM8750_LOUT2V, reg | 0x0100);
831 reg = wm8750_read_reg_cache(codec, WM8750_ROUT2V);
832 wm8750_write(codec, WM8750_ROUT2V, reg | 0x0100);
833 reg = wm8750_read_reg_cache(codec, WM8750_LINVOL);
834 wm8750_write(codec, WM8750_LINVOL, reg | 0x0100);
835 reg = wm8750_read_reg_cache(codec, WM8750_RINVOL);
836 wm8750_write(codec, WM8750_RINVOL, reg | 0x0100);
837
838 wm8750_add_controls(codec);
839 wm8750_add_widgets(codec);
840 ret = snd_soc_register_card(socdev);
841 if (ret < 0) {
e35115a5
LG		 842 printk(KERN_ERR "wm8750: failed to register card\n");
843 goto card_err;
abadfc92 844 }
e35115a5 845 return ret;
abadfc92 846
e35115a5
LG		 847card_err:
848 snd_soc_free_pcms(socdev);
849 snd_soc_dapm_free(socdev);
850pcm_err:
851 kfree(codec->reg_cache);
abadfc92
RP		 852 return ret;
853}
854
855/* If the i2c layer weren't so broken, we could pass this kind of data
856 around */
857static struct snd_soc_device *wm8750_socdev;
858
42f3030f 859#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
abadfc92
RP		 860
861/*
862 * WM8731 2 wire address is determined by GPIO5
863 * state during powerup.
864 * low = 0x1a
865 * high = 0x1b
866 */
867static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END };
868
869/* Magic definition of all other variables and things */
870I2C_CLIENT_INSMOD;
871
872static struct i2c_driver wm8750_i2c_driver;
873static struct i2c_client client_template;
874
875static int wm8750_codec_probe(struct i2c_adapter *adap, int addr, int kind)
876{
877 struct snd_soc_device *socdev = wm8750_socdev;
878 struct wm8750_setup_data *setup = socdev->codec_data;
879 struct snd_soc_codec *codec = socdev->codec;
880 struct i2c_client *i2c;
881 int ret;
882
883 if (addr != setup->i2c_address)
884 return -ENODEV;
885
886 client_template.adapter = adap;
887 client_template.addr = addr;
888
88cb4290 889 i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL);
abadfc92
RP		 890 if (i2c == NULL) {
891 kfree(codec);
892 return -ENOMEM;
893 }
abadfc92
RP		 894 i2c_set_clientdata(i2c, codec);
895 codec->control_data = i2c;
896
897 ret = i2c_attach_client(i2c);
898 if (ret < 0) {
899 err("failed to attach codec at addr %x\n", addr);
900 goto err;
901 }
902
903 ret = wm8750_init(socdev);
904 if (ret < 0) {
905 err("failed to initialise WM8750\n");
906 goto err;
907 }
908 return ret;
909
910err:
911 kfree(codec);
912 kfree(i2c);
913 return ret;
914}
915
916static int wm8750_i2c_detach(struct i2c_client *client)
917{
918 struct snd_soc_codec *codec = i2c_get_clientdata(client);
919 i2c_detach_client(client);
920 kfree(codec->reg_cache);
921 kfree(client);
922 return 0;
923}
924
925static int wm8750_i2c_attach(struct i2c_adapter *adap)
926{
927 return i2c_probe(adap, &addr_data, wm8750_codec_probe);
928}
929
930/* corgi i2c codec control layer */
931static struct i2c_driver wm8750_i2c_driver = {
932 .driver = {
933 .name = "WM8750 I2C Codec",
934 .owner = THIS_MODULE,
935 },
936 .id = I2C_DRIVERID_WM8750,
937 .attach_adapter = wm8750_i2c_attach,
938 .detach_client = wm8750_i2c_detach,
939 .command = NULL,
940};
941
942static struct i2c_client client_template = {
943 .name = "WM8750",
944 .driver = &wm8750_i2c_driver,
945};
946#endif
947
948static int wm8750_probe(struct platform_device *pdev)
949{
950 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
951 struct wm8750_setup_data *setup = socdev->codec_data;
952 struct snd_soc_codec *codec;
4422b606 953 struct wm8750_priv *wm8750;
abadfc92
RP		 954 int ret = 0;
955
956 info("WM8750 Audio Codec %s", WM8750_VERSION);
957 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
958 if (codec == NULL)
959 return -ENOMEM;
960
4422b606
LG		 961 wm8750 = kzalloc(sizeof(struct wm8750_priv), GFP_KERNEL);
962 if (wm8750 == NULL) {
963 kfree(codec);
964 return -ENOMEM;
965 }
966
967 codec->private_data = wm8750;
abadfc92
RP		 968 socdev->codec = codec;
969 mutex_init(&codec->mutex);
970 INIT_LIST_HEAD(&codec->dapm_widgets);
971 INIT_LIST_HEAD(&codec->dapm_paths);
972 wm8750_socdev = socdev;
1321b160 973 INIT_DELAYED_WORK(&codec->delayed_work, wm8750_work);
42f3030f
MB		 974
975#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
abadfc92
RP		 976 if (setup->i2c_address) {
977 normal_i2c[0] = setup->i2c_address;
978 codec->hw_write = (hw_write_t)i2c_master_send;
979 ret = i2c_add_driver(&wm8750_i2c_driver);
980 if (ret != 0)
981 printk(KERN_ERR "can't add i2c driver");
982 }
983#else
984 /* Add other interfaces here */
985#endif
986
987 return ret;
988}
989
4422b606
LG		 990/*
991 * This function forces any delayed work to be queued and run.
992 */
993static int run_delayed_work(struct delayed_work *dwork)
994{
995 int ret;
996
997 /* cancel any work waiting to be queued. */
998 ret = cancel_delayed_work(dwork);
999
1000 /* if there was any work waiting then we run it now and
1001 * wait for it's completion */
1002 if (ret) {
1003 schedule_delayed_work(dwork, 0);
1004 flush_scheduled_work();
1005 }
1006 return ret;
1007}
1008
abadfc92
RP		 1009/* power down chip */
1010static int wm8750_remove(struct platform_device *pdev)
1011{
1012 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1013 struct snd_soc_codec *codec = socdev->codec;
1014
1015 if (codec->control_data)
0be9898a 1016 wm8750_set_bias_level(codec, SND_SOC_BIAS_OFF);
4422b606 1017 run_delayed_work(&codec->delayed_work);
abadfc92
RP		 1018 snd_soc_free_pcms(socdev);
1019 snd_soc_dapm_free(socdev);
42f3030f 1020#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
abadfc92
RP		 1021 i2c_del_driver(&wm8750_i2c_driver);
1022#endif
4422b606 1023 kfree(codec->private_data);
abadfc92
RP		 1024 kfree(codec);
1025
1026 return 0;
1027}
1028
1029struct snd_soc_codec_device soc_codec_dev_wm8750 = {
1030 .probe = wm8750_probe,
1031 .remove = wm8750_remove,
1032 .suspend = wm8750_suspend,
1033 .resume = wm8750_resume,
1034};
abadfc92
RP		 1035EXPORT_SYMBOL_GPL(soc_codec_dev_wm8750);
1036
1037MODULE_DESCRIPTION("ASoC WM8750 driver");
1038MODULE_AUTHOR("Liam Girdwood");
1039MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)