projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'for-2.6.29' into for-2.6.30
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / wm8750.c
CommitLineData
abadfc92
RP		 1/*
2 * wm8750.c -- WM8750 ALSA SoC audio driver
3 *
4 * Copyright 2005 Openedhand Ltd.
5 *
6 * Author: Richard Purdie <richard@openedhand.com>
7 *
8 * Based on WM8753.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/pm.h>
20#include <linux/i2c.h>
21#include <linux/platform_device.h>
2f3dfaf5 22#include <linux/spi/spi.h>
abadfc92
RP		 23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h>
29
30#include "wm8750.h"
31
4422b606 32#define WM8750_VERSION "0.12"
abadfc92 33
4422b606
LG		 34/* codec private data */
35struct wm8750_priv {
36 unsigned int sysclk;
37};
38
abadfc92
RP		 39/*
40 * wm8750 register cache
41 * We can't read the WM8750 register space when we
42 * are using 2 wire for device control, so we cache them instead.
43 */
44static const u16 wm8750_reg[] = {
45 0x0097, 0x0097, 0x0079, 0x0079, /* 0 */
46 0x0000, 0x0008, 0x0000, 0x000a, /* 4 */
47 0x0000, 0x0000, 0x00ff, 0x00ff, /* 8 */
48 0x000f, 0x000f, 0x0000, 0x0000, /* 12 */
49 0x0000, 0x007b, 0x0000, 0x0032, /* 16 */
50 0x0000, 0x00c3, 0x00c3, 0x00c0, /* 20 */
51 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
52 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
53 0x0000, 0x0000, 0x0050, 0x0050, /* 32 */
54 0x0050, 0x0050, 0x0050, 0x0050, /* 36 */
55 0x0079, 0x0079, 0x0079, /* 40 */
56};
57
abadfc92
RP		 58/*
59 * read wm8750 register cache
60 */
61static inline unsigned int wm8750_read_reg_cache(struct snd_soc_codec *codec,
62 unsigned int reg)
63{
64 u16 *cache = codec->reg_cache;
65 if (reg > WM8750_CACHE_REGNUM)
66 return -1;
67 return cache[reg];
68}
69
70/*
71 * write wm8750 register cache
72 */
73static inline void wm8750_write_reg_cache(struct snd_soc_codec *codec,
74 unsigned int reg, unsigned int value)
75{
76 u16 *cache = codec->reg_cache;
77 if (reg > WM8750_CACHE_REGNUM)
78 return;
79 cache[reg] = value;
80}
81
82static int wm8750_write(struct snd_soc_codec *codec, unsigned int reg,
83 unsigned int value)
84{
85 u8 data[2];
86
87 /* data is
88 * D15..D9 WM8753 register offset
89 * D8...D0 register data
90 */
91 data[0] = (reg << 1) | ((value >> 8) & 0x0001);
92 data[1] = value & 0x00ff;
93
42f3030f 94 wm8750_write_reg_cache(codec, reg, value);
abadfc92
RP		 95 if (codec->hw_write(codec->control_data, data, 2) == 2)
96 return 0;
97 else
98 return -EIO;
99}
100
101#define wm8750_reset(c) wm8750_write(c, WM8750_RESET, 0)
102
103/*
104 * WM8750 Controls
105 */
106static const char *wm8750_bass[] = {"Linear Control", "Adaptive Boost"};
107static const char *wm8750_bass_filter[] = { "130Hz @ 48kHz", "200Hz @ 48kHz" };
108static const char *wm8750_treble[] = {"8kHz", "4kHz"};
109static const char *wm8750_3d_lc[] = {"200Hz", "500Hz"};
110static const char *wm8750_3d_uc[] = {"2.2kHz", "1.5kHz"};
111static const char *wm8750_3d_func[] = {"Capture", "Playback"};
112static const char *wm8750_alc_func[] = {"Off", "Right", "Left", "Stereo"};
113static const char *wm8750_ng_type[] = {"Constant PGA Gain",
114 "Mute ADC Output"};
115static const char *wm8750_line_mux[] = {"Line 1", "Line 2", "Line 3", "PGA",
116 "Differential"};
117static const char *wm8750_pga_sel[] = {"Line 1", "Line 2", "Line 3",
118 "Differential"};
119static const char *wm8750_out3[] = {"VREF", "ROUT1 + Vol", "MonoOut",
120 "ROUT1"};
121static const char *wm8750_diff_sel[] = {"Line 1", "Line 2"};
122static const char *wm8750_adcpol[] = {"Normal", "L Invert", "R Invert",
123 "L + R Invert"};
124static const char *wm8750_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
125static const char *wm8750_mono_mux[] = {"Stereo", "Mono (Left)",
126 "Mono (Right)", "Digital Mono"};
127
128static const struct soc_enum wm8750_enum[] = {
129SOC_ENUM_SINGLE(WM8750_BASS, 7, 2, wm8750_bass),
130SOC_ENUM_SINGLE(WM8750_BASS, 6, 2, wm8750_bass_filter),
131SOC_ENUM_SINGLE(WM8750_TREBLE, 6, 2, wm8750_treble),
132SOC_ENUM_SINGLE(WM8750_3D, 5, 2, wm8750_3d_lc),
133SOC_ENUM_SINGLE(WM8750_3D, 6, 2, wm8750_3d_uc),
134SOC_ENUM_SINGLE(WM8750_3D, 7, 2, wm8750_3d_func),
135SOC_ENUM_SINGLE(WM8750_ALC1, 7, 4, wm8750_alc_func),
136SOC_ENUM_SINGLE(WM8750_NGATE, 1, 2, wm8750_ng_type),
137SOC_ENUM_SINGLE(WM8750_LOUTM1, 0, 5, wm8750_line_mux),
138SOC_ENUM_SINGLE(WM8750_ROUTM1, 0, 5, wm8750_line_mux),
139SOC_ENUM_SINGLE(WM8750_LADCIN, 6, 4, wm8750_pga_sel), /* 10 */
140SOC_ENUM_SINGLE(WM8750_RADCIN, 6, 4, wm8750_pga_sel),
141SOC_ENUM_SINGLE(WM8750_ADCTL2, 7, 4, wm8750_out3),
142SOC_ENUM_SINGLE(WM8750_ADCIN, 8, 2, wm8750_diff_sel),
143SOC_ENUM_SINGLE(WM8750_ADCDAC, 5, 4, wm8750_adcpol),
144SOC_ENUM_SINGLE(WM8750_ADCDAC, 1, 4, wm8750_deemph),
145SOC_ENUM_SINGLE(WM8750_ADCIN, 6, 4, wm8750_mono_mux), /* 16 */
146
147};
148
149static const struct snd_kcontrol_new wm8750_snd_controls[] = {
150
151SOC_DOUBLE_R("Capture Volume", WM8750_LINVOL, WM8750_RINVOL, 0, 63, 0),
152SOC_DOUBLE_R("Capture ZC Switch", WM8750_LINVOL, WM8750_RINVOL, 6, 1, 0),
153SOC_DOUBLE_R("Capture Switch", WM8750_LINVOL, WM8750_RINVOL, 7, 1, 1),
154
bd903b6e 155SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8750_LOUT1V,
abadfc92 156 WM8750_ROUT1V, 7, 1, 0),
bd903b6e 157SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8750_LOUT2V,
abadfc92
RP		 158 WM8750_ROUT2V, 7, 1, 0),
159
160SOC_ENUM("Playback De-emphasis", wm8750_enum[15]),
161
162SOC_ENUM("Capture Polarity", wm8750_enum[14]),
163SOC_SINGLE("Playback 6dB Attenuate", WM8750_ADCDAC, 7, 1, 0),
164SOC_SINGLE("Capture 6dB Attenuate", WM8750_ADCDAC, 8, 1, 0),
165
166SOC_DOUBLE_R("PCM Volume", WM8750_LDAC, WM8750_RDAC, 0, 255, 0),
167
168SOC_ENUM("Bass Boost", wm8750_enum[0]),
169SOC_ENUM("Bass Filter", wm8750_enum[1]),
170SOC_SINGLE("Bass Volume", WM8750_BASS, 0, 15, 1),
171
6a7b8cf4 172SOC_SINGLE("Treble Volume", WM8750_TREBLE, 0, 15, 1),
abadfc92
RP		 173SOC_ENUM("Treble Cut-off", wm8750_enum[2]),
174
175SOC_SINGLE("3D Switch", WM8750_3D, 0, 1, 0),
176SOC_SINGLE("3D Volume", WM8750_3D, 1, 15, 0),
177SOC_ENUM("3D Lower Cut-off", wm8750_enum[3]),
178SOC_ENUM("3D Upper Cut-off", wm8750_enum[4]),
179SOC_ENUM("3D Mode", wm8750_enum[5]),
180
181SOC_SINGLE("ALC Capture Target Volume", WM8750_ALC1, 0, 7, 0),
182SOC_SINGLE("ALC Capture Max Volume", WM8750_ALC1, 4, 7, 0),
183SOC_ENUM("ALC Capture Function", wm8750_enum[6]),
184SOC_SINGLE("ALC Capture ZC Switch", WM8750_ALC2, 7, 1, 0),
185SOC_SINGLE("ALC Capture Hold Time", WM8750_ALC2, 0, 15, 0),
186SOC_SINGLE("ALC Capture Decay Time", WM8750_ALC3, 4, 15, 0),
187SOC_SINGLE("ALC Capture Attack Time", WM8750_ALC3, 0, 15, 0),
188SOC_SINGLE("ALC Capture NG Threshold", WM8750_NGATE, 3, 31, 0),
189SOC_ENUM("ALC Capture NG Type", wm8750_enum[4]),
190SOC_SINGLE("ALC Capture NG Switch", WM8750_NGATE, 0, 1, 0),
191
192SOC_SINGLE("Left ADC Capture Volume", WM8750_LADC, 0, 255, 0),
193SOC_SINGLE("Right ADC Capture Volume", WM8750_RADC, 0, 255, 0),
194
195SOC_SINGLE("ZC Timeout Switch", WM8750_ADCTL1, 0, 1, 0),
196SOC_SINGLE("Playback Invert Switch", WM8750_ADCTL1, 1, 1, 0),
197
bd903b6e 198SOC_SINGLE("Right Speaker Playback Invert Switch", WM8750_ADCTL2, 4, 1, 0),
abadfc92
RP		 199
200/* Unimplemented */
201/* ADCDAC Bit 0 - ADCHPD */
202/* ADCDAC Bit 4 - HPOR */
203/* ADCTL1 Bit 2,3 - DATSEL */
204/* ADCTL1 Bit 4,5 - DMONOMIX */
205/* ADCTL1 Bit 6,7 - VSEL */
206/* ADCTL2 Bit 2 - LRCM */
207/* ADCTL2 Bit 3 - TRI */
208/* ADCTL3 Bit 5 - HPFLREN */
209/* ADCTL3 Bit 6 - VROI */
210/* ADCTL3 Bit 7,8 - ADCLRM */
211/* ADCIN Bit 4 - LDCM */
212/* ADCIN Bit 5 - RDCM */
213
214SOC_DOUBLE_R("Mic Boost", WM8750_LADCIN, WM8750_RADCIN, 4, 3, 0),
215
216SOC_DOUBLE_R("Bypass Left Playback Volume", WM8750_LOUTM1,
217 WM8750_LOUTM2, 4, 7, 1),
218SOC_DOUBLE_R("Bypass Right Playback Volume", WM8750_ROUTM1,
219 WM8750_ROUTM2, 4, 7, 1),
220SOC_DOUBLE_R("Bypass Mono Playback Volume", WM8750_MOUTM1,
221 WM8750_MOUTM2, 4, 7, 1),
222
223SOC_SINGLE("Mono Playback ZC Switch", WM8750_MOUTV, 7, 1, 0),
224
bd903b6e
LG		 225SOC_DOUBLE_R("Headphone Playback Volume", WM8750_LOUT1V, WM8750_ROUT1V,
226 0, 127, 0),
227SOC_DOUBLE_R("Speaker Playback Volume", WM8750_LOUT2V, WM8750_ROUT2V,
228 0, 127, 0),
abadfc92
RP		 229
230SOC_SINGLE("Mono Playback Volume", WM8750_MOUTV, 0, 127, 0),
231
232};
233
abadfc92
RP		 234/*
235 * DAPM Controls
236 */
237
238/* Left Mixer */
239static const struct snd_kcontrol_new wm8750_left_mixer_controls[] = {
240SOC_DAPM_SINGLE("Playback Switch", WM8750_LOUTM1, 8, 1, 0),
241SOC_DAPM_SINGLE("Left Bypass Switch", WM8750_LOUTM1, 7, 1, 0),
242SOC_DAPM_SINGLE("Right Playback Switch", WM8750_LOUTM2, 8, 1, 0),
243SOC_DAPM_SINGLE("Right Bypass Switch", WM8750_LOUTM2, 7, 1, 0),
244};
245
246/* Right Mixer */
247static const struct snd_kcontrol_new wm8750_right_mixer_controls[] = {
248SOC_DAPM_SINGLE("Left Playback Switch", WM8750_ROUTM1, 8, 1, 0),
249SOC_DAPM_SINGLE("Left Bypass Switch", WM8750_ROUTM1, 7, 1, 0),
250SOC_DAPM_SINGLE("Playback Switch", WM8750_ROUTM2, 8, 1, 0),
251SOC_DAPM_SINGLE("Right Bypass Switch", WM8750_ROUTM2, 7, 1, 0),
252};
253
254/* Mono Mixer */
255static const struct snd_kcontrol_new wm8750_mono_mixer_controls[] = {
256SOC_DAPM_SINGLE("Left Playback Switch", WM8750_MOUTM1, 8, 1, 0),
257SOC_DAPM_SINGLE("Left Bypass Switch", WM8750_MOUTM1, 7, 1, 0),
258SOC_DAPM_SINGLE("Right Playback Switch", WM8750_MOUTM2, 8, 1, 0),
259SOC_DAPM_SINGLE("Right Bypass Switch", WM8750_MOUTM2, 7, 1, 0),
260};
261
262/* Left Line Mux */
263static const struct snd_kcontrol_new wm8750_left_line_controls =
264SOC_DAPM_ENUM("Route", wm8750_enum[8]);
265
266/* Right Line Mux */
267static const struct snd_kcontrol_new wm8750_right_line_controls =
268SOC_DAPM_ENUM("Route", wm8750_enum[9]);
269
270/* Left PGA Mux */
271static const struct snd_kcontrol_new wm8750_left_pga_controls =
272SOC_DAPM_ENUM("Route", wm8750_enum[10]);
273
274/* Right PGA Mux */
275static const struct snd_kcontrol_new wm8750_right_pga_controls =
276SOC_DAPM_ENUM("Route", wm8750_enum[11]);
277
278/* Out 3 Mux */
279static const struct snd_kcontrol_new wm8750_out3_controls =
280SOC_DAPM_ENUM("Route", wm8750_enum[12]);
281
282/* Differential Mux */
283static const struct snd_kcontrol_new wm8750_diffmux_controls =
284SOC_DAPM_ENUM("Route", wm8750_enum[13]);
285
286/* Mono ADC Mux */
287static const struct snd_kcontrol_new wm8750_monomux_controls =
288SOC_DAPM_ENUM("Route", wm8750_enum[16]);
289
290static const struct snd_soc_dapm_widget wm8750_dapm_widgets[] = {
291 SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
292 &wm8750_left_mixer_controls[0],
293 ARRAY_SIZE(wm8750_left_mixer_controls)),
294 SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
295 &wm8750_right_mixer_controls[0],
296 ARRAY_SIZE(wm8750_right_mixer_controls)),
297 SND_SOC_DAPM_MIXER("Mono Mixer", WM8750_PWR2, 2, 0,
298 &wm8750_mono_mixer_controls[0],
299 ARRAY_SIZE(wm8750_mono_mixer_controls)),
300
301 SND_SOC_DAPM_PGA("Right Out 2", WM8750_PWR2, 3, 0, NULL, 0),
302 SND_SOC_DAPM_PGA("Left Out 2", WM8750_PWR2, 4, 0, NULL, 0),
303 SND_SOC_DAPM_PGA("Right Out 1", WM8750_PWR2, 5, 0, NULL, 0),
304 SND_SOC_DAPM_PGA("Left Out 1", WM8750_PWR2, 6, 0, NULL, 0),
305 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8750_PWR2, 7, 0),
306 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8750_PWR2, 8, 0),
307
308 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8750_PWR1, 1, 0),
309 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8750_PWR1, 2, 0),
310 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8750_PWR1, 3, 0),
311
312 SND_SOC_DAPM_MUX("Left PGA Mux", WM8750_PWR1, 5, 0,
313 &wm8750_left_pga_controls),
314 SND_SOC_DAPM_MUX("Right PGA Mux", WM8750_PWR1, 4, 0,
315 &wm8750_right_pga_controls),
316 SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
317 &wm8750_left_line_controls),
318 SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
319 &wm8750_right_line_controls),
320
321 SND_SOC_DAPM_MUX("Out3 Mux", SND_SOC_NOPM, 0, 0, &wm8750_out3_controls),
322 SND_SOC_DAPM_PGA("Out 3", WM8750_PWR2, 1, 0, NULL, 0),
323 SND_SOC_DAPM_PGA("Mono Out 1", WM8750_PWR2, 2, 0, NULL, 0),
324
325 SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
326 &wm8750_diffmux_controls),
327 SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
328 &wm8750_monomux_controls),
329 SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
330 &wm8750_monomux_controls),
331
332 SND_SOC_DAPM_OUTPUT("LOUT1"),
333 SND_SOC_DAPM_OUTPUT("ROUT1"),
334 SND_SOC_DAPM_OUTPUT("LOUT2"),
335 SND_SOC_DAPM_OUTPUT("ROUT2"),
23ba79bd 336 SND_SOC_DAPM_OUTPUT("MONO1"),
abadfc92 337 SND_SOC_DAPM_OUTPUT("OUT3"),
04489eeb 338 SND_SOC_DAPM_OUTPUT("VREF"),
abadfc92
RP		 339
340 SND_SOC_DAPM_INPUT("LINPUT1"),
341 SND_SOC_DAPM_INPUT("LINPUT2"),
342 SND_SOC_DAPM_INPUT("LINPUT3"),
343 SND_SOC_DAPM_INPUT("RINPUT1"),
344 SND_SOC_DAPM_INPUT("RINPUT2"),
345 SND_SOC_DAPM_INPUT("RINPUT3"),
346};
347
a65f0568 348static const struct snd_soc_dapm_route audio_map[] = {
abadfc92
RP		 349 /* left mixer */
350 {"Left Mixer", "Playback Switch", "Left DAC"},
351 {"Left Mixer", "Left Bypass Switch", "Left Line Mux"},
352 {"Left Mixer", "Right Playback Switch", "Right DAC"},
353 {"Left Mixer", "Right Bypass Switch", "Right Line Mux"},
354
355 /* right mixer */
356 {"Right Mixer", "Left Playback Switch", "Left DAC"},
357 {"Right Mixer", "Left Bypass Switch", "Left Line Mux"},
358 {"Right Mixer", "Playback Switch", "Right DAC"},
359 {"Right Mixer", "Right Bypass Switch", "Right Line Mux"},
360
361 /* left out 1 */
362 {"Left Out 1", NULL, "Left Mixer"},
363 {"LOUT1", NULL, "Left Out 1"},
364
365 /* left out 2 */
366 {"Left Out 2", NULL, "Left Mixer"},
367 {"LOUT2", NULL, "Left Out 2"},
368
369 /* right out 1 */
370 {"Right Out 1", NULL, "Right Mixer"},
371 {"ROUT1", NULL, "Right Out 1"},
372
373 /* right out 2 */
374 {"Right Out 2", NULL, "Right Mixer"},
375 {"ROUT2", NULL, "Right Out 2"},
376
377 /* mono mixer */
378 {"Mono Mixer", "Left Playback Switch", "Left DAC"},
379 {"Mono Mixer", "Left Bypass Switch", "Left Line Mux"},
380 {"Mono Mixer", "Right Playback Switch", "Right DAC"},
381 {"Mono Mixer", "Right Bypass Switch", "Right Line Mux"},
382
383 /* mono out */
384 {"Mono Out 1", NULL, "Mono Mixer"},
385 {"MONO1", NULL, "Mono Out 1"},
386
387 /* out 3 */
388 {"Out3 Mux", "VREF", "VREF"},
389 {"Out3 Mux", "ROUT1 + Vol", "ROUT1"},
390 {"Out3 Mux", "ROUT1", "Right Mixer"},
391 {"Out3 Mux", "MonoOut", "MONO1"},
392 {"Out 3", NULL, "Out3 Mux"},
393 {"OUT3", NULL, "Out 3"},
394
395 /* Left Line Mux */
396 {"Left Line Mux", "Line 1", "LINPUT1"},
397 {"Left Line Mux", "Line 2", "LINPUT2"},
398 {"Left Line Mux", "Line 3", "LINPUT3"},
399 {"Left Line Mux", "PGA", "Left PGA Mux"},
400 {"Left Line Mux", "Differential", "Differential Mux"},
401
402 /* Right Line Mux */
403 {"Right Line Mux", "Line 1", "RINPUT1"},
404 {"Right Line Mux", "Line 2", "RINPUT2"},
405 {"Right Line Mux", "Line 3", "RINPUT3"},
406 {"Right Line Mux", "PGA", "Right PGA Mux"},
407 {"Right Line Mux", "Differential", "Differential Mux"},
408
409 /* Left PGA Mux */
410 {"Left PGA Mux", "Line 1", "LINPUT1"},
411 {"Left PGA Mux", "Line 2", "LINPUT2"},
412 {"Left PGA Mux", "Line 3", "LINPUT3"},
413 {"Left PGA Mux", "Differential", "Differential Mux"},
414
415 /* Right PGA Mux */
416 {"Right PGA Mux", "Line 1", "RINPUT1"},
417 {"Right PGA Mux", "Line 2", "RINPUT2"},
418 {"Right PGA Mux", "Line 3", "RINPUT3"},
419 {"Right PGA Mux", "Differential", "Differential Mux"},
420
421 /* Differential Mux */
422 {"Differential Mux", "Line 1", "LINPUT1"},
423 {"Differential Mux", "Line 1", "RINPUT1"},
424 {"Differential Mux", "Line 2", "LINPUT2"},
425 {"Differential Mux", "Line 2", "RINPUT2"},
426
427 /* Left ADC Mux */
428 {"Left ADC Mux", "Stereo", "Left PGA Mux"},
429 {"Left ADC Mux", "Mono (Left)", "Left PGA Mux"},
430 {"Left ADC Mux", "Digital Mono", "Left PGA Mux"},
431
432 /* Right ADC Mux */
433 {"Right ADC Mux", "Stereo", "Right PGA Mux"},
434 {"Right ADC Mux", "Mono (Right)", "Right PGA Mux"},
435 {"Right ADC Mux", "Digital Mono", "Right PGA Mux"},
436
437 /* ADC */
438 {"Left ADC", NULL, "Left ADC Mux"},
439 {"Right ADC", NULL, "Right ADC Mux"},
abadfc92
RP		 440};
441
442static int wm8750_add_widgets(struct snd_soc_codec *codec)
443{
a65f0568
MB		 444 snd_soc_dapm_new_controls(codec, wm8750_dapm_widgets,
445 ARRAY_SIZE(wm8750_dapm_widgets));
abadfc92 446
a65f0568 447 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
abadfc92
RP		 448
449 snd_soc_dapm_new_widgets(codec);
450 return 0;
451}
452
453struct _coeff_div {
454 u32 mclk;
455 u32 rate;
456 u16 fs;
457 u8 sr:5;
458 u8 usb:1;
459};
460
461/* codec hifi mclk clock divider coefficients */
462static const struct _coeff_div coeff_div[] = {
463 /* 8k */
464 {12288000, 8000, 1536, 0x6, 0x0},
465 {11289600, 8000, 1408, 0x16, 0x0},
466 {18432000, 8000, 2304, 0x7, 0x0},
467 {16934400, 8000, 2112, 0x17, 0x0},
468 {12000000, 8000, 1500, 0x6, 0x1},
469
470 /* 11.025k */
471 {11289600, 11025, 1024, 0x18, 0x0},
472 {16934400, 11025, 1536, 0x19, 0x0},
473 {12000000, 11025, 1088, 0x19, 0x1},
474
475 /* 16k */
476 {12288000, 16000, 768, 0xa, 0x0},
477 {18432000, 16000, 1152, 0xb, 0x0},
478 {12000000, 16000, 750, 0xa, 0x1},
479
480 /* 22.05k */
481 {11289600, 22050, 512, 0x1a, 0x0},
482 {16934400, 22050, 768, 0x1b, 0x0},
483 {12000000, 22050, 544, 0x1b, 0x1},
484
485 /* 32k */
486 {12288000, 32000, 384, 0xc, 0x0},
487 {18432000, 32000, 576, 0xd, 0x0},
488 {12000000, 32000, 375, 0xa, 0x1},
489
490 /* 44.1k */
491 {11289600, 44100, 256, 0x10, 0x0},
492 {16934400, 44100, 384, 0x11, 0x0},
493 {12000000, 44100, 272, 0x11, 0x1},
494
495 /* 48k */
496 {12288000, 48000, 256, 0x0, 0x0},
497 {18432000, 48000, 384, 0x1, 0x0},
498 {12000000, 48000, 250, 0x0, 0x1},
499
500 /* 88.2k */
501 {11289600, 88200, 128, 0x1e, 0x0},
502 {16934400, 88200, 192, 0x1f, 0x0},
503 {12000000, 88200, 136, 0x1f, 0x1},
504
505 /* 96k */
506 {12288000, 96000, 128, 0xe, 0x0},
507 {18432000, 96000, 192, 0xf, 0x0},
508 {12000000, 96000, 125, 0xe, 0x1},
509};
510
511static inline int get_coeff(int mclk, int rate)
512{
513 int i;
514
515 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
516 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
517 return i;
518 }
a71a468a
LG		 519
520 printk(KERN_ERR "wm8750: could not get coeff for mclk %d @ rate %d\n",
521 mclk, rate);
abadfc92
RP		 522 return -EINVAL;
523}
524
e550e17f 525static int wm8750_set_dai_sysclk(struct snd_soc_dai *codec_dai,
4422b606 526 int clk_id, unsigned int freq, int dir)
abadfc92 527{
4422b606
LG		 528 struct snd_soc_codec *codec = codec_dai->codec;
529 struct wm8750_priv *wm8750 = codec->private_data;
530
531 switch (freq) {
532 case 11289600:
533 case 12000000:
534 case 12288000:
535 case 16934400:
536 case 18432000:
537 wm8750->sysclk = freq;
538 return 0;
539 }
540 return -EINVAL;
abadfc92
RP		 541}
542
e550e17f 543static int wm8750_set_dai_fmt(struct snd_soc_dai *codec_dai,
4422b606 544 unsigned int fmt)
abadfc92 545{
4422b606
LG		 546 struct snd_soc_codec *codec = codec_dai->codec;
547 u16 iface = 0;
abadfc92
RP		 548
549 /* set master/slave audio interface */
4422b606 550 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
abadfc92
RP		 551 case SND_SOC_DAIFMT_CBM_CFM:
552 iface = 0x0040;
553 break;
554 case SND_SOC_DAIFMT_CBS_CFS:
555 break;
4422b606
LG		 556 default:
557 return -EINVAL;
abadfc92
RP		 558 }
559
560 /* interface format */
4422b606 561 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
abadfc92
RP		 562 case SND_SOC_DAIFMT_I2S:
563 iface |= 0x0002;
564 break;
565 case SND_SOC_DAIFMT_RIGHT_J:
566 break;
567 case SND_SOC_DAIFMT_LEFT_J:
568 iface |= 0x0001;
569 break;
570 case SND_SOC_DAIFMT_DSP_A:
571 iface |= 0x0003;
572 break;
573 case SND_SOC_DAIFMT_DSP_B:
574 iface |= 0x0013;
575 break;
4422b606
LG		 576 default:
577 return -EINVAL;
abadfc92
RP		 578 }
579
580 /* clock inversion */
4422b606 581 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
abadfc92
RP		 582 case SND_SOC_DAIFMT_NB_NF:
583 break;
584 case SND_SOC_DAIFMT_IB_IF:
585 iface |= 0x0090;
586 break;
587 case SND_SOC_DAIFMT_IB_NF:
588 iface |= 0x0080;
589 break;
590 case SND_SOC_DAIFMT_NB_IF:
591 iface |= 0x0010;
592 break;
4422b606
LG		 593 default:
594 return -EINVAL;
abadfc92
RP		 595 }
596
4422b606
LG		 597 wm8750_write(codec, WM8750_IFACE, iface);
598 return 0;
599}
600
601static int wm8750_pcm_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 602 struct snd_pcm_hw_params *params,
603 struct snd_soc_dai *dai)
4422b606
LG		 604{
605 struct snd_soc_pcm_runtime *rtd = substream->private_data;
606 struct snd_soc_device *socdev = rtd->socdev;
6627a653 607 struct snd_soc_codec *codec = socdev->card->codec;
4422b606
LG		 608 struct wm8750_priv *wm8750 = codec->private_data;
609 u16 iface = wm8750_read_reg_cache(codec, WM8750_IFACE) & 0x1f3;
610 u16 srate = wm8750_read_reg_cache(codec, WM8750_SRATE) & 0x1c0;
611 int coeff = get_coeff(wm8750->sysclk, params_rate(params));
612
613 /* bit size */
614 switch (params_format(params)) {
615 case SNDRV_PCM_FORMAT_S16_LE:
abadfc92 616 break;
4422b606
LG		 617 case SNDRV_PCM_FORMAT_S20_3LE:
618 iface |= 0x0004;
abadfc92 619 break;
4422b606
LG		 620 case SNDRV_PCM_FORMAT_S24_LE:
621 iface |= 0x0008;
abadfc92 622 break;
4422b606
LG		 623 case SNDRV_PCM_FORMAT_S32_LE:
624 iface |= 0x000c;
abadfc92
RP		 625 break;
626 }
627
628 /* set iface & srate */
629 wm8750_write(codec, WM8750_IFACE, iface);
4422b606
LG		 630 if (coeff >= 0)
631 wm8750_write(codec, WM8750_SRATE, srate |
632 (coeff_div[coeff].sr << 1) | coeff_div[coeff].usb);
abadfc92
RP		 633
634 return 0;
635}
636
e550e17f 637static int wm8750_mute(struct snd_soc_dai *dai, int mute)
abadfc92 638{
4422b606 639 struct snd_soc_codec *codec = dai->codec;
abadfc92 640 u16 mute_reg = wm8750_read_reg_cache(codec, WM8750_ADCDAC) & 0xfff7;
4422b606 641
abadfc92
RP		 642 if (mute)
643 wm8750_write(codec, WM8750_ADCDAC, mute_reg | 0x8);
644 else
645 wm8750_write(codec, WM8750_ADCDAC, mute_reg);
646 return 0;
647}
648
0be9898a
MB		 649static int wm8750_set_bias_level(struct snd_soc_codec *codec,
650 enum snd_soc_bias_level level)
abadfc92
RP		 651{
652 u16 pwr_reg = wm8750_read_reg_cache(codec, WM8750_PWR1) & 0xfe3e;
653
0be9898a
MB		 654 switch (level) {
655 case SND_SOC_BIAS_ON:
abadfc92
RP		 656 /* set vmid to 50k and unmute dac */
657 wm8750_write(codec, WM8750_PWR1, pwr_reg | 0x00c0);
658 break;
0be9898a 659 case SND_SOC_BIAS_PREPARE:
abadfc92
RP		 660 /* set vmid to 5k for quick power up */
661 wm8750_write(codec, WM8750_PWR1, pwr_reg | 0x01c1);
662 break;
0be9898a 663 case SND_SOC_BIAS_STANDBY:
abadfc92
RP		 664 /* mute dac and set vmid to 500k, enable VREF */
665 wm8750_write(codec, WM8750_PWR1, pwr_reg | 0x0141);
666 break;
0be9898a 667 case SND_SOC_BIAS_OFF:
abadfc92
RP		 668 wm8750_write(codec, WM8750_PWR1, 0x0001);
669 break;
670 }
0be9898a 671 codec->bias_level = level;
abadfc92
RP		 672 return 0;
673}
674
4422b606 675#define WM8750_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
42f3030f
MB		 676 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
677 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
4422b606
LG		 678
679#define WM8750_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
680 SNDRV_PCM_FMTBIT_S24_LE)
681
e550e17f 682struct snd_soc_dai wm8750_dai = {
abadfc92
RP		 683 .name = "WM8750",
684 .playback = {
685 .stream_name = "Playback",
686 .channels_min = 1,
687 .channels_max = 2,
4422b606
LG		 688 .rates = WM8750_RATES,
689 .formats = WM8750_FORMATS,},
abadfc92
RP		 690 .capture = {
691 .stream_name = "Capture",
692 .channels_min = 1,
693 .channels_max = 2,
4422b606
LG		 694 .rates = WM8750_RATES,
695 .formats = WM8750_FORMATS,},
abadfc92 696 .ops = {
4422b606 697 .hw_params = wm8750_pcm_hw_params,
4422b606
LG		 698 .digital_mute = wm8750_mute,
699 .set_fmt = wm8750_set_dai_fmt,
700 .set_sysclk = wm8750_set_dai_sysclk,
abadfc92
RP		 701 },
702};
703EXPORT_SYMBOL_GPL(wm8750_dai);
704
1321b160 705static void wm8750_work(struct work_struct *work)
abadfc92 706{
1321b160
TI		 707 struct snd_soc_codec *codec =
708 container_of(work, struct snd_soc_codec, delayed_work.work);
0be9898a 709 wm8750_set_bias_level(codec, codec->bias_level);
abadfc92
RP		 710}
711
712static int wm8750_suspend(struct platform_device *pdev, pm_message_t state)
713{
714 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 715 struct snd_soc_codec *codec = socdev->card->codec;
abadfc92 716
0be9898a 717 wm8750_set_bias_level(codec, SND_SOC_BIAS_OFF);
abadfc92
RP		 718 return 0;
719}
720
721static int wm8750_resume(struct platform_device *pdev)
722{
723 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 724 struct snd_soc_codec *codec = socdev->card->codec;
abadfc92
RP		 725 int i;
726 u8 data[2];
727 u16 *cache = codec->reg_cache;
728
729 /* Sync reg_cache with the hardware */
730 for (i = 0; i < ARRAY_SIZE(wm8750_reg); i++) {
731 if (i == WM8750_RESET)
732 continue;
733 data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
734 data[1] = cache[i] & 0x00ff;
735 codec->hw_write(codec->control_data, data, 2);
736 }
737
0be9898a 738 wm8750_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
abadfc92
RP		 739
740 /* charge wm8750 caps */
0be9898a
MB		 741 if (codec->suspend_bias_level == SND_SOC_BIAS_ON) {
742 wm8750_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
743 codec->bias_level = SND_SOC_BIAS_ON;
42f3030f
MB		 744 schedule_delayed_work(&codec->delayed_work,
745 msecs_to_jiffies(1000));
abadfc92
RP		 746 }
747
748 return 0;
749}
750
751/*
752 * initialise the WM8750 driver
753 * register the mixer and dsp interfaces with the kernel
754 */
755static int wm8750_init(struct snd_soc_device *socdev)
756{
6627a653 757 struct snd_soc_codec *codec = socdev->card->codec;
abadfc92
RP		 758 int reg, ret = 0;
759
760 codec->name = "WM8750";
761 codec->owner = THIS_MODULE;
762 codec->read = wm8750_read_reg_cache;
763 codec->write = wm8750_write;
0be9898a 764 codec->set_bias_level = wm8750_set_bias_level;
abadfc92
RP		 765 codec->dai = &wm8750_dai;
766 codec->num_dai = 1;
d751b233 767 codec->reg_cache_size = ARRAY_SIZE(wm8750_reg);
713fb939 768 codec->reg_cache = kmemdup(wm8750_reg, sizeof(wm8750_reg), GFP_KERNEL);
abadfc92
RP		 769 if (codec->reg_cache == NULL)
770 return -ENOMEM;
abadfc92
RP		 771
772 wm8750_reset(codec);
773
774 /* register pcms */
775 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
776 if (ret < 0) {
e35115a5
LG		 777 printk(KERN_ERR "wm8750: failed to create pcms\n");
778 goto pcm_err;
abadfc92
RP		 779 }
780
781 /* charge output caps */
0be9898a
MB		 782 wm8750_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
783 codec->bias_level = SND_SOC_BIAS_STANDBY;
1321b160 784 schedule_delayed_work(&codec->delayed_work, msecs_to_jiffies(1000));
abadfc92
RP		 785
786 /* set the update bits */
787 reg = wm8750_read_reg_cache(codec, WM8750_LDAC);
788 wm8750_write(codec, WM8750_LDAC, reg | 0x0100);
789 reg = wm8750_read_reg_cache(codec, WM8750_RDAC);
790 wm8750_write(codec, WM8750_RDAC, reg | 0x0100);
791 reg = wm8750_read_reg_cache(codec, WM8750_LOUT1V);
792 wm8750_write(codec, WM8750_LOUT1V, reg | 0x0100);
793 reg = wm8750_read_reg_cache(codec, WM8750_ROUT1V);
794 wm8750_write(codec, WM8750_ROUT1V, reg | 0x0100);
795 reg = wm8750_read_reg_cache(codec, WM8750_LOUT2V);
796 wm8750_write(codec, WM8750_LOUT2V, reg | 0x0100);
797 reg = wm8750_read_reg_cache(codec, WM8750_ROUT2V);
798 wm8750_write(codec, WM8750_ROUT2V, reg | 0x0100);
799 reg = wm8750_read_reg_cache(codec, WM8750_LINVOL);
800 wm8750_write(codec, WM8750_LINVOL, reg | 0x0100);
801 reg = wm8750_read_reg_cache(codec, WM8750_RINVOL);
802 wm8750_write(codec, WM8750_RINVOL, reg | 0x0100);
803
3e8e1952
IM		 804 snd_soc_add_controls(codec, wm8750_snd_controls,
805 ARRAY_SIZE(wm8750_snd_controls));
abadfc92 806 wm8750_add_widgets(codec);
968a6025 807 ret = snd_soc_init_card(socdev);
abadfc92 808 if (ret < 0) {
e35115a5
LG		 809 printk(KERN_ERR "wm8750: failed to register card\n");
810 goto card_err;
abadfc92 811 }
e35115a5 812 return ret;
abadfc92 813
e35115a5
LG		 814card_err:
815 snd_soc_free_pcms(socdev);
816 snd_soc_dapm_free(socdev);
817pcm_err:
818 kfree(codec->reg_cache);
abadfc92
RP		 819 return ret;
820}
821
822/* If the i2c layer weren't so broken, we could pass this kind of data
823 around */
824static struct snd_soc_device *wm8750_socdev;
825
42f3030f 826#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
abadfc92
RP		 827
828/*
2f3dfaf5 829 * WM8750 2 wire address is determined by GPIO5
abadfc92
RP		 830 * state during powerup.
831 * low = 0x1a
832 * high = 0x1b
833 */
abadfc92 834
ee1d0099
JD		 835static int wm8750_i2c_probe(struct i2c_client *i2c,
836 const struct i2c_device_id *id)
abadfc92
RP		 837{
838 struct snd_soc_device *socdev = wm8750_socdev;
6627a653 839 struct snd_soc_codec *codec = socdev->card->codec;
abadfc92
RP		 840 int ret;
841
abadfc92
RP		 842 i2c_set_clientdata(i2c, codec);
843 codec->control_data = i2c;
844
abadfc92 845 ret = wm8750_init(socdev);
ee1d0099 846 if (ret < 0)
a5c95e90 847 pr_err("failed to initialise WM8750\n");
abadfc92 848
abadfc92
RP		 849 return ret;
850}
851
ee1d0099 852static int wm8750_i2c_remove(struct i2c_client *client)
abadfc92
RP		 853{
854 struct snd_soc_codec *codec = i2c_get_clientdata(client);
abadfc92 855 kfree(codec->reg_cache);
abadfc92
RP		 856 return 0;
857}
858
ee1d0099
JD		 859static const struct i2c_device_id wm8750_i2c_id[] = {
860 { "wm8750", 0 },
861 { }
862};
863MODULE_DEVICE_TABLE(i2c, wm8750_i2c_id);
abadfc92 864
abadfc92
RP		 865static struct i2c_driver wm8750_i2c_driver = {
866 .driver = {
867 .name = "WM8750 I2C Codec",
868 .owner = THIS_MODULE,
869 },
ee1d0099
JD		 870 .probe = wm8750_i2c_probe,
871 .remove = wm8750_i2c_remove,
872 .id_table = wm8750_i2c_id,
abadfc92
RP		 873};
874
ee1d0099
JD		 875static int wm8750_add_i2c_device(struct platform_device *pdev,
876 const struct wm8750_setup_data *setup)
877{
878 struct i2c_board_info info;
879 struct i2c_adapter *adapter;
880 struct i2c_client *client;
881 int ret;
882
883 ret = i2c_add_driver(&wm8750_i2c_driver);
884 if (ret != 0) {
885 dev_err(&pdev->dev, "can't add i2c driver\n");
886 return ret;
887 }
888
889 memset(&info, 0, sizeof(struct i2c_board_info));
890 info.addr = setup->i2c_address;
891 strlcpy(info.type, "wm8750", I2C_NAME_SIZE);
892
893 adapter = i2c_get_adapter(setup->i2c_bus);
894 if (!adapter) {
895 dev_err(&pdev->dev, "can't get i2c adapter %d\n",
896 setup->i2c_bus);
897 goto err_driver;
898 }
899
900 client = i2c_new_device(adapter, &info);
901 i2c_put_adapter(adapter);
902 if (!client) {
903 dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
904 (unsigned int)info.addr);
905 goto err_driver;
906 }
907
908 return 0;
909
910err_driver:
911 i2c_del_driver(&wm8750_i2c_driver);
912 return -ENODEV;
913}
abadfc92
RP		 914#endif
915
2f3dfaf5
MB		 916#if defined(CONFIG_SPI_MASTER)
917static int __devinit wm8750_spi_probe(struct spi_device *spi)
918{
919 struct snd_soc_device *socdev = wm8750_socdev;
6627a653 920 struct snd_soc_codec *codec = socdev->card->codec;
2f3dfaf5
MB		 921 int ret;
922
923 codec->control_data = spi;
924
925 ret = wm8750_init(socdev);
926 if (ret < 0)
927 dev_err(&spi->dev, "failed to initialise WM8750\n");
928
929 return ret;
930}
931
932static int __devexit wm8750_spi_remove(struct spi_device *spi)
933{
934 return 0;
935}
936
937static struct spi_driver wm8750_spi_driver = {
938 .driver = {
939 .name = "wm8750",
940 .bus = &spi_bus_type,
941 .owner = THIS_MODULE,
942 },
943 .probe = wm8750_spi_probe,
944 .remove = __devexit_p(wm8750_spi_remove),
945};
946
947static int wm8750_spi_write(struct spi_device *spi, const char *data, int len)
948{
949 struct spi_transfer t;
950 struct spi_message m;
951 u8 msg[2];
952
953 if (len <= 0)
954 return 0;
955
956 msg[0] = data[0];
957 msg[1] = data[1];
958
959 spi_message_init(&m);
960 memset(&t, 0, (sizeof t));
961
962 t.tx_buf = &msg[0];
963 t.len = len;
964
965 spi_message_add_tail(&t, &m);
966 spi_sync(spi, &m);
967
968 return len;
969}
970#endif
971
abadfc92
RP		 972static int wm8750_probe(struct platform_device *pdev)
973{
974 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
975 struct wm8750_setup_data *setup = socdev->codec_data;
976 struct snd_soc_codec *codec;
4422b606 977 struct wm8750_priv *wm8750;
b7c9d852 978 int ret;
abadfc92 979
a5c95e90 980 pr_info("WM8750 Audio Codec %s", WM8750_VERSION);
abadfc92
RP		 981 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
982 if (codec == NULL)
983 return -ENOMEM;
984
4422b606
LG		 985 wm8750 = kzalloc(sizeof(struct wm8750_priv), GFP_KERNEL);
986 if (wm8750 == NULL) {
987 kfree(codec);
988 return -ENOMEM;
989 }
990
991 codec->private_data = wm8750;
6627a653 992 socdev->card->codec = codec;
abadfc92
RP		 993 mutex_init(&codec->mutex);
994 INIT_LIST_HEAD(&codec->dapm_widgets);
995 INIT_LIST_HEAD(&codec->dapm_paths);
996 wm8750_socdev = socdev;
1321b160 997 INIT_DELAYED_WORK(&codec->delayed_work, wm8750_work);
42f3030f 998
b7c9d852
MB		 999 ret = -ENODEV;
1000
42f3030f 1001#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
abadfc92 1002 if (setup->i2c_address) {
abadfc92 1003 codec->hw_write = (hw_write_t)i2c_master_send;
ee1d0099 1004 ret = wm8750_add_i2c_device(pdev, setup);
abadfc92 1005 }
abadfc92 1006#endif
2f3dfaf5
MB		 1007#if defined(CONFIG_SPI_MASTER)
1008 if (setup->spi) {
1009 codec->hw_write = (hw_write_t)wm8750_spi_write;
1010 ret = spi_register_driver(&wm8750_spi_driver);
1011 if (ret != 0)
1012 printk(KERN_ERR "can't add spi driver");
1013 }
1014#endif
abadfc92 1015
3051e41a
JD		 1016 if (ret != 0) {
1017 kfree(codec->private_data);
1018 kfree(codec);
1019 }
abadfc92
RP		 1020 return ret;
1021}
1022
4422b606
LG		 1023/*
1024 * This function forces any delayed work to be queued and run.
1025 */
1026static int run_delayed_work(struct delayed_work *dwork)
1027{
1028 int ret;
1029
1030 /* cancel any work waiting to be queued. */
1031 ret = cancel_delayed_work(dwork);
1032
1033 /* if there was any work waiting then we run it now and
1034 * wait for it's completion */
1035 if (ret) {
1036 schedule_delayed_work(dwork, 0);
1037 flush_scheduled_work();
1038 }
1039 return ret;
1040}
1041
abadfc92
RP		 1042/* power down chip */
1043static int wm8750_remove(struct platform_device *pdev)
1044{
1045 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1046 struct snd_soc_codec *codec = socdev->card->codec;
abadfc92
RP		 1047
1048 if (codec->control_data)
0be9898a 1049 wm8750_set_bias_level(codec, SND_SOC_BIAS_OFF);
4422b606 1050 run_delayed_work(&codec->delayed_work);
abadfc92
RP		 1051 snd_soc_free_pcms(socdev);
1052 snd_soc_dapm_free(socdev);
42f3030f 1053#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
ee1d0099 1054 i2c_unregister_device(codec->control_data);
abadfc92 1055 i2c_del_driver(&wm8750_i2c_driver);
2f3dfaf5
MB		 1056#endif
1057#if defined(CONFIG_SPI_MASTER)
1058 spi_unregister_driver(&wm8750_spi_driver);
abadfc92 1059#endif
4422b606 1060 kfree(codec->private_data);
abadfc92
RP		 1061 kfree(codec);
1062
1063 return 0;
1064}
1065
1066struct snd_soc_codec_device soc_codec_dev_wm8750 = {
1067 .probe = wm8750_probe,
1068 .remove = wm8750_remove,
1069 .suspend = wm8750_suspend,
1070 .resume = wm8750_resume,
1071};
abadfc92
RP		 1072EXPORT_SYMBOL_GPL(soc_codec_dev_wm8750);
1073
c9b3a40f 1074static int __init wm8750_modinit(void)
64089b84
MB		 1075{
1076 return snd_soc_register_dai(&wm8750_dai);
1077}
1078module_init(wm8750_modinit);
1079
1080static void __exit wm8750_exit(void)
1081{
1082 snd_soc_unregister_dai(&wm8750_dai);
1083}
1084module_exit(wm8750_exit);
1085
abadfc92
RP		 1086MODULE_DESCRIPTION("ASoC WM8750 driver");
1087MODULE_AUTHOR("Liam Girdwood");
1088MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)