projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| d5315a23 MB |
1 | /* |
| 2 | * wm2200.h - WM2200 audio codec interface | |
| 3 | * | |
| 4 | * Copyright 2012 Wolfson Microelectronics PLC. | |
| 5 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or modify it | |
| 8 | * under the terms of the GNU General Public License as published by the | |
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | |
| 10 | * option) any later version. | |
| 11 | */ | |
| 12 | ||
| 13 | #ifndef _WM2200_H | |
| 14 | #define _WM2200_H | |
| 15 | ||
| 16 | #define WM2200_CLK_SYSCLK 1 | |
| 17 | ||
| 18 | #define WM2200_CLKSRC_MCLK1 0 | |
| 19 | #define WM2200_CLKSRC_MCLK2 1 | |
| 20 | #define WM2200_CLKSRC_FLL 4 | |
| 21 | #define WM2200_CLKSRC_BCLK1 8 | |
| 22 | ||
| 23 | #define WM2200_FLL_SRC_MCLK1 0 | |
| 24 | #define WM2200_FLL_SRC_MCLK2 1 | |
| 25 | #define WM2200_FLL_SRC_BCLK 2 | |
| 26 | ||
| 27 | /* | |
| 28 | * Register values. | |
| 29 | */ | |
| 30 | #define WM2200_SOFTWARE_RESET 0x00 | |
| 31 | #define WM2200_DEVICE_REVISION 0x01 | |
| 32 | #define WM2200_TONE_GENERATOR_1 0x0B | |
| 33 | #define WM2200_CLOCKING_3 0x102 | |
| 34 | #define WM2200_CLOCKING_4 0x103 | |
| 35 | #define WM2200_FLL_CONTROL_1 0x111 | |
| 36 | #define WM2200_FLL_CONTROL_2 0x112 | |
| 37 | #define WM2200_FLL_CONTROL_3 0x113 | |
| 38 | #define WM2200_FLL_CONTROL_4 0x114 | |
| 39 | #define WM2200_FLL_CONTROL_6 0x116 | |
| 40 | #define WM2200_FLL_CONTROL_7 0x117 | |
| 41 | #define WM2200_FLL_EFS_1 0x119 | |
| 42 | #define WM2200_FLL_EFS_2 0x11A | |
| 43 | #define WM2200_MIC_CHARGE_PUMP_1 0x200 | |
| 44 | #define WM2200_MIC_CHARGE_PUMP_2 0x201 | |
| 45 | #define WM2200_DM_CHARGE_PUMP_1 0x202 | |
| 46 | #define WM2200_MIC_BIAS_CTRL_1 0x20C | |
| 47 | #define WM2200_MIC_BIAS_CTRL_2 0x20D | |
| 48 | #define WM2200_EAR_PIECE_CTRL_1 0x20F | |
| 49 | #define WM2200_EAR_PIECE_CTRL_2 0x210 | |
| 50 | #define WM2200_INPUT_ENABLES 0x301 | |
| 51 | #define WM2200_IN1L_CONTROL 0x302 | |
| 52 | #define WM2200_IN1R_CONTROL 0x303 | |
| 53 | #define WM2200_IN2L_CONTROL 0x304 | |
| 54 | #define WM2200_IN2R_CONTROL 0x305 | |
| 55 | #define WM2200_IN3L_CONTROL 0x306 | |
| 56 | #define WM2200_IN3R_CONTROL 0x307 | |
| 57 | #define WM2200_RXANC_SRC 0x30A | |
| 58 | #define WM2200_INPUT_VOLUME_RAMP 0x30B | |
| 59 | #define WM2200_ADC_DIGITAL_VOLUME_1L 0x30C | |
| 60 | #define WM2200_ADC_DIGITAL_VOLUME_1R 0x30D | |
| 61 | #define WM2200_ADC_DIGITAL_VOLUME_2L 0x30E | |
| 62 | #define WM2200_ADC_DIGITAL_VOLUME_2R 0x30F | |
| 63 | #define WM2200_ADC_DIGITAL_VOLUME_3L 0x310 | |
| 64 | #define WM2200_ADC_DIGITAL_VOLUME_3R 0x311 | |
| 65 | #define WM2200_OUTPUT_ENABLES 0x400 | |
| 66 | #define WM2200_DAC_VOLUME_LIMIT_1L 0x401 | |
| 67 | #define WM2200_DAC_VOLUME_LIMIT_1R 0x402 | |
| 68 | #define WM2200_DAC_VOLUME_LIMIT_2L 0x403 | |
| 69 | #define WM2200_DAC_VOLUME_LIMIT_2R 0x404 | |
| 70 | #define WM2200_DAC_AEC_CONTROL_1 0x409 | |
| 71 | #define WM2200_OUTPUT_VOLUME_RAMP 0x40A | |
| 72 | #define WM2200_DAC_DIGITAL_VOLUME_1L 0x40B | |
| 73 | #define WM2200_DAC_DIGITAL_VOLUME_1R 0x40C | |
| 74 | #define WM2200_DAC_DIGITAL_VOLUME_2L 0x40D | |
| 75 | #define WM2200_DAC_DIGITAL_VOLUME_2R 0x40E | |
| 76 | #define WM2200_PDM_1 0x417 | |
| 77 | #define WM2200_PDM_2 0x418 | |
| 78 | #define WM2200_AUDIO_IF_1_1 0x500 | |
| 79 | #define WM2200_AUDIO_IF_1_2 0x501 | |
| 80 | #define WM2200_AUDIO_IF_1_3 0x502 | |
| 81 | #define WM2200_AUDIO_IF_1_4 0x503 | |
| 82 | #define WM2200_AUDIO_IF_1_5 0x504 | |
| 83 | #define WM2200_AUDIO_IF_1_6 0x505 | |
| 84 | #define WM2200_AUDIO_IF_1_7 0x506 | |
| 85 | #define WM2200_AUDIO_IF_1_8 0x507 | |
| 86 | #define WM2200_AUDIO_IF_1_9 0x508 | |
| 87 | #define WM2200_AUDIO_IF_1_10 0x509 | |
| 88 | #define WM2200_AUDIO_IF_1_11 0x50A | |
| 89 | #define WM2200_AUDIO_IF_1_12 0x50B | |
| 90 | #define WM2200_AUDIO_IF_1_13 0x50C | |
| 91 | #define WM2200_AUDIO_IF_1_14 0x50D | |
| 92 | #define WM2200_AUDIO_IF_1_15 0x50E | |
| 93 | #define WM2200_AUDIO_IF_1_16 0x50F | |
| 94 | #define WM2200_AUDIO_IF_1_17 0x510 | |
| 95 | #define WM2200_AUDIO_IF_1_18 0x511 | |
| 96 | #define WM2200_AUDIO_IF_1_19 0x512 | |
| 97 | #define WM2200_AUDIO_IF_1_20 0x513 | |
| 98 | #define WM2200_AUDIO_IF_1_21 0x514 | |
| 99 | #define WM2200_AUDIO_IF_1_22 0x515 | |
| 100 | #define WM2200_OUT1LMIX_INPUT_1_SOURCE 0x600 | |
| 101 | #define WM2200_OUT1LMIX_INPUT_1_VOLUME 0x601 | |
| 102 | #define WM2200_OUT1LMIX_INPUT_2_SOURCE 0x602 | |
| 103 | #define WM2200_OUT1LMIX_INPUT_2_VOLUME 0x603 | |
| 104 | #define WM2200_OUT1LMIX_INPUT_3_SOURCE 0x604 | |
| 105 | #define WM2200_OUT1LMIX_INPUT_3_VOLUME 0x605 | |
| 106 | #define WM2200_OUT1LMIX_INPUT_4_SOURCE 0x606 | |
| 107 | #define WM2200_OUT1LMIX_INPUT_4_VOLUME 0x607 | |
| 108 | #define WM2200_OUT1RMIX_INPUT_1_SOURCE 0x608 | |
| 109 | #define WM2200_OUT1RMIX_INPUT_1_VOLUME 0x609 | |
| 110 | #define WM2200_OUT1RMIX_INPUT_2_SOURCE 0x60A | |
| 111 | #define WM2200_OUT1RMIX_INPUT_2_VOLUME 0x60B | |
| 112 | #define WM2200_OUT1RMIX_INPUT_3_SOURCE 0x60C | |
| 113 | #define WM2200_OUT1RMIX_INPUT_3_VOLUME 0x60D | |
| 114 | #define WM2200_OUT1RMIX_INPUT_4_SOURCE 0x60E | |
| 115 | #define WM2200_OUT1RMIX_INPUT_4_VOLUME 0x60F | |
| 116 | #define WM2200_OUT2LMIX_INPUT_1_SOURCE 0x610 | |
| 117 | #define WM2200_OUT2LMIX_INPUT_1_VOLUME 0x611 | |
| 118 | #define WM2200_OUT2LMIX_INPUT_2_SOURCE 0x612 | |
| 119 | #define WM2200_OUT2LMIX_INPUT_2_VOLUME 0x613 | |
| 120 | #define WM2200_OUT2LMIX_INPUT_3_SOURCE 0x614 | |
| 121 | #define WM2200_OUT2LMIX_INPUT_3_VOLUME 0x615 | |
| 122 | #define WM2200_OUT2LMIX_INPUT_4_SOURCE 0x616 | |
| 123 | #define WM2200_OUT2LMIX_INPUT_4_VOLUME 0x617 | |
| 124 | #define WM2200_OUT2RMIX_INPUT_1_SOURCE 0x618 | |
| 125 | #define WM2200_OUT2RMIX_INPUT_1_VOLUME 0x619 | |
| 126 | #define WM2200_OUT2RMIX_INPUT_2_SOURCE 0x61A | |
| 127 | #define WM2200_OUT2RMIX_INPUT_2_VOLUME 0x61B | |
| 128 | #define WM2200_OUT2RMIX_INPUT_3_SOURCE 0x61C | |
| 129 | #define WM2200_OUT2RMIX_INPUT_3_VOLUME 0x61D | |
| 130 | #define WM2200_OUT2RMIX_INPUT_4_SOURCE 0x61E | |
| 131 | #define WM2200_OUT2RMIX_INPUT_4_VOLUME 0x61F | |
| 132 | #define WM2200_AIF1TX1MIX_INPUT_1_SOURCE 0x620 | |
| 133 | #define WM2200_AIF1TX1MIX_INPUT_1_VOLUME 0x621 | |
| 134 | #define WM2200_AIF1TX1MIX_INPUT_2_SOURCE 0x622 | |
| 135 | #define WM2200_AIF1TX1MIX_INPUT_2_VOLUME 0x623 | |
| 136 | #define WM2200_AIF1TX1MIX_INPUT_3_SOURCE 0x624 | |
| 137 | #define WM2200_AIF1TX1MIX_INPUT_3_VOLUME 0x625 | |
| 138 | #define WM2200_AIF1TX1MIX_INPUT_4_SOURCE 0x626 | |
| 139 | #define WM2200_AIF1TX1MIX_INPUT_4_VOLUME 0x627 | |
| 140 | #define WM2200_AIF1TX2MIX_INPUT_1_SOURCE 0x628 | |
| 141 | #define WM2200_AIF1TX2MIX_INPUT_1_VOLUME 0x629 | |
| 142 | #define WM2200_AIF1TX2MIX_INPUT_2_SOURCE 0x62A | |
| 143 | #define WM2200_AIF1TX2MIX_INPUT_2_VOLUME 0x62B | |
| 144 | #define WM2200_AIF1TX2MIX_INPUT_3_SOURCE 0x62C | |
| 145 | #define WM2200_AIF1TX2MIX_INPUT_3_VOLUME 0x62D | |
| 146 | #define WM2200_AIF1TX2MIX_INPUT_4_SOURCE 0x62E | |
| 147 | #define WM2200_AIF1TX2MIX_INPUT_4_VOLUME 0x62F | |
| 148 | #define WM2200_AIF1TX3MIX_INPUT_1_SOURCE 0x630 | |
| 149 | #define WM2200_AIF1TX3MIX_INPUT_1_VOLUME 0x631 | |
| 150 | #define WM2200_AIF1TX3MIX_INPUT_2_SOURCE 0x632 | |
| 151 | #define WM2200_AIF1TX3MIX_INPUT_2_VOLUME 0x633 | |
| 152 | #define WM2200_AIF1TX3MIX_INPUT_3_SOURCE 0x634 | |
| 153 | #define WM2200_AIF1TX3MIX_INPUT_3_VOLUME 0x635 | |
| 154 | #define WM2200_AIF1TX3MIX_INPUT_4_SOURCE 0x636 | |
| 155 | #define WM2200_AIF1TX3MIX_INPUT_4_VOLUME 0x637 | |
| 156 | #define WM2200_AIF1TX4MIX_INPUT_1_SOURCE 0x638 | |
| 157 | #define WM2200_AIF1TX4MIX_INPUT_1_VOLUME 0x639 | |
| 158 | #define WM2200_AIF1TX4MIX_INPUT_2_SOURCE 0x63A | |
| 159 | #define WM2200_AIF1TX4MIX_INPUT_2_VOLUME 0x63B | |
| 160 | #define WM2200_AIF1TX4MIX_INPUT_3_SOURCE 0x63C | |
| 161 | #define WM2200_AIF1TX4MIX_INPUT_3_VOLUME 0x63D | |
| 162 | #define WM2200_AIF1TX4MIX_INPUT_4_SOURCE 0x63E | |
| 163 | #define WM2200_AIF1TX4MIX_INPUT_4_VOLUME 0x63F | |
| 164 | #define WM2200_AIF1TX5MIX_INPUT_1_SOURCE 0x640 | |
| 165 | #define WM2200_AIF1TX5MIX_INPUT_1_VOLUME 0x641 | |
| 166 | #define WM2200_AIF1TX5MIX_INPUT_2_SOURCE 0x642 | |
| 167 | #define WM2200_AIF1TX5MIX_INPUT_2_VOLUME 0x643 | |
| 168 | #define WM2200_AIF1TX5MIX_INPUT_3_SOURCE 0x644 | |
| 169 | #define WM2200_AIF1TX5MIX_INPUT_3_VOLUME 0x645 | |
| 170 | #define WM2200_AIF1TX5MIX_INPUT_4_SOURCE 0x646 | |
| 171 | #define WM2200_AIF1TX5MIX_INPUT_4_VOLUME 0x647 | |
| 172 | #define WM2200_AIF1TX6MIX_INPUT_1_SOURCE 0x648 | |
| 173 | #define WM2200_AIF1TX6MIX_INPUT_1_VOLUME 0x649 | |
| 174 | #define WM2200_AIF1TX6MIX_INPUT_2_SOURCE 0x64A | |
| 175 | #define WM2200_AIF1TX6MIX_INPUT_2_VOLUME 0x64B | |
| 176 | #define WM2200_AIF1TX6MIX_INPUT_3_SOURCE 0x64C | |
| 177 | #define WM2200_AIF1TX6MIX_INPUT_3_VOLUME 0x64D | |
| 178 | #define WM2200_AIF1TX6MIX_INPUT_4_SOURCE 0x64E | |
| 179 | #define WM2200_AIF1TX6MIX_INPUT_4_VOLUME 0x64F | |
| 180 | #define WM2200_EQLMIX_INPUT_1_SOURCE 0x650 | |
| 181 | #define WM2200_EQLMIX_INPUT_1_VOLUME 0x651 | |
| 182 | #define WM2200_EQLMIX_INPUT_2_SOURCE 0x652 | |
| 183 | #define WM2200_EQLMIX_INPUT_2_VOLUME 0x653 | |
| 184 | #define WM2200_EQLMIX_INPUT_3_SOURCE 0x654 | |
| 185 | #define WM2200_EQLMIX_INPUT_3_VOLUME 0x655 | |
| 186 | #define WM2200_EQLMIX_INPUT_4_SOURCE 0x656 | |
| 187 | #define WM2200_EQLMIX_INPUT_4_VOLUME 0x657 | |
| 188 | #define WM2200_EQRMIX_INPUT_1_SOURCE 0x658 | |
| 189 | #define WM2200_EQRMIX_INPUT_1_VOLUME 0x659 | |
| 190 | #define WM2200_EQRMIX_INPUT_2_SOURCE 0x65A | |
| 191 | #define WM2200_EQRMIX_INPUT_2_VOLUME 0x65B | |
| 192 | #define WM2200_EQRMIX_INPUT_3_SOURCE 0x65C | |
| 193 | #define WM2200_EQRMIX_INPUT_3_VOLUME 0x65D | |
| 194 | #define WM2200_EQRMIX_INPUT_4_SOURCE 0x65E | |
| 195 | #define WM2200_EQRMIX_INPUT_4_VOLUME 0x65F | |
| 196 | #define WM2200_LHPF1MIX_INPUT_1_SOURCE 0x660 | |
| 197 | #define WM2200_LHPF1MIX_INPUT_1_VOLUME 0x661 | |
| 198 | #define WM2200_LHPF1MIX_INPUT_2_SOURCE 0x662 | |
| 199 | #define WM2200_LHPF1MIX_INPUT_2_VOLUME 0x663 | |
| 200 | #define WM2200_LHPF1MIX_INPUT_3_SOURCE 0x664 | |
| 201 | #define WM2200_LHPF1MIX_INPUT_3_VOLUME 0x665 | |
| 202 | #define WM2200_LHPF1MIX_INPUT_4_SOURCE 0x666 | |
| 203 | #define WM2200_LHPF1MIX_INPUT_4_VOLUME 0x667 | |
| 204 | #define WM2200_LHPF2MIX_INPUT_1_SOURCE 0x668 | |
| 205 | #define WM2200_LHPF2MIX_INPUT_1_VOLUME 0x669 | |
| 206 | #define WM2200_LHPF2MIX_INPUT_2_SOURCE 0x66A | |
| 207 | #define WM2200_LHPF2MIX_INPUT_2_VOLUME 0x66B | |
| 208 | #define WM2200_LHPF2MIX_INPUT_3_SOURCE 0x66C | |
| 209 | #define WM2200_LHPF2MIX_INPUT_3_VOLUME 0x66D | |
| 210 | #define WM2200_LHPF2MIX_INPUT_4_SOURCE 0x66E | |
| 211 | #define WM2200_LHPF2MIX_INPUT_4_VOLUME 0x66F | |
| 212 | #define WM2200_DSP1LMIX_INPUT_1_SOURCE 0x670 | |
| 213 | #define WM2200_DSP1LMIX_INPUT_1_VOLUME 0x671 | |
| 214 | #define WM2200_DSP1LMIX_INPUT_2_SOURCE 0x672 | |
| 215 | #define WM2200_DSP1LMIX_INPUT_2_VOLUME 0x673 | |
| 216 | #define WM2200_DSP1LMIX_INPUT_3_SOURCE 0x674 | |
| 217 | #define WM2200_DSP1LMIX_INPUT_3_VOLUME 0x675 | |
| 218 | #define WM2200_DSP1LMIX_INPUT_4_SOURCE 0x676 | |
| 219 | #define WM2200_DSP1LMIX_INPUT_4_VOLUME 0x677 | |
| 220 | #define WM2200_DSP1RMIX_INPUT_1_SOURCE 0x678 | |
| 221 | #define WM2200_DSP1RMIX_INPUT_1_VOLUME 0x679 | |
| 222 | #define WM2200_DSP1RMIX_INPUT_2_SOURCE 0x67A | |
| 223 | #define WM2200_DSP1RMIX_INPUT_2_VOLUME 0x67B | |
| 224 | #define WM2200_DSP1RMIX_INPUT_3_SOURCE 0x67C | |
| 225 | #define WM2200_DSP1RMIX_INPUT_3_VOLUME 0x67D | |
| 226 | #define WM2200_DSP1RMIX_INPUT_4_SOURCE 0x67E | |
| 227 | #define WM2200_DSP1RMIX_INPUT_4_VOLUME 0x67F | |
| 228 | #define WM2200_DSP1AUX1MIX_INPUT_1_SOURCE 0x680 | |
| 229 | #define WM2200_DSP1AUX2MIX_INPUT_1_SOURCE 0x681 | |
| 230 | #define WM2200_DSP1AUX3MIX_INPUT_1_SOURCE 0x682 | |
| 231 | #define WM2200_DSP1AUX4MIX_INPUT_1_SOURCE 0x683 | |
| 232 | #define WM2200_DSP1AUX5MIX_INPUT_1_SOURCE 0x684 | |
| 233 | #define WM2200_DSP1AUX6MIX_INPUT_1_SOURCE 0x685 | |
| 234 | #define WM2200_DSP2LMIX_INPUT_1_SOURCE 0x686 | |
| 235 | #define WM2200_DSP2LMIX_INPUT_1_VOLUME 0x687 | |
| 236 | #define WM2200_DSP2LMIX_INPUT_2_SOURCE 0x688 | |
| 237 | #define WM2200_DSP2LMIX_INPUT_2_VOLUME 0x689 | |
| 238 | #define WM2200_DSP2LMIX_INPUT_3_SOURCE 0x68A | |
| 239 | #define WM2200_DSP2LMIX_INPUT_3_VOLUME 0x68B | |
| 240 | #define WM2200_DSP2LMIX_INPUT_4_SOURCE 0x68C | |
| 241 | #define WM2200_DSP2LMIX_INPUT_4_VOLUME 0x68D | |
| 242 | #define WM2200_DSP2RMIX_INPUT_1_SOURCE 0x68E | |
| 243 | #define WM2200_DSP2RMIX_INPUT_1_VOLUME 0x68F | |
| 244 | #define WM2200_DSP2RMIX_INPUT_2_SOURCE 0x690 | |
| 245 | #define WM2200_DSP2RMIX_INPUT_2_VOLUME 0x691 | |
| 246 | #define WM2200_DSP2RMIX_INPUT_3_SOURCE 0x692 | |
| 247 | #define WM2200_DSP2RMIX_INPUT_3_VOLUME 0x693 | |
| 248 | #define WM2200_DSP2RMIX_INPUT_4_SOURCE 0x694 | |
| 249 | #define WM2200_DSP2RMIX_INPUT_4_VOLUME 0x695 | |
| 250 | #define WM2200_DSP2AUX1MIX_INPUT_1_SOURCE 0x696 | |
| 251 | #define WM2200_DSP2AUX2MIX_INPUT_1_SOURCE 0x697 | |
| 252 | #define WM2200_DSP2AUX3MIX_INPUT_1_SOURCE 0x698 | |
| 253 | #define WM2200_DSP2AUX4MIX_INPUT_1_SOURCE 0x699 | |
| 254 | #define WM2200_DSP2AUX5MIX_INPUT_1_SOURCE 0x69A | |
| 255 | #define WM2200_DSP2AUX6MIX_INPUT_1_SOURCE 0x69B | |
| 256 | #define WM2200_GPIO_CTRL_1 0x700 | |
| 257 | #define WM2200_GPIO_CTRL_2 0x701 | |
| 258 | #define WM2200_GPIO_CTRL_3 0x702 | |
| 259 | #define WM2200_GPIO_CTRL_4 0x703 | |
| 260 | #define WM2200_ADPS1_IRQ0 0x707 | |
| 261 | #define WM2200_ADPS1_IRQ1 0x708 | |
| 262 | #define WM2200_MISC_PAD_CTRL_1 0x709 | |
| 263 | #define WM2200_INTERRUPT_STATUS_1 0x800 | |
| 264 | #define WM2200_INTERRUPT_STATUS_1_MASK 0x801 | |
| 265 | #define WM2200_INTERRUPT_STATUS_2 0x802 | |
| 266 | #define WM2200_INTERRUPT_RAW_STATUS_2 0x803 | |
| 267 | #define WM2200_INTERRUPT_STATUS_2_MASK 0x804 | |
| 268 | #define WM2200_INTERRUPT_CONTROL 0x808 | |
| 269 | #define WM2200_EQL_1 0x900 | |
| 270 | #define WM2200_EQL_2 0x901 | |
| 271 | #define WM2200_EQL_3 0x902 | |
| 272 | #define WM2200_EQL_4 0x903 | |
| 273 | #define WM2200_EQL_5 0x904 | |
| 274 | #define WM2200_EQL_6 0x905 | |
| 275 | #define WM2200_EQL_7 0x906 | |
| 276 | #define WM2200_EQL_8 0x907 | |
| 277 | #define WM2200_EQL_9 0x908 | |
| 278 | #define WM2200_EQL_10 0x909 | |
| 279 | #define WM2200_EQL_11 0x90A | |
| 280 | #define WM2200_EQL_12 0x90B | |
| 281 | #define WM2200_EQL_13 0x90C | |
| 282 | #define WM2200_EQL_14 0x90D | |
| 283 | #define WM2200_EQL_15 0x90E | |
| 284 | #define WM2200_EQL_16 0x90F | |
| 285 | #define WM2200_EQL_17 0x910 | |
| 286 | #define WM2200_EQL_18 0x911 | |
| 287 | #define WM2200_EQL_19 0x912 | |
| 288 | #define WM2200_EQL_20 0x913 | |
| 289 | #define WM2200_EQR_1 0x916 | |
| 290 | #define WM2200_EQR_2 0x917 | |
| 291 | #define WM2200_EQR_3 0x918 | |
| 292 | #define WM2200_EQR_4 0x919 | |
| 293 | #define WM2200_EQR_5 0x91A | |
| 294 | #define WM2200_EQR_6 0x91B | |
| 295 | #define WM2200_EQR_7 0x91C | |
| 296 | #define WM2200_EQR_8 0x91D | |
| 297 | #define WM2200_EQR_9 0x91E | |
| 298 | #define WM2200_EQR_10 0x91F | |
| 299 | #define WM2200_EQR_11 0x920 | |
| 300 | #define WM2200_EQR_12 0x921 | |
| 301 | #define WM2200_EQR_13 0x922 | |
| 302 | #define WM2200_EQR_14 0x923 | |
| 303 | #define WM2200_EQR_15 0x924 | |
| 304 | #define WM2200_EQR_16 0x925 | |
| 305 | #define WM2200_EQR_17 0x926 | |
| 306 | #define WM2200_EQR_18 0x927 | |
| 307 | #define WM2200_EQR_19 0x928 | |
| 308 | #define WM2200_EQR_20 0x929 | |
| 309 | #define WM2200_HPLPF1_1 0x93E | |
| 310 | #define WM2200_HPLPF1_2 0x93F | |
| 311 | #define WM2200_HPLPF2_1 0x942 | |
| 312 | #define WM2200_HPLPF2_2 0x943 | |
| 313 | #define WM2200_DSP1_CONTROL_1 0xA00 | |
| 314 | #define WM2200_DSP1_CONTROL_2 0xA02 | |
| 315 | #define WM2200_DSP1_CONTROL_3 0xA03 | |
| 316 | #define WM2200_DSP1_CONTROL_4 0xA04 | |
| 317 | #define WM2200_DSP1_CONTROL_5 0xA06 | |
| 318 | #define WM2200_DSP1_CONTROL_6 0xA07 | |
| 319 | #define WM2200_DSP1_CONTROL_7 0xA08 | |
| 320 | #define WM2200_DSP1_CONTROL_8 0xA09 | |
| 321 | #define WM2200_DSP1_CONTROL_9 0xA0A | |
| 322 | #define WM2200_DSP1_CONTROL_10 0xA0B | |
| 323 | #define WM2200_DSP1_CONTROL_11 0xA0C | |
| 324 | #define WM2200_DSP1_CONTROL_12 0xA0D | |
| 325 | #define WM2200_DSP1_CONTROL_13 0xA0F | |
| 326 | #define WM2200_DSP1_CONTROL_14 0xA10 | |
| 327 | #define WM2200_DSP1_CONTROL_15 0xA11 | |
| 328 | #define WM2200_DSP1_CONTROL_16 0xA12 | |
| 329 | #define WM2200_DSP1_CONTROL_17 0xA13 | |
| 330 | #define WM2200_DSP1_CONTROL_18 0xA14 | |
| 331 | #define WM2200_DSP1_CONTROL_19 0xA16 | |
| 332 | #define WM2200_DSP1_CONTROL_20 0xA17 | |
| 333 | #define WM2200_DSP1_CONTROL_21 0xA18 | |
| 334 | #define WM2200_DSP1_CONTROL_22 0xA1A | |
| 335 | #define WM2200_DSP1_CONTROL_23 0xA1B | |
| 336 | #define WM2200_DSP1_CONTROL_24 0xA1C | |
| 337 | #define WM2200_DSP1_CONTROL_25 0xA1E | |
| 338 | #define WM2200_DSP1_CONTROL_26 0xA20 | |
| 339 | #define WM2200_DSP1_CONTROL_27 0xA21 | |
| 340 | #define WM2200_DSP1_CONTROL_28 0xA22 | |
| 341 | #define WM2200_DSP1_CONTROL_29 0xA23 | |
| 342 | #define WM2200_DSP1_CONTROL_30 0xA24 | |
| 343 | #define WM2200_DSP1_CONTROL_31 0xA26 | |
| 344 | #define WM2200_DSP2_CONTROL_1 0xB00 | |
| 345 | #define WM2200_DSP2_CONTROL_2 0xB02 | |
| 346 | #define WM2200_DSP2_CONTROL_3 0xB03 | |
| 347 | #define WM2200_DSP2_CONTROL_4 0xB04 | |
| 348 | #define WM2200_DSP2_CONTROL_5 0xB06 | |
| 349 | #define WM2200_DSP2_CONTROL_6 0xB07 | |
| 350 | #define WM2200_DSP2_CONTROL_7 0xB08 | |
| 351 | #define WM2200_DSP2_CONTROL_8 0xB09 | |
| 352 | #define WM2200_DSP2_CONTROL_9 0xB0A | |
| 353 | #define WM2200_DSP2_CONTROL_10 0xB0B | |
| 354 | #define WM2200_DSP2_CONTROL_11 0xB0C | |
| 355 | #define WM2200_DSP2_CONTROL_12 0xB0D | |
| 356 | #define WM2200_DSP2_CONTROL_13 0xB0F | |
| 357 | #define WM2200_DSP2_CONTROL_14 0xB10 | |
| 358 | #define WM2200_DSP2_CONTROL_15 0xB11 | |
| 359 | #define WM2200_DSP2_CONTROL_16 0xB12 | |
| 360 | #define WM2200_DSP2_CONTROL_17 0xB13 | |
| 361 | #define WM2200_DSP2_CONTROL_18 0xB14 | |
| 362 | #define WM2200_DSP2_CONTROL_19 0xB16 | |
| 363 | #define WM2200_DSP2_CONTROL_20 0xB17 | |
| 364 | #define WM2200_DSP2_CONTROL_21 0xB18 | |
| 365 | #define WM2200_DSP2_CONTROL_22 0xB1A | |
| 366 | #define WM2200_DSP2_CONTROL_23 0xB1B | |
| 367 | #define WM2200_DSP2_CONTROL_24 0xB1C | |
| 368 | #define WM2200_DSP2_CONTROL_25 0xB1E | |
| 369 | #define WM2200_DSP2_CONTROL_26 0xB20 | |
| 370 | #define WM2200_DSP2_CONTROL_27 0xB21 | |
| 371 | #define WM2200_DSP2_CONTROL_28 0xB22 | |
| 372 | #define WM2200_DSP2_CONTROL_29 0xB23 | |
| 373 | #define WM2200_DSP2_CONTROL_30 0xB24 | |
| 374 | #define WM2200_DSP2_CONTROL_31 0xB26 | |
| 375 | #define WM2200_ANC_CTRL1 0xD00 | |
| 376 | #define WM2200_ANC_CTRL2 0xD01 | |
| 377 | #define WM2200_ANC_CTRL3 0xD02 | |
| 378 | #define WM2200_ANC_CTRL7 0xD08 | |
| 379 | #define WM2200_ANC_CTRL8 0xD09 | |
| 380 | #define WM2200_ANC_CTRL9 0xD0A | |
| 381 | #define WM2200_ANC_CTRL10 0xD0B | |
| 382 | #define WM2200_ANC_CTRL11 0xD0C | |
| 383 | #define WM2200_ANC_CTRL12 0xD0D | |
| 384 | #define WM2200_ANC_CTRL13 0xD0E | |
| 385 | #define WM2200_ANC_CTRL14 0xD0F | |
| 386 | #define WM2200_ANC_CTRL15 0xD10 | |
| 387 | #define WM2200_ANC_CTRL16 0xD11 | |
| 388 | #define WM2200_ANC_CTRL17 0xD12 | |
| 389 | #define WM2200_ANC_CTRL18 0xD15 | |
| 390 | #define WM2200_ANC_CTRL19 0xD16 | |
| 391 | #define WM2200_ANC_CTRL20 0xD17 | |
| 392 | #define WM2200_ANC_CTRL21 0xD18 | |
| 393 | #define WM2200_ANC_CTRL22 0xD19 | |
| 394 | #define WM2200_ANC_CTRL23 0xD1A | |
| 395 | #define WM2200_ANC_CTRL24 0xD1B | |
| 396 | #define WM2200_ANC_CTRL25 0xD1C | |
| 397 | #define WM2200_ANC_CTRL26 0xD1D | |
| 398 | #define WM2200_ANC_CTRL27 0xD1E | |
| 399 | #define WM2200_ANC_CTRL28 0xD1F | |
| 400 | #define WM2200_ANC_CTRL29 0xD20 | |
| 401 | #define WM2200_ANC_CTRL30 0xD21 | |
| 402 | #define WM2200_ANC_CTRL31 0xD23 | |
| 403 | #define WM2200_ANC_CTRL32 0xD24 | |
| 404 | #define WM2200_ANC_CTRL33 0xD25 | |
| 405 | #define WM2200_ANC_CTRL34 0xD27 | |
| 406 | #define WM2200_ANC_CTRL35 0xD28 | |
| 407 | #define WM2200_ANC_CTRL36 0xD29 | |
| 408 | #define WM2200_ANC_CTRL37 0xD2A | |
| 409 | #define WM2200_ANC_CTRL38 0xD2B | |
| 410 | #define WM2200_ANC_CTRL39 0xD2C | |
| 411 | #define WM2200_ANC_CTRL40 0xD2D | |
| 412 | #define WM2200_ANC_CTRL41 0xD2E | |
| 413 | #define WM2200_ANC_CTRL42 0xD2F | |
| 414 | #define WM2200_ANC_CTRL43 0xD30 | |
| 415 | #define WM2200_ANC_CTRL44 0xD31 | |
| 416 | #define WM2200_ANC_CTRL45 0xD32 | |
| 417 | #define WM2200_ANC_CTRL46 0xD33 | |
| 418 | #define WM2200_ANC_CTRL47 0xD34 | |
| 419 | #define WM2200_ANC_CTRL48 0xD35 | |
| 420 | #define WM2200_ANC_CTRL49 0xD36 | |
| 421 | #define WM2200_ANC_CTRL50 0xD37 | |
| 422 | #define WM2200_ANC_CTRL51 0xD38 | |
| 423 | #define WM2200_ANC_CTRL52 0xD39 | |
| 424 | #define WM2200_ANC_CTRL53 0xD3A | |
| 425 | #define WM2200_ANC_CTRL54 0xD3B | |
| 426 | #define WM2200_ANC_CTRL55 0xD3C | |
| 427 | #define WM2200_ANC_CTRL56 0xD3D | |
| 428 | #define WM2200_ANC_CTRL57 0xD3E | |
| 429 | #define WM2200_ANC_CTRL58 0xD3F | |
| 430 | #define WM2200_ANC_CTRL59 0xD40 | |
| 431 | #define WM2200_ANC_CTRL60 0xD41 | |
| 432 | #define WM2200_ANC_CTRL61 0xD42 | |
| 433 | #define WM2200_ANC_CTRL62 0xD43 | |
| 434 | #define WM2200_ANC_CTRL63 0xD44 | |
| 435 | #define WM2200_ANC_CTRL64 0xD45 | |
| 436 | #define WM2200_ANC_CTRL65 0xD46 | |
| 437 | #define WM2200_ANC_CTRL66 0xD47 | |
| 438 | #define WM2200_ANC_CTRL67 0xD48 | |
| 439 | #define WM2200_ANC_CTRL68 0xD49 | |
| 440 | #define WM2200_ANC_CTRL69 0xD4A | |
| 441 | #define WM2200_ANC_CTRL70 0xD4B | |
| 442 | #define WM2200_ANC_CTRL71 0xD4C | |
| 443 | #define WM2200_ANC_CTRL72 0xD4D | |
| 444 | #define WM2200_ANC_CTRL73 0xD4E | |
| 445 | #define WM2200_ANC_CTRL74 0xD4F | |
| 446 | #define WM2200_ANC_CTRL75 0xD50 | |
| 447 | #define WM2200_ANC_CTRL76 0xD51 | |
| 448 | #define WM2200_ANC_CTRL77 0xD52 | |
| 449 | #define WM2200_ANC_CTRL78 0xD53 | |
| 450 | #define WM2200_ANC_CTRL79 0xD54 | |
| 451 | #define WM2200_ANC_CTRL80 0xD55 | |
| 452 | #define WM2200_ANC_CTRL81 0xD56 | |
| 453 | #define WM2200_ANC_CTRL82 0xD57 | |
| 454 | #define WM2200_ANC_CTRL83 0xD58 | |
| 455 | #define WM2200_ANC_CTRL84 0xD5B | |
| 456 | #define WM2200_ANC_CTRL85 0xD5C | |
| 457 | #define WM2200_ANC_CTRL86 0xD5F | |
| 458 | #define WM2200_ANC_CTRL87 0xD60 | |
| 459 | #define WM2200_ANC_CTRL88 0xD61 | |
| 460 | #define WM2200_ANC_CTRL89 0xD62 | |
| 461 | #define WM2200_ANC_CTRL90 0xD63 | |
| 462 | #define WM2200_ANC_CTRL91 0xD64 | |
| 463 | #define WM2200_ANC_CTRL92 0xD65 | |
| 464 | #define WM2200_ANC_CTRL93 0xD66 | |
| 465 | #define WM2200_ANC_CTRL94 0xD67 | |
| 466 | #define WM2200_ANC_CTRL95 0xD68 | |
| 467 | #define WM2200_ANC_CTRL96 0xD69 | |
| 468 | #define WM2200_DSP1_DM_0 0x3000 | |
| 469 | #define WM2200_DSP1_DM_1 0x3001 | |
| 470 | #define WM2200_DSP1_DM_2 0x3002 | |
| 471 | #define WM2200_DSP1_DM_3 0x3003 | |
| 472 | #define WM2200_DSP1_DM_2044 0x37FC | |
| 473 | #define WM2200_DSP1_DM_2045 0x37FD | |
| 474 | #define WM2200_DSP1_DM_2046 0x37FE | |
| 475 | #define WM2200_DSP1_DM_2047 0x37FF | |
| 476 | #define WM2200_DSP1_PM_0 0x3800 | |
| 477 | #define WM2200_DSP1_PM_1 0x3801 | |
| 478 | #define WM2200_DSP1_PM_2 0x3802 | |
| 479 | #define WM2200_DSP1_PM_3 0x3803 | |
| 480 | #define WM2200_DSP1_PM_4 0x3804 | |
| 481 | #define WM2200_DSP1_PM_5 0x3805 | |
| 482 | #define WM2200_DSP1_PM_762 0x3AFA | |
| 483 | #define WM2200_DSP1_PM_763 0x3AFB | |
| 484 | #define WM2200_DSP1_PM_764 0x3AFC | |
| 485 | #define WM2200_DSP1_PM_765 0x3AFD | |
| 486 | #define WM2200_DSP1_PM_766 0x3AFE | |
| 487 | #define WM2200_DSP1_PM_767 0x3AFF | |
| 488 | #define WM2200_DSP1_ZM_0 0x3C00 | |
| 489 | #define WM2200_DSP1_ZM_1 0x3C01 | |
| 490 | #define WM2200_DSP1_ZM_2 0x3C02 | |
| 491 | #define WM2200_DSP1_ZM_3 0x3C03 | |
| 492 | #define WM2200_DSP1_ZM_1020 0x3FFC | |
| 493 | #define WM2200_DSP1_ZM_1021 0x3FFD | |
| 494 | #define WM2200_DSP1_ZM_1022 0x3FFE | |
| 495 | #define WM2200_DSP1_ZM_1023 0x3FFF | |
| 496 | #define WM2200_DSP2_DM_0 0x4000 | |
| 497 | #define WM2200_DSP2_DM_1 0x4001 | |
| 498 | #define WM2200_DSP2_DM_2 0x4002 | |
| 499 | #define WM2200_DSP2_DM_3 0x4003 | |
| 500 | #define WM2200_DSP2_DM_2044 0x47FC | |
| 501 | #define WM2200_DSP2_DM_2045 0x47FD | |
| 502 | #define WM2200_DSP2_DM_2046 0x47FE | |
| 503 | #define WM2200_DSP2_DM_2047 0x47FF | |
| 504 | #define WM2200_DSP2_PM_0 0x4800 | |
| 505 | #define WM2200_DSP2_PM_1 0x4801 | |
| 506 | #define WM2200_DSP2_PM_2 0x4802 | |
| 507 | #define WM2200_DSP2_PM_3 0x4803 | |
| 508 | #define WM2200_DSP2_PM_4 0x4804 | |
| 509 | #define WM2200_DSP2_PM_5 0x4805 | |
| 510 | #define WM2200_DSP2_PM_762 0x4AFA | |
| 511 | #define WM2200_DSP2_PM_763 0x4AFB | |
| 512 | #define WM2200_DSP2_PM_764 0x4AFC | |
| 513 | #define WM2200_DSP2_PM_765 0x4AFD | |
| 514 | #define WM2200_DSP2_PM_766 0x4AFE | |
| 515 | #define WM2200_DSP2_PM_767 0x4AFF | |
| 516 | #define WM2200_DSP2_ZM_0 0x4C00 | |
| 517 | #define WM2200_DSP2_ZM_1 0x4C01 | |
| 518 | #define WM2200_DSP2_ZM_2 0x4C02 | |
| 519 | #define WM2200_DSP2_ZM_3 0x4C03 | |
| 520 | #define WM2200_DSP2_ZM_1020 0x4FFC | |
| 521 | #define WM2200_DSP2_ZM_1021 0x4FFD | |
| 522 | #define WM2200_DSP2_ZM_1022 0x4FFE | |
| 523 | #define WM2200_DSP2_ZM_1023 0x4FFF | |
| 524 | ||
| 525 | #define WM2200_REGISTER_COUNT 494 | |
| 526 | #define WM2200_MAX_REGISTER 0x4FFF | |
| 527 | ||
| 528 | /* | |
| 529 | * Field Definitions. | |
| 530 | */ | |
| 531 | ||
| 532 | /* | |
| 533 | * R0 (0x00) - software reset | |
| 534 | */ | |
| 535 | #define WM2200_SW_RESET_CHIP_ID1_MASK 0xFFFF /* SW_RESET_CHIP_ID1 - [15:0] */ | |
| 536 | #define WM2200_SW_RESET_CHIP_ID1_SHIFT 0 /* SW_RESET_CHIP_ID1 - [15:0] */ | |
| 537 | #define WM2200_SW_RESET_CHIP_ID1_WIDTH 16 /* SW_RESET_CHIP_ID1 - [15:0] */ | |
| 538 | ||
| 539 | /* | |
| 540 | * R1 (0x01) - Device Revision | |
| 541 | */ | |
| 542 | #define WM2200_DEVICE_REVISION_MASK 0x000F /* DEVICE_REVISION - [3:0] */ | |
| 543 | #define WM2200_DEVICE_REVISION_SHIFT 0 /* DEVICE_REVISION - [3:0] */ | |
| 544 | #define WM2200_DEVICE_REVISION_WIDTH 4 /* DEVICE_REVISION - [3:0] */ | |
| 545 | ||
| 546 | /* | |
| 547 | * R11 (0x0B) - Tone Generator 1 | |
| 548 | */ | |
| 549 | #define WM2200_TONE_ENA 0x0001 /* TONE_ENA */ | |
| 550 | #define WM2200_TONE_ENA_MASK 0x0001 /* TONE_ENA */ | |
| 551 | #define WM2200_TONE_ENA_SHIFT 0 /* TONE_ENA */ | |
| 552 | #define WM2200_TONE_ENA_WIDTH 1 /* TONE_ENA */ | |
| 553 | ||
| 554 | /* | |
| 555 | * R258 (0x102) - Clocking 3 | |
| 556 | */ | |
| 557 | #define WM2200_SYSCLK_FREQ_MASK 0x0700 /* SYSCLK_FREQ - [10:8] */ | |
| 558 | #define WM2200_SYSCLK_FREQ_SHIFT 8 /* SYSCLK_FREQ - [10:8] */ | |
| 559 | #define WM2200_SYSCLK_FREQ_WIDTH 3 /* SYSCLK_FREQ - [10:8] */ | |
| 560 | #define WM2200_SYSCLK_ENA 0x0040 /* SYSCLK_ENA */ | |
| 561 | #define WM2200_SYSCLK_ENA_MASK 0x0040 /* SYSCLK_ENA */ | |
| 562 | #define WM2200_SYSCLK_ENA_SHIFT 6 /* SYSCLK_ENA */ | |
| 563 | #define WM2200_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */ | |
| 564 | #define WM2200_SYSCLK_SRC_MASK 0x000F /* SYSCLK_SRC - [3:0] */ | |
| 565 | #define WM2200_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC - [3:0] */ | |
| 566 | #define WM2200_SYSCLK_SRC_WIDTH 4 /* SYSCLK_SRC - [3:0] */ | |
| 567 | ||
| 568 | /* | |
| 569 | * R259 (0x103) - Clocking 4 | |
| 570 | */ | |
| 571 | #define WM2200_SAMPLE_RATE_1_MASK 0x001F /* SAMPLE_RATE_1 - [4:0] */ | |
| 572 | #define WM2200_SAMPLE_RATE_1_SHIFT 0 /* SAMPLE_RATE_1 - [4:0] */ | |
| 573 | #define WM2200_SAMPLE_RATE_1_WIDTH 5 /* SAMPLE_RATE_1 - [4:0] */ | |
| 574 | ||
| 575 | /* | |
| 576 | * R273 (0x111) - FLL Control 1 | |
| 577 | */ | |
| 578 | #define WM2200_FLL_ENA 0x0001 /* FLL_ENA */ | |
| 579 | #define WM2200_FLL_ENA_MASK 0x0001 /* FLL_ENA */ | |
| 580 | #define WM2200_FLL_ENA_SHIFT 0 /* FLL_ENA */ | |
| 581 | #define WM2200_FLL_ENA_WIDTH 1 /* FLL_ENA */ | |
| 582 | ||
| 583 | /* | |
| 584 | * R274 (0x112) - FLL Control 2 | |
| 585 | */ | |
| 586 | #define WM2200_FLL_OUTDIV_MASK 0x3F00 /* FLL_OUTDIV - [13:8] */ | |
| 587 | #define WM2200_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [13:8] */ | |
| 588 | #define WM2200_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [13:8] */ | |
| 589 | #define WM2200_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */ | |
| 590 | #define WM2200_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */ | |
| 591 | #define WM2200_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */ | |
| 592 | ||
| 593 | /* | |
| 594 | * R275 (0x113) - FLL Control 3 | |
| 595 | */ | |
| 596 | #define WM2200_FLL_FRACN_ENA 0x0001 /* FLL_FRACN_ENA */ | |
| 597 | #define WM2200_FLL_FRACN_ENA_MASK 0x0001 /* FLL_FRACN_ENA */ | |
| 598 | #define WM2200_FLL_FRACN_ENA_SHIFT 0 /* FLL_FRACN_ENA */ | |
| 599 | #define WM2200_FLL_FRACN_ENA_WIDTH 1 /* FLL_FRACN_ENA */ | |
| 600 | ||
| 601 | /* | |
| 602 | * R276 (0x114) - FLL Control 4 | |
| 603 | */ | |
| 604 | #define WM2200_FLL_THETA_MASK 0xFFFF /* FLL_THETA - [15:0] */ | |
| 605 | #define WM2200_FLL_THETA_SHIFT 0 /* FLL_THETA - [15:0] */ | |
| 606 | #define WM2200_FLL_THETA_WIDTH 16 /* FLL_THETA - [15:0] */ | |
| 607 | ||
| 608 | /* | |
| 609 | * R278 (0x116) - FLL Control 6 | |
| 610 | */ | |
| 611 | #define WM2200_FLL_N_MASK 0x03FF /* FLL_N - [9:0] */ | |
| 612 | #define WM2200_FLL_N_SHIFT 0 /* FLL_N - [9:0] */ | |
| 613 | #define WM2200_FLL_N_WIDTH 10 /* FLL_N - [9:0] */ | |
| 614 | ||
| 615 | /* | |
| 616 | * R279 (0x117) - FLL Control 7 | |
| 617 | */ | |
| 618 | #define WM2200_FLL_CLK_REF_DIV_MASK 0x0030 /* FLL_CLK_REF_DIV - [5:4] */ | |
| 619 | #define WM2200_FLL_CLK_REF_DIV_SHIFT 4 /* FLL_CLK_REF_DIV - [5:4] */ | |
| 620 | #define WM2200_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [5:4] */ | |
| 621 | #define WM2200_FLL_CLK_REF_SRC_MASK 0x0003 /* FLL_CLK_REF_SRC - [1:0] */ | |
| 622 | #define WM2200_FLL_CLK_REF_SRC_SHIFT 0 /* FLL_CLK_REF_SRC - [1:0] */ | |
| 623 | #define WM2200_FLL_CLK_REF_SRC_WIDTH 2 /* FLL_CLK_REF_SRC - [1:0] */ | |
| 624 | ||
| 625 | /* | |
| 626 | * R281 (0x119) - FLL EFS 1 | |
| 627 | */ | |
| 628 | #define WM2200_FLL_LAMBDA_MASK 0xFFFF /* FLL_LAMBDA - [15:0] */ | |
| 629 | #define WM2200_FLL_LAMBDA_SHIFT 0 /* FLL_LAMBDA - [15:0] */ | |
| 630 | #define WM2200_FLL_LAMBDA_WIDTH 16 /* FLL_LAMBDA - [15:0] */ | |
| 631 | ||
| 632 | /* | |
| 633 | * R282 (0x11A) - FLL EFS 2 | |
| 634 | */ | |
| 635 | #define WM2200_FLL_EFS_ENA 0x0001 /* FLL_EFS_ENA */ | |
| 636 | #define WM2200_FLL_EFS_ENA_MASK 0x0001 /* FLL_EFS_ENA */ | |
| 637 | #define WM2200_FLL_EFS_ENA_SHIFT 0 /* FLL_EFS_ENA */ | |
| 638 | #define WM2200_FLL_EFS_ENA_WIDTH 1 /* FLL_EFS_ENA */ | |
| 639 | ||
| 640 | /* | |
| 641 | * R512 (0x200) - Mic Charge Pump 1 | |
| 642 | */ | |
| 643 | #define WM2200_CPMIC_BYPASS_MODE 0x0020 /* CPMIC_BYPASS_MODE */ | |
| 644 | #define WM2200_CPMIC_BYPASS_MODE_MASK 0x0020 /* CPMIC_BYPASS_MODE */ | |
| 645 | #define WM2200_CPMIC_BYPASS_MODE_SHIFT 5 /* CPMIC_BYPASS_MODE */ | |
| 646 | #define WM2200_CPMIC_BYPASS_MODE_WIDTH 1 /* CPMIC_BYPASS_MODE */ | |
| 647 | #define WM2200_CPMIC_ENA 0x0001 /* CPMIC_ENA */ | |
| 648 | #define WM2200_CPMIC_ENA_MASK 0x0001 /* CPMIC_ENA */ | |
| 649 | #define WM2200_CPMIC_ENA_SHIFT 0 /* CPMIC_ENA */ | |
| 650 | #define WM2200_CPMIC_ENA_WIDTH 1 /* CPMIC_ENA */ | |
| 651 | ||
| 652 | /* | |
| 653 | * R513 (0x201) - Mic Charge Pump 2 | |
| 654 | */ | |
| 655 | #define WM2200_CPMIC_LDO_VSEL_OVERRIDE_MASK 0xF800 /* CPMIC_LDO_VSEL_OVERRIDE - [15:11] */ | |
| 656 | #define WM2200_CPMIC_LDO_VSEL_OVERRIDE_SHIFT 11 /* CPMIC_LDO_VSEL_OVERRIDE - [15:11] */ | |
| 657 | #define WM2200_CPMIC_LDO_VSEL_OVERRIDE_WIDTH 5 /* CPMIC_LDO_VSEL_OVERRIDE - [15:11] */ | |
| 658 | ||
| 659 | /* | |
| 660 | * R514 (0x202) - DM Charge Pump 1 | |
| 661 | */ | |
| 662 | #define WM2200_CPDM_ENA 0x0001 /* CPDM_ENA */ | |
| 663 | #define WM2200_CPDM_ENA_MASK 0x0001 /* CPDM_ENA */ | |
| 664 | #define WM2200_CPDM_ENA_SHIFT 0 /* CPDM_ENA */ | |
| 665 | #define WM2200_CPDM_ENA_WIDTH 1 /* CPDM_ENA */ | |
| 666 | ||
| 667 | /* | |
| 668 | * R524 (0x20C) - Mic Bias Ctrl 1 | |
| 669 | */ | |
| 670 | #define WM2200_MICB1_DISCH 0x0040 /* MICB1_DISCH */ | |
| 671 | #define WM2200_MICB1_DISCH_MASK 0x0040 /* MICB1_DISCH */ | |
| 672 | #define WM2200_MICB1_DISCH_SHIFT 6 /* MICB1_DISCH */ | |
| 673 | #define WM2200_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */ | |
| 674 | #define WM2200_MICB1_RATE 0x0020 /* MICB1_RATE */ | |
| 675 | #define WM2200_MICB1_RATE_MASK 0x0020 /* MICB1_RATE */ | |
| 676 | #define WM2200_MICB1_RATE_SHIFT 5 /* MICB1_RATE */ | |
| 677 | #define WM2200_MICB1_RATE_WIDTH 1 /* MICB1_RATE */ | |
| 678 | #define WM2200_MICB1_LVL_MASK 0x001C /* MICB1_LVL - [4:2] */ | |
| 679 | #define WM2200_MICB1_LVL_SHIFT 2 /* MICB1_LVL - [4:2] */ | |
| 680 | #define WM2200_MICB1_LVL_WIDTH 3 /* MICB1_LVL - [4:2] */ | |
| 681 | #define WM2200_MICB1_MODE 0x0002 /* MICB1_MODE */ | |
| 682 | #define WM2200_MICB1_MODE_MASK 0x0002 /* MICB1_MODE */ | |
| 683 | #define WM2200_MICB1_MODE_SHIFT 1 /* MICB1_MODE */ | |
| 684 | #define WM2200_MICB1_MODE_WIDTH 1 /* MICB1_MODE */ | |
| 685 | #define WM2200_MICB1_ENA 0x0001 /* MICB1_ENA */ | |
| 686 | #define WM2200_MICB1_ENA_MASK 0x0001 /* MICB1_ENA */ | |
| 687 | #define WM2200_MICB1_ENA_SHIFT 0 /* MICB1_ENA */ | |
| 688 | #define WM2200_MICB1_ENA_WIDTH 1 /* MICB1_ENA */ | |
| 689 | ||
| 690 | /* | |
| 691 | * R525 (0x20D) - Mic Bias Ctrl 2 | |
| 692 | */ | |
| 693 | #define WM2200_MICB2_DISCH 0x0040 /* MICB2_DISCH */ | |
| 694 | #define WM2200_MICB2_DISCH_MASK 0x0040 /* MICB2_DISCH */ | |
| 695 | #define WM2200_MICB2_DISCH_SHIFT 6 /* MICB2_DISCH */ | |
| 696 | #define WM2200_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */ | |
| 697 | #define WM2200_MICB2_RATE 0x0020 /* MICB2_RATE */ | |
| 698 | #define WM2200_MICB2_RATE_MASK 0x0020 /* MICB2_RATE */ | |
| 699 | #define WM2200_MICB2_RATE_SHIFT 5 /* MICB2_RATE */ | |
| 700 | #define WM2200_MICB2_RATE_WIDTH 1 /* MICB2_RATE */ | |
| 701 | #define WM2200_MICB2_LVL_MASK 0x001C /* MICB2_LVL - [4:2] */ | |
| 702 | #define WM2200_MICB2_LVL_SHIFT 2 /* MICB2_LVL - [4:2] */ | |
| 703 | #define WM2200_MICB2_LVL_WIDTH 3 /* MICB2_LVL - [4:2] */ | |
| 704 | #define WM2200_MICB2_MODE 0x0002 /* MICB2_MODE */ | |
| 705 | #define WM2200_MICB2_MODE_MASK 0x0002 /* MICB2_MODE */ | |
| 706 | #define WM2200_MICB2_MODE_SHIFT 1 /* MICB2_MODE */ | |
| 707 | #define WM2200_MICB2_MODE_WIDTH 1 /* MICB2_MODE */ | |
| 708 | #define WM2200_MICB2_ENA 0x0001 /* MICB2_ENA */ | |
| 709 | #define WM2200_MICB2_ENA_MASK 0x0001 /* MICB2_ENA */ | |
| 710 | #define WM2200_MICB2_ENA_SHIFT 0 /* MICB2_ENA */ | |
| 711 | #define WM2200_MICB2_ENA_WIDTH 1 /* MICB2_ENA */ | |
| 712 | ||
| 713 | /* | |
| 714 | * R527 (0x20F) - Ear Piece Ctrl 1 | |
| 715 | */ | |
| 716 | #define WM2200_EPD_LP_ENA 0x4000 /* EPD_LP_ENA */ | |
| 717 | #define WM2200_EPD_LP_ENA_MASK 0x4000 /* EPD_LP_ENA */ | |
| 718 | #define WM2200_EPD_LP_ENA_SHIFT 14 /* EPD_LP_ENA */ | |
| 719 | #define WM2200_EPD_LP_ENA_WIDTH 1 /* EPD_LP_ENA */ | |
| 720 | #define WM2200_EPD_OUTP_LP_ENA 0x2000 /* EPD_OUTP_LP_ENA */ | |
| 721 | #define WM2200_EPD_OUTP_LP_ENA_MASK 0x2000 /* EPD_OUTP_LP_ENA */ | |
| 722 | #define WM2200_EPD_OUTP_LP_ENA_SHIFT 13 /* EPD_OUTP_LP_ENA */ | |
| 723 | #define WM2200_EPD_OUTP_LP_ENA_WIDTH 1 /* EPD_OUTP_LP_ENA */ | |
| 724 | #define WM2200_EPD_RMV_SHRT_LP 0x1000 /* EPD_RMV_SHRT_LP */ | |
| 725 | #define WM2200_EPD_RMV_SHRT_LP_MASK 0x1000 /* EPD_RMV_SHRT_LP */ | |
| 726 | #define WM2200_EPD_RMV_SHRT_LP_SHIFT 12 /* EPD_RMV_SHRT_LP */ | |
| 727 | #define WM2200_EPD_RMV_SHRT_LP_WIDTH 1 /* EPD_RMV_SHRT_LP */ | |
| 728 | #define WM2200_EPD_LN_ENA 0x0800 /* EPD_LN_ENA */ | |
| 729 | #define WM2200_EPD_LN_ENA_MASK 0x0800 /* EPD_LN_ENA */ | |
| 730 | #define WM2200_EPD_LN_ENA_SHIFT 11 /* EPD_LN_ENA */ | |
| 731 | #define WM2200_EPD_LN_ENA_WIDTH 1 /* EPD_LN_ENA */ | |
| 732 | #define WM2200_EPD_OUTP_LN_ENA 0x0400 /* EPD_OUTP_LN_ENA */ | |
| 733 | #define WM2200_EPD_OUTP_LN_ENA_MASK 0x0400 /* EPD_OUTP_LN_ENA */ | |
| 734 | #define WM2200_EPD_OUTP_LN_ENA_SHIFT 10 /* EPD_OUTP_LN_ENA */ | |
| 735 | #define WM2200_EPD_OUTP_LN_ENA_WIDTH 1 /* EPD_OUTP_LN_ENA */ | |
| 736 | #define WM2200_EPD_RMV_SHRT_LN 0x0200 /* EPD_RMV_SHRT_LN */ | |
| 737 | #define WM2200_EPD_RMV_SHRT_LN_MASK 0x0200 /* EPD_RMV_SHRT_LN */ | |
| 738 | #define WM2200_EPD_RMV_SHRT_LN_SHIFT 9 /* EPD_RMV_SHRT_LN */ | |
| 739 | #define WM2200_EPD_RMV_SHRT_LN_WIDTH 1 /* EPD_RMV_SHRT_LN */ | |
| 740 | ||
| 741 | /* | |
| 742 | * R528 (0x210) - Ear Piece Ctrl 2 | |
| 743 | */ | |
| 744 | #define WM2200_EPD_RP_ENA 0x4000 /* EPD_RP_ENA */ | |
| 745 | #define WM2200_EPD_RP_ENA_MASK 0x4000 /* EPD_RP_ENA */ | |
| 746 | #define WM2200_EPD_RP_ENA_SHIFT 14 /* EPD_RP_ENA */ | |
| 747 | #define WM2200_EPD_RP_ENA_WIDTH 1 /* EPD_RP_ENA */ | |
| 748 | #define WM2200_EPD_OUTP_RP_ENA 0x2000 /* EPD_OUTP_RP_ENA */ | |
| 749 | #define WM2200_EPD_OUTP_RP_ENA_MASK 0x2000 /* EPD_OUTP_RP_ENA */ | |
| 750 | #define WM2200_EPD_OUTP_RP_ENA_SHIFT 13 /* EPD_OUTP_RP_ENA */ | |
| 751 | #define WM2200_EPD_OUTP_RP_ENA_WIDTH 1 /* EPD_OUTP_RP_ENA */ | |
| 752 | #define WM2200_EPD_RMV_SHRT_RP 0x1000 /* EPD_RMV_SHRT_RP */ | |
| 753 | #define WM2200_EPD_RMV_SHRT_RP_MASK 0x1000 /* EPD_RMV_SHRT_RP */ | |
| 754 | #define WM2200_EPD_RMV_SHRT_RP_SHIFT 12 /* EPD_RMV_SHRT_RP */ | |
| 755 | #define WM2200_EPD_RMV_SHRT_RP_WIDTH 1 /* EPD_RMV_SHRT_RP */ | |
| 756 | #define WM2200_EPD_RN_ENA 0x0800 /* EPD_RN_ENA */ | |
| 757 | #define WM2200_EPD_RN_ENA_MASK 0x0800 /* EPD_RN_ENA */ | |
| 758 | #define WM2200_EPD_RN_ENA_SHIFT 11 /* EPD_RN_ENA */ | |
| 759 | #define WM2200_EPD_RN_ENA_WIDTH 1 /* EPD_RN_ENA */ | |
| 760 | #define WM2200_EPD_OUTP_RN_ENA 0x0400 /* EPD_OUTP_RN_ENA */ | |
| 761 | #define WM2200_EPD_OUTP_RN_ENA_MASK 0x0400 /* EPD_OUTP_RN_ENA */ | |
| 762 | #define WM2200_EPD_OUTP_RN_ENA_SHIFT 10 /* EPD_OUTP_RN_ENA */ | |
| 763 | #define WM2200_EPD_OUTP_RN_ENA_WIDTH 1 /* EPD_OUTP_RN_ENA */ | |
| 764 | #define WM2200_EPD_RMV_SHRT_RN 0x0200 /* EPD_RMV_SHRT_RN */ | |
| 765 | #define WM2200_EPD_RMV_SHRT_RN_MASK 0x0200 /* EPD_RMV_SHRT_RN */ | |
| 766 | #define WM2200_EPD_RMV_SHRT_RN_SHIFT 9 /* EPD_RMV_SHRT_RN */ | |
| 767 | #define WM2200_EPD_RMV_SHRT_RN_WIDTH 1 /* EPD_RMV_SHRT_RN */ | |
| 768 | ||
| 769 | /* | |
| 770 | * R769 (0x301) - Input Enables | |
| 771 | */ | |
| 772 | #define WM2200_IN3L_ENA 0x0020 /* IN3L_ENA */ | |
| 773 | #define WM2200_IN3L_ENA_MASK 0x0020 /* IN3L_ENA */ | |
| 774 | #define WM2200_IN3L_ENA_SHIFT 5 /* IN3L_ENA */ | |
| 775 | #define WM2200_IN3L_ENA_WIDTH 1 /* IN3L_ENA */ | |
| 776 | #define WM2200_IN3R_ENA 0x0010 /* IN3R_ENA */ | |
| 777 | #define WM2200_IN3R_ENA_MASK 0x0010 /* IN3R_ENA */ | |
| 778 | #define WM2200_IN3R_ENA_SHIFT 4 /* IN3R_ENA */ | |
| 779 | #define WM2200_IN3R_ENA_WIDTH 1 /* IN3R_ENA */ | |
| 780 | #define WM2200_IN2L_ENA 0x0008 /* IN2L_ENA */ | |
| 781 | #define WM2200_IN2L_ENA_MASK 0x0008 /* IN2L_ENA */ | |
| 782 | #define WM2200_IN2L_ENA_SHIFT 3 /* IN2L_ENA */ | |
| 783 | #define WM2200_IN2L_ENA_WIDTH 1 /* IN2L_ENA */ | |
| 784 | #define WM2200_IN2R_ENA 0x0004 /* IN2R_ENA */ | |
| 785 | #define WM2200_IN2R_ENA_MASK 0x0004 /* IN2R_ENA */ | |
| 786 | #define WM2200_IN2R_ENA_SHIFT 2 /* IN2R_ENA */ | |
| 787 | #define WM2200_IN2R_ENA_WIDTH 1 /* IN2R_ENA */ | |
| 788 | #define WM2200_IN1L_ENA 0x0002 /* IN1L_ENA */ | |
| 789 | #define WM2200_IN1L_ENA_MASK 0x0002 /* IN1L_ENA */ | |
| 790 | #define WM2200_IN1L_ENA_SHIFT 1 /* IN1L_ENA */ | |
| 791 | #define WM2200_IN1L_ENA_WIDTH 1 /* IN1L_ENA */ | |
| 792 | #define WM2200_IN1R_ENA 0x0001 /* IN1R_ENA */ | |
| 793 | #define WM2200_IN1R_ENA_MASK 0x0001 /* IN1R_ENA */ | |
| 794 | #define WM2200_IN1R_ENA_SHIFT 0 /* IN1R_ENA */ | |
| 795 | #define WM2200_IN1R_ENA_WIDTH 1 /* IN1R_ENA */ | |
| 796 | ||
| 797 | /* | |
| 798 | * R770 (0x302) - IN1L Control | |
| 799 | */ | |
| 800 | #define WM2200_IN1_OSR 0x2000 /* IN1_OSR */ | |
| 801 | #define WM2200_IN1_OSR_MASK 0x2000 /* IN1_OSR */ | |
| 802 | #define WM2200_IN1_OSR_SHIFT 13 /* IN1_OSR */ | |
| 803 | #define WM2200_IN1_OSR_WIDTH 1 /* IN1_OSR */ | |
| 804 | #define WM2200_IN1_DMIC_SUP_MASK 0x1800 /* IN1_DMIC_SUP - [12:11] */ | |
| 805 | #define WM2200_IN1_DMIC_SUP_SHIFT 11 /* IN1_DMIC_SUP - [12:11] */ | |
| 806 | #define WM2200_IN1_DMIC_SUP_WIDTH 2 /* IN1_DMIC_SUP - [12:11] */ | |
| 807 | #define WM2200_IN1_MODE_MASK 0x0600 /* IN1_MODE - [10:9] */ | |
| 808 | #define WM2200_IN1_MODE_SHIFT 9 /* IN1_MODE - [10:9] */ | |
| 809 | #define WM2200_IN1_MODE_WIDTH 2 /* IN1_MODE - [10:9] */ | |
| 810 | #define WM2200_IN1L_PGA_VOL_MASK 0x00FE /* IN1L_PGA_VOL - [7:1] */ | |
| 811 | #define WM2200_IN1L_PGA_VOL_SHIFT 1 /* IN1L_PGA_VOL - [7:1] */ | |
| 812 | #define WM2200_IN1L_PGA_VOL_WIDTH 7 /* IN1L_PGA_VOL - [7:1] */ | |
| 813 | ||
| 814 | /* | |
| 815 | * R771 (0x303) - IN1R Control | |
| 816 | */ | |
| 817 | #define WM2200_IN1R_PGA_VOL_MASK 0x00FE /* IN1R_PGA_VOL - [7:1] */ | |
| 818 | #define WM2200_IN1R_PGA_VOL_SHIFT 1 /* IN1R_PGA_VOL - [7:1] */ | |
| 819 | #define WM2200_IN1R_PGA_VOL_WIDTH 7 /* IN1R_PGA_VOL - [7:1] */ | |
| 820 | ||
| 821 | /* | |
| 822 | * R772 (0x304) - IN2L Control | |
| 823 | */ | |
| 824 | #define WM2200_IN2_OSR 0x2000 /* IN2_OSR */ | |
| 825 | #define WM2200_IN2_OSR_MASK 0x2000 /* IN2_OSR */ | |
| 826 | #define WM2200_IN2_OSR_SHIFT 13 /* IN2_OSR */ | |
| 827 | #define WM2200_IN2_OSR_WIDTH 1 /* IN2_OSR */ | |
| 828 | #define WM2200_IN2_DMIC_SUP_MASK 0x1800 /* IN2_DMIC_SUP - [12:11] */ | |
| 829 | #define WM2200_IN2_DMIC_SUP_SHIFT 11 /* IN2_DMIC_SUP - [12:11] */ | |
| 830 | #define WM2200_IN2_DMIC_SUP_WIDTH 2 /* IN2_DMIC_SUP - [12:11] */ | |
| 831 | #define WM2200_IN2_MODE_MASK 0x0600 /* IN2_MODE - [10:9] */ | |
| 832 | #define WM2200_IN2_MODE_SHIFT 9 /* IN2_MODE - [10:9] */ | |
| 833 | #define WM2200_IN2_MODE_WIDTH 2 /* IN2_MODE - [10:9] */ | |
| 834 | #define WM2200_IN2L_PGA_VOL_MASK 0x00FE /* IN2L_PGA_VOL - [7:1] */ | |
| 835 | #define WM2200_IN2L_PGA_VOL_SHIFT 1 /* IN2L_PGA_VOL - [7:1] */ | |
| 836 | #define WM2200_IN2L_PGA_VOL_WIDTH 7 /* IN2L_PGA_VOL - [7:1] */ | |
| 837 | ||
| 838 | /* | |
| 839 | * R773 (0x305) - IN2R Control | |
| 840 | */ | |
| 841 | #define WM2200_IN2R_PGA_VOL_MASK 0x00FE /* IN2R_PGA_VOL - [7:1] */ | |
| 842 | #define WM2200_IN2R_PGA_VOL_SHIFT 1 /* IN2R_PGA_VOL - [7:1] */ | |
| 843 | #define WM2200_IN2R_PGA_VOL_WIDTH 7 /* IN2R_PGA_VOL - [7:1] */ | |
| 844 | ||
| 845 | /* | |
| 846 | * R774 (0x306) - IN3L Control | |
| 847 | */ | |
| 848 | #define WM2200_IN3_OSR 0x2000 /* IN3_OSR */ | |
| 849 | #define WM2200_IN3_OSR_MASK 0x2000 /* IN3_OSR */ | |
| 850 | #define WM2200_IN3_OSR_SHIFT 13 /* IN3_OSR */ | |
| 851 | #define WM2200_IN3_OSR_WIDTH 1 /* IN3_OSR */ | |
| 852 | #define WM2200_IN3_DMIC_SUP_MASK 0x1800 /* IN3_DMIC_SUP - [12:11] */ | |
| 853 | #define WM2200_IN3_DMIC_SUP_SHIFT 11 /* IN3_DMIC_SUP - [12:11] */ | |
| 854 | #define WM2200_IN3_DMIC_SUP_WIDTH 2 /* IN3_DMIC_SUP - [12:11] */ | |
| 855 | #define WM2200_IN3_MODE_MASK 0x0600 /* IN3_MODE - [10:9] */ | |
| 856 | #define WM2200_IN3_MODE_SHIFT 9 /* IN3_MODE - [10:9] */ | |
| 857 | #define WM2200_IN3_MODE_WIDTH 2 /* IN3_MODE - [10:9] */ | |
| 858 | #define WM2200_IN3L_PGA_VOL_MASK 0x00FE /* IN3L_PGA_VOL - [7:1] */ | |
| 859 | #define WM2200_IN3L_PGA_VOL_SHIFT 1 /* IN3L_PGA_VOL - [7:1] */ | |
| 860 | #define WM2200_IN3L_PGA_VOL_WIDTH 7 /* IN3L_PGA_VOL - [7:1] */ | |
| 861 | ||
| 862 | /* | |
| 863 | * R775 (0x307) - IN3R Control | |
| 864 | */ | |
| 865 | #define WM2200_IN3R_PGA_VOL_MASK 0x00FE /* IN3R_PGA_VOL - [7:1] */ | |
| 866 | #define WM2200_IN3R_PGA_VOL_SHIFT 1 /* IN3R_PGA_VOL - [7:1] */ | |
| 867 | #define WM2200_IN3R_PGA_VOL_WIDTH 7 /* IN3R_PGA_VOL - [7:1] */ | |
| 868 | ||
| 869 | /* | |
| 870 | * R778 (0x30A) - RXANC_SRC | |
| 871 | */ | |
| 872 | #define WM2200_IN_RXANC_SEL_MASK 0x0007 /* IN_RXANC_SEL - [2:0] */ | |
| 873 | #define WM2200_IN_RXANC_SEL_SHIFT 0 /* IN_RXANC_SEL - [2:0] */ | |
| 874 | #define WM2200_IN_RXANC_SEL_WIDTH 3 /* IN_RXANC_SEL - [2:0] */ | |
| 875 | ||
| 876 | /* | |
| 877 | * R779 (0x30B) - Input Volume Ramp | |
| 878 | */ | |
| 879 | #define WM2200_IN_VD_RAMP_MASK 0x0070 /* IN_VD_RAMP - [6:4] */ | |
| 880 | #define WM2200_IN_VD_RAMP_SHIFT 4 /* IN_VD_RAMP - [6:4] */ | |
| 881 | #define WM2200_IN_VD_RAMP_WIDTH 3 /* IN_VD_RAMP - [6:4] */ | |
| 882 | #define WM2200_IN_VI_RAMP_MASK 0x0007 /* IN_VI_RAMP - [2:0] */ | |
| 883 | #define WM2200_IN_VI_RAMP_SHIFT 0 /* IN_VI_RAMP - [2:0] */ | |
| 884 | #define WM2200_IN_VI_RAMP_WIDTH 3 /* IN_VI_RAMP - [2:0] */ | |
| 885 | ||
| 886 | /* | |
| 887 | * R780 (0x30C) - ADC Digital Volume 1L | |
| 888 | */ | |
| 889 | #define WM2200_IN_VU 0x0200 /* IN_VU */ | |
| 890 | #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */ | |
| 891 | #define WM2200_IN_VU_SHIFT 9 /* IN_VU */ | |
| 892 | #define WM2200_IN_VU_WIDTH 1 /* IN_VU */ | |
| 893 | #define WM2200_IN1L_MUTE 0x0100 /* IN1L_MUTE */ | |
| 894 | #define WM2200_IN1L_MUTE_MASK 0x0100 /* IN1L_MUTE */ | |
| 895 | #define WM2200_IN1L_MUTE_SHIFT 8 /* IN1L_MUTE */ | |
| 896 | #define WM2200_IN1L_MUTE_WIDTH 1 /* IN1L_MUTE */ | |
| 897 | #define WM2200_IN1L_DIG_VOL_MASK 0x00FF /* IN1L_DIG_VOL - [7:0] */ | |
| 898 | #define WM2200_IN1L_DIG_VOL_SHIFT 0 /* IN1L_DIG_VOL - [7:0] */ | |
| 899 | #define WM2200_IN1L_DIG_VOL_WIDTH 8 /* IN1L_DIG_VOL - [7:0] */ | |
| 900 | ||
| 901 | /* | |
| 902 | * R781 (0x30D) - ADC Digital Volume 1R | |
| 903 | */ | |
| 904 | #define WM2200_IN_VU 0x0200 /* IN_VU */ | |
| 905 | #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */ | |
| 906 | #define WM2200_IN_VU_SHIFT 9 /* IN_VU */ | |
| 907 | #define WM2200_IN_VU_WIDTH 1 /* IN_VU */ | |
| 908 | #define WM2200_IN1R_MUTE 0x0100 /* IN1R_MUTE */ | |
| 909 | #define WM2200_IN1R_MUTE_MASK 0x0100 /* IN1R_MUTE */ | |
| 910 | #define WM2200_IN1R_MUTE_SHIFT 8 /* IN1R_MUTE */ | |
| 911 | #define WM2200_IN1R_MUTE_WIDTH 1 /* IN1R_MUTE */ | |
| 912 | #define WM2200_IN1R_DIG_VOL_MASK 0x00FF /* IN1R_DIG_VOL - [7:0] */ | |
| 913 | #define WM2200_IN1R_DIG_VOL_SHIFT 0 /* IN1R_DIG_VOL - [7:0] */ | |
| 914 | #define WM2200_IN1R_DIG_VOL_WIDTH 8 /* IN1R_DIG_VOL - [7:0] */ | |
| 915 | ||
| 916 | /* | |
| 917 | * R782 (0x30E) - ADC Digital Volume 2L | |
| 918 | */ | |
| 919 | #define WM2200_IN_VU 0x0200 /* IN_VU */ | |
| 920 | #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */ | |
| 921 | #define WM2200_IN_VU_SHIFT 9 /* IN_VU */ | |
| 922 | #define WM2200_IN_VU_WIDTH 1 /* IN_VU */ | |
| 923 | #define WM2200_IN2L_MUTE 0x0100 /* IN2L_MUTE */ | |
| 924 | #define WM2200_IN2L_MUTE_MASK 0x0100 /* IN2L_MUTE */ | |
| 925 | #define WM2200_IN2L_MUTE_SHIFT 8 /* IN2L_MUTE */ | |
| 926 | #define WM2200_IN2L_MUTE_WIDTH 1 /* IN2L_MUTE */ | |
| 927 | #define WM2200_IN2L_DIG_VOL_MASK 0x00FF /* IN2L_DIG_VOL - [7:0] */ | |
| 928 | #define WM2200_IN2L_DIG_VOL_SHIFT 0 /* IN2L_DIG_VOL - [7:0] */ | |
| 929 | #define WM2200_IN2L_DIG_VOL_WIDTH 8 /* IN2L_DIG_VOL - [7:0] */ | |
| 930 | ||
| 931 | /* | |
| 932 | * R783 (0x30F) - ADC Digital Volume 2R | |
| 933 | */ | |
| 934 | #define WM2200_IN_VU 0x0200 /* IN_VU */ | |
| 935 | #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */ | |
| 936 | #define WM2200_IN_VU_SHIFT 9 /* IN_VU */ | |
| 937 | #define WM2200_IN_VU_WIDTH 1 /* IN_VU */ | |
| 938 | #define WM2200_IN2R_MUTE 0x0100 /* IN2R_MUTE */ | |
| 939 | #define WM2200_IN2R_MUTE_MASK 0x0100 /* IN2R_MUTE */ | |
| 940 | #define WM2200_IN2R_MUTE_SHIFT 8 /* IN2R_MUTE */ | |
| 941 | #define WM2200_IN2R_MUTE_WIDTH 1 /* IN2R_MUTE */ | |
| 942 | #define WM2200_IN2R_DIG_VOL_MASK 0x00FF /* IN2R_DIG_VOL - [7:0] */ | |
| 943 | #define WM2200_IN2R_DIG_VOL_SHIFT 0 /* IN2R_DIG_VOL - [7:0] */ | |
| 944 | #define WM2200_IN2R_DIG_VOL_WIDTH 8 /* IN2R_DIG_VOL - [7:0] */ | |
| 945 | ||
| 946 | /* | |
| 947 | * R784 (0x310) - ADC Digital Volume 3L | |
| 948 | */ | |
| 949 | #define WM2200_IN_VU 0x0200 /* IN_VU */ | |
| 950 | #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */ | |
| 951 | #define WM2200_IN_VU_SHIFT 9 /* IN_VU */ | |
| 952 | #define WM2200_IN_VU_WIDTH 1 /* IN_VU */ | |
| 953 | #define WM2200_IN3L_MUTE 0x0100 /* IN3L_MUTE */ | |
| 954 | #define WM2200_IN3L_MUTE_MASK 0x0100 /* IN3L_MUTE */ | |
| 955 | #define WM2200_IN3L_MUTE_SHIFT 8 /* IN3L_MUTE */ | |
| 956 | #define WM2200_IN3L_MUTE_WIDTH 1 /* IN3L_MUTE */ | |
| 957 | #define WM2200_IN3L_DIG_VOL_MASK 0x00FF /* IN3L_DIG_VOL - [7:0] */ | |
| 958 | #define WM2200_IN3L_DIG_VOL_SHIFT 0 /* IN3L_DIG_VOL - [7:0] */ | |
| 959 | #define WM2200_IN3L_DIG_VOL_WIDTH 8 /* IN3L_DIG_VOL - [7:0] */ | |
| 960 | ||
| 961 | /* | |
| 962 | * R785 (0x311) - ADC Digital Volume 3R | |
| 963 | */ | |
| 964 | #define WM2200_IN_VU 0x0200 /* IN_VU */ | |
| 965 | #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */ | |
| 966 | #define WM2200_IN_VU_SHIFT 9 /* IN_VU */ | |
| 967 | #define WM2200_IN_VU_WIDTH 1 /* IN_VU */ | |
| 968 | #define WM2200_IN3R_MUTE 0x0100 /* IN3R_MUTE */ | |
| 969 | #define WM2200_IN3R_MUTE_MASK 0x0100 /* IN3R_MUTE */ | |
| 970 | #define WM2200_IN3R_MUTE_SHIFT 8 /* IN3R_MUTE */ | |
| 971 | #define WM2200_IN3R_MUTE_WIDTH 1 /* IN3R_MUTE */ | |
| 972 | #define WM2200_IN3R_DIG_VOL_MASK 0x00FF /* IN3R_DIG_VOL - [7:0] */ | |
| 973 | #define WM2200_IN3R_DIG_VOL_SHIFT 0 /* IN3R_DIG_VOL - [7:0] */ | |
| 974 | #define WM2200_IN3R_DIG_VOL_WIDTH 8 /* IN3R_DIG_VOL - [7:0] */ | |
| 975 | ||
| 976 | /* | |
| 977 | * R1024 (0x400) - Output Enables | |
| 978 | */ | |
| 979 | #define WM2200_OUT2L_ENA 0x0008 /* OUT2L_ENA */ | |
| 980 | #define WM2200_OUT2L_ENA_MASK 0x0008 /* OUT2L_ENA */ | |
| 981 | #define WM2200_OUT2L_ENA_SHIFT 3 /* OUT2L_ENA */ | |
| 982 | #define WM2200_OUT2L_ENA_WIDTH 1 /* OUT2L_ENA */ | |
| 983 | #define WM2200_OUT2R_ENA 0x0004 /* OUT2R_ENA */ | |
| 984 | #define WM2200_OUT2R_ENA_MASK 0x0004 /* OUT2R_ENA */ | |
| 985 | #define WM2200_OUT2R_ENA_SHIFT 2 /* OUT2R_ENA */ | |
| 986 | #define WM2200_OUT2R_ENA_WIDTH 1 /* OUT2R_ENA */ | |
| 987 | #define WM2200_OUT1L_ENA 0x0002 /* OUT1L_ENA */ | |
| 988 | #define WM2200_OUT1L_ENA_MASK 0x0002 /* OUT1L_ENA */ | |
| 989 | #define WM2200_OUT1L_ENA_SHIFT 1 /* OUT1L_ENA */ | |
| 990 | #define WM2200_OUT1L_ENA_WIDTH 1 /* OUT1L_ENA */ | |
| 991 | #define WM2200_OUT1R_ENA 0x0001 /* OUT1R_ENA */ | |
| 992 | #define WM2200_OUT1R_ENA_MASK 0x0001 /* OUT1R_ENA */ | |
| 993 | #define WM2200_OUT1R_ENA_SHIFT 0 /* OUT1R_ENA */ | |
| 994 | #define WM2200_OUT1R_ENA_WIDTH 1 /* OUT1R_ENA */ | |
| 995 | ||
| 996 | /* | |
| 997 | * R1025 (0x401) - DAC Volume Limit 1L | |
| 998 | */ | |
| 999 | #define WM2200_OUT1_OSR 0x2000 /* OUT1_OSR */ | |
| 1000 | #define WM2200_OUT1_OSR_MASK 0x2000 /* OUT1_OSR */ | |
| 1001 | #define WM2200_OUT1_OSR_SHIFT 13 /* OUT1_OSR */ | |
| 1002 | #define WM2200_OUT1_OSR_WIDTH 1 /* OUT1_OSR */ | |
| 1003 | #define WM2200_OUT1L_ANC_SRC 0x0800 /* OUT1L_ANC_SRC */ | |
| 1004 | #define WM2200_OUT1L_ANC_SRC_MASK 0x0800 /* OUT1L_ANC_SRC */ | |
| 1005 | #define WM2200_OUT1L_ANC_SRC_SHIFT 11 /* OUT1L_ANC_SRC */ | |
| 1006 | #define WM2200_OUT1L_ANC_SRC_WIDTH 1 /* OUT1L_ANC_SRC */ | |
| 1007 | #define WM2200_OUT1L_PGA_VOL_MASK 0x00FE /* OUT1L_PGA_VOL - [7:1] */ | |
| 1008 | #define WM2200_OUT1L_PGA_VOL_SHIFT 1 /* OUT1L_PGA_VOL - [7:1] */ | |
| 1009 | #define WM2200_OUT1L_PGA_VOL_WIDTH 7 /* OUT1L_PGA_VOL - [7:1] */ | |
| 1010 | ||
| 1011 | /* | |
| 1012 | * R1026 (0x402) - DAC Volume Limit 1R | |
| 1013 | */ | |
| 1014 | #define WM2200_OUT1R_ANC_SRC 0x0800 /* OUT1R_ANC_SRC */ | |
| 1015 | #define WM2200_OUT1R_ANC_SRC_MASK 0x0800 /* OUT1R_ANC_SRC */ | |
| 1016 | #define WM2200_OUT1R_ANC_SRC_SHIFT 11 /* OUT1R_ANC_SRC */ | |
| 1017 | #define WM2200_OUT1R_ANC_SRC_WIDTH 1 /* OUT1R_ANC_SRC */ | |
| 1018 | #define WM2200_OUT1R_PGA_VOL_MASK 0x00FE /* OUT1R_PGA_VOL - [7:1] */ | |
| 1019 | #define WM2200_OUT1R_PGA_VOL_SHIFT 1 /* OUT1R_PGA_VOL - [7:1] */ | |
| 1020 | #define WM2200_OUT1R_PGA_VOL_WIDTH 7 /* OUT1R_PGA_VOL - [7:1] */ | |
| 1021 | ||
| 1022 | /* | |
| 1023 | * R1027 (0x403) - DAC Volume Limit 2L | |
| 1024 | */ | |
| 1025 | #define WM2200_OUT2_OSR 0x2000 /* OUT2_OSR */ | |
| 1026 | #define WM2200_OUT2_OSR_MASK 0x2000 /* OUT2_OSR */ | |
| 1027 | #define WM2200_OUT2_OSR_SHIFT 13 /* OUT2_OSR */ | |
| 1028 | #define WM2200_OUT2_OSR_WIDTH 1 /* OUT2_OSR */ | |
| 1029 | #define WM2200_OUT2L_ANC_SRC 0x0800 /* OUT2L_ANC_SRC */ | |
| 1030 | #define WM2200_OUT2L_ANC_SRC_MASK 0x0800 /* OUT2L_ANC_SRC */ | |
| 1031 | #define WM2200_OUT2L_ANC_SRC_SHIFT 11 /* OUT2L_ANC_SRC */ | |
| 1032 | #define WM2200_OUT2L_ANC_SRC_WIDTH 1 /* OUT2L_ANC_SRC */ | |
| 1033 | ||
| 1034 | /* | |
| 1035 | * R1028 (0x404) - DAC Volume Limit 2R | |
| 1036 | */ | |
| 1037 | #define WM2200_OUT2R_ANC_SRC 0x0800 /* OUT2R_ANC_SRC */ | |
| 1038 | #define WM2200_OUT2R_ANC_SRC_MASK 0x0800 /* OUT2R_ANC_SRC */ | |
| 1039 | #define WM2200_OUT2R_ANC_SRC_SHIFT 11 /* OUT2R_ANC_SRC */ | |
| 1040 | #define WM2200_OUT2R_ANC_SRC_WIDTH 1 /* OUT2R_ANC_SRC */ | |
| 1041 | ||
| 1042 | /* | |
| 1043 | * R1033 (0x409) - DAC AEC Control 1 | |
| 1044 | */ | |
| 1045 | #define WM2200_AEC_LOOPBACK_ENA 0x0004 /* AEC_LOOPBACK_ENA */ | |
| 1046 | #define WM2200_AEC_LOOPBACK_ENA_MASK 0x0004 /* AEC_LOOPBACK_ENA */ | |
| 1047 | #define WM2200_AEC_LOOPBACK_ENA_SHIFT 2 /* AEC_LOOPBACK_ENA */ | |
| 1048 | #define WM2200_AEC_LOOPBACK_ENA_WIDTH 1 /* AEC_LOOPBACK_ENA */ | |
| 1049 | #define WM2200_AEC_LOOPBACK_SRC_MASK 0x0003 /* AEC_LOOPBACK_SRC - [1:0] */ | |
| 1050 | #define WM2200_AEC_LOOPBACK_SRC_SHIFT 0 /* AEC_LOOPBACK_SRC - [1:0] */ | |
| 1051 | #define WM2200_AEC_LOOPBACK_SRC_WIDTH 2 /* AEC_LOOPBACK_SRC - [1:0] */ | |
| 1052 | ||
| 1053 | /* | |
| 1054 | * R1034 (0x40A) - Output Volume Ramp | |
| 1055 | */ | |
| 1056 | #define WM2200_OUT_VD_RAMP_MASK 0x0070 /* OUT_VD_RAMP - [6:4] */ | |
| 1057 | #define WM2200_OUT_VD_RAMP_SHIFT 4 /* OUT_VD_RAMP - [6:4] */ | |
| 1058 | #define WM2200_OUT_VD_RAMP_WIDTH 3 /* OUT_VD_RAMP - [6:4] */ | |
| 1059 | #define WM2200_OUT_VI_RAMP_MASK 0x0007 /* OUT_VI_RAMP - [2:0] */ | |
| 1060 | #define WM2200_OUT_VI_RAMP_SHIFT 0 /* OUT_VI_RAMP - [2:0] */ | |
| 1061 | #define WM2200_OUT_VI_RAMP_WIDTH 3 /* OUT_VI_RAMP - [2:0] */ | |
| 1062 | ||
| 1063 | /* | |
| 1064 | * R1035 (0x40B) - DAC Digital Volume 1L | |
| 1065 | */ | |
| 1066 | #define WM2200_OUT_VU 0x0200 /* OUT_VU */ | |
| 1067 | #define WM2200_OUT_VU_MASK 0x0200 /* OUT_VU */ | |
| 1068 | #define WM2200_OUT_VU_SHIFT 9 /* OUT_VU */ | |
| 1069 | #define WM2200_OUT_VU_WIDTH 1 /* OUT_VU */ | |
| 1070 | #define WM2200_OUT1L_MUTE 0x0100 /* OUT1L_MUTE */ | |
| 1071 | #define WM2200_OUT1L_MUTE_MASK 0x0100 /* OUT1L_MUTE */ | |
| 1072 | #define WM2200_OUT1L_MUTE_SHIFT 8 /* OUT1L_MUTE */ | |
| 1073 | #define WM2200_OUT1L_MUTE_WIDTH 1 /* OUT1L_MUTE */ | |
| 1074 | #define WM2200_OUT1L_VOL_MASK 0x00FF /* OUT1L_VOL - [7:0] */ | |
| 1075 | #define WM2200_OUT1L_VOL_SHIFT 0 /* OUT1L_VOL - [7:0] */ | |
| 1076 | #define WM2200_OUT1L_VOL_WIDTH 8 /* OUT1L_VOL - [7:0] */ | |
| 1077 | ||
| 1078 | /* | |
| 1079 | * R1036 (0x40C) - DAC Digital Volume 1R | |
| 1080 | */ | |
| 1081 | #define WM2200_OUT_VU 0x0200 /* OUT_VU */ | |
| 1082 | #define WM2200_OUT_VU_MASK 0x0200 /* OUT_VU */ | |
| 1083 | #define WM2200_OUT_VU_SHIFT 9 /* OUT_VU */ | |
| 1084 | #define WM2200_OUT_VU_WIDTH 1 /* OUT_VU */ | |
| 1085 | #define WM2200_OUT1R_MUTE 0x0100 /* OUT1R_MUTE */ | |
| 1086 | #define WM2200_OUT1R_MUTE_MASK 0x0100 /* OUT1R_MUTE */ | |
| 1087 | #define WM2200_OUT1R_MUTE_SHIFT 8 /* OUT1R_MUTE */ | |
| 1088 | #define WM2200_OUT1R_MUTE_WIDTH 1 /* OUT1R_MUTE */ | |
| 1089 | #define WM2200_OUT1R_VOL_MASK 0x00FF /* OUT1R_VOL - [7:0] */ | |
| 1090 | #define WM2200_OUT1R_VOL_SHIFT 0 /* OUT1R_VOL - [7:0] */ | |
| 1091 | #define WM2200_OUT1R_VOL_WIDTH 8 /* OUT1R_VOL - [7:0] */ | |
| 1092 | ||
| 1093 | /* | |
| 1094 | * R1037 (0x40D) - DAC Digital Volume 2L | |
| 1095 | */ | |
| 1096 | #define WM2200_OUT_VU 0x0200 /* OUT_VU */ | |
| 1097 | #define WM2200_OUT_VU_MASK 0x0200 /* OUT_VU */ | |
| 1098 | #define WM2200_OUT_VU_SHIFT 9 /* OUT_VU */ | |
| 1099 | #define WM2200_OUT_VU_WIDTH 1 /* OUT_VU */ | |
| 1100 | #define WM2200_OUT2L_MUTE 0x0100 /* OUT2L_MUTE */ | |
| 1101 | #define WM2200_OUT2L_MUTE_MASK 0x0100 /* OUT2L_MUTE */ | |
| 1102 | #define WM2200_OUT2L_MUTE_SHIFT 8 /* OUT2L_MUTE */ | |
| 1103 | #define WM2200_OUT2L_MUTE_WIDTH 1 /* OUT2L_MUTE */ | |
| 1104 | #define WM2200_OUT2L_VOL_MASK 0x00FF /* OUT2L_VOL - [7:0] */ | |
| 1105 | #define WM2200_OUT2L_VOL_SHIFT 0 /* OUT2L_VOL - [7:0] */ | |
| 1106 | #define WM2200_OUT2L_VOL_WIDTH 8 /* OUT2L_VOL - [7:0] */ | |
| 1107 | ||
| 1108 | /* | |
| 1109 | * R1038 (0x40E) - DAC Digital Volume 2R | |
| 1110 | */ | |
| 1111 | #define WM2200_OUT_VU 0x0200 /* OUT_VU */ | |
| 1112 | #define WM2200_OUT_VU_MASK 0x0200 /* OUT_VU */ | |
| 1113 | #define WM2200_OUT_VU_SHIFT 9 /* OUT_VU */ | |
| 1114 | #define WM2200_OUT_VU_WIDTH 1 /* OUT_VU */ | |
| 1115 | #define WM2200_OUT2R_MUTE 0x0100 /* OUT2R_MUTE */ | |
| 1116 | #define WM2200_OUT2R_MUTE_MASK 0x0100 /* OUT2R_MUTE */ | |
| 1117 | #define WM2200_OUT2R_MUTE_SHIFT 8 /* OUT2R_MUTE */ | |
| 1118 | #define WM2200_OUT2R_MUTE_WIDTH 1 /* OUT2R_MUTE */ | |
| 1119 | #define WM2200_OUT2R_VOL_MASK 0x00FF /* OUT2R_VOL - [7:0] */ | |
| 1120 | #define WM2200_OUT2R_VOL_SHIFT 0 /* OUT2R_VOL - [7:0] */ | |
| 1121 | #define WM2200_OUT2R_VOL_WIDTH 8 /* OUT2R_VOL - [7:0] */ | |
| 1122 | ||
| 1123 | /* | |
| 1124 | * R1047 (0x417) - PDM 1 | |
| 1125 | */ | |
| 1126 | #define WM2200_SPK1R_MUTE 0x2000 /* SPK1R_MUTE */ | |
| 1127 | #define WM2200_SPK1R_MUTE_MASK 0x2000 /* SPK1R_MUTE */ | |
| 1128 | #define WM2200_SPK1R_MUTE_SHIFT 13 /* SPK1R_MUTE */ | |
| 1129 | #define WM2200_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */ | |
| 1130 | #define WM2200_SPK1L_MUTE 0x1000 /* SPK1L_MUTE */ | |
| 1131 | #define WM2200_SPK1L_MUTE_MASK 0x1000 /* SPK1L_MUTE */ | |
| 1132 | #define WM2200_SPK1L_MUTE_SHIFT 12 /* SPK1L_MUTE */ | |
| 1133 | #define WM2200_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */ | |
| 1134 | #define WM2200_SPK1_MUTE_ENDIAN 0x0100 /* SPK1_MUTE_ENDIAN */ | |
| 1135 | #define WM2200_SPK1_MUTE_ENDIAN_MASK 0x0100 /* SPK1_MUTE_ENDIAN */ | |
| 1136 | #define WM2200_SPK1_MUTE_ENDIAN_SHIFT 8 /* SPK1_MUTE_ENDIAN */ | |
| 1137 | #define WM2200_SPK1_MUTE_ENDIAN_WIDTH 1 /* SPK1_MUTE_ENDIAN */ | |
| 1138 | #define WM2200_SPK1_MUTE_SEQL_MASK 0x00FF /* SPK1_MUTE_SEQL - [7:0] */ | |
| 1139 | #define WM2200_SPK1_MUTE_SEQL_SHIFT 0 /* SPK1_MUTE_SEQL - [7:0] */ | |
| 1140 | #define WM2200_SPK1_MUTE_SEQL_WIDTH 8 /* SPK1_MUTE_SEQL - [7:0] */ | |
| 1141 | ||
| 1142 | /* | |
| 1143 | * R1048 (0x418) - PDM 2 | |
| 1144 | */ | |
| 1145 | #define WM2200_SPK1_FMT 0x0001 /* SPK1_FMT */ | |
| 1146 | #define WM2200_SPK1_FMT_MASK 0x0001 /* SPK1_FMT */ | |
| 1147 | #define WM2200_SPK1_FMT_SHIFT 0 /* SPK1_FMT */ | |
| 1148 | #define WM2200_SPK1_FMT_WIDTH 1 /* SPK1_FMT */ | |
| 1149 | ||
| 1150 | /* | |
| 1151 | * R1280 (0x500) - Audio IF 1_1 | |
| 1152 | */ | |
| 1153 | #define WM2200_AIF1_BCLK_INV 0x0040 /* AIF1_BCLK_INV */ | |
| 1154 | #define WM2200_AIF1_BCLK_INV_MASK 0x0040 /* AIF1_BCLK_INV */ | |
| 1155 | #define WM2200_AIF1_BCLK_INV_SHIFT 6 /* AIF1_BCLK_INV */ | |
| 1156 | #define WM2200_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */ | |
| 1157 | #define WM2200_AIF1_BCLK_FRC 0x0020 /* AIF1_BCLK_FRC */ | |
| 1158 | #define WM2200_AIF1_BCLK_FRC_MASK 0x0020 /* AIF1_BCLK_FRC */ | |
| 1159 | #define WM2200_AIF1_BCLK_FRC_SHIFT 5 /* AIF1_BCLK_FRC */ | |
| 1160 | #define WM2200_AIF1_BCLK_FRC_WIDTH 1 /* AIF1_BCLK_FRC */ | |
| 1161 | #define WM2200_AIF1_BCLK_MSTR 0x0010 /* AIF1_BCLK_MSTR */ | |
| 1162 | #define WM2200_AIF1_BCLK_MSTR_MASK 0x0010 /* AIF1_BCLK_MSTR */ | |
| 1163 | #define WM2200_AIF1_BCLK_MSTR_SHIFT 4 /* AIF1_BCLK_MSTR */ | |
| 1164 | #define WM2200_AIF1_BCLK_MSTR_WIDTH 1 /* AIF1_BCLK_MSTR */ | |
| 1165 | #define WM2200_AIF1_BCLK_DIV_MASK 0x000F /* AIF1_BCLK_DIV - [3:0] */ | |
| 1166 | #define WM2200_AIF1_BCLK_DIV_SHIFT 0 /* AIF1_BCLK_DIV - [3:0] */ | |
| 1167 | #define WM2200_AIF1_BCLK_DIV_WIDTH 4 /* AIF1_BCLK_DIV - [3:0] */ | |
| 1168 | ||
| 1169 | /* | |
| 1170 | * R1281 (0x501) - Audio IF 1_2 | |
| 1171 | */ | |
| 1172 | #define WM2200_AIF1TX_DAT_TRI 0x0020 /* AIF1TX_DAT_TRI */ | |
| 1173 | #define WM2200_AIF1TX_DAT_TRI_MASK 0x0020 /* AIF1TX_DAT_TRI */ | |
| 1174 | #define WM2200_AIF1TX_DAT_TRI_SHIFT 5 /* AIF1TX_DAT_TRI */ | |
| 1175 | #define WM2200_AIF1TX_DAT_TRI_WIDTH 1 /* AIF1TX_DAT_TRI */ | |
| 1176 | #define WM2200_AIF1TX_LRCLK_SRC 0x0008 /* AIF1TX_LRCLK_SRC */ | |
| 1177 | #define WM2200_AIF1TX_LRCLK_SRC_MASK 0x0008 /* AIF1TX_LRCLK_SRC */ | |
| 1178 | #define WM2200_AIF1TX_LRCLK_SRC_SHIFT 3 /* AIF1TX_LRCLK_SRC */ | |
| 1179 | #define WM2200_AIF1TX_LRCLK_SRC_WIDTH 1 /* AIF1TX_LRCLK_SRC */ | |
| 1180 | #define WM2200_AIF1TX_LRCLK_INV 0x0004 /* AIF1TX_LRCLK_INV */ | |
| 1181 | #define WM2200_AIF1TX_LRCLK_INV_MASK 0x0004 /* AIF1TX_LRCLK_INV */ | |
| 1182 | #define WM2200_AIF1TX_LRCLK_INV_SHIFT 2 /* AIF1TX_LRCLK_INV */ | |
| 1183 | #define WM2200_AIF1TX_LRCLK_INV_WIDTH 1 /* AIF1TX_LRCLK_INV */ | |
| 1184 | #define WM2200_AIF1TX_LRCLK_FRC 0x0002 /* AIF1TX_LRCLK_FRC */ | |
| 1185 | #define WM2200_AIF1TX_LRCLK_FRC_MASK 0x0002 /* AIF1TX_LRCLK_FRC */ | |
| 1186 | #define WM2200_AIF1TX_LRCLK_FRC_SHIFT 1 /* AIF1TX_LRCLK_FRC */ | |
| 1187 | #define WM2200_AIF1TX_LRCLK_FRC_WIDTH 1 /* AIF1TX_LRCLK_FRC */ | |
| 1188 | #define WM2200_AIF1TX_LRCLK_MSTR 0x0001 /* AIF1TX_LRCLK_MSTR */ | |
| 1189 | #define WM2200_AIF1TX_LRCLK_MSTR_MASK 0x0001 /* AIF1TX_LRCLK_MSTR */ | |
| 1190 | #define WM2200_AIF1TX_LRCLK_MSTR_SHIFT 0 /* AIF1TX_LRCLK_MSTR */ | |
| 1191 | #define WM2200_AIF1TX_LRCLK_MSTR_WIDTH 1 /* AIF1TX_LRCLK_MSTR */ | |
| 1192 | ||
| 1193 | /* | |
| 1194 | * R1282 (0x502) - Audio IF 1_3 | |
| 1195 | */ | |
| 1196 | #define WM2200_AIF1RX_LRCLK_INV 0x0004 /* AIF1RX_LRCLK_INV */ | |
| 1197 | #define WM2200_AIF1RX_LRCLK_INV_MASK 0x0004 /* AIF1RX_LRCLK_INV */ | |
| 1198 | #define WM2200_AIF1RX_LRCLK_INV_SHIFT 2 /* AIF1RX_LRCLK_INV */ | |
| 1199 | #define WM2200_AIF1RX_LRCLK_INV_WIDTH 1 /* AIF1RX_LRCLK_INV */ | |
| 1200 | #define WM2200_AIF1RX_LRCLK_FRC 0x0002 /* AIF1RX_LRCLK_FRC */ | |
| 1201 | #define WM2200_AIF1RX_LRCLK_FRC_MASK 0x0002 /* AIF1RX_LRCLK_FRC */ | |
| 1202 | #define WM2200_AIF1RX_LRCLK_FRC_SHIFT 1 /* AIF1RX_LRCLK_FRC */ | |
| 1203 | #define WM2200_AIF1RX_LRCLK_FRC_WIDTH 1 /* AIF1RX_LRCLK_FRC */ | |
| 1204 | #define WM2200_AIF1RX_LRCLK_MSTR 0x0001 /* AIF1RX_LRCLK_MSTR */ | |
| 1205 | #define WM2200_AIF1RX_LRCLK_MSTR_MASK 0x0001 /* AIF1RX_LRCLK_MSTR */ | |
| 1206 | #define WM2200_AIF1RX_LRCLK_MSTR_SHIFT 0 /* AIF1RX_LRCLK_MSTR */ | |
| 1207 | #define WM2200_AIF1RX_LRCLK_MSTR_WIDTH 1 /* AIF1RX_LRCLK_MSTR */ | |
| 1208 | ||
| 1209 | /* | |
| 1210 | * R1283 (0x503) - Audio IF 1_4 | |
| 1211 | */ | |
| 1212 | #define WM2200_AIF1_TRI 0x0040 /* AIF1_TRI */ | |
| 1213 | #define WM2200_AIF1_TRI_MASK 0x0040 /* AIF1_TRI */ | |
| 1214 | #define WM2200_AIF1_TRI_SHIFT 6 /* AIF1_TRI */ | |
| 1215 | #define WM2200_AIF1_TRI_WIDTH 1 /* AIF1_TRI */ | |
| 1216 | ||
| 1217 | /* | |
| 1218 | * R1284 (0x504) - Audio IF 1_5 | |
| 1219 | */ | |
| 1220 | #define WM2200_AIF1_FMT_MASK 0x0007 /* AIF1_FMT - [2:0] */ | |
| 1221 | #define WM2200_AIF1_FMT_SHIFT 0 /* AIF1_FMT - [2:0] */ | |
| 1222 | #define WM2200_AIF1_FMT_WIDTH 3 /* AIF1_FMT - [2:0] */ | |
| 1223 | ||
| 1224 | /* | |
| 1225 | * R1285 (0x505) - Audio IF 1_6 | |
| 1226 | */ | |
| 1227 | #define WM2200_AIF1TX_BCPF_MASK 0x07FF /* AIF1TX_BCPF - [10:0] */ | |
| 1228 | #define WM2200_AIF1TX_BCPF_SHIFT 0 /* AIF1TX_BCPF - [10:0] */ | |
| 1229 | #define WM2200_AIF1TX_BCPF_WIDTH 11 /* AIF1TX_BCPF - [10:0] */ | |
| 1230 | ||
| 1231 | /* | |
| 1232 | * R1286 (0x506) - Audio IF 1_7 | |
| 1233 | */ | |
| 1234 | #define WM2200_AIF1RX_BCPF_MASK 0x07FF /* AIF1RX_BCPF - [10:0] */ | |
| 1235 | #define WM2200_AIF1RX_BCPF_SHIFT 0 /* AIF1RX_BCPF - [10:0] */ | |
| 1236 | #define WM2200_AIF1RX_BCPF_WIDTH 11 /* AIF1RX_BCPF - [10:0] */ | |
| 1237 | ||
| 1238 | /* | |
| 1239 | * R1287 (0x507) - Audio IF 1_8 | |
| 1240 | */ | |
| 1241 | #define WM2200_AIF1TX_WL_MASK 0x3F00 /* AIF1TX_WL - [13:8] */ | |
| 1242 | #define WM2200_AIF1TX_WL_SHIFT 8 /* AIF1TX_WL - [13:8] */ | |
| 1243 | #define WM2200_AIF1TX_WL_WIDTH 6 /* AIF1TX_WL - [13:8] */ | |
| 1244 | #define WM2200_AIF1TX_SLOT_LEN_MASK 0x00FF /* AIF1TX_SLOT_LEN - [7:0] */ | |
| 1245 | #define WM2200_AIF1TX_SLOT_LEN_SHIFT 0 /* AIF1TX_SLOT_LEN - [7:0] */ | |
| 1246 | #define WM2200_AIF1TX_SLOT_LEN_WIDTH 8 /* AIF1TX_SLOT_LEN - [7:0] */ | |
| 1247 | ||
| 1248 | /* | |
| 1249 | * R1288 (0x508) - Audio IF 1_9 | |
| 1250 | */ | |
| 1251 | #define WM2200_AIF1RX_WL_MASK 0x3F00 /* AIF1RX_WL - [13:8] */ | |
| 1252 | #define WM2200_AIF1RX_WL_SHIFT 8 /* AIF1RX_WL - [13:8] */ | |
| 1253 | #define WM2200_AIF1RX_WL_WIDTH 6 /* AIF1RX_WL - [13:8] */ | |
| 1254 | #define WM2200_AIF1RX_SLOT_LEN_MASK 0x00FF /* AIF1RX_SLOT_LEN - [7:0] */ | |
| 1255 | #define WM2200_AIF1RX_SLOT_LEN_SHIFT 0 /* AIF1RX_SLOT_LEN - [7:0] */ | |
| 1256 | #define WM2200_AIF1RX_SLOT_LEN_WIDTH 8 /* AIF1RX_SLOT_LEN - [7:0] */ | |
| 1257 | ||
| 1258 | /* | |
| 1259 | * R1289 (0x509) - Audio IF 1_10 | |
| 1260 | */ | |
| 1261 | #define WM2200_AIF1TX1_SLOT_MASK 0x003F /* AIF1TX1_SLOT - [5:0] */ | |
| 1262 | #define WM2200_AIF1TX1_SLOT_SHIFT 0 /* AIF1TX1_SLOT - [5:0] */ | |
| 1263 | #define WM2200_AIF1TX1_SLOT_WIDTH 6 /* AIF1TX1_SLOT - [5:0] */ | |
| 1264 | ||
| 1265 | /* | |
| 1266 | * R1290 (0x50A) - Audio IF 1_11 | |
| 1267 | */ | |
| 1268 | #define WM2200_AIF1TX2_SLOT_MASK 0x003F /* AIF1TX2_SLOT - [5:0] */ | |
| 1269 | #define WM2200_AIF1TX2_SLOT_SHIFT 0 /* AIF1TX2_SLOT - [5:0] */ | |
| 1270 | #define WM2200_AIF1TX2_SLOT_WIDTH 6 /* AIF1TX2_SLOT - [5:0] */ | |
| 1271 | ||
| 1272 | /* | |
| 1273 | * R1291 (0x50B) - Audio IF 1_12 | |
| 1274 | */ | |
| 1275 | #define WM2200_AIF1TX3_SLOT_MASK 0x003F /* AIF1TX3_SLOT - [5:0] */ | |
| 1276 | #define WM2200_AIF1TX3_SLOT_SHIFT 0 /* AIF1TX3_SLOT - [5:0] */ | |
| 1277 | #define WM2200_AIF1TX3_SLOT_WIDTH 6 /* AIF1TX3_SLOT - [5:0] */ | |
| 1278 | ||
| 1279 | /* | |
| 1280 | * R1292 (0x50C) - Audio IF 1_13 | |
| 1281 | */ | |
| 1282 | #define WM2200_AIF1TX4_SLOT_MASK 0x003F /* AIF1TX4_SLOT - [5:0] */ | |
| 1283 | #define WM2200_AIF1TX4_SLOT_SHIFT 0 /* AIF1TX4_SLOT - [5:0] */ | |
| 1284 | #define WM2200_AIF1TX4_SLOT_WIDTH 6 /* AIF1TX4_SLOT - [5:0] */ | |
| 1285 | ||
| 1286 | /* | |
| 1287 | * R1293 (0x50D) - Audio IF 1_14 | |
| 1288 | */ | |
| 1289 | #define WM2200_AIF1TX5_SLOT_MASK 0x003F /* AIF1TX5_SLOT - [5:0] */ | |
| 1290 | #define WM2200_AIF1TX5_SLOT_SHIFT 0 /* AIF1TX5_SLOT - [5:0] */ | |
| 1291 | #define WM2200_AIF1TX5_SLOT_WIDTH 6 /* AIF1TX5_SLOT - [5:0] */ | |
| 1292 | ||
| 1293 | /* | |
| 1294 | * R1294 (0x50E) - Audio IF 1_15 | |
| 1295 | */ | |
| 1296 | #define WM2200_AIF1TX6_SLOT_MASK 0x003F /* AIF1TX6_SLOT - [5:0] */ | |
| 1297 | #define WM2200_AIF1TX6_SLOT_SHIFT 0 /* AIF1TX6_SLOT - [5:0] */ | |
| 1298 | #define WM2200_AIF1TX6_SLOT_WIDTH 6 /* AIF1TX6_SLOT - [5:0] */ | |
| 1299 | ||
| 1300 | /* | |
| 1301 | * R1295 (0x50F) - Audio IF 1_16 | |
| 1302 | */ | |
| 1303 | #define WM2200_AIF1RX1_SLOT_MASK 0x003F /* AIF1RX1_SLOT - [5:0] */ | |
| 1304 | #define WM2200_AIF1RX1_SLOT_SHIFT 0 /* AIF1RX1_SLOT - [5:0] */ | |
| 1305 | #define WM2200_AIF1RX1_SLOT_WIDTH 6 /* AIF1RX1_SLOT - [5:0] */ | |
| 1306 | ||
| 1307 | /* | |
| 1308 | * R1296 (0x510) - Audio IF 1_17 | |
| 1309 | */ | |
| 1310 | #define WM2200_AIF1RX2_SLOT_MASK 0x003F /* AIF1RX2_SLOT - [5:0] */ | |
| 1311 | #define WM2200_AIF1RX2_SLOT_SHIFT 0 /* AIF1RX2_SLOT - [5:0] */ | |
| 1312 | #define WM2200_AIF1RX2_SLOT_WIDTH 6 /* AIF1RX2_SLOT - [5:0] */ | |
| 1313 | ||
| 1314 | /* | |
| 1315 | * R1297 (0x511) - Audio IF 1_18 | |
| 1316 | */ | |
| 1317 | #define WM2200_AIF1RX3_SLOT_MASK 0x003F /* AIF1RX3_SLOT - [5:0] */ | |
| 1318 | #define WM2200_AIF1RX3_SLOT_SHIFT 0 /* AIF1RX3_SLOT - [5:0] */ | |
| 1319 | #define WM2200_AIF1RX3_SLOT_WIDTH 6 /* AIF1RX3_SLOT - [5:0] */ | |
| 1320 | ||
| 1321 | /* | |
| 1322 | * R1298 (0x512) - Audio IF 1_19 | |
| 1323 | */ | |
| 1324 | #define WM2200_AIF1RX4_SLOT_MASK 0x003F /* AIF1RX4_SLOT - [5:0] */ | |
| 1325 | #define WM2200_AIF1RX4_SLOT_SHIFT 0 /* AIF1RX4_SLOT - [5:0] */ | |
| 1326 | #define WM2200_AIF1RX4_SLOT_WIDTH 6 /* AIF1RX4_SLOT - [5:0] */ | |
| 1327 | ||
| 1328 | /* | |
| 1329 | * R1299 (0x513) - Audio IF 1_20 | |
| 1330 | */ | |
| 1331 | #define WM2200_AIF1RX5_SLOT_MASK 0x003F /* AIF1RX5_SLOT - [5:0] */ | |
| 1332 | #define WM2200_AIF1RX5_SLOT_SHIFT 0 /* AIF1RX5_SLOT - [5:0] */ | |
| 1333 | #define WM2200_AIF1RX5_SLOT_WIDTH 6 /* AIF1RX5_SLOT - [5:0] */ | |
| 1334 | ||
| 1335 | /* | |
| 1336 | * R1300 (0x514) - Audio IF 1_21 | |
| 1337 | */ | |
| 1338 | #define WM2200_AIF1RX6_SLOT_MASK 0x003F /* AIF1RX6_SLOT - [5:0] */ | |
| 1339 | #define WM2200_AIF1RX6_SLOT_SHIFT 0 /* AIF1RX6_SLOT - [5:0] */ | |
| 1340 | #define WM2200_AIF1RX6_SLOT_WIDTH 6 /* AIF1RX6_SLOT - [5:0] */ | |
| 1341 | ||
| 1342 | /* | |
| 1343 | * R1301 (0x515) - Audio IF 1_22 | |
| 1344 | */ | |
| 1345 | #define WM2200_AIF1RX6_ENA 0x0800 /* AIF1RX6_ENA */ | |
| 1346 | #define WM2200_AIF1RX6_ENA_MASK 0x0800 /* AIF1RX6_ENA */ | |
| 1347 | #define WM2200_AIF1RX6_ENA_SHIFT 11 /* AIF1RX6_ENA */ | |
| 1348 | #define WM2200_AIF1RX6_ENA_WIDTH 1 /* AIF1RX6_ENA */ | |
| 1349 | #define WM2200_AIF1RX5_ENA 0x0400 /* AIF1RX5_ENA */ | |
| 1350 | #define WM2200_AIF1RX5_ENA_MASK 0x0400 /* AIF1RX5_ENA */ | |
| 1351 | #define WM2200_AIF1RX5_ENA_SHIFT 10 /* AIF1RX5_ENA */ | |
| 1352 | #define WM2200_AIF1RX5_ENA_WIDTH 1 /* AIF1RX5_ENA */ | |
| 1353 | #define WM2200_AIF1RX4_ENA 0x0200 /* AIF1RX4_ENA */ | |
| 1354 | #define WM2200_AIF1RX4_ENA_MASK 0x0200 /* AIF1RX4_ENA */ | |
| 1355 | #define WM2200_AIF1RX4_ENA_SHIFT 9 /* AIF1RX4_ENA */ | |
| 1356 | #define WM2200_AIF1RX4_ENA_WIDTH 1 /* AIF1RX4_ENA */ | |
| 1357 | #define WM2200_AIF1RX3_ENA 0x0100 /* AIF1RX3_ENA */ | |
| 1358 | #define WM2200_AIF1RX3_ENA_MASK 0x0100 /* AIF1RX3_ENA */ | |
| 1359 | #define WM2200_AIF1RX3_ENA_SHIFT 8 /* AIF1RX3_ENA */ | |
| 1360 | #define WM2200_AIF1RX3_ENA_WIDTH 1 /* AIF1RX3_ENA */ | |
| 1361 | #define WM2200_AIF1RX2_ENA 0x0080 /* AIF1RX2_ENA */ | |
| 1362 | #define WM2200_AIF1RX2_ENA_MASK 0x0080 /* AIF1RX2_ENA */ | |
| 1363 | #define WM2200_AIF1RX2_ENA_SHIFT 7 /* AIF1RX2_ENA */ | |
| 1364 | #define WM2200_AIF1RX2_ENA_WIDTH 1 /* AIF1RX2_ENA */ | |
| 1365 | #define WM2200_AIF1RX1_ENA 0x0040 /* AIF1RX1_ENA */ | |
| 1366 | #define WM2200_AIF1RX1_ENA_MASK 0x0040 /* AIF1RX1_ENA */ | |
| 1367 | #define WM2200_AIF1RX1_ENA_SHIFT 6 /* AIF1RX1_ENA */ | |
| 1368 | #define WM2200_AIF1RX1_ENA_WIDTH 1 /* AIF1RX1_ENA */ | |
| 1369 | #define WM2200_AIF1TX6_ENA 0x0020 /* AIF1TX6_ENA */ | |
| 1370 | #define WM2200_AIF1TX6_ENA_MASK 0x0020 /* AIF1TX6_ENA */ | |
| 1371 | #define WM2200_AIF1TX6_ENA_SHIFT 5 /* AIF1TX6_ENA */ | |
| 1372 | #define WM2200_AIF1TX6_ENA_WIDTH 1 /* AIF1TX6_ENA */ | |
| 1373 | #define WM2200_AIF1TX5_ENA 0x0010 /* AIF1TX5_ENA */ | |
| 1374 | #define WM2200_AIF1TX5_ENA_MASK 0x0010 /* AIF1TX5_ENA */ | |
| 1375 | #define WM2200_AIF1TX5_ENA_SHIFT 4 /* AIF1TX5_ENA */ | |
| 1376 | #define WM2200_AIF1TX5_ENA_WIDTH 1 /* AIF1TX5_ENA */ | |
| 1377 | #define WM2200_AIF1TX4_ENA 0x0008 /* AIF1TX4_ENA */ | |
| 1378 | #define WM2200_AIF1TX4_ENA_MASK 0x0008 /* AIF1TX4_ENA */ | |
| 1379 | #define WM2200_AIF1TX4_ENA_SHIFT 3 /* AIF1TX4_ENA */ | |
| 1380 | #define WM2200_AIF1TX4_ENA_WIDTH 1 /* AIF1TX4_ENA */ | |
| 1381 | #define WM2200_AIF1TX3_ENA 0x0004 /* AIF1TX3_ENA */ | |
| 1382 | #define WM2200_AIF1TX3_ENA_MASK 0x0004 /* AIF1TX3_ENA */ | |
| 1383 | #define WM2200_AIF1TX3_ENA_SHIFT 2 /* AIF1TX3_ENA */ | |
| 1384 | #define WM2200_AIF1TX3_ENA_WIDTH 1 /* AIF1TX3_ENA */ | |
| 1385 | #define WM2200_AIF1TX2_ENA 0x0002 /* AIF1TX2_ENA */ | |
| 1386 | #define WM2200_AIF1TX2_ENA_MASK 0x0002 /* AIF1TX2_ENA */ | |
| 1387 | #define WM2200_AIF1TX2_ENA_SHIFT 1 /* AIF1TX2_ENA */ | |
| 1388 | #define WM2200_AIF1TX2_ENA_WIDTH 1 /* AIF1TX2_ENA */ | |
| 1389 | #define WM2200_AIF1TX1_ENA 0x0001 /* AIF1TX1_ENA */ | |
| 1390 | #define WM2200_AIF1TX1_ENA_MASK 0x0001 /* AIF1TX1_ENA */ | |
| 1391 | #define WM2200_AIF1TX1_ENA_SHIFT 0 /* AIF1TX1_ENA */ | |
| 1392 | #define WM2200_AIF1TX1_ENA_WIDTH 1 /* AIF1TX1_ENA */ | |
| 1393 | ||
| 1394 | /* | |
| 1395 | * R1536 (0x600) - OUT1LMIX Input 1 Source | |
| 1396 | */ | |
| 1397 | #define WM2200_OUT1LMIX_SRC1_MASK 0x007F /* OUT1LMIX_SRC1 - [6:0] */ | |
| 1398 | #define WM2200_OUT1LMIX_SRC1_SHIFT 0 /* OUT1LMIX_SRC1 - [6:0] */ | |
| 1399 | #define WM2200_OUT1LMIX_SRC1_WIDTH 7 /* OUT1LMIX_SRC1 - [6:0] */ | |
| 1400 | ||
| 1401 | /* | |
| 1402 | * R1537 (0x601) - OUT1LMIX Input 1 Volume | |
| 1403 | */ | |
| 1404 | #define WM2200_OUT1LMIX_VOL1_MASK 0x00FE /* OUT1LMIX_VOL1 - [7:1] */ | |
| 1405 | #define WM2200_OUT1LMIX_VOL1_SHIFT 1 /* OUT1LMIX_VOL1 - [7:1] */ | |
| 1406 | #define WM2200_OUT1LMIX_VOL1_WIDTH 7 /* OUT1LMIX_VOL1 - [7:1] */ | |
| 1407 | ||
| 1408 | /* | |
| 1409 | * R1538 (0x602) - OUT1LMIX Input 2 Source | |
| 1410 | */ | |
| 1411 | #define WM2200_OUT1LMIX_SRC2_MASK 0x007F /* OUT1LMIX_SRC2 - [6:0] */ | |
| 1412 | #define WM2200_OUT1LMIX_SRC2_SHIFT 0 /* OUT1LMIX_SRC2 - [6:0] */ | |
| 1413 | #define WM2200_OUT1LMIX_SRC2_WIDTH 7 /* OUT1LMIX_SRC2 - [6:0] */ | |
| 1414 | ||
| 1415 | /* | |
| 1416 | * R1539 (0x603) - OUT1LMIX Input 2 Volume | |
| 1417 | */ | |
| 1418 | #define WM2200_OUT1LMIX_VOL2_MASK 0x00FE /* OUT1LMIX_VOL2 - [7:1] */ | |
| 1419 | #define WM2200_OUT1LMIX_VOL2_SHIFT 1 /* OUT1LMIX_VOL2 - [7:1] */ | |
| 1420 | #define WM2200_OUT1LMIX_VOL2_WIDTH 7 /* OUT1LMIX_VOL2 - [7:1] */ | |
| 1421 | ||
| 1422 | /* | |
| 1423 | * R1540 (0x604) - OUT1LMIX Input 3 Source | |
| 1424 | */ | |
| 1425 | #define WM2200_OUT1LMIX_SRC3_MASK 0x007F /* OUT1LMIX_SRC3 - [6:0] */ | |
| 1426 | #define WM2200_OUT1LMIX_SRC3_SHIFT 0 /* OUT1LMIX_SRC3 - [6:0] */ | |
| 1427 | #define WM2200_OUT1LMIX_SRC3_WIDTH 7 /* OUT1LMIX_SRC3 - [6:0] */ | |
| 1428 | ||
| 1429 | /* | |
| 1430 | * R1541 (0x605) - OUT1LMIX Input 3 Volume | |
| 1431 | */ | |
| 1432 | #define WM2200_OUT1LMIX_VOL3_MASK 0x00FE /* OUT1LMIX_VOL3 - [7:1] */ | |
| 1433 | #define WM2200_OUT1LMIX_VOL3_SHIFT 1 /* OUT1LMIX_VOL3 - [7:1] */ | |
| 1434 | #define WM2200_OUT1LMIX_VOL3_WIDTH 7 /* OUT1LMIX_VOL3 - [7:1] */ | |
| 1435 | ||
| 1436 | /* | |
| 1437 | * R1542 (0x606) - OUT1LMIX Input 4 Source | |
| 1438 | */ | |
| 1439 | #define WM2200_OUT1LMIX_SRC4_MASK 0x007F /* OUT1LMIX_SRC4 - [6:0] */ | |
| 1440 | #define WM2200_OUT1LMIX_SRC4_SHIFT 0 /* OUT1LMIX_SRC4 - [6:0] */ | |
| 1441 | #define WM2200_OUT1LMIX_SRC4_WIDTH 7 /* OUT1LMIX_SRC4 - [6:0] */ | |
| 1442 | ||
| 1443 | /* | |
| 1444 | * R1543 (0x607) - OUT1LMIX Input 4 Volume | |
| 1445 | */ | |
| 1446 | #define WM2200_OUT1LMIX_VOL4_MASK 0x00FE /* OUT1LMIX_VOL4 - [7:1] */ | |
| 1447 | #define WM2200_OUT1LMIX_VOL4_SHIFT 1 /* OUT1LMIX_VOL4 - [7:1] */ | |
| 1448 | #define WM2200_OUT1LMIX_VOL4_WIDTH 7 /* OUT1LMIX_VOL4 - [7:1] */ | |
| 1449 | ||
| 1450 | /* | |
| 1451 | * R1544 (0x608) - OUT1RMIX Input 1 Source | |
| 1452 | */ | |
| 1453 | #define WM2200_OUT1RMIX_SRC1_MASK 0x007F /* OUT1RMIX_SRC1 - [6:0] */ | |
| 1454 | #define WM2200_OUT1RMIX_SRC1_SHIFT 0 /* OUT1RMIX_SRC1 - [6:0] */ | |
| 1455 | #define WM2200_OUT1RMIX_SRC1_WIDTH 7 /* OUT1RMIX_SRC1 - [6:0] */ | |
| 1456 | ||
| 1457 | /* | |
| 1458 | * R1545 (0x609) - OUT1RMIX Input 1 Volume | |
| 1459 | */ | |
| 1460 | #define WM2200_OUT1RMIX_VOL1_MASK 0x00FE /* OUT1RMIX_VOL1 - [7:1] */ | |
| 1461 | #define WM2200_OUT1RMIX_VOL1_SHIFT 1 /* OUT1RMIX_VOL1 - [7:1] */ | |
| 1462 | #define WM2200_OUT1RMIX_VOL1_WIDTH 7 /* OUT1RMIX_VOL1 - [7:1] */ | |
| 1463 | ||
| 1464 | /* | |
| 1465 | * R1546 (0x60A) - OUT1RMIX Input 2 Source | |
| 1466 | */ | |
| 1467 | #define WM2200_OUT1RMIX_SRC2_MASK 0x007F /* OUT1RMIX_SRC2 - [6:0] */ | |
| 1468 | #define WM2200_OUT1RMIX_SRC2_SHIFT 0 /* OUT1RMIX_SRC2 - [6:0] */ | |
| 1469 | #define WM2200_OUT1RMIX_SRC2_WIDTH 7 /* OUT1RMIX_SRC2 - [6:0] */ | |
| 1470 | ||
| 1471 | /* | |
| 1472 | * R1547 (0x60B) - OUT1RMIX Input 2 Volume | |
| 1473 | */ | |
| 1474 | #define WM2200_OUT1RMIX_VOL2_MASK 0x00FE /* OUT1RMIX_VOL2 - [7:1] */ | |
| 1475 | #define WM2200_OUT1RMIX_VOL2_SHIFT 1 /* OUT1RMIX_VOL2 - [7:1] */ | |
| 1476 | #define WM2200_OUT1RMIX_VOL2_WIDTH 7 /* OUT1RMIX_VOL2 - [7:1] */ | |
| 1477 | ||
| 1478 | /* | |
| 1479 | * R1548 (0x60C) - OUT1RMIX Input 3 Source | |
| 1480 | */ | |
| 1481 | #define WM2200_OUT1RMIX_SRC3_MASK 0x007F /* OUT1RMIX_SRC3 - [6:0] */ | |
| 1482 | #define WM2200_OUT1RMIX_SRC3_SHIFT 0 /* OUT1RMIX_SRC3 - [6:0] */ | |
| 1483 | #define WM2200_OUT1RMIX_SRC3_WIDTH 7 /* OUT1RMIX_SRC3 - [6:0] */ | |
| 1484 | ||
| 1485 | /* | |
| 1486 | * R1549 (0x60D) - OUT1RMIX Input 3 Volume | |
| 1487 | */ | |
| 1488 | #define WM2200_OUT1RMIX_VOL3_MASK 0x00FE /* OUT1RMIX_VOL3 - [7:1] */ | |
| 1489 | #define WM2200_OUT1RMIX_VOL3_SHIFT 1 /* OUT1RMIX_VOL3 - [7:1] */ | |
| 1490 | #define WM2200_OUT1RMIX_VOL3_WIDTH 7 /* OUT1RMIX_VOL3 - [7:1] */ | |
| 1491 | ||
| 1492 | /* | |
| 1493 | * R1550 (0x60E) - OUT1RMIX Input 4 Source | |
| 1494 | */ | |
| 1495 | #define WM2200_OUT1RMIX_SRC4_MASK 0x007F /* OUT1RMIX_SRC4 - [6:0] */ | |
| 1496 | #define WM2200_OUT1RMIX_SRC4_SHIFT 0 /* OUT1RMIX_SRC4 - [6:0] */ | |
| 1497 | #define WM2200_OUT1RMIX_SRC4_WIDTH 7 /* OUT1RMIX_SRC4 - [6:0] */ | |
| 1498 | ||
| 1499 | /* | |
| 1500 | * R1551 (0x60F) - OUT1RMIX Input 4 Volume | |
| 1501 | */ | |
| 1502 | #define WM2200_OUT1RMIX_VOL4_MASK 0x00FE /* OUT1RMIX_VOL4 - [7:1] */ | |
| 1503 | #define WM2200_OUT1RMIX_VOL4_SHIFT 1 /* OUT1RMIX_VOL4 - [7:1] */ | |
| 1504 | #define WM2200_OUT1RMIX_VOL4_WIDTH 7 /* OUT1RMIX_VOL4 - [7:1] */ | |
| 1505 | ||
| 1506 | /* | |
| 1507 | * R1552 (0x610) - OUT2LMIX Input 1 Source | |
| 1508 | */ | |
| 1509 | #define WM2200_OUT2LMIX_SRC1_MASK 0x007F /* OUT2LMIX_SRC1 - [6:0] */ | |
| 1510 | #define WM2200_OUT2LMIX_SRC1_SHIFT 0 /* OUT2LMIX_SRC1 - [6:0] */ | |
| 1511 | #define WM2200_OUT2LMIX_SRC1_WIDTH 7 /* OUT2LMIX_SRC1 - [6:0] */ | |
| 1512 | ||
| 1513 | /* | |
| 1514 | * R1553 (0x611) - OUT2LMIX Input 1 Volume | |
| 1515 | */ | |
| 1516 | #define WM2200_OUT2LMIX_VOL1_MASK 0x00FE /* OUT2LMIX_VOL1 - [7:1] */ | |
| 1517 | #define WM2200_OUT2LMIX_VOL1_SHIFT 1 /* OUT2LMIX_VOL1 - [7:1] */ | |
| 1518 | #define WM2200_OUT2LMIX_VOL1_WIDTH 7 /* OUT2LMIX_VOL1 - [7:1] */ | |
| 1519 | ||
| 1520 | /* | |
| 1521 | * R1554 (0x612) - OUT2LMIX Input 2 Source | |
| 1522 | */ | |
| 1523 | #define WM2200_OUT2LMIX_SRC2_MASK 0x007F /* OUT2LMIX_SRC2 - [6:0] */ | |
| 1524 | #define WM2200_OUT2LMIX_SRC2_SHIFT 0 /* OUT2LMIX_SRC2 - [6:0] */ | |
| 1525 | #define WM2200_OUT2LMIX_SRC2_WIDTH 7 /* OUT2LMIX_SRC2 - [6:0] */ | |
| 1526 | ||
| 1527 | /* | |
| 1528 | * R1555 (0x613) - OUT2LMIX Input 2 Volume | |
| 1529 | */ | |
| 1530 | #define WM2200_OUT2LMIX_VOL2_MASK 0x00FE /* OUT2LMIX_VOL2 - [7:1] */ | |
| 1531 | #define WM2200_OUT2LMIX_VOL2_SHIFT 1 /* OUT2LMIX_VOL2 - [7:1] */ | |
| 1532 | #define WM2200_OUT2LMIX_VOL2_WIDTH 7 /* OUT2LMIX_VOL2 - [7:1] */ | |
| 1533 | ||
| 1534 | /* | |
| 1535 | * R1556 (0x614) - OUT2LMIX Input 3 Source | |
| 1536 | */ | |
| 1537 | #define WM2200_OUT2LMIX_SRC3_MASK 0x007F /* OUT2LMIX_SRC3 - [6:0] */ | |
| 1538 | #define WM2200_OUT2LMIX_SRC3_SHIFT 0 /* OUT2LMIX_SRC3 - [6:0] */ | |
| 1539 | #define WM2200_OUT2LMIX_SRC3_WIDTH 7 /* OUT2LMIX_SRC3 - [6:0] */ | |
| 1540 | ||
| 1541 | /* | |
| 1542 | * R1557 (0x615) - OUT2LMIX Input 3 Volume | |
| 1543 | */ | |
| 1544 | #define WM2200_OUT2LMIX_VOL3_MASK 0x00FE /* OUT2LMIX_VOL3 - [7:1] */ | |
| 1545 | #define WM2200_OUT2LMIX_VOL3_SHIFT 1 /* OUT2LMIX_VOL3 - [7:1] */ | |
| 1546 | #define WM2200_OUT2LMIX_VOL3_WIDTH 7 /* OUT2LMIX_VOL3 - [7:1] */ | |
| 1547 | ||
| 1548 | /* | |
| 1549 | * R1558 (0x616) - OUT2LMIX Input 4 Source | |
| 1550 | */ | |
| 1551 | #define WM2200_OUT2LMIX_SRC4_MASK 0x007F /* OUT2LMIX_SRC4 - [6:0] */ | |
| 1552 | #define WM2200_OUT2LMIX_SRC4_SHIFT 0 /* OUT2LMIX_SRC4 - [6:0] */ | |
| 1553 | #define WM2200_OUT2LMIX_SRC4_WIDTH 7 /* OUT2LMIX_SRC4 - [6:0] */ | |
| 1554 | ||
| 1555 | /* | |
| 1556 | * R1559 (0x617) - OUT2LMIX Input 4 Volume | |
| 1557 | */ | |
| 1558 | #define WM2200_OUT2LMIX_VOL4_MASK 0x00FE /* OUT2LMIX_VOL4 - [7:1] */ | |
| 1559 | #define WM2200_OUT2LMIX_VOL4_SHIFT 1 /* OUT2LMIX_VOL4 - [7:1] */ | |
| 1560 | #define WM2200_OUT2LMIX_VOL4_WIDTH 7 /* OUT2LMIX_VOL4 - [7:1] */ | |
| 1561 | ||
| 1562 | /* | |
| 1563 | * R1560 (0x618) - OUT2RMIX Input 1 Source | |
| 1564 | */ | |
| 1565 | #define WM2200_OUT2RMIX_SRC1_MASK 0x007F /* OUT2RMIX_SRC1 - [6:0] */ | |
| 1566 | #define WM2200_OUT2RMIX_SRC1_SHIFT 0 /* OUT2RMIX_SRC1 - [6:0] */ | |
| 1567 | #define WM2200_OUT2RMIX_SRC1_WIDTH 7 /* OUT2RMIX_SRC1 - [6:0] */ | |
| 1568 | ||
| 1569 | /* | |
| 1570 | * R1561 (0x619) - OUT2RMIX Input 1 Volume | |
| 1571 | */ | |
| 1572 | #define WM2200_OUT2RMIX_VOL1_MASK 0x00FE /* OUT2RMIX_VOL1 - [7:1] */ | |
| 1573 | #define WM2200_OUT2RMIX_VOL1_SHIFT 1 /* OUT2RMIX_VOL1 - [7:1] */ | |
| 1574 | #define WM2200_OUT2RMIX_VOL1_WIDTH 7 /* OUT2RMIX_VOL1 - [7:1] */ | |
| 1575 | ||
| 1576 | /* | |
| 1577 | * R1562 (0x61A) - OUT2RMIX Input 2 Source | |
| 1578 | */ | |
| 1579 | #define WM2200_OUT2RMIX_SRC2_MASK 0x007F /* OUT2RMIX_SRC2 - [6:0] */ | |
| 1580 | #define WM2200_OUT2RMIX_SRC2_SHIFT 0 /* OUT2RMIX_SRC2 - [6:0] */ | |
| 1581 | #define WM2200_OUT2RMIX_SRC2_WIDTH 7 /* OUT2RMIX_SRC2 - [6:0] */ | |
| 1582 | ||
| 1583 | /* | |
| 1584 | * R1563 (0x61B) - OUT2RMIX Input 2 Volume | |
| 1585 | */ | |
| 1586 | #define WM2200_OUT2RMIX_VOL2_MASK 0x00FE /* OUT2RMIX_VOL2 - [7:1] */ | |
| 1587 | #define WM2200_OUT2RMIX_VOL2_SHIFT 1 /* OUT2RMIX_VOL2 - [7:1] */ | |
| 1588 | #define WM2200_OUT2RMIX_VOL2_WIDTH 7 /* OUT2RMIX_VOL2 - [7:1] */ | |
| 1589 | ||
| 1590 | /* | |
| 1591 | * R1564 (0x61C) - OUT2RMIX Input 3 Source | |
| 1592 | */ | |
| 1593 | #define WM2200_OUT2RMIX_SRC3_MASK 0x007F /* OUT2RMIX_SRC3 - [6:0] */ | |
| 1594 | #define WM2200_OUT2RMIX_SRC3_SHIFT 0 /* OUT2RMIX_SRC3 - [6:0] */ | |
| 1595 | #define WM2200_OUT2RMIX_SRC3_WIDTH 7 /* OUT2RMIX_SRC3 - [6:0] */ | |
| 1596 | ||
| 1597 | /* | |
| 1598 | * R1565 (0x61D) - OUT2RMIX Input 3 Volume | |
| 1599 | */ | |
| 1600 | #define WM2200_OUT2RMIX_VOL3_MASK 0x00FE /* OUT2RMIX_VOL3 - [7:1] */ | |
| 1601 | #define WM2200_OUT2RMIX_VOL3_SHIFT 1 /* OUT2RMIX_VOL3 - [7:1] */ | |
| 1602 | #define WM2200_OUT2RMIX_VOL3_WIDTH 7 /* OUT2RMIX_VOL3 - [7:1] */ | |
| 1603 | ||
| 1604 | /* | |
| 1605 | * R1566 (0x61E) - OUT2RMIX Input 4 Source | |
| 1606 | */ | |
| 1607 | #define WM2200_OUT2RMIX_SRC4_MASK 0x007F /* OUT2RMIX_SRC4 - [6:0] */ | |
| 1608 | #define WM2200_OUT2RMIX_SRC4_SHIFT 0 /* OUT2RMIX_SRC4 - [6:0] */ | |
| 1609 | #define WM2200_OUT2RMIX_SRC4_WIDTH 7 /* OUT2RMIX_SRC4 - [6:0] */ | |
| 1610 | ||
| 1611 | /* | |
| 1612 | * R1567 (0x61F) - OUT2RMIX Input 4 Volume | |
| 1613 | */ | |
| 1614 | #define WM2200_OUT2RMIX_VOL4_MASK 0x00FE /* OUT2RMIX_VOL4 - [7:1] */ | |
| 1615 | #define WM2200_OUT2RMIX_VOL4_SHIFT 1 /* OUT2RMIX_VOL4 - [7:1] */ | |
| 1616 | #define WM2200_OUT2RMIX_VOL4_WIDTH 7 /* OUT2RMIX_VOL4 - [7:1] */ | |
| 1617 | ||
| 1618 | /* | |
| 1619 | * R1568 (0x620) - AIF1TX1MIX Input 1 Source | |
| 1620 | */ | |
| 1621 | #define WM2200_AIF1TX1MIX_SRC1_MASK 0x007F /* AIF1TX1MIX_SRC1 - [6:0] */ | |
| 1622 | #define WM2200_AIF1TX1MIX_SRC1_SHIFT 0 /* AIF1TX1MIX_SRC1 - [6:0] */ | |
| 1623 | #define WM2200_AIF1TX1MIX_SRC1_WIDTH 7 /* AIF1TX1MIX_SRC1 - [6:0] */ | |
| 1624 | ||
| 1625 | /* | |
| 1626 | * R1569 (0x621) - AIF1TX1MIX Input 1 Volume | |
| 1627 | */ | |
| 1628 | #define WM2200_AIF1TX1MIX_VOL1_MASK 0x00FE /* AIF1TX1MIX_VOL1 - [7:1] */ | |
| 1629 | #define WM2200_AIF1TX1MIX_VOL1_SHIFT 1 /* AIF1TX1MIX_VOL1 - [7:1] */ | |
| 1630 | #define WM2200_AIF1TX1MIX_VOL1_WIDTH 7 /* AIF1TX1MIX_VOL1 - [7:1] */ | |
| 1631 | ||
| 1632 | /* | |
| 1633 | * R1570 (0x622) - AIF1TX1MIX Input 2 Source | |
| 1634 | */ | |
| 1635 | #define WM2200_AIF1TX1MIX_SRC2_MASK 0x007F /* AIF1TX1MIX_SRC2 - [6:0] */ | |
| 1636 | #define WM2200_AIF1TX1MIX_SRC2_SHIFT 0 /* AIF1TX1MIX_SRC2 - [6:0] */ | |
| 1637 | #define WM2200_AIF1TX1MIX_SRC2_WIDTH 7 /* AIF1TX1MIX_SRC2 - [6:0] */ | |
| 1638 | ||
| 1639 | /* | |
| 1640 | * R1571 (0x623) - AIF1TX1MIX Input 2 Volume | |
| 1641 | */ | |
| 1642 | #define WM2200_AIF1TX1MIX_VOL2_MASK 0x00FE /* AIF1TX1MIX_VOL2 - [7:1] */ | |
| 1643 | #define WM2200_AIF1TX1MIX_VOL2_SHIFT 1 /* AIF1TX1MIX_VOL2 - [7:1] */ | |
| 1644 | #define WM2200_AIF1TX1MIX_VOL2_WIDTH 7 /* AIF1TX1MIX_VOL2 - [7:1] */ | |
| 1645 | ||
| 1646 | /* | |
| 1647 | * R1572 (0x624) - AIF1TX1MIX Input 3 Source | |
| 1648 | */ | |
| 1649 | #define WM2200_AIF1TX1MIX_SRC3_MASK 0x007F /* AIF1TX1MIX_SRC3 - [6:0] */ | |
| 1650 | #define WM2200_AIF1TX1MIX_SRC3_SHIFT 0 /* AIF1TX1MIX_SRC3 - [6:0] */ | |
| 1651 | #define WM2200_AIF1TX1MIX_SRC3_WIDTH 7 /* AIF1TX1MIX_SRC3 - [6:0] */ | |
| 1652 | ||
| 1653 | /* | |
| 1654 | * R1573 (0x625) - AIF1TX1MIX Input 3 Volume | |
| 1655 | */ | |
| 1656 | #define WM2200_AIF1TX1MIX_VOL3_MASK 0x00FE /* AIF1TX1MIX_VOL3 - [7:1] */ | |
| 1657 | #define WM2200_AIF1TX1MIX_VOL3_SHIFT 1 /* AIF1TX1MIX_VOL3 - [7:1] */ | |
| 1658 | #define WM2200_AIF1TX1MIX_VOL3_WIDTH 7 /* AIF1TX1MIX_VOL3 - [7:1] */ | |
| 1659 | ||
| 1660 | /* | |
| 1661 | * R1574 (0x626) - AIF1TX1MIX Input 4 Source | |
| 1662 | */ | |
| 1663 | #define WM2200_AIF1TX1MIX_SRC4_MASK 0x007F /* AIF1TX1MIX_SRC4 - [6:0] */ | |
| 1664 | #define WM2200_AIF1TX1MIX_SRC4_SHIFT 0 /* AIF1TX1MIX_SRC4 - [6:0] */ | |
| 1665 | #define WM2200_AIF1TX1MIX_SRC4_WIDTH 7 /* AIF1TX1MIX_SRC4 - [6:0] */ | |
| 1666 | ||
| 1667 | /* | |
| 1668 | * R1575 (0x627) - AIF1TX1MIX Input 4 Volume | |
| 1669 | */ | |
| 1670 | #define WM2200_AIF1TX1MIX_VOL4_MASK 0x00FE /* AIF1TX1MIX_VOL4 - [7:1] */ | |
| 1671 | #define WM2200_AIF1TX1MIX_VOL4_SHIFT 1 /* AIF1TX1MIX_VOL4 - [7:1] */ | |
| 1672 | #define WM2200_AIF1TX1MIX_VOL4_WIDTH 7 /* AIF1TX1MIX_VOL4 - [7:1] */ | |
| 1673 | ||
| 1674 | /* | |
| 1675 | * R1576 (0x628) - AIF1TX2MIX Input 1 Source | |
| 1676 | */ | |
| 1677 | #define WM2200_AIF1TX2MIX_SRC1_MASK 0x007F /* AIF1TX2MIX_SRC1 - [6:0] */ | |
| 1678 | #define WM2200_AIF1TX2MIX_SRC1_SHIFT 0 /* AIF1TX2MIX_SRC1 - [6:0] */ | |
| 1679 | #define WM2200_AIF1TX2MIX_SRC1_WIDTH 7 /* AIF1TX2MIX_SRC1 - [6:0] */ | |
| 1680 | ||
| 1681 | /* | |
| 1682 | * R1577 (0x629) - AIF1TX2MIX Input 1 Volume | |
| 1683 | */ | |
| 1684 | #define WM2200_AIF1TX2MIX_VOL1_MASK 0x00FE /* AIF1TX2MIX_VOL1 - [7:1] */ | |
| 1685 | #define WM2200_AIF1TX2MIX_VOL1_SHIFT 1 /* AIF1TX2MIX_VOL1 - [7:1] */ | |
| 1686 | #define WM2200_AIF1TX2MIX_VOL1_WIDTH 7 /* AIF1TX2MIX_VOL1 - [7:1] */ | |
| 1687 | ||
| 1688 | /* | |
| 1689 | * R1578 (0x62A) - AIF1TX2MIX Input 2 Source | |
| 1690 | */ | |
| 1691 | #define WM2200_AIF1TX2MIX_SRC2_MASK 0x007F /* AIF1TX2MIX_SRC2 - [6:0] */ | |
| 1692 | #define WM2200_AIF1TX2MIX_SRC2_SHIFT 0 /* AIF1TX2MIX_SRC2 - [6:0] */ | |
| 1693 | #define WM2200_AIF1TX2MIX_SRC2_WIDTH 7 /* AIF1TX2MIX_SRC2 - [6:0] */ | |
| 1694 | ||
| 1695 | /* | |
| 1696 | * R1579 (0x62B) - AIF1TX2MIX Input 2 Volume | |
| 1697 | */ | |
| 1698 | #define WM2200_AIF1TX2MIX_VOL2_MASK 0x00FE /* AIF1TX2MIX_VOL2 - [7:1] */ | |
| 1699 | #define WM2200_AIF1TX2MIX_VOL2_SHIFT 1 /* AIF1TX2MIX_VOL2 - [7:1] */ | |
| 1700 | #define WM2200_AIF1TX2MIX_VOL2_WIDTH 7 /* AIF1TX2MIX_VOL2 - [7:1] */ | |
| 1701 | ||
| 1702 | /* | |
| 1703 | * R1580 (0x62C) - AIF1TX2MIX Input 3 Source | |
| 1704 | */ | |
| 1705 | #define WM2200_AIF1TX2MIX_SRC3_MASK 0x007F /* AIF1TX2MIX_SRC3 - [6:0] */ | |
| 1706 | #define WM2200_AIF1TX2MIX_SRC3_SHIFT 0 /* AIF1TX2MIX_SRC3 - [6:0] */ | |
| 1707 | #define WM2200_AIF1TX2MIX_SRC3_WIDTH 7 /* AIF1TX2MIX_SRC3 - [6:0] */ | |
| 1708 | ||
| 1709 | /* | |
| 1710 | * R1581 (0x62D) - AIF1TX2MIX Input 3 Volume | |
| 1711 | */ | |
| 1712 | #define WM2200_AIF1TX2MIX_VOL3_MASK 0x00FE /* AIF1TX2MIX_VOL3 - [7:1] */ | |
| 1713 | #define WM2200_AIF1TX2MIX_VOL3_SHIFT 1 /* AIF1TX2MIX_VOL3 - [7:1] */ | |
| 1714 | #define WM2200_AIF1TX2MIX_VOL3_WIDTH 7 /* AIF1TX2MIX_VOL3 - [7:1] */ | |
| 1715 | ||
| 1716 | /* | |
| 1717 | * R1582 (0x62E) - AIF1TX2MIX Input 4 Source | |
| 1718 | */ | |
| 1719 | #define WM2200_AIF1TX2MIX_SRC4_MASK 0x007F /* AIF1TX2MIX_SRC4 - [6:0] */ | |
| 1720 | #define WM2200_AIF1TX2MIX_SRC4_SHIFT 0 /* AIF1TX2MIX_SRC4 - [6:0] */ | |
| 1721 | #define WM2200_AIF1TX2MIX_SRC4_WIDTH 7 /* AIF1TX2MIX_SRC4 - [6:0] */ | |
| 1722 | ||
| 1723 | /* | |
| 1724 | * R1583 (0x62F) - AIF1TX2MIX Input 4 Volume | |
| 1725 | */ | |
| 1726 | #define WM2200_AIF1TX2MIX_VOL4_MASK 0x00FE /* AIF1TX2MIX_VOL4 - [7:1] */ | |
| 1727 | #define WM2200_AIF1TX2MIX_VOL4_SHIFT 1 /* AIF1TX2MIX_VOL4 - [7:1] */ | |
| 1728 | #define WM2200_AIF1TX2MIX_VOL4_WIDTH 7 /* AIF1TX2MIX_VOL4 - [7:1] */ | |
| 1729 | ||
| 1730 | /* | |
| 1731 | * R1584 (0x630) - AIF1TX3MIX Input 1 Source | |
| 1732 | */ | |
| 1733 | #define WM2200_AIF1TX3MIX_SRC1_MASK 0x007F /* AIF1TX3MIX_SRC1 - [6:0] */ | |
| 1734 | #define WM2200_AIF1TX3MIX_SRC1_SHIFT 0 /* AIF1TX3MIX_SRC1 - [6:0] */ | |
| 1735 | #define WM2200_AIF1TX3MIX_SRC1_WIDTH 7 /* AIF1TX3MIX_SRC1 - [6:0] */ | |
| 1736 | ||
| 1737 | /* | |
| 1738 | * R1585 (0x631) - AIF1TX3MIX Input 1 Volume | |
| 1739 | */ | |
| 1740 | #define WM2200_AIF1TX3MIX_VOL1_MASK 0x00FE /* AIF1TX3MIX_VOL1 - [7:1] */ | |
| 1741 | #define WM2200_AIF1TX3MIX_VOL1_SHIFT 1 /* AIF1TX3MIX_VOL1 - [7:1] */ | |
| 1742 | #define WM2200_AIF1TX3MIX_VOL1_WIDTH 7 /* AIF1TX3MIX_VOL1 - [7:1] */ | |
| 1743 | ||
| 1744 | /* | |
| 1745 | * R1586 (0x632) - AIF1TX3MIX Input 2 Source | |
| 1746 | */ | |
| 1747 | #define WM2200_AIF1TX3MIX_SRC2_MASK 0x007F /* AIF1TX3MIX_SRC2 - [6:0] */ | |
| 1748 | #define WM2200_AIF1TX3MIX_SRC2_SHIFT 0 /* AIF1TX3MIX_SRC2 - [6:0] */ | |
| 1749 | #define WM2200_AIF1TX3MIX_SRC2_WIDTH 7 /* AIF1TX3MIX_SRC2 - [6:0] */ | |
| 1750 | ||
| 1751 | /* | |
| 1752 | * R1587 (0x633) - AIF1TX3MIX Input 2 Volume | |
| 1753 | */ | |
| 1754 | #define WM2200_AIF1TX3MIX_VOL2_MASK 0x00FE /* AIF1TX3MIX_VOL2 - [7:1] */ | |
| 1755 | #define WM2200_AIF1TX3MIX_VOL2_SHIFT 1 /* AIF1TX3MIX_VOL2 - [7:1] */ | |
| 1756 | #define WM2200_AIF1TX3MIX_VOL2_WIDTH 7 /* AIF1TX3MIX_VOL2 - [7:1] */ | |
| 1757 | ||
| 1758 | /* | |
| 1759 | * R1588 (0x634) - AIF1TX3MIX Input 3 Source | |
| 1760 | */ | |
| 1761 | #define WM2200_AIF1TX3MIX_SRC3_MASK 0x007F /* AIF1TX3MIX_SRC3 - [6:0] */ | |
| 1762 | #define WM2200_AIF1TX3MIX_SRC3_SHIFT 0 /* AIF1TX3MIX_SRC3 - [6:0] */ | |
| 1763 | #define WM2200_AIF1TX3MIX_SRC3_WIDTH 7 /* AIF1TX3MIX_SRC3 - [6:0] */ | |
| 1764 | ||
| 1765 | /* | |
| 1766 | * R1589 (0x635) - AIF1TX3MIX Input 3 Volume | |
| 1767 | */ | |
| 1768 | #define WM2200_AIF1TX3MIX_VOL3_MASK 0x00FE /* AIF1TX3MIX_VOL3 - [7:1] */ | |
| 1769 | #define WM2200_AIF1TX3MIX_VOL3_SHIFT 1 /* AIF1TX3MIX_VOL3 - [7:1] */ | |
| 1770 | #define WM2200_AIF1TX3MIX_VOL3_WIDTH 7 /* AIF1TX3MIX_VOL3 - [7:1] */ | |
| 1771 | ||
| 1772 | /* | |
| 1773 | * R1590 (0x636) - AIF1TX3MIX Input 4 Source | |
| 1774 | */ | |
| 1775 | #define WM2200_AIF1TX3MIX_SRC4_MASK 0x007F /* AIF1TX3MIX_SRC4 - [6:0] */ | |
| 1776 | #define WM2200_AIF1TX3MIX_SRC4_SHIFT 0 /* AIF1TX3MIX_SRC4 - [6:0] */ | |
| 1777 | #define WM2200_AIF1TX3MIX_SRC4_WIDTH 7 /* AIF1TX3MIX_SRC4 - [6:0] */ | |
| 1778 | ||
| 1779 | /* | |
| 1780 | * R1591 (0x637) - AIF1TX3MIX Input 4 Volume | |
| 1781 | */ | |
| 1782 | #define WM2200_AIF1TX3MIX_VOL4_MASK 0x00FE /* AIF1TX3MIX_VOL4 - [7:1] */ | |
| 1783 | #define WM2200_AIF1TX3MIX_VOL4_SHIFT 1 /* AIF1TX3MIX_VOL4 - [7:1] */ | |
| 1784 | #define WM2200_AIF1TX3MIX_VOL4_WIDTH 7 /* AIF1TX3MIX_VOL4 - [7:1] */ | |
| 1785 | ||
| 1786 | /* | |
| 1787 | * R1592 (0x638) - AIF1TX4MIX Input 1 Source | |
| 1788 | */ | |
| 1789 | #define WM2200_AIF1TX4MIX_SRC1_MASK 0x007F /* AIF1TX4MIX_SRC1 - [6:0] */ | |
| 1790 | #define WM2200_AIF1TX4MIX_SRC1_SHIFT 0 /* AIF1TX4MIX_SRC1 - [6:0] */ | |
| 1791 | #define WM2200_AIF1TX4MIX_SRC1_WIDTH 7 /* AIF1TX4MIX_SRC1 - [6:0] */ | |
| 1792 | ||
| 1793 | /* | |
| 1794 | * R1593 (0x639) - AIF1TX4MIX Input 1 Volume | |
| 1795 | */ | |
| 1796 | #define WM2200_AIF1TX4MIX_VOL1_MASK 0x00FE /* AIF1TX4MIX_VOL1 - [7:1] */ | |
| 1797 | #define WM2200_AIF1TX4MIX_VOL1_SHIFT 1 /* AIF1TX4MIX_VOL1 - [7:1] */ | |
| 1798 | #define WM2200_AIF1TX4MIX_VOL1_WIDTH 7 /* AIF1TX4MIX_VOL1 - [7:1] */ | |
| 1799 | ||
| 1800 | /* | |
| 1801 | * R1594 (0x63A) - AIF1TX4MIX Input 2 Source | |
| 1802 | */ | |
| 1803 | #define WM2200_AIF1TX4MIX_SRC2_MASK 0x007F /* AIF1TX4MIX_SRC2 - [6:0] */ | |
| 1804 | #define WM2200_AIF1TX4MIX_SRC2_SHIFT 0 /* AIF1TX4MIX_SRC2 - [6:0] */ | |
| 1805 | #define WM2200_AIF1TX4MIX_SRC2_WIDTH 7 /* AIF1TX4MIX_SRC2 - [6:0] */ | |
| 1806 | ||
| 1807 | /* | |
| 1808 | * R1595 (0x63B) - AIF1TX4MIX Input 2 Volume | |
| 1809 | */ | |
| 1810 | #define WM2200_AIF1TX4MIX_VOL2_MASK 0x00FE /* AIF1TX4MIX_VOL2 - [7:1] */ | |
| 1811 | #define WM2200_AIF1TX4MIX_VOL2_SHIFT 1 /* AIF1TX4MIX_VOL2 - [7:1] */ | |
| 1812 | #define WM2200_AIF1TX4MIX_VOL2_WIDTH 7 /* AIF1TX4MIX_VOL2 - [7:1] */ | |
| 1813 | ||
| 1814 | /* | |
| 1815 | * R1596 (0x63C) - AIF1TX4MIX Input 3 Source | |
| 1816 | */ | |
| 1817 | #define WM2200_AIF1TX4MIX_SRC3_MASK 0x007F /* AIF1TX4MIX_SRC3 - [6:0] */ | |
| 1818 | #define WM2200_AIF1TX4MIX_SRC3_SHIFT 0 /* AIF1TX4MIX_SRC3 - [6:0] */ | |
| 1819 | #define WM2200_AIF1TX4MIX_SRC3_WIDTH 7 /* AIF1TX4MIX_SRC3 - [6:0] */ | |
| 1820 | ||
| 1821 | /* | |
| 1822 | * R1597 (0x63D) - AIF1TX4MIX Input 3 Volume | |
| 1823 | */ | |
| 1824 | #define WM2200_AIF1TX4MIX_VOL3_MASK 0x00FE /* AIF1TX4MIX_VOL3 - [7:1] */ | |
| 1825 | #define WM2200_AIF1TX4MIX_VOL3_SHIFT 1 /* AIF1TX4MIX_VOL3 - [7:1] */ | |
| 1826 | #define WM2200_AIF1TX4MIX_VOL3_WIDTH 7 /* AIF1TX4MIX_VOL3 - [7:1] */ | |
| 1827 | ||
| 1828 | /* | |
| 1829 | * R1598 (0x63E) - AIF1TX4MIX Input 4 Source | |
| 1830 | */ | |
| 1831 | #define WM2200_AIF1TX4MIX_SRC4_MASK 0x007F /* AIF1TX4MIX_SRC4 - [6:0] */ | |
| 1832 | #define WM2200_AIF1TX4MIX_SRC4_SHIFT 0 /* AIF1TX4MIX_SRC4 - [6:0] */ | |
| 1833 | #define WM2200_AIF1TX4MIX_SRC4_WIDTH 7 /* AIF1TX4MIX_SRC4 - [6:0] */ | |
| 1834 | ||
| 1835 | /* | |
| 1836 | * R1599 (0x63F) - AIF1TX4MIX Input 4 Volume | |
| 1837 | */ | |
| 1838 | #define WM2200_AIF1TX4MIX_VOL4_MASK 0x00FE /* AIF1TX4MIX_VOL4 - [7:1] */ | |
| 1839 | #define WM2200_AIF1TX4MIX_VOL4_SHIFT 1 /* AIF1TX4MIX_VOL4 - [7:1] */ | |
| 1840 | #define WM2200_AIF1TX4MIX_VOL4_WIDTH 7 /* AIF1TX4MIX_VOL4 - [7:1] */ | |
| 1841 | ||
| 1842 | /* | |
| 1843 | * R1600 (0x640) - AIF1TX5MIX Input 1 Source | |
| 1844 | */ | |
| 1845 | #define WM2200_AIF1TX5MIX_SRC1_MASK 0x007F /* AIF1TX5MIX_SRC1 - [6:0] */ | |
| 1846 | #define WM2200_AIF1TX5MIX_SRC1_SHIFT 0 /* AIF1TX5MIX_SRC1 - [6:0] */ | |
| 1847 | #define WM2200_AIF1TX5MIX_SRC1_WIDTH 7 /* AIF1TX5MIX_SRC1 - [6:0] */ | |
| 1848 | ||
| 1849 | /* | |
| 1850 | * R1601 (0x641) - AIF1TX5MIX Input 1 Volume | |
| 1851 | */ | |
| 1852 | #define WM2200_AIF1TX5MIX_VOL1_MASK 0x00FE /* AIF1TX5MIX_VOL1 - [7:1] */ | |
| 1853 | #define WM2200_AIF1TX5MIX_VOL1_SHIFT 1 /* AIF1TX5MIX_VOL1 - [7:1] */ | |
| 1854 | #define WM2200_AIF1TX5MIX_VOL1_WIDTH 7 /* AIF1TX5MIX_VOL1 - [7:1] */ | |
| 1855 | ||
| 1856 | /* | |
| 1857 | * R1602 (0x642) - AIF1TX5MIX Input 2 Source | |
| 1858 | */ | |
| 1859 | #define WM2200_AIF1TX5MIX_SRC2_MASK 0x007F /* AIF1TX5MIX_SRC2 - [6:0] */ | |
| 1860 | #define WM2200_AIF1TX5MIX_SRC2_SHIFT 0 /* AIF1TX5MIX_SRC2 - [6:0] */ | |
| 1861 | #define WM2200_AIF1TX5MIX_SRC2_WIDTH 7 /* AIF1TX5MIX_SRC2 - [6:0] */ | |
| 1862 | ||
| 1863 | /* | |
| 1864 | * R1603 (0x643) - AIF1TX5MIX Input 2 Volume | |
| 1865 | */ | |
| 1866 | #define WM2200_AIF1TX5MIX_VOL2_MASK 0x00FE /* AIF1TX5MIX_VOL2 - [7:1] */ | |
| 1867 | #define WM2200_AIF1TX5MIX_VOL2_SHIFT 1 /* AIF1TX5MIX_VOL2 - [7:1] */ | |
| 1868 | #define WM2200_AIF1TX5MIX_VOL2_WIDTH 7 /* AIF1TX5MIX_VOL2 - [7:1] */ | |
| 1869 | ||
| 1870 | /* | |
| 1871 | * R1604 (0x644) - AIF1TX5MIX Input 3 Source | |
| 1872 | */ | |
| 1873 | #define WM2200_AIF1TX5MIX_SRC3_MASK 0x007F /* AIF1TX5MIX_SRC3 - [6:0] */ | |
| 1874 | #define WM2200_AIF1TX5MIX_SRC3_SHIFT 0 /* AIF1TX5MIX_SRC3 - [6:0] */ | |
| 1875 | #define WM2200_AIF1TX5MIX_SRC3_WIDTH 7 /* AIF1TX5MIX_SRC3 - [6:0] */ | |
| 1876 | ||
| 1877 | /* | |
| 1878 | * R1605 (0x645) - AIF1TX5MIX Input 3 Volume | |
| 1879 | */ | |
| 1880 | #define WM2200_AIF1TX5MIX_VOL3_MASK 0x00FE /* AIF1TX5MIX_VOL3 - [7:1] */ | |
| 1881 | #define WM2200_AIF1TX5MIX_VOL3_SHIFT 1 /* AIF1TX5MIX_VOL3 - [7:1] */ | |
| 1882 | #define WM2200_AIF1TX5MIX_VOL3_WIDTH 7 /* AIF1TX5MIX_VOL3 - [7:1] */ | |
| 1883 | ||
| 1884 | /* | |
| 1885 | * R1606 (0x646) - AIF1TX5MIX Input 4 Source | |
| 1886 | */ | |
| 1887 | #define WM2200_AIF1TX5MIX_SRC4_MASK 0x007F /* AIF1TX5MIX_SRC4 - [6:0] */ | |
| 1888 | #define WM2200_AIF1TX5MIX_SRC4_SHIFT 0 /* AIF1TX5MIX_SRC4 - [6:0] */ | |
| 1889 | #define WM2200_AIF1TX5MIX_SRC4_WIDTH 7 /* AIF1TX5MIX_SRC4 - [6:0] */ | |
| 1890 | ||
| 1891 | /* | |
| 1892 | * R1607 (0x647) - AIF1TX5MIX Input 4 Volume | |
| 1893 | */ | |
| 1894 | #define WM2200_AIF1TX5MIX_VOL4_MASK 0x00FE /* AIF1TX5MIX_VOL4 - [7:1] */ | |
| 1895 | #define WM2200_AIF1TX5MIX_VOL4_SHIFT 1 /* AIF1TX5MIX_VOL4 - [7:1] */ | |
| 1896 | #define WM2200_AIF1TX5MIX_VOL4_WIDTH 7 /* AIF1TX5MIX_VOL4 - [7:1] */ | |
| 1897 | ||
| 1898 | /* | |
| 1899 | * R1608 (0x648) - AIF1TX6MIX Input 1 Source | |
| 1900 | */ | |
| 1901 | #define WM2200_AIF1TX6MIX_SRC1_MASK 0x007F /* AIF1TX6MIX_SRC1 - [6:0] */ | |
| 1902 | #define WM2200_AIF1TX6MIX_SRC1_SHIFT 0 /* AIF1TX6MIX_SRC1 - [6:0] */ | |
| 1903 | #define WM2200_AIF1TX6MIX_SRC1_WIDTH 7 /* AIF1TX6MIX_SRC1 - [6:0] */ | |
| 1904 | ||
| 1905 | /* | |
| 1906 | * R1609 (0x649) - AIF1TX6MIX Input 1 Volume | |
| 1907 | */ | |
| 1908 | #define WM2200_AIF1TX6MIX_VOL1_MASK 0x00FE /* AIF1TX6MIX_VOL1 - [7:1] */ | |
| 1909 | #define WM2200_AIF1TX6MIX_VOL1_SHIFT 1 /* AIF1TX6MIX_VOL1 - [7:1] */ | |
| 1910 | #define WM2200_AIF1TX6MIX_VOL1_WIDTH 7 /* AIF1TX6MIX_VOL1 - [7:1] */ | |
| 1911 | ||
| 1912 | /* | |
| 1913 | * R1610 (0x64A) - AIF1TX6MIX Input 2 Source | |
| 1914 | */ | |
| 1915 | #define WM2200_AIF1TX6MIX_SRC2_MASK 0x007F /* AIF1TX6MIX_SRC2 - [6:0] */ | |
| 1916 | #define WM2200_AIF1TX6MIX_SRC2_SHIFT 0 /* AIF1TX6MIX_SRC2 - [6:0] */ | |
| 1917 | #define WM2200_AIF1TX6MIX_SRC2_WIDTH 7 /* AIF1TX6MIX_SRC2 - [6:0] */ | |
| 1918 | ||
| 1919 | /* | |
| 1920 | * R1611 (0x64B) - AIF1TX6MIX Input 2 Volume | |
| 1921 | */ | |
| 1922 | #define WM2200_AIF1TX6MIX_VOL2_MASK 0x00FE /* AIF1TX6MIX_VOL2 - [7:1] */ | |
| 1923 | #define WM2200_AIF1TX6MIX_VOL2_SHIFT 1 /* AIF1TX6MIX_VOL2 - [7:1] */ | |
| 1924 | #define WM2200_AIF1TX6MIX_VOL2_WIDTH 7 /* AIF1TX6MIX_VOL2 - [7:1] */ | |
| 1925 | ||
| 1926 | /* | |
| 1927 | * R1612 (0x64C) - AIF1TX6MIX Input 3 Source | |
| 1928 | */ | |
| 1929 | #define WM2200_AIF1TX6MIX_SRC3_MASK 0x007F /* AIF1TX6MIX_SRC3 - [6:0] */ | |
| 1930 | #define WM2200_AIF1TX6MIX_SRC3_SHIFT 0 /* AIF1TX6MIX_SRC3 - [6:0] */ | |
| 1931 | #define WM2200_AIF1TX6MIX_SRC3_WIDTH 7 /* AIF1TX6MIX_SRC3 - [6:0] */ | |
| 1932 | ||
| 1933 | /* | |
| 1934 | * R1613 (0x64D) - AIF1TX6MIX Input 3 Volume | |
| 1935 | */ | |
| 1936 | #define WM2200_AIF1TX6MIX_VOL3_MASK 0x00FE /* AIF1TX6MIX_VOL3 - [7:1] */ | |
| 1937 | #define WM2200_AIF1TX6MIX_VOL3_SHIFT 1 /* AIF1TX6MIX_VOL3 - [7:1] */ | |
| 1938 | #define WM2200_AIF1TX6MIX_VOL3_WIDTH 7 /* AIF1TX6MIX_VOL3 - [7:1] */ | |
| 1939 | ||
| 1940 | /* | |
| 1941 | * R1614 (0x64E) - AIF1TX6MIX Input 4 Source | |
| 1942 | */ | |
| 1943 | #define WM2200_AIF1TX6MIX_SRC4_MASK 0x007F /* AIF1TX6MIX_SRC4 - [6:0] */ | |
| 1944 | #define WM2200_AIF1TX6MIX_SRC4_SHIFT 0 /* AIF1TX6MIX_SRC4 - [6:0] */ | |
| 1945 | #define WM2200_AIF1TX6MIX_SRC4_WIDTH 7 /* AIF1TX6MIX_SRC4 - [6:0] */ | |
| 1946 | ||
| 1947 | /* | |
| 1948 | * R1615 (0x64F) - AIF1TX6MIX Input 4 Volume | |
| 1949 | */ | |
| 1950 | #define WM2200_AIF1TX6MIX_VOL4_MASK 0x00FE /* AIF1TX6MIX_VOL4 - [7:1] */ | |
| 1951 | #define WM2200_AIF1TX6MIX_VOL4_SHIFT 1 /* AIF1TX6MIX_VOL4 - [7:1] */ | |
| 1952 | #define WM2200_AIF1TX6MIX_VOL4_WIDTH 7 /* AIF1TX6MIX_VOL4 - [7:1] */ | |
| 1953 | ||
| 1954 | /* | |
| 1955 | * R1616 (0x650) - EQLMIX Input 1 Source | |
| 1956 | */ | |
| 1957 | #define WM2200_EQLMIX_SRC1_MASK 0x007F /* EQLMIX_SRC1 - [6:0] */ | |
| 1958 | #define WM2200_EQLMIX_SRC1_SHIFT 0 /* EQLMIX_SRC1 - [6:0] */ | |
| 1959 | #define WM2200_EQLMIX_SRC1_WIDTH 7 /* EQLMIX_SRC1 - [6:0] */ | |
| 1960 | ||
| 1961 | /* | |
| 1962 | * R1617 (0x651) - EQLMIX Input 1 Volume | |
| 1963 | */ | |
| 1964 | #define WM2200_EQLMIX_VOL1_MASK 0x00FE /* EQLMIX_VOL1 - [7:1] */ | |
| 1965 | #define WM2200_EQLMIX_VOL1_SHIFT 1 /* EQLMIX_VOL1 - [7:1] */ | |
| 1966 | #define WM2200_EQLMIX_VOL1_WIDTH 7 /* EQLMIX_VOL1 - [7:1] */ | |
| 1967 | ||
| 1968 | /* | |
| 1969 | * R1618 (0x652) - EQLMIX Input 2 Source | |
| 1970 | */ | |
| 1971 | #define WM2200_EQLMIX_SRC2_MASK 0x007F /* EQLMIX_SRC2 - [6:0] */ | |
| 1972 | #define WM2200_EQLMIX_SRC2_SHIFT 0 /* EQLMIX_SRC2 - [6:0] */ | |
| 1973 | #define WM2200_EQLMIX_SRC2_WIDTH 7 /* EQLMIX_SRC2 - [6:0] */ | |
| 1974 | ||
| 1975 | /* | |
| 1976 | * R1619 (0x653) - EQLMIX Input 2 Volume | |
| 1977 | */ | |
| 1978 | #define WM2200_EQLMIX_VOL2_MASK 0x00FE /* EQLMIX_VOL2 - [7:1] */ | |
| 1979 | #define WM2200_EQLMIX_VOL2_SHIFT 1 /* EQLMIX_VOL2 - [7:1] */ | |
| 1980 | #define WM2200_EQLMIX_VOL2_WIDTH 7 /* EQLMIX_VOL2 - [7:1] */ | |
| 1981 | ||
| 1982 | /* | |
| 1983 | * R1620 (0x654) - EQLMIX Input 3 Source | |
| 1984 | */ | |
| 1985 | #define WM2200_EQLMIX_SRC3_MASK 0x007F /* EQLMIX_SRC3 - [6:0] */ | |
| 1986 | #define WM2200_EQLMIX_SRC3_SHIFT 0 /* EQLMIX_SRC3 - [6:0] */ | |
| 1987 | #define WM2200_EQLMIX_SRC3_WIDTH 7 /* EQLMIX_SRC3 - [6:0] */ | |
| 1988 | ||
| 1989 | /* | |
| 1990 | * R1621 (0x655) - EQLMIX Input 3 Volume | |
| 1991 | */ | |
| 1992 | #define WM2200_EQLMIX_VOL3_MASK 0x00FE /* EQLMIX_VOL3 - [7:1] */ | |
| 1993 | #define WM2200_EQLMIX_VOL3_SHIFT 1 /* EQLMIX_VOL3 - [7:1] */ | |
| 1994 | #define WM2200_EQLMIX_VOL3_WIDTH 7 /* EQLMIX_VOL3 - [7:1] */ | |
| 1995 | ||
| 1996 | /* | |
| 1997 | * R1622 (0x656) - EQLMIX Input 4 Source | |
| 1998 | */ | |
| 1999 | #define WM2200_EQLMIX_SRC4_MASK 0x007F /* EQLMIX_SRC4 - [6:0] */ | |
| 2000 | #define WM2200_EQLMIX_SRC4_SHIFT 0 /* EQLMIX_SRC4 - [6:0] */ | |
| 2001 | #define WM2200_EQLMIX_SRC4_WIDTH 7 /* EQLMIX_SRC4 - [6:0] */ | |
| 2002 | ||
| 2003 | /* | |
| 2004 | * R1623 (0x657) - EQLMIX Input 4 Volume | |
| 2005 | */ | |
| 2006 | #define WM2200_EQLMIX_VOL4_MASK 0x00FE /* EQLMIX_VOL4 - [7:1] */ | |
| 2007 | #define WM2200_EQLMIX_VOL4_SHIFT 1 /* EQLMIX_VOL4 - [7:1] */ | |
| 2008 | #define WM2200_EQLMIX_VOL4_WIDTH 7 /* EQLMIX_VOL4 - [7:1] */ | |
| 2009 | ||
| 2010 | /* | |
| 2011 | * R1624 (0x658) - EQRMIX Input 1 Source | |
| 2012 | */ | |
| 2013 | #define WM2200_EQRMIX_SRC1_MASK 0x007F /* EQRMIX_SRC1 - [6:0] */ | |
| 2014 | #define WM2200_EQRMIX_SRC1_SHIFT 0 /* EQRMIX_SRC1 - [6:0] */ | |
| 2015 | #define WM2200_EQRMIX_SRC1_WIDTH 7 /* EQRMIX_SRC1 - [6:0] */ | |
| 2016 | ||
| 2017 | /* | |
| 2018 | * R1625 (0x659) - EQRMIX Input 1 Volume | |
| 2019 | */ | |
| 2020 | #define WM2200_EQRMIX_VOL1_MASK 0x00FE /* EQRMIX_VOL1 - [7:1] */ | |
| 2021 | #define WM2200_EQRMIX_VOL1_SHIFT 1 /* EQRMIX_VOL1 - [7:1] */ | |
| 2022 | #define WM2200_EQRMIX_VOL1_WIDTH 7 /* EQRMIX_VOL1 - [7:1] */ | |
| 2023 | ||
| 2024 | /* | |
| 2025 | * R1626 (0x65A) - EQRMIX Input 2 Source | |
| 2026 | */ | |
| 2027 | #define WM2200_EQRMIX_SRC2_MASK 0x007F /* EQRMIX_SRC2 - [6:0] */ | |
| 2028 | #define WM2200_EQRMIX_SRC2_SHIFT 0 /* EQRMIX_SRC2 - [6:0] */ | |
| 2029 | #define WM2200_EQRMIX_SRC2_WIDTH 7 /* EQRMIX_SRC2 - [6:0] */ | |
| 2030 | ||
| 2031 | /* | |
| 2032 | * R1627 (0x65B) - EQRMIX Input 2 Volume | |
| 2033 | */ | |
| 2034 | #define WM2200_EQRMIX_VOL2_MASK 0x00FE /* EQRMIX_VOL2 - [7:1] */ | |
| 2035 | #define WM2200_EQRMIX_VOL2_SHIFT 1 /* EQRMIX_VOL2 - [7:1] */ | |
| 2036 | #define WM2200_EQRMIX_VOL2_WIDTH 7 /* EQRMIX_VOL2 - [7:1] */ | |
| 2037 | ||
| 2038 | /* | |
| 2039 | * R1628 (0x65C) - EQRMIX Input 3 Source | |
| 2040 | */ | |
| 2041 | #define WM2200_EQRMIX_SRC3_MASK 0x007F /* EQRMIX_SRC3 - [6:0] */ | |
| 2042 | #define WM2200_EQRMIX_SRC3_SHIFT 0 /* EQRMIX_SRC3 - [6:0] */ | |
| 2043 | #define WM2200_EQRMIX_SRC3_WIDTH 7 /* EQRMIX_SRC3 - [6:0] */ | |
| 2044 | ||
| 2045 | /* | |
| 2046 | * R1629 (0x65D) - EQRMIX Input 3 Volume | |
| 2047 | */ | |
| 2048 | #define WM2200_EQRMIX_VOL3_MASK 0x00FE /* EQRMIX_VOL3 - [7:1] */ | |
| 2049 | #define WM2200_EQRMIX_VOL3_SHIFT 1 /* EQRMIX_VOL3 - [7:1] */ | |
| 2050 | #define WM2200_EQRMIX_VOL3_WIDTH 7 /* EQRMIX_VOL3 - [7:1] */ | |
| 2051 | ||
| 2052 | /* | |
| 2053 | * R1630 (0x65E) - EQRMIX Input 4 Source | |
| 2054 | */ | |
| 2055 | #define WM2200_EQRMIX_SRC4_MASK 0x007F /* EQRMIX_SRC4 - [6:0] */ | |
| 2056 | #define WM2200_EQRMIX_SRC4_SHIFT 0 /* EQRMIX_SRC4 - [6:0] */ | |
| 2057 | #define WM2200_EQRMIX_SRC4_WIDTH 7 /* EQRMIX_SRC4 - [6:0] */ | |
| 2058 | ||
| 2059 | /* | |
| 2060 | * R1631 (0x65F) - EQRMIX Input 4 Volume | |
| 2061 | */ | |
| 2062 | #define WM2200_EQRMIX_VOL4_MASK 0x00FE /* EQRMIX_VOL4 - [7:1] */ | |
| 2063 | #define WM2200_EQRMIX_VOL4_SHIFT 1 /* EQRMIX_VOL4 - [7:1] */ | |
| 2064 | #define WM2200_EQRMIX_VOL4_WIDTH 7 /* EQRMIX_VOL4 - [7:1] */ | |
| 2065 | ||
| 2066 | /* | |
| 2067 | * R1632 (0x660) - LHPF1MIX Input 1 Source | |
| 2068 | */ | |
| 2069 | #define WM2200_LHPF1MIX_SRC1_MASK 0x007F /* LHPF1MIX_SRC1 - [6:0] */ | |
| 2070 | #define WM2200_LHPF1MIX_SRC1_SHIFT 0 /* LHPF1MIX_SRC1 - [6:0] */ | |
| 2071 | #define WM2200_LHPF1MIX_SRC1_WIDTH 7 /* LHPF1MIX_SRC1 - [6:0] */ | |
| 2072 | ||
| 2073 | /* | |
| 2074 | * R1633 (0x661) - LHPF1MIX Input 1 Volume | |
| 2075 | */ | |
| 2076 | #define WM2200_LHPF1MIX_VOL1_MASK 0x00FE /* LHPF1MIX_VOL1 - [7:1] */ | |
| 2077 | #define WM2200_LHPF1MIX_VOL1_SHIFT 1 /* LHPF1MIX_VOL1 - [7:1] */ | |
| 2078 | #define WM2200_LHPF1MIX_VOL1_WIDTH 7 /* LHPF1MIX_VOL1 - [7:1] */ | |
| 2079 | ||
| 2080 | /* | |
| 2081 | * R1634 (0x662) - LHPF1MIX Input 2 Source | |
| 2082 | */ | |
| 2083 | #define WM2200_LHPF1MIX_SRC2_MASK 0x007F /* LHPF1MIX_SRC2 - [6:0] */ | |
| 2084 | #define WM2200_LHPF1MIX_SRC2_SHIFT 0 /* LHPF1MIX_SRC2 - [6:0] */ | |
| 2085 | #define WM2200_LHPF1MIX_SRC2_WIDTH 7 /* LHPF1MIX_SRC2 - [6:0] */ | |
| 2086 | ||
| 2087 | /* | |
| 2088 | * R1635 (0x663) - LHPF1MIX Input 2 Volume | |
| 2089 | */ | |
| 2090 | #define WM2200_LHPF1MIX_VOL2_MASK 0x00FE /* LHPF1MIX_VOL2 - [7:1] */ | |
| 2091 | #define WM2200_LHPF1MIX_VOL2_SHIFT 1 /* LHPF1MIX_VOL2 - [7:1] */ | |
| 2092 | #define WM2200_LHPF1MIX_VOL2_WIDTH 7 /* LHPF1MIX_VOL2 - [7:1] */ | |
| 2093 | ||
| 2094 | /* | |
| 2095 | * R1636 (0x664) - LHPF1MIX Input 3 Source | |
| 2096 | */ | |
| 2097 | #define WM2200_LHPF1MIX_SRC3_MASK 0x007F /* LHPF1MIX_SRC3 - [6:0] */ | |
| 2098 | #define WM2200_LHPF1MIX_SRC3_SHIFT 0 /* LHPF1MIX_SRC3 - [6:0] */ | |
| 2099 | #define WM2200_LHPF1MIX_SRC3_WIDTH 7 /* LHPF1MIX_SRC3 - [6:0] */ | |
| 2100 | ||
| 2101 | /* | |
| 2102 | * R1637 (0x665) - LHPF1MIX Input 3 Volume | |
| 2103 | */ | |
| 2104 | #define WM2200_LHPF1MIX_VOL3_MASK 0x00FE /* LHPF1MIX_VOL3 - [7:1] */ | |
| 2105 | #define WM2200_LHPF1MIX_VOL3_SHIFT 1 /* LHPF1MIX_VOL3 - [7:1] */ | |
| 2106 | #define WM2200_LHPF1MIX_VOL3_WIDTH 7 /* LHPF1MIX_VOL3 - [7:1] */ | |
| 2107 | ||
| 2108 | /* | |
| 2109 | * R1638 (0x666) - LHPF1MIX Input 4 Source | |
| 2110 | */ | |
| 2111 | #define WM2200_LHPF1MIX_SRC4_MASK 0x007F /* LHPF1MIX_SRC4 - [6:0] */ | |
| 2112 | #define WM2200_LHPF1MIX_SRC4_SHIFT 0 /* LHPF1MIX_SRC4 - [6:0] */ | |
| 2113 | #define WM2200_LHPF1MIX_SRC4_WIDTH 7 /* LHPF1MIX_SRC4 - [6:0] */ | |
| 2114 | ||
| 2115 | /* | |
| 2116 | * R1639 (0x667) - LHPF1MIX Input 4 Volume | |
| 2117 | */ | |
| 2118 | #define WM2200_LHPF1MIX_VOL4_MASK 0x00FE /* LHPF1MIX_VOL4 - [7:1] */ | |
| 2119 | #define WM2200_LHPF1MIX_VOL4_SHIFT 1 /* LHPF1MIX_VOL4 - [7:1] */ | |
| 2120 | #define WM2200_LHPF1MIX_VOL4_WIDTH 7 /* LHPF1MIX_VOL4 - [7:1] */ | |
| 2121 | ||
| 2122 | /* | |
| 2123 | * R1640 (0x668) - LHPF2MIX Input 1 Source | |
| 2124 | */ | |
| 2125 | #define WM2200_LHPF2MIX_SRC1_MASK 0x007F /* LHPF2MIX_SRC1 - [6:0] */ | |
| 2126 | #define WM2200_LHPF2MIX_SRC1_SHIFT 0 /* LHPF2MIX_SRC1 - [6:0] */ | |
| 2127 | #define WM2200_LHPF2MIX_SRC1_WIDTH 7 /* LHPF2MIX_SRC1 - [6:0] */ | |
| 2128 | ||
| 2129 | /* | |
| 2130 | * R1641 (0x669) - LHPF2MIX Input 1 Volume | |
| 2131 | */ | |
| 2132 | #define WM2200_LHPF2MIX_VOL1_MASK 0x00FE /* LHPF2MIX_VOL1 - [7:1] */ | |
| 2133 | #define WM2200_LHPF2MIX_VOL1_SHIFT 1 /* LHPF2MIX_VOL1 - [7:1] */ | |
| 2134 | #define WM2200_LHPF2MIX_VOL1_WIDTH 7 /* LHPF2MIX_VOL1 - [7:1] */ | |
| 2135 | ||
| 2136 | /* | |
| 2137 | * R1642 (0x66A) - LHPF2MIX Input 2 Source | |
| 2138 | */ | |
| 2139 | #define WM2200_LHPF2MIX_SRC2_MASK 0x007F /* LHPF2MIX_SRC2 - [6:0] */ | |
| 2140 | #define WM2200_LHPF2MIX_SRC2_SHIFT 0 /* LHPF2MIX_SRC2 - [6:0] */ | |
| 2141 | #define WM2200_LHPF2MIX_SRC2_WIDTH 7 /* LHPF2MIX_SRC2 - [6:0] */ | |
| 2142 | ||
| 2143 | /* | |
| 2144 | * R1643 (0x66B) - LHPF2MIX Input 2 Volume | |
| 2145 | */ | |
| 2146 | #define WM2200_LHPF2MIX_VOL2_MASK 0x00FE /* LHPF2MIX_VOL2 - [7:1] */ | |
| 2147 | #define WM2200_LHPF2MIX_VOL2_SHIFT 1 /* LHPF2MIX_VOL2 - [7:1] */ | |
| 2148 | #define WM2200_LHPF2MIX_VOL2_WIDTH 7 /* LHPF2MIX_VOL2 - [7:1] */ | |
| 2149 | ||
| 2150 | /* | |
| 2151 | * R1644 (0x66C) - LHPF2MIX Input 3 Source | |
| 2152 | */ | |
| 2153 | #define WM2200_LHPF2MIX_SRC3_MASK 0x007F /* LHPF2MIX_SRC3 - [6:0] */ | |
| 2154 | #define WM2200_LHPF2MIX_SRC3_SHIFT 0 /* LHPF2MIX_SRC3 - [6:0] */ | |
| 2155 | #define WM2200_LHPF2MIX_SRC3_WIDTH 7 /* LHPF2MIX_SRC3 - [6:0] */ | |
| 2156 | ||
| 2157 | /* | |
| 2158 | * R1645 (0x66D) - LHPF2MIX Input 3 Volume | |
| 2159 | */ | |
| 2160 | #define WM2200_LHPF2MIX_VOL3_MASK 0x00FE /* LHPF2MIX_VOL3 - [7:1] */ | |
| 2161 | #define WM2200_LHPF2MIX_VOL3_SHIFT 1 /* LHPF2MIX_VOL3 - [7:1] */ | |
| 2162 | #define WM2200_LHPF2MIX_VOL3_WIDTH 7 /* LHPF2MIX_VOL3 - [7:1] */ | |
| 2163 | ||
| 2164 | /* | |
| 2165 | * R1646 (0x66E) - LHPF2MIX Input 4 Source | |
| 2166 | */ | |
| 2167 | #define WM2200_LHPF2MIX_SRC4_MASK 0x007F /* LHPF2MIX_SRC4 - [6:0] */ | |
| 2168 | #define WM2200_LHPF2MIX_SRC4_SHIFT 0 /* LHPF2MIX_SRC4 - [6:0] */ | |
| 2169 | #define WM2200_LHPF2MIX_SRC4_WIDTH 7 /* LHPF2MIX_SRC4 - [6:0] */ | |
| 2170 | ||
| 2171 | /* | |
| 2172 | * R1647 (0x66F) - LHPF2MIX Input 4 Volume | |
| 2173 | */ | |
| 2174 | #define WM2200_LHPF2MIX_VOL4_MASK 0x00FE /* LHPF2MIX_VOL4 - [7:1] */ | |
| 2175 | #define WM2200_LHPF2MIX_VOL4_SHIFT 1 /* LHPF2MIX_VOL4 - [7:1] */ | |
| 2176 | #define WM2200_LHPF2MIX_VOL4_WIDTH 7 /* LHPF2MIX_VOL4 - [7:1] */ | |
| 2177 | ||
| 2178 | /* | |
| 2179 | * R1648 (0x670) - DSP1LMIX Input 1 Source | |
| 2180 | */ | |
| 2181 | #define WM2200_DSP1LMIX_SRC1_MASK 0x007F /* DSP1LMIX_SRC1 - [6:0] */ | |
| 2182 | #define WM2200_DSP1LMIX_SRC1_SHIFT 0 /* DSP1LMIX_SRC1 - [6:0] */ | |
| 2183 | #define WM2200_DSP1LMIX_SRC1_WIDTH 7 /* DSP1LMIX_SRC1 - [6:0] */ | |
| 2184 | ||
| 2185 | /* | |
| 2186 | * R1649 (0x671) - DSP1LMIX Input 1 Volume | |
| 2187 | */ | |
| 2188 | #define WM2200_DSP1LMIX_VOL1_MASK 0x00FE /* DSP1LMIX_VOL1 - [7:1] */ | |
| 2189 | #define WM2200_DSP1LMIX_VOL1_SHIFT 1 /* DSP1LMIX_VOL1 - [7:1] */ | |
| 2190 | #define WM2200_DSP1LMIX_VOL1_WIDTH 7 /* DSP1LMIX_VOL1 - [7:1] */ | |
| 2191 | ||
| 2192 | /* | |
| 2193 | * R1650 (0x672) - DSP1LMIX Input 2 Source | |
| 2194 | */ | |
| 2195 | #define WM2200_DSP1LMIX_SRC2_MASK 0x007F /* DSP1LMIX_SRC2 - [6:0] */ | |
| 2196 | #define WM2200_DSP1LMIX_SRC2_SHIFT 0 /* DSP1LMIX_SRC2 - [6:0] */ | |
| 2197 | #define WM2200_DSP1LMIX_SRC2_WIDTH 7 /* DSP1LMIX_SRC2 - [6:0] */ | |
| 2198 | ||
| 2199 | /* | |
| 2200 | * R1651 (0x673) - DSP1LMIX Input 2 Volume | |
| 2201 | */ | |
| 2202 | #define WM2200_DSP1LMIX_VOL2_MASK 0x00FE /* DSP1LMIX_VOL2 - [7:1] */ | |
| 2203 | #define WM2200_DSP1LMIX_VOL2_SHIFT 1 /* DSP1LMIX_VOL2 - [7:1] */ | |
| 2204 | #define WM2200_DSP1LMIX_VOL2_WIDTH 7 /* DSP1LMIX_VOL2 - [7:1] */ | |
| 2205 | ||
| 2206 | /* | |
| 2207 | * R1652 (0x674) - DSP1LMIX Input 3 Source | |
| 2208 | */ | |
| 2209 | #define WM2200_DSP1LMIX_SRC3_MASK 0x007F /* DSP1LMIX_SRC3 - [6:0] */ | |
| 2210 | #define WM2200_DSP1LMIX_SRC3_SHIFT 0 /* DSP1LMIX_SRC3 - [6:0] */ | |
| 2211 | #define WM2200_DSP1LMIX_SRC3_WIDTH 7 /* DSP1LMIX_SRC3 - [6:0] */ | |
| 2212 | ||
| 2213 | /* | |
| 2214 | * R1653 (0x675) - DSP1LMIX Input 3 Volume | |
| 2215 | */ | |
| 2216 | #define WM2200_DSP1LMIX_VOL3_MASK 0x00FE /* DSP1LMIX_VOL3 - [7:1] */ | |
| 2217 | #define WM2200_DSP1LMIX_VOL3_SHIFT 1 /* DSP1LMIX_VOL3 - [7:1] */ | |
| 2218 | #define WM2200_DSP1LMIX_VOL3_WIDTH 7 /* DSP1LMIX_VOL3 - [7:1] */ | |
| 2219 | ||
| 2220 | /* | |
| 2221 | * R1654 (0x676) - DSP1LMIX Input 4 Source | |
| 2222 | */ | |
| 2223 | #define WM2200_DSP1LMIX_SRC4_MASK 0x007F /* DSP1LMIX_SRC4 - [6:0] */ | |
| 2224 | #define WM2200_DSP1LMIX_SRC4_SHIFT 0 /* DSP1LMIX_SRC4 - [6:0] */ | |
| 2225 | #define WM2200_DSP1LMIX_SRC4_WIDTH 7 /* DSP1LMIX_SRC4 - [6:0] */ | |
| 2226 | ||
| 2227 | /* | |
| 2228 | * R1655 (0x677) - DSP1LMIX Input 4 Volume | |
| 2229 | */ | |
| 2230 | #define WM2200_DSP1LMIX_VOL4_MASK 0x00FE /* DSP1LMIX_VOL4 - [7:1] */ | |
| 2231 | #define WM2200_DSP1LMIX_VOL4_SHIFT 1 /* DSP1LMIX_VOL4 - [7:1] */ | |
| 2232 | #define WM2200_DSP1LMIX_VOL4_WIDTH 7 /* DSP1LMIX_VOL4 - [7:1] */ | |
| 2233 | ||
| 2234 | /* | |
| 2235 | * R1656 (0x678) - DSP1RMIX Input 1 Source | |
| 2236 | */ | |
| 2237 | #define WM2200_DSP1RMIX_SRC1_MASK 0x007F /* DSP1RMIX_SRC1 - [6:0] */ | |
| 2238 | #define WM2200_DSP1RMIX_SRC1_SHIFT 0 /* DSP1RMIX_SRC1 - [6:0] */ | |
| 2239 | #define WM2200_DSP1RMIX_SRC1_WIDTH 7 /* DSP1RMIX_SRC1 - [6:0] */ | |
| 2240 | ||
| 2241 | /* | |
| 2242 | * R1657 (0x679) - DSP1RMIX Input 1 Volume | |
| 2243 | */ | |
| 2244 | #define WM2200_DSP1RMIX_VOL1_MASK 0x00FE /* DSP1RMIX_VOL1 - [7:1] */ | |
| 2245 | #define WM2200_DSP1RMIX_VOL1_SHIFT 1 /* DSP1RMIX_VOL1 - [7:1] */ | |
| 2246 | #define WM2200_DSP1RMIX_VOL1_WIDTH 7 /* DSP1RMIX_VOL1 - [7:1] */ | |
| 2247 | ||
| 2248 | /* | |
| 2249 | * R1658 (0x67A) - DSP1RMIX Input 2 Source | |
| 2250 | */ | |
| 2251 | #define WM2200_DSP1RMIX_SRC2_MASK 0x007F /* DSP1RMIX_SRC2 - [6:0] */ | |
| 2252 | #define WM2200_DSP1RMIX_SRC2_SHIFT 0 /* DSP1RMIX_SRC2 - [6:0] */ | |
| 2253 | #define WM2200_DSP1RMIX_SRC2_WIDTH 7 /* DSP1RMIX_SRC2 - [6:0] */ | |
| 2254 | ||
| 2255 | /* | |
| 2256 | * R1659 (0x67B) - DSP1RMIX Input 2 Volume | |
| 2257 | */ | |
| 2258 | #define WM2200_DSP1RMIX_VOL2_MASK 0x00FE /* DSP1RMIX_VOL2 - [7:1] */ | |
| 2259 | #define WM2200_DSP1RMIX_VOL2_SHIFT 1 /* DSP1RMIX_VOL2 - [7:1] */ | |
| 2260 | #define WM2200_DSP1RMIX_VOL2_WIDTH 7 /* DSP1RMIX_VOL2 - [7:1] */ | |
| 2261 | ||
| 2262 | /* | |
| 2263 | * R1660 (0x67C) - DSP1RMIX Input 3 Source | |
| 2264 | */ | |
| 2265 | #define WM2200_DSP1RMIX_SRC3_MASK 0x007F /* DSP1RMIX_SRC3 - [6:0] */ | |
| 2266 | #define WM2200_DSP1RMIX_SRC3_SHIFT 0 /* DSP1RMIX_SRC3 - [6:0] */ | |
| 2267 | #define WM2200_DSP1RMIX_SRC3_WIDTH 7 /* DSP1RMIX_SRC3 - [6:0] */ | |
| 2268 | ||
| 2269 | /* | |
| 2270 | * R1661 (0x67D) - DSP1RMIX Input 3 Volume | |
| 2271 | */ | |
| 2272 | #define WM2200_DSP1RMIX_VOL3_MASK 0x00FE /* DSP1RMIX_VOL3 - [7:1] */ | |
| 2273 | #define WM2200_DSP1RMIX_VOL3_SHIFT 1 /* DSP1RMIX_VOL3 - [7:1] */ | |
| 2274 | #define WM2200_DSP1RMIX_VOL3_WIDTH 7 /* DSP1RMIX_VOL3 - [7:1] */ | |
| 2275 | ||
| 2276 | /* | |
| 2277 | * R1662 (0x67E) - DSP1RMIX Input 4 Source | |
| 2278 | */ | |
| 2279 | #define WM2200_DSP1RMIX_SRC4_MASK 0x007F /* DSP1RMIX_SRC4 - [6:0] */ | |
| 2280 | #define WM2200_DSP1RMIX_SRC4_SHIFT 0 /* DSP1RMIX_SRC4 - [6:0] */ | |
| 2281 | #define WM2200_DSP1RMIX_SRC4_WIDTH 7 /* DSP1RMIX_SRC4 - [6:0] */ | |
| 2282 | ||
| 2283 | /* | |
| 2284 | * R1663 (0x67F) - DSP1RMIX Input 4 Volume | |
| 2285 | */ | |
| 2286 | #define WM2200_DSP1RMIX_VOL4_MASK 0x00FE /* DSP1RMIX_VOL4 - [7:1] */ | |
| 2287 | #define WM2200_DSP1RMIX_VOL4_SHIFT 1 /* DSP1RMIX_VOL4 - [7:1] */ | |
| 2288 | #define WM2200_DSP1RMIX_VOL4_WIDTH 7 /* DSP1RMIX_VOL4 - [7:1] */ | |
| 2289 | ||
| 2290 | /* | |
| 2291 | * R1664 (0x680) - DSP1AUX1MIX Input 1 Source | |
| 2292 | */ | |
| 2293 | #define WM2200_DSP1AUX1MIX_SRC1_MASK 0x007F /* DSP1AUX1MIX_SRC1 - [6:0] */ | |
| 2294 | #define WM2200_DSP1AUX1MIX_SRC1_SHIFT 0 /* DSP1AUX1MIX_SRC1 - [6:0] */ | |
| 2295 | #define WM2200_DSP1AUX1MIX_SRC1_WIDTH 7 /* DSP1AUX1MIX_SRC1 - [6:0] */ | |
| 2296 | ||
| 2297 | /* | |
| 2298 | * R1665 (0x681) - DSP1AUX2MIX Input 1 Source | |
| 2299 | */ | |
| 2300 | #define WM2200_DSP1AUX2MIX_SRC1_MASK 0x007F /* DSP1AUX2MIX_SRC1 - [6:0] */ | |
| 2301 | #define WM2200_DSP1AUX2MIX_SRC1_SHIFT 0 /* DSP1AUX2MIX_SRC1 - [6:0] */ | |
| 2302 | #define WM2200_DSP1AUX2MIX_SRC1_WIDTH 7 /* DSP1AUX2MIX_SRC1 - [6:0] */ | |
| 2303 | ||
| 2304 | /* | |
| 2305 | * R1666 (0x682) - DSP1AUX3MIX Input 1 Source | |
| 2306 | */ | |
| 2307 | #define WM2200_DSP1AUX3MIX_SRC1_MASK 0x007F /* DSP1AUX3MIX_SRC1 - [6:0] */ | |
| 2308 | #define WM2200_DSP1AUX3MIX_SRC1_SHIFT 0 /* DSP1AUX3MIX_SRC1 - [6:0] */ | |
| 2309 | #define WM2200_DSP1AUX3MIX_SRC1_WIDTH 7 /* DSP1AUX3MIX_SRC1 - [6:0] */ | |
| 2310 | ||
| 2311 | /* | |
| 2312 | * R1667 (0x683) - DSP1AUX4MIX Input 1 Source | |
| 2313 | */ | |
| 2314 | #define WM2200_DSP1AUX4MIX_SRC1_MASK 0x007F /* DSP1AUX4MIX_SRC1 - [6:0] */ | |
| 2315 | #define WM2200_DSP1AUX4MIX_SRC1_SHIFT 0 /* DSP1AUX4MIX_SRC1 - [6:0] */ | |
| 2316 | #define WM2200_DSP1AUX4MIX_SRC1_WIDTH 7 /* DSP1AUX4MIX_SRC1 - [6:0] */ | |
| 2317 | ||
| 2318 | /* | |
| 2319 | * R1668 (0x684) - DSP1AUX5MIX Input 1 Source | |
| 2320 | */ | |
| 2321 | #define WM2200_DSP1AUX5MIX_SRC1_MASK 0x007F /* DSP1AUX5MIX_SRC1 - [6:0] */ | |
| 2322 | #define WM2200_DSP1AUX5MIX_SRC1_SHIFT 0 /* DSP1AUX5MIX_SRC1 - [6:0] */ | |
| 2323 | #define WM2200_DSP1AUX5MIX_SRC1_WIDTH 7 /* DSP1AUX5MIX_SRC1 - [6:0] */ | |
| 2324 | ||
| 2325 | /* | |
| 2326 | * R1669 (0x685) - DSP1AUX6MIX Input 1 Source | |
| 2327 | */ | |
| 2328 | #define WM2200_DSP1AUX6MIX_SRC1_MASK 0x007F /* DSP1AUX6MIX_SRC1 - [6:0] */ | |
| 2329 | #define WM2200_DSP1AUX6MIX_SRC1_SHIFT 0 /* DSP1AUX6MIX_SRC1 - [6:0] */ | |
| 2330 | #define WM2200_DSP1AUX6MIX_SRC1_WIDTH 7 /* DSP1AUX6MIX_SRC1 - [6:0] */ | |
| 2331 | ||
| 2332 | /* | |
| 2333 | * R1670 (0x686) - DSP2LMIX Input 1 Source | |
| 2334 | */ | |
| 2335 | #define WM2200_DSP2LMIX_SRC1_MASK 0x007F /* DSP2LMIX_SRC1 - [6:0] */ | |
| 2336 | #define WM2200_DSP2LMIX_SRC1_SHIFT 0 /* DSP2LMIX_SRC1 - [6:0] */ | |
| 2337 | #define WM2200_DSP2LMIX_SRC1_WIDTH 7 /* DSP2LMIX_SRC1 - [6:0] */ | |
| 2338 | ||
| 2339 | /* | |
| 2340 | * R1671 (0x687) - DSP2LMIX Input 1 Volume | |
| 2341 | */ | |
| 2342 | #define WM2200_DSP2LMIX_VOL1_MASK 0x00FE /* DSP2LMIX_VOL1 - [7:1] */ | |
| 2343 | #define WM2200_DSP2LMIX_VOL1_SHIFT 1 /* DSP2LMIX_VOL1 - [7:1] */ | |
| 2344 | #define WM2200_DSP2LMIX_VOL1_WIDTH 7 /* DSP2LMIX_VOL1 - [7:1] */ | |
| 2345 | ||
| 2346 | /* | |
| 2347 | * R1672 (0x688) - DSP2LMIX Input 2 Source | |
| 2348 | */ | |
| 2349 | #define WM2200_DSP2LMIX_SRC2_MASK 0x007F /* DSP2LMIX_SRC2 - [6:0] */ | |
| 2350 | #define WM2200_DSP2LMIX_SRC2_SHIFT 0 /* DSP2LMIX_SRC2 - [6:0] */ | |
| 2351 | #define WM2200_DSP2LMIX_SRC2_WIDTH 7 /* DSP2LMIX_SRC2 - [6:0] */ | |
| 2352 | ||
| 2353 | /* | |
| 2354 | * R1673 (0x689) - DSP2LMIX Input 2 Volume | |
| 2355 | */ | |
| 2356 | #define WM2200_DSP2LMIX_VOL2_MASK 0x00FE /* DSP2LMIX_VOL2 - [7:1] */ | |
| 2357 | #define WM2200_DSP2LMIX_VOL2_SHIFT 1 /* DSP2LMIX_VOL2 - [7:1] */ | |
| 2358 | #define WM2200_DSP2LMIX_VOL2_WIDTH 7 /* DSP2LMIX_VOL2 - [7:1] */ | |
| 2359 | ||
| 2360 | /* | |
| 2361 | * R1674 (0x68A) - DSP2LMIX Input 3 Source | |
| 2362 | */ | |
| 2363 | #define WM2200_DSP2LMIX_SRC3_MASK 0x007F /* DSP2LMIX_SRC3 - [6:0] */ | |
| 2364 | #define WM2200_DSP2LMIX_SRC3_SHIFT 0 /* DSP2LMIX_SRC3 - [6:0] */ | |
| 2365 | #define WM2200_DSP2LMIX_SRC3_WIDTH 7 /* DSP2LMIX_SRC3 - [6:0] */ | |
| 2366 | ||
| 2367 | /* | |
| 2368 | * R1675 (0x68B) - DSP2LMIX Input 3 Volume | |
| 2369 | */ | |
| 2370 | #define WM2200_DSP2LMIX_VOL3_MASK 0x00FE /* DSP2LMIX_VOL3 - [7:1] */ | |
| 2371 | #define WM2200_DSP2LMIX_VOL3_SHIFT 1 /* DSP2LMIX_VOL3 - [7:1] */ | |
| 2372 | #define WM2200_DSP2LMIX_VOL3_WIDTH 7 /* DSP2LMIX_VOL3 - [7:1] */ | |
| 2373 | ||
| 2374 | /* | |
| 2375 | * R1676 (0x68C) - DSP2LMIX Input 4 Source | |
| 2376 | */ | |
| 2377 | #define WM2200_DSP2LMIX_SRC4_MASK 0x007F /* DSP2LMIX_SRC4 - [6:0] */ | |
| 2378 | #define WM2200_DSP2LMIX_SRC4_SHIFT 0 /* DSP2LMIX_SRC4 - [6:0] */ | |
| 2379 | #define WM2200_DSP2LMIX_SRC4_WIDTH 7 /* DSP2LMIX_SRC4 - [6:0] */ | |
| 2380 | ||
| 2381 | /* | |
| 2382 | * R1677 (0x68D) - DSP2LMIX Input 4 Volume | |
| 2383 | */ | |
| 2384 | #define WM2200_DSP2LMIX_VOL4_MASK 0x00FE /* DSP2LMIX_VOL4 - [7:1] */ | |
| 2385 | #define WM2200_DSP2LMIX_VOL4_SHIFT 1 /* DSP2LMIX_VOL4 - [7:1] */ | |
| 2386 | #define WM2200_DSP2LMIX_VOL4_WIDTH 7 /* DSP2LMIX_VOL4 - [7:1] */ | |
| 2387 | ||
| 2388 | /* | |
| 2389 | * R1678 (0x68E) - DSP2RMIX Input 1 Source | |
| 2390 | */ | |
| 2391 | #define WM2200_DSP2RMIX_SRC1_MASK 0x007F /* DSP2RMIX_SRC1 - [6:0] */ | |
| 2392 | #define WM2200_DSP2RMIX_SRC1_SHIFT 0 /* DSP2RMIX_SRC1 - [6:0] */ | |
| 2393 | #define WM2200_DSP2RMIX_SRC1_WIDTH 7 /* DSP2RMIX_SRC1 - [6:0] */ | |
| 2394 | ||
| 2395 | /* | |
| 2396 | * R1679 (0x68F) - DSP2RMIX Input 1 Volume | |
| 2397 | */ | |
| 2398 | #define WM2200_DSP2RMIX_VOL1_MASK 0x00FE /* DSP2RMIX_VOL1 - [7:1] */ | |
| 2399 | #define WM2200_DSP2RMIX_VOL1_SHIFT 1 /* DSP2RMIX_VOL1 - [7:1] */ | |
| 2400 | #define WM2200_DSP2RMIX_VOL1_WIDTH 7 /* DSP2RMIX_VOL1 - [7:1] */ | |
| 2401 | ||
| 2402 | /* | |
| 2403 | * R1680 (0x690) - DSP2RMIX Input 2 Source | |
| 2404 | */ | |
| 2405 | #define WM2200_DSP2RMIX_SRC2_MASK 0x007F /* DSP2RMIX_SRC2 - [6:0] */ | |
| 2406 | #define WM2200_DSP2RMIX_SRC2_SHIFT 0 /* DSP2RMIX_SRC2 - [6:0] */ | |
| 2407 | #define WM2200_DSP2RMIX_SRC2_WIDTH 7 /* DSP2RMIX_SRC2 - [6:0] */ | |
| 2408 | ||
| 2409 | /* | |
| 2410 | * R1681 (0x691) - DSP2RMIX Input 2 Volume | |
| 2411 | */ | |
| 2412 | #define WM2200_DSP2RMIX_VOL2_MASK 0x00FE /* DSP2RMIX_VOL2 - [7:1] */ | |
| 2413 | #define WM2200_DSP2RMIX_VOL2_SHIFT 1 /* DSP2RMIX_VOL2 - [7:1] */ | |
| 2414 | #define WM2200_DSP2RMIX_VOL2_WIDTH 7 /* DSP2RMIX_VOL2 - [7:1] */ | |
| 2415 | ||
| 2416 | /* | |
| 2417 | * R1682 (0x692) - DSP2RMIX Input 3 Source | |
| 2418 | */ | |
| 2419 | #define WM2200_DSP2RMIX_SRC3_MASK 0x007F /* DSP2RMIX_SRC3 - [6:0] */ | |
| 2420 | #define WM2200_DSP2RMIX_SRC3_SHIFT 0 /* DSP2RMIX_SRC3 - [6:0] */ | |
| 2421 | #define WM2200_DSP2RMIX_SRC3_WIDTH 7 /* DSP2RMIX_SRC3 - [6:0] */ | |
| 2422 | ||
| 2423 | /* | |
| 2424 | * R1683 (0x693) - DSP2RMIX Input 3 Volume | |
| 2425 | */ | |
| 2426 | #define WM2200_DSP2RMIX_VOL3_MASK 0x00FE /* DSP2RMIX_VOL3 - [7:1] */ | |
| 2427 | #define WM2200_DSP2RMIX_VOL3_SHIFT 1 /* DSP2RMIX_VOL3 - [7:1] */ | |
| 2428 | #define WM2200_DSP2RMIX_VOL3_WIDTH 7 /* DSP2RMIX_VOL3 - [7:1] */ | |
| 2429 | ||
| 2430 | /* | |
| 2431 | * R1684 (0x694) - DSP2RMIX Input 4 Source | |
| 2432 | */ | |
| 2433 | #define WM2200_DSP2RMIX_SRC4_MASK 0x007F /* DSP2RMIX_SRC4 - [6:0] */ | |
| 2434 | #define WM2200_DSP2RMIX_SRC4_SHIFT 0 /* DSP2RMIX_SRC4 - [6:0] */ | |
| 2435 | #define WM2200_DSP2RMIX_SRC4_WIDTH 7 /* DSP2RMIX_SRC4 - [6:0] */ | |
| 2436 | ||
| 2437 | /* | |
| 2438 | * R1685 (0x695) - DSP2RMIX Input 4 Volume | |
| 2439 | */ | |
| 2440 | #define WM2200_DSP2RMIX_VOL4_MASK 0x00FE /* DSP2RMIX_VOL4 - [7:1] */ | |
| 2441 | #define WM2200_DSP2RMIX_VOL4_SHIFT 1 /* DSP2RMIX_VOL4 - [7:1] */ | |
| 2442 | #define WM2200_DSP2RMIX_VOL4_WIDTH 7 /* DSP2RMIX_VOL4 - [7:1] */ | |
| 2443 | ||
| 2444 | /* | |
| 2445 | * R1686 (0x696) - DSP2AUX1MIX Input 1 Source | |
| 2446 | */ | |
| 2447 | #define WM2200_DSP2AUX1MIX_SRC1_MASK 0x007F /* DSP2AUX1MIX_SRC1 - [6:0] */ | |
| 2448 | #define WM2200_DSP2AUX1MIX_SRC1_SHIFT 0 /* DSP2AUX1MIX_SRC1 - [6:0] */ | |
| 2449 | #define WM2200_DSP2AUX1MIX_SRC1_WIDTH 7 /* DSP2AUX1MIX_SRC1 - [6:0] */ | |
| 2450 | ||
| 2451 | /* | |
| 2452 | * R1687 (0x697) - DSP2AUX2MIX Input 1 Source | |
| 2453 | */ | |
| 2454 | #define WM2200_DSP2AUX2MIX_SRC1_MASK 0x007F /* DSP2AUX2MIX_SRC1 - [6:0] */ | |
| 2455 | #define WM2200_DSP2AUX2MIX_SRC1_SHIFT 0 /* DSP2AUX2MIX_SRC1 - [6:0] */ | |
| 2456 | #define WM2200_DSP2AUX2MIX_SRC1_WIDTH 7 /* DSP2AUX2MIX_SRC1 - [6:0] */ | |
| 2457 | ||
| 2458 | /* | |
| 2459 | * R1688 (0x698) - DSP2AUX3MIX Input 1 Source | |
| 2460 | */ | |
| 2461 | #define WM2200_DSP2AUX3MIX_SRC1_MASK 0x007F /* DSP2AUX3MIX_SRC1 - [6:0] */ | |
| 2462 | #define WM2200_DSP2AUX3MIX_SRC1_SHIFT 0 /* DSP2AUX3MIX_SRC1 - [6:0] */ | |
| 2463 | #define WM2200_DSP2AUX3MIX_SRC1_WIDTH 7 /* DSP2AUX3MIX_SRC1 - [6:0] */ | |
| 2464 | ||
| 2465 | /* | |
| 2466 | * R1689 (0x699) - DSP2AUX4MIX Input 1 Source | |
| 2467 | */ | |
| 2468 | #define WM2200_DSP2AUX4MIX_SRC1_MASK 0x007F /* DSP2AUX4MIX_SRC1 - [6:0] */ | |
| 2469 | #define WM2200_DSP2AUX4MIX_SRC1_SHIFT 0 /* DSP2AUX4MIX_SRC1 - [6:0] */ | |
| 2470 | #define WM2200_DSP2AUX4MIX_SRC1_WIDTH 7 /* DSP2AUX4MIX_SRC1 - [6:0] */ | |
| 2471 | ||
| 2472 | /* | |
| 2473 | * R1690 (0x69A) - DSP2AUX5MIX Input 1 Source | |
| 2474 | */ | |
| 2475 | #define WM2200_DSP2AUX5MIX_SRC1_MASK 0x007F /* DSP2AUX5MIX_SRC1 - [6:0] */ | |
| 2476 | #define WM2200_DSP2AUX5MIX_SRC1_SHIFT 0 /* DSP2AUX5MIX_SRC1 - [6:0] */ | |
| 2477 | #define WM2200_DSP2AUX5MIX_SRC1_WIDTH 7 /* DSP2AUX5MIX_SRC1 - [6:0] */ | |
| 2478 | ||
| 2479 | /* | |
| 2480 | * R1691 (0x69B) - DSP2AUX6MIX Input 1 Source | |
| 2481 | */ | |
| 2482 | #define WM2200_DSP2AUX6MIX_SRC1_MASK 0x007F /* DSP2AUX6MIX_SRC1 - [6:0] */ | |
| 2483 | #define WM2200_DSP2AUX6MIX_SRC1_SHIFT 0 /* DSP2AUX6MIX_SRC1 - [6:0] */ | |
| 2484 | #define WM2200_DSP2AUX6MIX_SRC1_WIDTH 7 /* DSP2AUX6MIX_SRC1 - [6:0] */ | |
| 2485 | ||
| 2486 | /* | |
| 2487 | * R1792 (0x700) - GPIO CTRL 1 | |
| 2488 | */ | |
| 2489 | #define WM2200_GP1_DIR 0x8000 /* GP1_DIR */ | |
| 2490 | #define WM2200_GP1_DIR_MASK 0x8000 /* GP1_DIR */ | |
| 2491 | #define WM2200_GP1_DIR_SHIFT 15 /* GP1_DIR */ | |
| 2492 | #define WM2200_GP1_DIR_WIDTH 1 /* GP1_DIR */ | |
| 2493 | #define WM2200_GP1_PU 0x4000 /* GP1_PU */ | |
| 2494 | #define WM2200_GP1_PU_MASK 0x4000 /* GP1_PU */ | |
| 2495 | #define WM2200_GP1_PU_SHIFT 14 /* GP1_PU */ | |
| 2496 | #define WM2200_GP1_PU_WIDTH 1 /* GP1_PU */ | |
| 2497 | #define WM2200_GP1_PD 0x2000 /* GP1_PD */ | |
| 2498 | #define WM2200_GP1_PD_MASK 0x2000 /* GP1_PD */ | |
| 2499 | #define WM2200_GP1_PD_SHIFT 13 /* GP1_PD */ | |
| 2500 | #define WM2200_GP1_PD_WIDTH 1 /* GP1_PD */ | |
| 2501 | #define WM2200_GP1_POL 0x0400 /* GP1_POL */ | |
| 2502 | #define WM2200_GP1_POL_MASK 0x0400 /* GP1_POL */ | |
| 2503 | #define WM2200_GP1_POL_SHIFT 10 /* GP1_POL */ | |
| 2504 | #define WM2200_GP1_POL_WIDTH 1 /* GP1_POL */ | |
| 2505 | #define WM2200_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */ | |
| 2506 | #define WM2200_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */ | |
| 2507 | #define WM2200_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */ | |
| 2508 | #define WM2200_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */ | |
| 2509 | #define WM2200_GP1_DB 0x0100 /* GP1_DB */ | |
| 2510 | #define WM2200_GP1_DB_MASK 0x0100 /* GP1_DB */ | |
| 2511 | #define WM2200_GP1_DB_SHIFT 8 /* GP1_DB */ | |
| 2512 | #define WM2200_GP1_DB_WIDTH 1 /* GP1_DB */ | |
| 2513 | #define WM2200_GP1_LVL 0x0040 /* GP1_LVL */ | |
| 2514 | #define WM2200_GP1_LVL_MASK 0x0040 /* GP1_LVL */ | |
| 2515 | #define WM2200_GP1_LVL_SHIFT 6 /* GP1_LVL */ | |
| 2516 | #define WM2200_GP1_LVL_WIDTH 1 /* GP1_LVL */ | |
| 2517 | #define WM2200_GP1_FN_MASK 0x003F /* GP1_FN - [5:0] */ | |
| 2518 | #define WM2200_GP1_FN_SHIFT 0 /* GP1_FN - [5:0] */ | |
| 2519 | #define WM2200_GP1_FN_WIDTH 6 /* GP1_FN - [5:0] */ | |
| 2520 | ||
| 2521 | /* | |
| 2522 | * R1793 (0x701) - GPIO CTRL 2 | |
| 2523 | */ | |
| 2524 | #define WM2200_GP2_DIR 0x8000 /* GP2_DIR */ | |
| 2525 | #define WM2200_GP2_DIR_MASK 0x8000 /* GP2_DIR */ | |
| 2526 | #define WM2200_GP2_DIR_SHIFT 15 /* GP2_DIR */ | |
| 2527 | #define WM2200_GP2_DIR_WIDTH 1 /* GP2_DIR */ | |
| 2528 | #define WM2200_GP2_PU 0x4000 /* GP2_PU */ | |
| 2529 | #define WM2200_GP2_PU_MASK 0x4000 /* GP2_PU */ | |
| 2530 | #define WM2200_GP2_PU_SHIFT 14 /* GP2_PU */ | |
| 2531 | #define WM2200_GP2_PU_WIDTH 1 /* GP2_PU */ | |
| 2532 | #define WM2200_GP2_PD 0x2000 /* GP2_PD */ | |
| 2533 | #define WM2200_GP2_PD_MASK 0x2000 /* GP2_PD */ | |
| 2534 | #define WM2200_GP2_PD_SHIFT 13 /* GP2_PD */ | |
| 2535 | #define WM2200_GP2_PD_WIDTH 1 /* GP2_PD */ | |
| 2536 | #define WM2200_GP2_POL 0x0400 /* GP2_POL */ | |
| 2537 | #define WM2200_GP2_POL_MASK 0x0400 /* GP2_POL */ | |
| 2538 | #define WM2200_GP2_POL_SHIFT 10 /* GP2_POL */ | |
| 2539 | #define WM2200_GP2_POL_WIDTH 1 /* GP2_POL */ | |
| 2540 | #define WM2200_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */ | |
| 2541 | #define WM2200_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */ | |
| 2542 | #define WM2200_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */ | |
| 2543 | #define WM2200_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */ | |
| 2544 | #define WM2200_GP2_DB 0x0100 /* GP2_DB */ | |
| 2545 | #define WM2200_GP2_DB_MASK 0x0100 /* GP2_DB */ | |
| 2546 | #define WM2200_GP2_DB_SHIFT 8 /* GP2_DB */ | |
| 2547 | #define WM2200_GP2_DB_WIDTH 1 /* GP2_DB */ | |
| 2548 | #define WM2200_GP2_LVL 0x0040 /* GP2_LVL */ | |
| 2549 | #define WM2200_GP2_LVL_MASK 0x0040 /* GP2_LVL */ | |
| 2550 | #define WM2200_GP2_LVL_SHIFT 6 /* GP2_LVL */ | |
| 2551 | #define WM2200_GP2_LVL_WIDTH 1 /* GP2_LVL */ | |
| 2552 | #define WM2200_GP2_FN_MASK 0x003F /* GP2_FN - [5:0] */ | |
| 2553 | #define WM2200_GP2_FN_SHIFT 0 /* GP2_FN - [5:0] */ | |
| 2554 | #define WM2200_GP2_FN_WIDTH 6 /* GP2_FN - [5:0] */ | |
| 2555 | ||
| 2556 | /* | |
| 2557 | * R1794 (0x702) - GPIO CTRL 3 | |
| 2558 | */ | |
| 2559 | #define WM2200_GP3_DIR 0x8000 /* GP3_DIR */ | |
| 2560 | #define WM2200_GP3_DIR_MASK 0x8000 /* GP3_DIR */ | |
| 2561 | #define WM2200_GP3_DIR_SHIFT 15 /* GP3_DIR */ | |
| 2562 | #define WM2200_GP3_DIR_WIDTH 1 /* GP3_DIR */ | |
| 2563 | #define WM2200_GP3_PU 0x4000 /* GP3_PU */ | |
| 2564 | #define WM2200_GP3_PU_MASK 0x4000 /* GP3_PU */ | |
| 2565 | #define WM2200_GP3_PU_SHIFT 14 /* GP3_PU */ | |
| 2566 | #define WM2200_GP3_PU_WIDTH 1 /* GP3_PU */ | |
| 2567 | #define WM2200_GP3_PD 0x2000 /* GP3_PD */ | |
| 2568 | #define WM2200_GP3_PD_MASK 0x2000 /* GP3_PD */ | |
| 2569 | #define WM2200_GP3_PD_SHIFT 13 /* GP3_PD */ | |
| 2570 | #define WM2200_GP3_PD_WIDTH 1 /* GP3_PD */ | |
| 2571 | #define WM2200_GP3_POL 0x0400 /* GP3_POL */ | |
| 2572 | #define WM2200_GP3_POL_MASK 0x0400 /* GP3_POL */ | |
| 2573 | #define WM2200_GP3_POL_SHIFT 10 /* GP3_POL */ | |
| 2574 | #define WM2200_GP3_POL_WIDTH 1 /* GP3_POL */ | |
| 2575 | #define WM2200_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */ | |
| 2576 | #define WM2200_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */ | |
| 2577 | #define WM2200_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */ | |
| 2578 | #define WM2200_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */ | |
| 2579 | #define WM2200_GP3_DB 0x0100 /* GP3_DB */ | |
| 2580 | #define WM2200_GP3_DB_MASK 0x0100 /* GP3_DB */ | |
| 2581 | #define WM2200_GP3_DB_SHIFT 8 /* GP3_DB */ | |
| 2582 | #define WM2200_GP3_DB_WIDTH 1 /* GP3_DB */ | |
| 2583 | #define WM2200_GP3_LVL 0x0040 /* GP3_LVL */ | |
| 2584 | #define WM2200_GP3_LVL_MASK 0x0040 /* GP3_LVL */ | |
| 2585 | #define WM2200_GP3_LVL_SHIFT 6 /* GP3_LVL */ | |
| 2586 | #define WM2200_GP3_LVL_WIDTH 1 /* GP3_LVL */ | |
| 2587 | #define WM2200_GP3_FN_MASK 0x003F /* GP3_FN - [5:0] */ | |
| 2588 | #define WM2200_GP3_FN_SHIFT 0 /* GP3_FN - [5:0] */ | |
| 2589 | #define WM2200_GP3_FN_WIDTH 6 /* GP3_FN - [5:0] */ | |
| 2590 | ||
| 2591 | /* | |
| 2592 | * R1795 (0x703) - GPIO CTRL 4 | |
| 2593 | */ | |
| 2594 | #define WM2200_GP4_DIR 0x8000 /* GP4_DIR */ | |
| 2595 | #define WM2200_GP4_DIR_MASK 0x8000 /* GP4_DIR */ | |
| 2596 | #define WM2200_GP4_DIR_SHIFT 15 /* GP4_DIR */ | |
| 2597 | #define WM2200_GP4_DIR_WIDTH 1 /* GP4_DIR */ | |
| 2598 | #define WM2200_GP4_PU 0x4000 /* GP4_PU */ | |
| 2599 | #define WM2200_GP4_PU_MASK 0x4000 /* GP4_PU */ | |
| 2600 | #define WM2200_GP4_PU_SHIFT 14 /* GP4_PU */ | |
| 2601 | #define WM2200_GP4_PU_WIDTH 1 /* GP4_PU */ | |
| 2602 | #define WM2200_GP4_PD 0x2000 /* GP4_PD */ | |
| 2603 | #define WM2200_GP4_PD_MASK 0x2000 /* GP4_PD */ | |
| 2604 | #define WM2200_GP4_PD_SHIFT 13 /* GP4_PD */ | |
| 2605 | #define WM2200_GP4_PD_WIDTH 1 /* GP4_PD */ | |
| 2606 | #define WM2200_GP4_POL 0x0400 /* GP4_POL */ | |
| 2607 | #define WM2200_GP4_POL_MASK 0x0400 /* GP4_POL */ | |
| 2608 | #define WM2200_GP4_POL_SHIFT 10 /* GP4_POL */ | |
| 2609 | #define WM2200_GP4_POL_WIDTH 1 /* GP4_POL */ | |
| 2610 | #define WM2200_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */ | |
| 2611 | #define WM2200_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */ | |
| 2612 | #define WM2200_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */ | |
| 2613 | #define WM2200_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */ | |
| 2614 | #define WM2200_GP4_DB 0x0100 /* GP4_DB */ | |
| 2615 | #define WM2200_GP4_DB_MASK 0x0100 /* GP4_DB */ | |
| 2616 | #define WM2200_GP4_DB_SHIFT 8 /* GP4_DB */ | |
| 2617 | #define WM2200_GP4_DB_WIDTH 1 /* GP4_DB */ | |
| 2618 | #define WM2200_GP4_LVL 0x0040 /* GP4_LVL */ | |
| 2619 | #define WM2200_GP4_LVL_MASK 0x0040 /* GP4_LVL */ | |
| 2620 | #define WM2200_GP4_LVL_SHIFT 6 /* GP4_LVL */ | |
| 2621 | #define WM2200_GP4_LVL_WIDTH 1 /* GP4_LVL */ | |
| 2622 | #define WM2200_GP4_FN_MASK 0x003F /* GP4_FN - [5:0] */ | |
| 2623 | #define WM2200_GP4_FN_SHIFT 0 /* GP4_FN - [5:0] */ | |
| 2624 | #define WM2200_GP4_FN_WIDTH 6 /* GP4_FN - [5:0] */ | |
| 2625 | ||
| 2626 | /* | |
| 2627 | * R1799 (0x707) - ADPS1 IRQ0 | |
| 2628 | */ | |
| 2629 | #define WM2200_DSP_IRQ1 0x0002 /* DSP_IRQ1 */ | |
| 2630 | #define WM2200_DSP_IRQ1_MASK 0x0002 /* DSP_IRQ1 */ | |
| 2631 | #define WM2200_DSP_IRQ1_SHIFT 1 /* DSP_IRQ1 */ | |
| 2632 | #define WM2200_DSP_IRQ1_WIDTH 1 /* DSP_IRQ1 */ | |
| 2633 | #define WM2200_DSP_IRQ0 0x0001 /* DSP_IRQ0 */ | |
| 2634 | #define WM2200_DSP_IRQ0_MASK 0x0001 /* DSP_IRQ0 */ | |
| 2635 | #define WM2200_DSP_IRQ0_SHIFT 0 /* DSP_IRQ0 */ | |
| 2636 | #define WM2200_DSP_IRQ0_WIDTH 1 /* DSP_IRQ0 */ | |
| 2637 | ||
| 2638 | /* | |
| 2639 | * R1800 (0x708) - ADPS1 IRQ1 | |
| 2640 | */ | |
| 2641 | #define WM2200_DSP_IRQ3 0x0002 /* DSP_IRQ3 */ | |
| 2642 | #define WM2200_DSP_IRQ3_MASK 0x0002 /* DSP_IRQ3 */ | |
| 2643 | #define WM2200_DSP_IRQ3_SHIFT 1 /* DSP_IRQ3 */ | |
| 2644 | #define WM2200_DSP_IRQ3_WIDTH 1 /* DSP_IRQ3 */ | |
| 2645 | #define WM2200_DSP_IRQ2 0x0001 /* DSP_IRQ2 */ | |
| 2646 | #define WM2200_DSP_IRQ2_MASK 0x0001 /* DSP_IRQ2 */ | |
| 2647 | #define WM2200_DSP_IRQ2_SHIFT 0 /* DSP_IRQ2 */ | |
| 2648 | #define WM2200_DSP_IRQ2_WIDTH 1 /* DSP_IRQ2 */ | |
| 2649 | ||
| 2650 | /* | |
| 2651 | * R1801 (0x709) - Misc Pad Ctrl 1 | |
| 2652 | */ | |
| 2653 | #define WM2200_LDO1ENA_PD 0x8000 /* LDO1ENA_PD */ | |
| 2654 | #define WM2200_LDO1ENA_PD_MASK 0x8000 /* LDO1ENA_PD */ | |
| 2655 | #define WM2200_LDO1ENA_PD_SHIFT 15 /* LDO1ENA_PD */ | |
| 2656 | #define WM2200_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */ | |
| 2657 | #define WM2200_MCLK2_PD 0x2000 /* MCLK2_PD */ | |
| 2658 | #define WM2200_MCLK2_PD_MASK 0x2000 /* MCLK2_PD */ | |
| 2659 | #define WM2200_MCLK2_PD_SHIFT 13 /* MCLK2_PD */ | |
| 2660 | #define WM2200_MCLK2_PD_WIDTH 1 /* MCLK2_PD */ | |
| 2661 | #define WM2200_MCLK1_PD 0x1000 /* MCLK1_PD */ | |
| 2662 | #define WM2200_MCLK1_PD_MASK 0x1000 /* MCLK1_PD */ | |
| 2663 | #define WM2200_MCLK1_PD_SHIFT 12 /* MCLK1_PD */ | |
| 2664 | #define WM2200_MCLK1_PD_WIDTH 1 /* MCLK1_PD */ | |
| 2665 | #define WM2200_DACLRCLK1_PU 0x0400 /* DACLRCLK1_PU */ | |
| 2666 | #define WM2200_DACLRCLK1_PU_MASK 0x0400 /* DACLRCLK1_PU */ | |
| 2667 | #define WM2200_DACLRCLK1_PU_SHIFT 10 /* DACLRCLK1_PU */ | |
| 2668 | #define WM2200_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */ | |
| 2669 | #define WM2200_DACLRCLK1_PD 0x0200 /* DACLRCLK1_PD */ | |
| 2670 | #define WM2200_DACLRCLK1_PD_MASK 0x0200 /* DACLRCLK1_PD */ | |
| 2671 | #define WM2200_DACLRCLK1_PD_SHIFT 9 /* DACLRCLK1_PD */ | |
| 2672 | #define WM2200_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */ | |
| 2673 | #define WM2200_BCLK1_PU 0x0100 /* BCLK1_PU */ | |
| 2674 | #define WM2200_BCLK1_PU_MASK 0x0100 /* BCLK1_PU */ | |
| 2675 | #define WM2200_BCLK1_PU_SHIFT 8 /* BCLK1_PU */ | |
| 2676 | #define WM2200_BCLK1_PU_WIDTH 1 /* BCLK1_PU */ | |
| 2677 | #define WM2200_BCLK1_PD 0x0080 /* BCLK1_PD */ | |
| 2678 | #define WM2200_BCLK1_PD_MASK 0x0080 /* BCLK1_PD */ | |
| 2679 | #define WM2200_BCLK1_PD_SHIFT 7 /* BCLK1_PD */ | |
| 2680 | #define WM2200_BCLK1_PD_WIDTH 1 /* BCLK1_PD */ | |
| 2681 | #define WM2200_DACDAT1_PU 0x0040 /* DACDAT1_PU */ | |
| 2682 | #define WM2200_DACDAT1_PU_MASK 0x0040 /* DACDAT1_PU */ | |
| 2683 | #define WM2200_DACDAT1_PU_SHIFT 6 /* DACDAT1_PU */ | |
| 2684 | #define WM2200_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */ | |
| 2685 | #define WM2200_DACDAT1_PD 0x0020 /* DACDAT1_PD */ | |
| 2686 | #define WM2200_DACDAT1_PD_MASK 0x0020 /* DACDAT1_PD */ | |
| 2687 | #define WM2200_DACDAT1_PD_SHIFT 5 /* DACDAT1_PD */ | |
| 2688 | #define WM2200_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */ | |
| 2689 | #define WM2200_DMICDAT3_PD 0x0010 /* DMICDAT3_PD */ | |
| 2690 | #define WM2200_DMICDAT3_PD_MASK 0x0010 /* DMICDAT3_PD */ | |
| 2691 | #define WM2200_DMICDAT3_PD_SHIFT 4 /* DMICDAT3_PD */ | |
| 2692 | #define WM2200_DMICDAT3_PD_WIDTH 1 /* DMICDAT3_PD */ | |
| 2693 | #define WM2200_DMICDAT2_PD 0x0008 /* DMICDAT2_PD */ | |
| 2694 | #define WM2200_DMICDAT2_PD_MASK 0x0008 /* DMICDAT2_PD */ | |
| 2695 | #define WM2200_DMICDAT2_PD_SHIFT 3 /* DMICDAT2_PD */ | |
| 2696 | #define WM2200_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */ | |
| 2697 | #define WM2200_DMICDAT1_PD 0x0004 /* DMICDAT1_PD */ | |
| 2698 | #define WM2200_DMICDAT1_PD_MASK 0x0004 /* DMICDAT1_PD */ | |
| 2699 | #define WM2200_DMICDAT1_PD_SHIFT 2 /* DMICDAT1_PD */ | |
| 2700 | #define WM2200_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */ | |
| 2701 | #define WM2200_RSTB_PU 0x0002 /* RSTB_PU */ | |
| 2702 | #define WM2200_RSTB_PU_MASK 0x0002 /* RSTB_PU */ | |
| 2703 | #define WM2200_RSTB_PU_SHIFT 1 /* RSTB_PU */ | |
| 2704 | #define WM2200_RSTB_PU_WIDTH 1 /* RSTB_PU */ | |
| 2705 | #define WM2200_ADDR_PD 0x0001 /* ADDR_PD */ | |
| 2706 | #define WM2200_ADDR_PD_MASK 0x0001 /* ADDR_PD */ | |
| 2707 | #define WM2200_ADDR_PD_SHIFT 0 /* ADDR_PD */ | |
| 2708 | #define WM2200_ADDR_PD_WIDTH 1 /* ADDR_PD */ | |
| 2709 | ||
| 2710 | /* | |
| 2711 | * R2048 (0x800) - Interrupt Status 1 | |
| 2712 | */ | |
| 2713 | #define WM2200_DSP_IRQ0_EINT 0x0080 /* DSP_IRQ0_EINT */ | |
| 2714 | #define WM2200_DSP_IRQ0_EINT_MASK 0x0080 /* DSP_IRQ0_EINT */ | |
| 2715 | #define WM2200_DSP_IRQ0_EINT_SHIFT 7 /* DSP_IRQ0_EINT */ | |
| 2716 | #define WM2200_DSP_IRQ0_EINT_WIDTH 1 /* DSP_IRQ0_EINT */ | |
| 2717 | #define WM2200_DSP_IRQ1_EINT 0x0040 /* DSP_IRQ1_EINT */ | |
| 2718 | #define WM2200_DSP_IRQ1_EINT_MASK 0x0040 /* DSP_IRQ1_EINT */ | |
| 2719 | #define WM2200_DSP_IRQ1_EINT_SHIFT 6 /* DSP_IRQ1_EINT */ | |
| 2720 | #define WM2200_DSP_IRQ1_EINT_WIDTH 1 /* DSP_IRQ1_EINT */ | |
| 2721 | #define WM2200_DSP_IRQ2_EINT 0x0020 /* DSP_IRQ2_EINT */ | |
| 2722 | #define WM2200_DSP_IRQ2_EINT_MASK 0x0020 /* DSP_IRQ2_EINT */ | |
| 2723 | #define WM2200_DSP_IRQ2_EINT_SHIFT 5 /* DSP_IRQ2_EINT */ | |
| 2724 | #define WM2200_DSP_IRQ2_EINT_WIDTH 1 /* DSP_IRQ2_EINT */ | |
| 2725 | #define WM2200_DSP_IRQ3_EINT 0x0010 /* DSP_IRQ3_EINT */ | |
| 2726 | #define WM2200_DSP_IRQ3_EINT_MASK 0x0010 /* DSP_IRQ3_EINT */ | |
| 2727 | #define WM2200_DSP_IRQ3_EINT_SHIFT 4 /* DSP_IRQ3_EINT */ | |
| 2728 | #define WM2200_DSP_IRQ3_EINT_WIDTH 1 /* DSP_IRQ3_EINT */ | |
| 2729 | #define WM2200_GP4_EINT 0x0008 /* GP4_EINT */ | |
| 2730 | #define WM2200_GP4_EINT_MASK 0x0008 /* GP4_EINT */ | |
| 2731 | #define WM2200_GP4_EINT_SHIFT 3 /* GP4_EINT */ | |
| 2732 | #define WM2200_GP4_EINT_WIDTH 1 /* GP4_EINT */ | |
| 2733 | #define WM2200_GP3_EINT 0x0004 /* GP3_EINT */ | |
| 2734 | #define WM2200_GP3_EINT_MASK 0x0004 /* GP3_EINT */ | |
| 2735 | #define WM2200_GP3_EINT_SHIFT 2 /* GP3_EINT */ | |
| 2736 | #define WM2200_GP3_EINT_WIDTH 1 /* GP3_EINT */ | |
| 2737 | #define WM2200_GP2_EINT 0x0002 /* GP2_EINT */ | |
| 2738 | #define WM2200_GP2_EINT_MASK 0x0002 /* GP2_EINT */ | |
| 2739 | #define WM2200_GP2_EINT_SHIFT 1 /* GP2_EINT */ | |
| 2740 | #define WM2200_GP2_EINT_WIDTH 1 /* GP2_EINT */ | |
| 2741 | #define WM2200_GP1_EINT 0x0001 /* GP1_EINT */ | |
| 2742 | #define WM2200_GP1_EINT_MASK 0x0001 /* GP1_EINT */ | |
| 2743 | #define WM2200_GP1_EINT_SHIFT 0 /* GP1_EINT */ | |
| 2744 | #define WM2200_GP1_EINT_WIDTH 1 /* GP1_EINT */ | |
| 2745 | ||
| 2746 | /* | |
| 2747 | * R2049 (0x801) - Interrupt Status 1 Mask | |
| 2748 | */ | |
| 2749 | #define WM2200_IM_DSP_IRQ0_EINT 0x0080 /* IM_DSP_IRQ0_EINT */ | |
| 2750 | #define WM2200_IM_DSP_IRQ0_EINT_MASK 0x0080 /* IM_DSP_IRQ0_EINT */ | |
| 2751 | #define WM2200_IM_DSP_IRQ0_EINT_SHIFT 7 /* IM_DSP_IRQ0_EINT */ | |
| 2752 | #define WM2200_IM_DSP_IRQ0_EINT_WIDTH 1 /* IM_DSP_IRQ0_EINT */ | |
| 2753 | #define WM2200_IM_DSP_IRQ1_EINT 0x0040 /* IM_DSP_IRQ1_EINT */ | |
| 2754 | #define WM2200_IM_DSP_IRQ1_EINT_MASK 0x0040 /* IM_DSP_IRQ1_EINT */ | |
| 2755 | #define WM2200_IM_DSP_IRQ1_EINT_SHIFT 6 /* IM_DSP_IRQ1_EINT */ | |
| 2756 | #define WM2200_IM_DSP_IRQ1_EINT_WIDTH 1 /* IM_DSP_IRQ1_EINT */ | |
| 2757 | #define WM2200_IM_DSP_IRQ2_EINT 0x0020 /* IM_DSP_IRQ2_EINT */ | |
| 2758 | #define WM2200_IM_DSP_IRQ2_EINT_MASK 0x0020 /* IM_DSP_IRQ2_EINT */ | |
| 2759 | #define WM2200_IM_DSP_IRQ2_EINT_SHIFT 5 /* IM_DSP_IRQ2_EINT */ | |
| 2760 | #define WM2200_IM_DSP_IRQ2_EINT_WIDTH 1 /* IM_DSP_IRQ2_EINT */ | |
| 2761 | #define WM2200_IM_DSP_IRQ3_EINT 0x0010 /* IM_DSP_IRQ3_EINT */ | |
| 2762 | #define WM2200_IM_DSP_IRQ3_EINT_MASK 0x0010 /* IM_DSP_IRQ3_EINT */ | |
| 2763 | #define WM2200_IM_DSP_IRQ3_EINT_SHIFT 4 /* IM_DSP_IRQ3_EINT */ | |
| 2764 | #define WM2200_IM_DSP_IRQ3_EINT_WIDTH 1 /* IM_DSP_IRQ3_EINT */ | |
| 2765 | #define WM2200_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */ | |
| 2766 | #define WM2200_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */ | |
| 2767 | #define WM2200_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */ | |
| 2768 | #define WM2200_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */ | |
| 2769 | #define WM2200_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */ | |
| 2770 | #define WM2200_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */ | |
| 2771 | #define WM2200_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */ | |
| 2772 | #define WM2200_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */ | |
| 2773 | #define WM2200_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */ | |
| 2774 | #define WM2200_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */ | |
| 2775 | #define WM2200_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */ | |
| 2776 | #define WM2200_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */ | |
| 2777 | #define WM2200_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */ | |
| 2778 | #define WM2200_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */ | |
| 2779 | #define WM2200_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */ | |
| 2780 | #define WM2200_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */ | |
| 2781 | ||
| 2782 | /* | |
| 2783 | * R2050 (0x802) - Interrupt Status 2 | |
| 2784 | */ | |
| 2785 | #define WM2200_WSEQ_BUSY_EINT 0x0100 /* WSEQ_BUSY_EINT */ | |
| 2786 | #define WM2200_WSEQ_BUSY_EINT_MASK 0x0100 /* WSEQ_BUSY_EINT */ | |
| 2787 | #define WM2200_WSEQ_BUSY_EINT_SHIFT 8 /* WSEQ_BUSY_EINT */ | |
| 2788 | #define WM2200_WSEQ_BUSY_EINT_WIDTH 1 /* WSEQ_BUSY_EINT */ | |
| 2789 | #define WM2200_FLL_LOCK_EINT 0x0002 /* FLL_LOCK_EINT */ | |
| 2790 | #define WM2200_FLL_LOCK_EINT_MASK 0x0002 /* FLL_LOCK_EINT */ | |
| 2791 | #define WM2200_FLL_LOCK_EINT_SHIFT 1 /* FLL_LOCK_EINT */ | |
| 2792 | #define WM2200_FLL_LOCK_EINT_WIDTH 1 /* FLL_LOCK_EINT */ | |
| 2793 | #define WM2200_CLKGEN_EINT 0x0001 /* CLKGEN_EINT */ | |
| 2794 | #define WM2200_CLKGEN_EINT_MASK 0x0001 /* CLKGEN_EINT */ | |
| 2795 | #define WM2200_CLKGEN_EINT_SHIFT 0 /* CLKGEN_EINT */ | |
| 2796 | #define WM2200_CLKGEN_EINT_WIDTH 1 /* CLKGEN_EINT */ | |
| 2797 | ||
| 2798 | /* | |
| 2799 | * R2051 (0x803) - Interrupt Raw Status 2 | |
| 2800 | */ | |
| 2801 | #define WM2200_WSEQ_BUSY_STS 0x0100 /* WSEQ_BUSY_STS */ | |
| 2802 | #define WM2200_WSEQ_BUSY_STS_MASK 0x0100 /* WSEQ_BUSY_STS */ | |
| 2803 | #define WM2200_WSEQ_BUSY_STS_SHIFT 8 /* WSEQ_BUSY_STS */ | |
| 2804 | #define WM2200_WSEQ_BUSY_STS_WIDTH 1 /* WSEQ_BUSY_STS */ | |
| 2805 | #define WM2200_FLL_LOCK_STS 0x0002 /* FLL_LOCK_STS */ | |
| 2806 | #define WM2200_FLL_LOCK_STS_MASK 0x0002 /* FLL_LOCK_STS */ | |
| 2807 | #define WM2200_FLL_LOCK_STS_SHIFT 1 /* FLL_LOCK_STS */ | |
| 2808 | #define WM2200_FLL_LOCK_STS_WIDTH 1 /* FLL_LOCK_STS */ | |
| 2809 | #define WM2200_CLKGEN_STS 0x0001 /* CLKGEN_STS */ | |
| 2810 | #define WM2200_CLKGEN_STS_MASK 0x0001 /* CLKGEN_STS */ | |
| 2811 | #define WM2200_CLKGEN_STS_SHIFT 0 /* CLKGEN_STS */ | |
| 2812 | #define WM2200_CLKGEN_STS_WIDTH 1 /* CLKGEN_STS */ | |
| 2813 | ||
| 2814 | /* | |
| 2815 | * R2052 (0x804) - Interrupt Status 2 Mask | |
| 2816 | */ | |
| 2817 | #define WM2200_IM_WSEQ_BUSY_EINT 0x0100 /* IM_WSEQ_BUSY_EINT */ | |
| 2818 | #define WM2200_IM_WSEQ_BUSY_EINT_MASK 0x0100 /* IM_WSEQ_BUSY_EINT */ | |
| 2819 | #define WM2200_IM_WSEQ_BUSY_EINT_SHIFT 8 /* IM_WSEQ_BUSY_EINT */ | |
| 2820 | #define WM2200_IM_WSEQ_BUSY_EINT_WIDTH 1 /* IM_WSEQ_BUSY_EINT */ | |
| 2821 | #define WM2200_IM_FLL_LOCK_EINT 0x0002 /* IM_FLL_LOCK_EINT */ | |
| 2822 | #define WM2200_IM_FLL_LOCK_EINT_MASK 0x0002 /* IM_FLL_LOCK_EINT */ | |
| 2823 | #define WM2200_IM_FLL_LOCK_EINT_SHIFT 1 /* IM_FLL_LOCK_EINT */ | |
| 2824 | #define WM2200_IM_FLL_LOCK_EINT_WIDTH 1 /* IM_FLL_LOCK_EINT */ | |
| 2825 | #define WM2200_IM_CLKGEN_EINT 0x0001 /* IM_CLKGEN_EINT */ | |
| 2826 | #define WM2200_IM_CLKGEN_EINT_MASK 0x0001 /* IM_CLKGEN_EINT */ | |
| 2827 | #define WM2200_IM_CLKGEN_EINT_SHIFT 0 /* IM_CLKGEN_EINT */ | |
| 2828 | #define WM2200_IM_CLKGEN_EINT_WIDTH 1 /* IM_CLKGEN_EINT */ | |
| 2829 | ||
| 2830 | /* | |
| 2831 | * R2056 (0x808) - Interrupt Control | |
| 2832 | */ | |
| 2833 | #define WM2200_IM_IRQ 0x0001 /* IM_IRQ */ | |
| 2834 | #define WM2200_IM_IRQ_MASK 0x0001 /* IM_IRQ */ | |
| 2835 | #define WM2200_IM_IRQ_SHIFT 0 /* IM_IRQ */ | |
| 2836 | #define WM2200_IM_IRQ_WIDTH 1 /* IM_IRQ */ | |
| 2837 | ||
| 2838 | /* | |
| 2839 | * R2304 (0x900) - EQL_1 | |
| 2840 | */ | |
| 2841 | #define WM2200_EQL_B1_GAIN_MASK 0xF800 /* EQL_B1_GAIN - [15:11] */ | |
| 2842 | #define WM2200_EQL_B1_GAIN_SHIFT 11 /* EQL_B1_GAIN - [15:11] */ | |
| 2843 | #define WM2200_EQL_B1_GAIN_WIDTH 5 /* EQL_B1_GAIN - [15:11] */ | |
| 2844 | #define WM2200_EQL_B2_GAIN_MASK 0x07C0 /* EQL_B2_GAIN - [10:6] */ | |
| 2845 | #define WM2200_EQL_B2_GAIN_SHIFT 6 /* EQL_B2_GAIN - [10:6] */ | |
| 2846 | #define WM2200_EQL_B2_GAIN_WIDTH 5 /* EQL_B2_GAIN - [10:6] */ | |
| 2847 | #define WM2200_EQL_B3_GAIN_MASK 0x003E /* EQL_B3_GAIN - [5:1] */ | |
| 2848 | #define WM2200_EQL_B3_GAIN_SHIFT 1 /* EQL_B3_GAIN - [5:1] */ | |
| 2849 | #define WM2200_EQL_B3_GAIN_WIDTH 5 /* EQL_B3_GAIN - [5:1] */ | |
| 2850 | #define WM2200_EQL_ENA 0x0001 /* EQL_ENA */ | |
| 2851 | #define WM2200_EQL_ENA_MASK 0x0001 /* EQL_ENA */ | |
| 2852 | #define WM2200_EQL_ENA_SHIFT 0 /* EQL_ENA */ | |
| 2853 | #define WM2200_EQL_ENA_WIDTH 1 /* EQL_ENA */ | |
| 2854 | ||
| 2855 | /* | |
| 2856 | * R2305 (0x901) - EQL_2 | |
| 2857 | */ | |
| 2858 | #define WM2200_EQL_B4_GAIN_MASK 0xF800 /* EQL_B4_GAIN - [15:11] */ | |
| 2859 | #define WM2200_EQL_B4_GAIN_SHIFT 11 /* EQL_B4_GAIN - [15:11] */ | |
| 2860 | #define WM2200_EQL_B4_GAIN_WIDTH 5 /* EQL_B4_GAIN - [15:11] */ | |
| 2861 | #define WM2200_EQL_B5_GAIN_MASK 0x07C0 /* EQL_B5_GAIN - [10:6] */ | |
| 2862 | #define WM2200_EQL_B5_GAIN_SHIFT 6 /* EQL_B5_GAIN - [10:6] */ | |
| 2863 | #define WM2200_EQL_B5_GAIN_WIDTH 5 /* EQL_B5_GAIN - [10:6] */ | |
| 2864 | ||
| 2865 | /* | |
| 2866 | * R2306 (0x902) - EQL_3 | |
| 2867 | */ | |
| 2868 | #define WM2200_EQL_B1_A_MASK 0xFFFF /* EQL_B1_A - [15:0] */ | |
| 2869 | #define WM2200_EQL_B1_A_SHIFT 0 /* EQL_B1_A - [15:0] */ | |
| 2870 | #define WM2200_EQL_B1_A_WIDTH 16 /* EQL_B1_A - [15:0] */ | |
| 2871 | ||
| 2872 | /* | |
| 2873 | * R2307 (0x903) - EQL_4 | |
| 2874 | */ | |
| 2875 | #define WM2200_EQL_B1_B_MASK 0xFFFF /* EQL_B1_B - [15:0] */ | |
| 2876 | #define WM2200_EQL_B1_B_SHIFT 0 /* EQL_B1_B - [15:0] */ | |
| 2877 | #define WM2200_EQL_B1_B_WIDTH 16 /* EQL_B1_B - [15:0] */ | |
| 2878 | ||
| 2879 | /* | |
| 2880 | * R2308 (0x904) - EQL_5 | |
| 2881 | */ | |
| 2882 | #define WM2200_EQL_B1_PG_MASK 0xFFFF /* EQL_B1_PG - [15:0] */ | |
| 2883 | #define WM2200_EQL_B1_PG_SHIFT 0 /* EQL_B1_PG - [15:0] */ | |
| 2884 | #define WM2200_EQL_B1_PG_WIDTH 16 /* EQL_B1_PG - [15:0] */ | |
| 2885 | ||
| 2886 | /* | |
| 2887 | * R2309 (0x905) - EQL_6 | |
| 2888 | */ | |
| 2889 | #define WM2200_EQL_B2_A_MASK 0xFFFF /* EQL_B2_A - [15:0] */ | |
| 2890 | #define WM2200_EQL_B2_A_SHIFT 0 /* EQL_B2_A - [15:0] */ | |
| 2891 | #define WM2200_EQL_B2_A_WIDTH 16 /* EQL_B2_A - [15:0] */ | |
| 2892 | ||
| 2893 | /* | |
| 2894 | * R2310 (0x906) - EQL_7 | |
| 2895 | */ | |
| 2896 | #define WM2200_EQL_B2_B_MASK 0xFFFF /* EQL_B2_B - [15:0] */ | |
| 2897 | #define WM2200_EQL_B2_B_SHIFT 0 /* EQL_B2_B - [15:0] */ | |
| 2898 | #define WM2200_EQL_B2_B_WIDTH 16 /* EQL_B2_B - [15:0] */ | |
| 2899 | ||
| 2900 | /* | |
| 2901 | * R2311 (0x907) - EQL_8 | |
| 2902 | */ | |
| 2903 | #define WM2200_EQL_B2_C_MASK 0xFFFF /* EQL_B2_C - [15:0] */ | |
| 2904 | #define WM2200_EQL_B2_C_SHIFT 0 /* EQL_B2_C - [15:0] */ | |
| 2905 | #define WM2200_EQL_B2_C_WIDTH 16 /* EQL_B2_C - [15:0] */ | |
| 2906 | ||
| 2907 | /* | |
| 2908 | * R2312 (0x908) - EQL_9 | |
| 2909 | */ | |
| 2910 | #define WM2200_EQL_B2_PG_MASK 0xFFFF /* EQL_B2_PG - [15:0] */ | |
| 2911 | #define WM2200_EQL_B2_PG_SHIFT 0 /* EQL_B2_PG - [15:0] */ | |
| 2912 | #define WM2200_EQL_B2_PG_WIDTH 16 /* EQL_B2_PG - [15:0] */ | |
| 2913 | ||
| 2914 | /* | |
| 2915 | * R2313 (0x909) - EQL_10 | |
| 2916 | */ | |
| 2917 | #define WM2200_EQL_B3_A_MASK 0xFFFF /* EQL_B3_A - [15:0] */ | |
| 2918 | #define WM2200_EQL_B3_A_SHIFT 0 /* EQL_B3_A - [15:0] */ | |
| 2919 | #define WM2200_EQL_B3_A_WIDTH 16 /* EQL_B3_A - [15:0] */ | |
| 2920 | ||
| 2921 | /* | |
| 2922 | * R2314 (0x90A) - EQL_11 | |
| 2923 | */ | |
| 2924 | #define WM2200_EQL_B3_B_MASK 0xFFFF /* EQL_B3_B - [15:0] */ | |
| 2925 | #define WM2200_EQL_B3_B_SHIFT 0 /* EQL_B3_B - [15:0] */ | |
| 2926 | #define WM2200_EQL_B3_B_WIDTH 16 /* EQL_B3_B - [15:0] */ | |
| 2927 | ||
| 2928 | /* | |
| 2929 | * R2315 (0x90B) - EQL_12 | |
| 2930 | */ | |
| 2931 | #define WM2200_EQL_B3_C_MASK 0xFFFF /* EQL_B3_C - [15:0] */ | |
| 2932 | #define WM2200_EQL_B3_C_SHIFT 0 /* EQL_B3_C - [15:0] */ | |
| 2933 | #define WM2200_EQL_B3_C_WIDTH 16 /* EQL_B3_C - [15:0] */ | |
| 2934 | ||
| 2935 | /* | |
| 2936 | * R2316 (0x90C) - EQL_13 | |
| 2937 | */ | |
| 2938 | #define WM2200_EQL_B3_PG_MASK 0xFFFF /* EQL_B3_PG - [15:0] */ | |
| 2939 | #define WM2200_EQL_B3_PG_SHIFT 0 /* EQL_B3_PG - [15:0] */ | |
| 2940 | #define WM2200_EQL_B3_PG_WIDTH 16 /* EQL_B3_PG - [15:0] */ | |
| 2941 | ||
| 2942 | /* | |
| 2943 | * R2317 (0x90D) - EQL_14 | |
| 2944 | */ | |
| 2945 | #define WM2200_EQL_B4_A_MASK 0xFFFF /* EQL_B4_A - [15:0] */ | |
| 2946 | #define WM2200_EQL_B4_A_SHIFT 0 /* EQL_B4_A - [15:0] */ | |
| 2947 | #define WM2200_EQL_B4_A_WIDTH 16 /* EQL_B4_A - [15:0] */ | |
| 2948 | ||
| 2949 | /* | |
| 2950 | * R2318 (0x90E) - EQL_15 | |
| 2951 | */ | |
| 2952 | #define WM2200_EQL_B4_B_MASK 0xFFFF /* EQL_B4_B - [15:0] */ | |
| 2953 | #define WM2200_EQL_B4_B_SHIFT 0 /* EQL_B4_B - [15:0] */ | |
| 2954 | #define WM2200_EQL_B4_B_WIDTH 16 /* EQL_B4_B - [15:0] */ | |
| 2955 | ||
| 2956 | /* | |
| 2957 | * R2319 (0x90F) - EQL_16 | |
| 2958 | */ | |
| 2959 | #define WM2200_EQL_B4_C_MASK 0xFFFF /* EQL_B4_C - [15:0] */ | |
| 2960 | #define WM2200_EQL_B4_C_SHIFT 0 /* EQL_B4_C - [15:0] */ | |
| 2961 | #define WM2200_EQL_B4_C_WIDTH 16 /* EQL_B4_C - [15:0] */ | |
| 2962 | ||
| 2963 | /* | |
| 2964 | * R2320 (0x910) - EQL_17 | |
| 2965 | */ | |
| 2966 | #define WM2200_EQL_B4_PG_MASK 0xFFFF /* EQL_B4_PG - [15:0] */ | |
| 2967 | #define WM2200_EQL_B4_PG_SHIFT 0 /* EQL_B4_PG - [15:0] */ | |
| 2968 | #define WM2200_EQL_B4_PG_WIDTH 16 /* EQL_B4_PG - [15:0] */ | |
| 2969 | ||
| 2970 | /* | |
| 2971 | * R2321 (0x911) - EQL_18 | |
| 2972 | */ | |
| 2973 | #define WM2200_EQL_B5_A_MASK 0xFFFF /* EQL_B5_A - [15:0] */ | |
| 2974 | #define WM2200_EQL_B5_A_SHIFT 0 /* EQL_B5_A - [15:0] */ | |
| 2975 | #define WM2200_EQL_B5_A_WIDTH 16 /* EQL_B5_A - [15:0] */ | |
| 2976 | ||
| 2977 | /* | |
| 2978 | * R2322 (0x912) - EQL_19 | |
| 2979 | */ | |
| 2980 | #define WM2200_EQL_B5_B_MASK 0xFFFF /* EQL_B5_B - [15:0] */ | |
| 2981 | #define WM2200_EQL_B5_B_SHIFT 0 /* EQL_B5_B - [15:0] */ | |
| 2982 | #define WM2200_EQL_B5_B_WIDTH 16 /* EQL_B5_B - [15:0] */ | |
| 2983 | ||
| 2984 | /* | |
| 2985 | * R2323 (0x913) - EQL_20 | |
| 2986 | */ | |
| 2987 | #define WM2200_EQL_B5_PG_MASK 0xFFFF /* EQL_B5_PG - [15:0] */ | |
| 2988 | #define WM2200_EQL_B5_PG_SHIFT 0 /* EQL_B5_PG - [15:0] */ | |
| 2989 | #define WM2200_EQL_B5_PG_WIDTH 16 /* EQL_B5_PG - [15:0] */ | |
| 2990 | ||
| 2991 | /* | |
| 2992 | * R2326 (0x916) - EQR_1 | |
| 2993 | */ | |
| 2994 | #define WM2200_EQR_B1_GAIN_MASK 0xF800 /* EQR_B1_GAIN - [15:11] */ | |
| 2995 | #define WM2200_EQR_B1_GAIN_SHIFT 11 /* EQR_B1_GAIN - [15:11] */ | |
| 2996 | #define WM2200_EQR_B1_GAIN_WIDTH 5 /* EQR_B1_GAIN - [15:11] */ | |
| 2997 | #define WM2200_EQR_B2_GAIN_MASK 0x07C0 /* EQR_B2_GAIN - [10:6] */ | |
| 2998 | #define WM2200_EQR_B2_GAIN_SHIFT 6 /* EQR_B2_GAIN - [10:6] */ | |
| 2999 | #define WM2200_EQR_B2_GAIN_WIDTH 5 /* EQR_B2_GAIN - [10:6] */ | |
| 3000 | #define WM2200_EQR_B3_GAIN_MASK 0x003E /* EQR_B3_GAIN - [5:1] */ | |
| 3001 | #define WM2200_EQR_B3_GAIN_SHIFT 1 /* EQR_B3_GAIN - [5:1] */ | |
| 3002 | #define WM2200_EQR_B3_GAIN_WIDTH 5 /* EQR_B3_GAIN - [5:1] */ | |
| 3003 | #define WM2200_EQR_ENA 0x0001 /* EQR_ENA */ | |
| 3004 | #define WM2200_EQR_ENA_MASK 0x0001 /* EQR_ENA */ | |
| 3005 | #define WM2200_EQR_ENA_SHIFT 0 /* EQR_ENA */ | |
| 3006 | #define WM2200_EQR_ENA_WIDTH 1 /* EQR_ENA */ | |
| 3007 | ||
| 3008 | /* | |
| 3009 | * R2327 (0x917) - EQR_2 | |
| 3010 | */ | |
| 3011 | #define WM2200_EQR_B4_GAIN_MASK 0xF800 /* EQR_B4_GAIN - [15:11] */ | |
| 3012 | #define WM2200_EQR_B4_GAIN_SHIFT 11 /* EQR_B4_GAIN - [15:11] */ | |
| 3013 | #define WM2200_EQR_B4_GAIN_WIDTH 5 /* EQR_B4_GAIN - [15:11] */ | |
| 3014 | #define WM2200_EQR_B5_GAIN_MASK 0x07C0 /* EQR_B5_GAIN - [10:6] */ | |
| 3015 | #define WM2200_EQR_B5_GAIN_SHIFT 6 /* EQR_B5_GAIN - [10:6] */ | |
| 3016 | #define WM2200_EQR_B5_GAIN_WIDTH 5 /* EQR_B5_GAIN - [10:6] */ | |
| 3017 | ||
| 3018 | /* | |
| 3019 | * R2328 (0x918) - EQR_3 | |
| 3020 | */ | |
| 3021 | #define WM2200_EQR_B1_A_MASK 0xFFFF /* EQR_B1_A - [15:0] */ | |
| 3022 | #define WM2200_EQR_B1_A_SHIFT 0 /* EQR_B1_A - [15:0] */ | |
| 3023 | #define WM2200_EQR_B1_A_WIDTH 16 /* EQR_B1_A - [15:0] */ | |
| 3024 | ||
| 3025 | /* | |
| 3026 | * R2329 (0x919) - EQR_4 | |
| 3027 | */ | |
| 3028 | #define WM2200_EQR_B1_B_MASK 0xFFFF /* EQR_B1_B - [15:0] */ | |
| 3029 | #define WM2200_EQR_B1_B_SHIFT 0 /* EQR_B1_B - [15:0] */ | |
| 3030 | #define WM2200_EQR_B1_B_WIDTH 16 /* EQR_B1_B - [15:0] */ | |
| 3031 | ||
| 3032 | /* | |
| 3033 | * R2330 (0x91A) - EQR_5 | |
| 3034 | */ | |
| 3035 | #define WM2200_EQR_B1_PG_MASK 0xFFFF /* EQR_B1_PG - [15:0] */ | |
| 3036 | #define WM2200_EQR_B1_PG_SHIFT 0 /* EQR_B1_PG - [15:0] */ | |
| 3037 | #define WM2200_EQR_B1_PG_WIDTH 16 /* EQR_B1_PG - [15:0] */ | |
| 3038 | ||
| 3039 | /* | |
| 3040 | * R2331 (0x91B) - EQR_6 | |
| 3041 | */ | |
| 3042 | #define WM2200_EQR_B2_A_MASK 0xFFFF /* EQR_B2_A - [15:0] */ | |
| 3043 | #define WM2200_EQR_B2_A_SHIFT 0 /* EQR_B2_A - [15:0] */ | |
| 3044 | #define WM2200_EQR_B2_A_WIDTH 16 /* EQR_B2_A - [15:0] */ | |
| 3045 | ||
| 3046 | /* | |
| 3047 | * R2332 (0x91C) - EQR_7 | |
| 3048 | */ | |
| 3049 | #define WM2200_EQR_B2_B_MASK 0xFFFF /* EQR_B2_B - [15:0] */ | |
| 3050 | #define WM2200_EQR_B2_B_SHIFT 0 /* EQR_B2_B - [15:0] */ | |
| 3051 | #define WM2200_EQR_B2_B_WIDTH 16 /* EQR_B2_B - [15:0] */ | |
| 3052 | ||
| 3053 | /* | |
| 3054 | * R2333 (0x91D) - EQR_8 | |
| 3055 | */ | |
| 3056 | #define WM2200_EQR_B2_C_MASK 0xFFFF /* EQR_B2_C - [15:0] */ | |
| 3057 | #define WM2200_EQR_B2_C_SHIFT 0 /* EQR_B2_C - [15:0] */ | |
| 3058 | #define WM2200_EQR_B2_C_WIDTH 16 /* EQR_B2_C - [15:0] */ | |
| 3059 | ||
| 3060 | /* | |
| 3061 | * R2334 (0x91E) - EQR_9 | |
| 3062 | */ | |
| 3063 | #define WM2200_EQR_B2_PG_MASK 0xFFFF /* EQR_B2_PG - [15:0] */ | |
| 3064 | #define WM2200_EQR_B2_PG_SHIFT 0 /* EQR_B2_PG - [15:0] */ | |
| 3065 | #define WM2200_EQR_B2_PG_WIDTH 16 /* EQR_B2_PG - [15:0] */ | |
| 3066 | ||
| 3067 | /* | |
| 3068 | * R2335 (0x91F) - EQR_10 | |
| 3069 | */ | |
| 3070 | #define WM2200_EQR_B3_A_MASK 0xFFFF /* EQR_B3_A - [15:0] */ | |
| 3071 | #define WM2200_EQR_B3_A_SHIFT 0 /* EQR_B3_A - [15:0] */ | |
| 3072 | #define WM2200_EQR_B3_A_WIDTH 16 /* EQR_B3_A - [15:0] */ | |
| 3073 | ||
| 3074 | /* | |
| 3075 | * R2336 (0x920) - EQR_11 | |
| 3076 | */ | |
| 3077 | #define WM2200_EQR_B3_B_MASK 0xFFFF /* EQR_B3_B - [15:0] */ | |
| 3078 | #define WM2200_EQR_B3_B_SHIFT 0 /* EQR_B3_B - [15:0] */ | |
| 3079 | #define WM2200_EQR_B3_B_WIDTH 16 /* EQR_B3_B - [15:0] */ | |
| 3080 | ||
| 3081 | /* | |
| 3082 | * R2337 (0x921) - EQR_12 | |
| 3083 | */ | |
| 3084 | #define WM2200_EQR_B3_C_MASK 0xFFFF /* EQR_B3_C - [15:0] */ | |
| 3085 | #define WM2200_EQR_B3_C_SHIFT 0 /* EQR_B3_C - [15:0] */ | |
| 3086 | #define WM2200_EQR_B3_C_WIDTH 16 /* EQR_B3_C - [15:0] */ | |
| 3087 | ||
| 3088 | /* | |
| 3089 | * R2338 (0x922) - EQR_13 | |
| 3090 | */ | |
| 3091 | #define WM2200_EQR_B3_PG_MASK 0xFFFF /* EQR_B3_PG - [15:0] */ | |
| 3092 | #define WM2200_EQR_B3_PG_SHIFT 0 /* EQR_B3_PG - [15:0] */ | |
| 3093 | #define WM2200_EQR_B3_PG_WIDTH 16 /* EQR_B3_PG - [15:0] */ | |
| 3094 | ||
| 3095 | /* | |
| 3096 | * R2339 (0x923) - EQR_14 | |
| 3097 | */ | |
| 3098 | #define WM2200_EQR_B4_A_MASK 0xFFFF /* EQR_B4_A - [15:0] */ | |
| 3099 | #define WM2200_EQR_B4_A_SHIFT 0 /* EQR_B4_A - [15:0] */ | |
| 3100 | #define WM2200_EQR_B4_A_WIDTH 16 /* EQR_B4_A - [15:0] */ | |
| 3101 | ||
| 3102 | /* | |
| 3103 | * R2340 (0x924) - EQR_15 | |
| 3104 | */ | |
| 3105 | #define WM2200_EQR_B4_B_MASK 0xFFFF /* EQR_B4_B - [15:0] */ | |
| 3106 | #define WM2200_EQR_B4_B_SHIFT 0 /* EQR_B4_B - [15:0] */ | |
| 3107 | #define WM2200_EQR_B4_B_WIDTH 16 /* EQR_B4_B - [15:0] */ | |
| 3108 | ||
| 3109 | /* | |
| 3110 | * R2341 (0x925) - EQR_16 | |
| 3111 | */ | |
| 3112 | #define WM2200_EQR_B4_C_MASK 0xFFFF /* EQR_B4_C - [15:0] */ | |
| 3113 | #define WM2200_EQR_B4_C_SHIFT 0 /* EQR_B4_C - [15:0] */ | |
| 3114 | #define WM2200_EQR_B4_C_WIDTH 16 /* EQR_B4_C - [15:0] */ | |
| 3115 | ||
| 3116 | /* | |
| 3117 | * R2342 (0x926) - EQR_17 | |
| 3118 | */ | |
| 3119 | #define WM2200_EQR_B4_PG_MASK 0xFFFF /* EQR_B4_PG - [15:0] */ | |
| 3120 | #define WM2200_EQR_B4_PG_SHIFT 0 /* EQR_B4_PG - [15:0] */ | |
| 3121 | #define WM2200_EQR_B4_PG_WIDTH 16 /* EQR_B4_PG - [15:0] */ | |
| 3122 | ||
| 3123 | /* | |
| 3124 | * R2343 (0x927) - EQR_18 | |
| 3125 | */ | |
| 3126 | #define WM2200_EQR_B5_A_MASK 0xFFFF /* EQR_B5_A - [15:0] */ | |
| 3127 | #define WM2200_EQR_B5_A_SHIFT 0 /* EQR_B5_A - [15:0] */ | |
| 3128 | #define WM2200_EQR_B5_A_WIDTH 16 /* EQR_B5_A - [15:0] */ | |
| 3129 | ||
| 3130 | /* | |
| 3131 | * R2344 (0x928) - EQR_19 | |
| 3132 | */ | |
| 3133 | #define WM2200_EQR_B5_B_MASK 0xFFFF /* EQR_B5_B - [15:0] */ | |
| 3134 | #define WM2200_EQR_B5_B_SHIFT 0 /* EQR_B5_B - [15:0] */ | |
| 3135 | #define WM2200_EQR_B5_B_WIDTH 16 /* EQR_B5_B - [15:0] */ | |
| 3136 | ||
| 3137 | /* | |
| 3138 | * R2345 (0x929) - EQR_20 | |
| 3139 | */ | |
| 3140 | #define WM2200_EQR_B5_PG_MASK 0xFFFF /* EQR_B5_PG - [15:0] */ | |
| 3141 | #define WM2200_EQR_B5_PG_SHIFT 0 /* EQR_B5_PG - [15:0] */ | |
| 3142 | #define WM2200_EQR_B5_PG_WIDTH 16 /* EQR_B5_PG - [15:0] */ | |
| 3143 | ||
| 3144 | /* | |
| 3145 | * R2366 (0x93E) - HPLPF1_1 | |
| 3146 | */ | |
| 3147 | #define WM2200_LHPF1_MODE 0x0002 /* LHPF1_MODE */ | |
| 3148 | #define WM2200_LHPF1_MODE_MASK 0x0002 /* LHPF1_MODE */ | |
| 3149 | #define WM2200_LHPF1_MODE_SHIFT 1 /* LHPF1_MODE */ | |
| 3150 | #define WM2200_LHPF1_MODE_WIDTH 1 /* LHPF1_MODE */ | |
| 3151 | #define WM2200_LHPF1_ENA 0x0001 /* LHPF1_ENA */ | |
| 3152 | #define WM2200_LHPF1_ENA_MASK 0x0001 /* LHPF1_ENA */ | |
| 3153 | #define WM2200_LHPF1_ENA_SHIFT 0 /* LHPF1_ENA */ | |
| 3154 | #define WM2200_LHPF1_ENA_WIDTH 1 /* LHPF1_ENA */ | |
| 3155 | ||
| 3156 | /* | |
| 3157 | * R2367 (0x93F) - HPLPF1_2 | |
| 3158 | */ | |
| 3159 | #define WM2200_LHPF1_COEFF_MASK 0xFFFF /* LHPF1_COEFF - [15:0] */ | |
| 3160 | #define WM2200_LHPF1_COEFF_SHIFT 0 /* LHPF1_COEFF - [15:0] */ | |
| 3161 | #define WM2200_LHPF1_COEFF_WIDTH 16 /* LHPF1_COEFF - [15:0] */ | |
| 3162 | ||
| 3163 | /* | |
| 3164 | * R2370 (0x942) - HPLPF2_1 | |
| 3165 | */ | |
| 3166 | #define WM2200_LHPF2_MODE 0x0002 /* LHPF2_MODE */ | |
| 3167 | #define WM2200_LHPF2_MODE_MASK 0x0002 /* LHPF2_MODE */ | |
| 3168 | #define WM2200_LHPF2_MODE_SHIFT 1 /* LHPF2_MODE */ | |
| 3169 | #define WM2200_LHPF2_MODE_WIDTH 1 /* LHPF2_MODE */ | |
| 3170 | #define WM2200_LHPF2_ENA 0x0001 /* LHPF2_ENA */ | |
| 3171 | #define WM2200_LHPF2_ENA_MASK 0x0001 /* LHPF2_ENA */ | |
| 3172 | #define WM2200_LHPF2_ENA_SHIFT 0 /* LHPF2_ENA */ | |
| 3173 | #define WM2200_LHPF2_ENA_WIDTH 1 /* LHPF2_ENA */ | |
| 3174 | ||
| 3175 | /* | |
| 3176 | * R2371 (0x943) - HPLPF2_2 | |
| 3177 | */ | |
| 3178 | #define WM2200_LHPF2_COEFF_MASK 0xFFFF /* LHPF2_COEFF - [15:0] */ | |
| 3179 | #define WM2200_LHPF2_COEFF_SHIFT 0 /* LHPF2_COEFF - [15:0] */ | |
| 3180 | #define WM2200_LHPF2_COEFF_WIDTH 16 /* LHPF2_COEFF - [15:0] */ | |
| 3181 | ||
| 3182 | /* | |
| 3183 | * R2560 (0xA00) - DSP1 Control 1 | |
| 3184 | */ | |
| 3185 | #define WM2200_DSP1_RW_SEQUENCE_ENA 0x0001 /* DSP1_RW_SEQUENCE_ENA */ | |
| 3186 | #define WM2200_DSP1_RW_SEQUENCE_ENA_MASK 0x0001 /* DSP1_RW_SEQUENCE_ENA */ | |
| 3187 | #define WM2200_DSP1_RW_SEQUENCE_ENA_SHIFT 0 /* DSP1_RW_SEQUENCE_ENA */ | |
| 3188 | #define WM2200_DSP1_RW_SEQUENCE_ENA_WIDTH 1 /* DSP1_RW_SEQUENCE_ENA */ | |
| 3189 | ||
| 3190 | /* | |
| 3191 | * R2562 (0xA02) - DSP1 Control 2 | |
| 3192 | */ | |
| 3193 | #define WM2200_DSP1_PAGE_BASE_PM_0_MASK 0xFF00 /* DSP1_PAGE_BASE_PM - [15:8] */ | |
| 3194 | #define WM2200_DSP1_PAGE_BASE_PM_0_SHIFT 8 /* DSP1_PAGE_BASE_PM - [15:8] */ | |
| 3195 | #define WM2200_DSP1_PAGE_BASE_PM_0_WIDTH 8 /* DSP1_PAGE_BASE_PM - [15:8] */ | |
| 3196 | ||
| 3197 | /* | |
| 3198 | * R2563 (0xA03) - DSP1 Control 3 | |
| 3199 | */ | |
| 3200 | #define WM2200_DSP1_PAGE_BASE_DM_0_MASK 0xFF00 /* DSP1_PAGE_BASE_DM - [15:8] */ | |
| 3201 | #define WM2200_DSP1_PAGE_BASE_DM_0_SHIFT 8 /* DSP1_PAGE_BASE_DM - [15:8] */ | |
| 3202 | #define WM2200_DSP1_PAGE_BASE_DM_0_WIDTH 8 /* DSP1_PAGE_BASE_DM - [15:8] */ | |
| 3203 | ||
| 3204 | /* | |
| 3205 | * R2564 (0xA04) - DSP1 Control 4 | |
| 3206 | */ | |
| 3207 | #define WM2200_DSP1_PAGE_BASE_ZM_0_MASK 0xFF00 /* DSP1_PAGE_BASE_ZM - [15:8] */ | |
| 3208 | #define WM2200_DSP1_PAGE_BASE_ZM_0_SHIFT 8 /* DSP1_PAGE_BASE_ZM - [15:8] */ | |
| 3209 | #define WM2200_DSP1_PAGE_BASE_ZM_0_WIDTH 8 /* DSP1_PAGE_BASE_ZM - [15:8] */ | |
| 3210 | ||
| 3211 | /* | |
| 3212 | * R2566 (0xA06) - DSP1 Control 5 | |
| 3213 | */ | |
| 3214 | #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_0_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */ | |
| 3215 | #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_0_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */ | |
| 3216 | #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_0_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */ | |
| 3217 | ||
| 3218 | /* | |
| 3219 | * R2567 (0xA07) - DSP1 Control 6 | |
| 3220 | */ | |
| 3221 | #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_1_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */ | |
| 3222 | #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_1_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */ | |
| 3223 | #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_1_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */ | |
| 3224 | ||
| 3225 | /* | |
| 3226 | * R2568 (0xA08) - DSP1 Control 7 | |
| 3227 | */ | |
| 3228 | #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_2_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */ | |
| 3229 | #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_2_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */ | |
| 3230 | #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_2_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */ | |
| 3231 | ||
| 3232 | /* | |
| 3233 | * R2569 (0xA09) - DSP1 Control 8 | |
| 3234 | */ | |
| 3235 | #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_3_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */ | |
| 3236 | #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_3_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */ | |
| 3237 | #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_3_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */ | |
| 3238 | ||
| 3239 | /* | |
| 3240 | * R2570 (0xA0A) - DSP1 Control 9 | |
| 3241 | */ | |
| 3242 | #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_4_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */ | |
| 3243 | #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_4_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */ | |
| 3244 | #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_4_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */ | |
| 3245 | ||
| 3246 | /* | |
| 3247 | * R2571 (0xA0B) - DSP1 Control 10 | |
| 3248 | */ | |
| 3249 | #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_5_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */ | |
| 3250 | #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_5_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */ | |
| 3251 | #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_5_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */ | |
| 3252 | ||
| 3253 | /* | |
| 3254 | * R2572 (0xA0C) - DSP1 Control 11 | |
| 3255 | */ | |
| 3256 | #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_6_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */ | |
| 3257 | #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_6_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */ | |
| 3258 | #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_6_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */ | |
| 3259 | ||
| 3260 | /* | |
| 3261 | * R2573 (0xA0D) - DSP1 Control 12 | |
| 3262 | */ | |
| 3263 | #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_7_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */ | |
| 3264 | #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_7_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */ | |
| 3265 | #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_7_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */ | |
| 3266 | ||
| 3267 | /* | |
| 3268 | * R2575 (0xA0F) - DSP1 Control 13 | |
| 3269 | */ | |
| 3270 | #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_0_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */ | |
| 3271 | #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_0_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */ | |
| 3272 | #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_0_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */ | |
| 3273 | ||
| 3274 | /* | |
| 3275 | * R2576 (0xA10) - DSP1 Control 14 | |
| 3276 | */ | |
| 3277 | #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_1_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */ | |
| 3278 | #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_1_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */ | |
| 3279 | #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_1_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */ | |
| 3280 | ||
| 3281 | /* | |
| 3282 | * R2577 (0xA11) - DSP1 Control 15 | |
| 3283 | */ | |
| 3284 | #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_2_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */ | |
| 3285 | #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_2_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */ | |
| 3286 | #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_2_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */ | |
| 3287 | ||
| 3288 | /* | |
| 3289 | * R2578 (0xA12) - DSP1 Control 16 | |
| 3290 | */ | |
| 3291 | #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_3_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */ | |
| 3292 | #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_3_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */ | |
| 3293 | #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_3_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */ | |
| 3294 | ||
| 3295 | /* | |
| 3296 | * R2579 (0xA13) - DSP1 Control 17 | |
| 3297 | */ | |
| 3298 | #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_4_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */ | |
| 3299 | #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_4_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */ | |
| 3300 | #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_4_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */ | |
| 3301 | ||
| 3302 | /* | |
| 3303 | * R2580 (0xA14) - DSP1 Control 18 | |
| 3304 | */ | |
| 3305 | #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_5_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */ | |
| 3306 | #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_5_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */ | |
| 3307 | #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_5_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */ | |
| 3308 | ||
| 3309 | /* | |
| 3310 | * R2582 (0xA16) - DSP1 Control 19 | |
| 3311 | */ | |
| 3312 | #define WM2200_DSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ | |
| 3313 | #define WM2200_DSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ | |
| 3314 | #define WM2200_DSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ | |
| 3315 | ||
| 3316 | /* | |
| 3317 | * R2583 (0xA17) - DSP1 Control 20 | |
| 3318 | */ | |
| 3319 | #define WM2200_DSP1_WDMA_CHANNEL_ENABLE_MASK 0x00FF /* DSP1_WDMA_CHANNEL_ENABLE - [7:0] */ | |
| 3320 | #define WM2200_DSP1_WDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP1_WDMA_CHANNEL_ENABLE - [7:0] */ | |
| 3321 | #define WM2200_DSP1_WDMA_CHANNEL_ENABLE_WIDTH 8 /* DSP1_WDMA_CHANNEL_ENABLE - [7:0] */ | |
| 3322 | ||
| 3323 | /* | |
| 3324 | * R2584 (0xA18) - DSP1 Control 21 | |
| 3325 | */ | |
| 3326 | #define WM2200_DSP1_RDMA_CHANNEL_ENABLE_MASK 0x003F /* DSP1_RDMA_CHANNEL_ENABLE - [5:0] */ | |
| 3327 | #define WM2200_DSP1_RDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP1_RDMA_CHANNEL_ENABLE - [5:0] */ | |
| 3328 | #define WM2200_DSP1_RDMA_CHANNEL_ENABLE_WIDTH 6 /* DSP1_RDMA_CHANNEL_ENABLE - [5:0] */ | |
| 3329 | ||
| 3330 | /* | |
| 3331 | * R2586 (0xA1A) - DSP1 Control 22 | |
| 3332 | */ | |
| 3333 | #define WM2200_DSP1_DM_SIZE_MASK 0xFFFF /* DSP1_DM_SIZE - [15:0] */ | |
| 3334 | #define WM2200_DSP1_DM_SIZE_SHIFT 0 /* DSP1_DM_SIZE - [15:0] */ | |
| 3335 | #define WM2200_DSP1_DM_SIZE_WIDTH 16 /* DSP1_DM_SIZE - [15:0] */ | |
| 3336 | ||
| 3337 | /* | |
| 3338 | * R2587 (0xA1B) - DSP1 Control 23 | |
| 3339 | */ | |
| 3340 | #define WM2200_DSP1_PM_SIZE_MASK 0xFFFF /* DSP1_PM_SIZE - [15:0] */ | |
| 3341 | #define WM2200_DSP1_PM_SIZE_SHIFT 0 /* DSP1_PM_SIZE - [15:0] */ | |
| 3342 | #define WM2200_DSP1_PM_SIZE_WIDTH 16 /* DSP1_PM_SIZE - [15:0] */ | |
| 3343 | ||
| 3344 | /* | |
| 3345 | * R2588 (0xA1C) - DSP1 Control 24 | |
| 3346 | */ | |
| 3347 | #define WM2200_DSP1_ZM_SIZE_MASK 0xFFFF /* DSP1_ZM_SIZE - [15:0] */ | |
| 3348 | #define WM2200_DSP1_ZM_SIZE_SHIFT 0 /* DSP1_ZM_SIZE - [15:0] */ | |
| 3349 | #define WM2200_DSP1_ZM_SIZE_WIDTH 16 /* DSP1_ZM_SIZE - [15:0] */ | |
| 3350 | ||
| 3351 | /* | |
| 3352 | * R2590 (0xA1E) - DSP1 Control 25 | |
| 3353 | */ | |
| 3354 | #define WM2200_DSP1_PING_FULL 0x8000 /* DSP1_PING_FULL */ | |
| 3355 | #define WM2200_DSP1_PING_FULL_MASK 0x8000 /* DSP1_PING_FULL */ | |
| 3356 | #define WM2200_DSP1_PING_FULL_SHIFT 15 /* DSP1_PING_FULL */ | |
| 3357 | #define WM2200_DSP1_PING_FULL_WIDTH 1 /* DSP1_PING_FULL */ | |
| 3358 | #define WM2200_DSP1_PONG_FULL 0x4000 /* DSP1_PONG_FULL */ | |
| 3359 | #define WM2200_DSP1_PONG_FULL_MASK 0x4000 /* DSP1_PONG_FULL */ | |
| 3360 | #define WM2200_DSP1_PONG_FULL_SHIFT 14 /* DSP1_PONG_FULL */ | |
| 3361 | #define WM2200_DSP1_PONG_FULL_WIDTH 1 /* DSP1_PONG_FULL */ | |
| 3362 | #define WM2200_DSP1_WDMA_ACTIVE_CHANNELS_MASK 0x00FF /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */ | |
| 3363 | #define WM2200_DSP1_WDMA_ACTIVE_CHANNELS_SHIFT 0 /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */ | |
| 3364 | #define WM2200_DSP1_WDMA_ACTIVE_CHANNELS_WIDTH 8 /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */ | |
| 3365 | ||
| 3366 | /* | |
| 3367 | * R2592 (0xA20) - DSP1 Control 26 | |
| 3368 | */ | |
| 3369 | #define WM2200_DSP1_SCRATCH_0_MASK 0xFFFF /* DSP1_SCRATCH_0 - [15:0] */ | |
| 3370 | #define WM2200_DSP1_SCRATCH_0_SHIFT 0 /* DSP1_SCRATCH_0 - [15:0] */ | |
| 3371 | #define WM2200_DSP1_SCRATCH_0_WIDTH 16 /* DSP1_SCRATCH_0 - [15:0] */ | |
| 3372 | ||
| 3373 | /* | |
| 3374 | * R2593 (0xA21) - DSP1 Control 27 | |
| 3375 | */ | |
| 3376 | #define WM2200_DSP1_SCRATCH_1_MASK 0xFFFF /* DSP1_SCRATCH_1 - [15:0] */ | |
| 3377 | #define WM2200_DSP1_SCRATCH_1_SHIFT 0 /* DSP1_SCRATCH_1 - [15:0] */ | |
| 3378 | #define WM2200_DSP1_SCRATCH_1_WIDTH 16 /* DSP1_SCRATCH_1 - [15:0] */ | |
| 3379 | ||
| 3380 | /* | |
| 3381 | * R2594 (0xA22) - DSP1 Control 28 | |
| 3382 | */ | |
| 3383 | #define WM2200_DSP1_SCRATCH_2_MASK 0xFFFF /* DSP1_SCRATCH_2 - [15:0] */ | |
| 3384 | #define WM2200_DSP1_SCRATCH_2_SHIFT 0 /* DSP1_SCRATCH_2 - [15:0] */ | |
| 3385 | #define WM2200_DSP1_SCRATCH_2_WIDTH 16 /* DSP1_SCRATCH_2 - [15:0] */ | |
| 3386 | ||
| 3387 | /* | |
| 3388 | * R2595 (0xA23) - DSP1 Control 29 | |
| 3389 | */ | |
| 3390 | #define WM2200_DSP1_SCRATCH_3_MASK 0xFFFF /* DSP1_SCRATCH_3 - [15:0] */ | |
| 3391 | #define WM2200_DSP1_SCRATCH_3_SHIFT 0 /* DSP1_SCRATCH_3 - [15:0] */ | |
| 3392 | #define WM2200_DSP1_SCRATCH_3_WIDTH 16 /* DSP1_SCRATCH_3 - [15:0] */ | |
| 3393 | ||
| 3394 | /* | |
| 3395 | * R2596 (0xA24) - DSP1 Control 30 | |
| 3396 | */ | |
| 3397 | #define WM2200_DSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */ | |
| 3398 | #define WM2200_DSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */ | |
| 3399 | #define WM2200_DSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */ | |
| 3400 | #define WM2200_DSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */ | |
| 3401 | #define WM2200_DSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */ | |
| 3402 | #define WM2200_DSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */ | |
| 3403 | #define WM2200_DSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */ | |
| 3404 | #define WM2200_DSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */ | |
| 3405 | #define WM2200_DSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */ | |
| 3406 | #define WM2200_DSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */ | |
| 3407 | #define WM2200_DSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */ | |
| 3408 | #define WM2200_DSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */ | |
| 3409 | #define WM2200_DSP1_START 0x0001 /* DSP1_START */ | |
| 3410 | #define WM2200_DSP1_START_MASK 0x0001 /* DSP1_START */ | |
| 3411 | #define WM2200_DSP1_START_SHIFT 0 /* DSP1_START */ | |
| 3412 | #define WM2200_DSP1_START_WIDTH 1 /* DSP1_START */ | |
| 3413 | ||
| 3414 | /* | |
| 3415 | * R2598 (0xA26) - DSP1 Control 31 | |
| 3416 | */ | |
| 3417 | #define WM2200_DSP1_CLK_RATE_MASK 0x0018 /* DSP1_CLK_RATE - [4:3] */ | |
| 3418 | #define WM2200_DSP1_CLK_RATE_SHIFT 3 /* DSP1_CLK_RATE - [4:3] */ | |
| 3419 | #define WM2200_DSP1_CLK_RATE_WIDTH 2 /* DSP1_CLK_RATE - [4:3] */ | |
| 3420 | #define WM2200_DSP1_CLK_AVAIL 0x0004 /* DSP1_CLK_AVAIL */ | |
| 3421 | #define WM2200_DSP1_CLK_AVAIL_MASK 0x0004 /* DSP1_CLK_AVAIL */ | |
| 3422 | #define WM2200_DSP1_CLK_AVAIL_SHIFT 2 /* DSP1_CLK_AVAIL */ | |
| 3423 | #define WM2200_DSP1_CLK_AVAIL_WIDTH 1 /* DSP1_CLK_AVAIL */ | |
| 3424 | #define WM2200_DSP1_CLK_REQ_MASK 0x0003 /* DSP1_CLK_REQ - [1:0] */ | |
| 3425 | #define WM2200_DSP1_CLK_REQ_SHIFT 0 /* DSP1_CLK_REQ - [1:0] */ | |
| 3426 | #define WM2200_DSP1_CLK_REQ_WIDTH 2 /* DSP1_CLK_REQ - [1:0] */ | |
| 3427 | ||
| 3428 | /* | |
| 3429 | * R2816 (0xB00) - DSP2 Control 1 | |
| 3430 | */ | |
| 3431 | #define WM2200_DSP2_RW_SEQUENCE_ENA 0x0001 /* DSP2_RW_SEQUENCE_ENA */ | |
| 3432 | #define WM2200_DSP2_RW_SEQUENCE_ENA_MASK 0x0001 /* DSP2_RW_SEQUENCE_ENA */ | |
| 3433 | #define WM2200_DSP2_RW_SEQUENCE_ENA_SHIFT 0 /* DSP2_RW_SEQUENCE_ENA */ | |
| 3434 | #define WM2200_DSP2_RW_SEQUENCE_ENA_WIDTH 1 /* DSP2_RW_SEQUENCE_ENA */ | |
| 3435 | ||
| 3436 | /* | |
| 3437 | * R2818 (0xB02) - DSP2 Control 2 | |
| 3438 | */ | |
| 3439 | #define WM2200_DSP2_PAGE_BASE_PM_0_MASK 0xFF00 /* DSP2_PAGE_BASE_PM - [15:8] */ | |
| 3440 | #define WM2200_DSP2_PAGE_BASE_PM_0_SHIFT 8 /* DSP2_PAGE_BASE_PM - [15:8] */ | |
| 3441 | #define WM2200_DSP2_PAGE_BASE_PM_0_WIDTH 8 /* DSP2_PAGE_BASE_PM - [15:8] */ | |
| 3442 | ||
| 3443 | /* | |
| 3444 | * R2819 (0xB03) - DSP2 Control 3 | |
| 3445 | */ | |
| 3446 | #define WM2200_DSP2_PAGE_BASE_DM_0_MASK 0xFF00 /* DSP2_PAGE_BASE_DM - [15:8] */ | |
| 3447 | #define WM2200_DSP2_PAGE_BASE_DM_0_SHIFT 8 /* DSP2_PAGE_BASE_DM - [15:8] */ | |
| 3448 | #define WM2200_DSP2_PAGE_BASE_DM_0_WIDTH 8 /* DSP2_PAGE_BASE_DM - [15:8] */ | |
| 3449 | ||
| 3450 | /* | |
| 3451 | * R2820 (0xB04) - DSP2 Control 4 | |
| 3452 | */ | |
| 3453 | #define WM2200_DSP2_PAGE_BASE_ZM_0_MASK 0xFF00 /* DSP2_PAGE_BASE_ZM - [15:8] */ | |
| 3454 | #define WM2200_DSP2_PAGE_BASE_ZM_0_SHIFT 8 /* DSP2_PAGE_BASE_ZM - [15:8] */ | |
| 3455 | #define WM2200_DSP2_PAGE_BASE_ZM_0_WIDTH 8 /* DSP2_PAGE_BASE_ZM - [15:8] */ | |
| 3456 | ||
| 3457 | /* | |
| 3458 | * R2822 (0xB06) - DSP2 Control 5 | |
| 3459 | */ | |
| 3460 | #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_0_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */ | |
| 3461 | #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_0_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */ | |
| 3462 | #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_0_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */ | |
| 3463 | ||
| 3464 | /* | |
| 3465 | * R2823 (0xB07) - DSP2 Control 6 | |
| 3466 | */ | |
| 3467 | #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_1_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */ | |
| 3468 | #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_1_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */ | |
| 3469 | #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_1_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */ | |
| 3470 | ||
| 3471 | /* | |
| 3472 | * R2824 (0xB08) - DSP2 Control 7 | |
| 3473 | */ | |
| 3474 | #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_2_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */ | |
| 3475 | #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_2_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */ | |
| 3476 | #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_2_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */ | |
| 3477 | ||
| 3478 | /* | |
| 3479 | * R2825 (0xB09) - DSP2 Control 8 | |
| 3480 | */ | |
| 3481 | #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_3_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */ | |
| 3482 | #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_3_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */ | |
| 3483 | #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_3_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */ | |
| 3484 | ||
| 3485 | /* | |
| 3486 | * R2826 (0xB0A) - DSP2 Control 9 | |
| 3487 | */ | |
| 3488 | #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_4_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */ | |
| 3489 | #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_4_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */ | |
| 3490 | #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_4_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */ | |
| 3491 | ||
| 3492 | /* | |
| 3493 | * R2827 (0xB0B) - DSP2 Control 10 | |
| 3494 | */ | |
| 3495 | #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_5_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */ | |
| 3496 | #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_5_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */ | |
| 3497 | #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_5_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */ | |
| 3498 | ||
| 3499 | /* | |
| 3500 | * R2828 (0xB0C) - DSP2 Control 11 | |
| 3501 | */ | |
| 3502 | #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_6_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */ | |
| 3503 | #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_6_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */ | |
| 3504 | #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_6_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */ | |
| 3505 | ||
| 3506 | /* | |
| 3507 | * R2829 (0xB0D) - DSP2 Control 12 | |
| 3508 | */ | |
| 3509 | #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_7_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */ | |
| 3510 | #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_7_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */ | |
| 3511 | #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_7_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */ | |
| 3512 | ||
| 3513 | /* | |
| 3514 | * R2831 (0xB0F) - DSP2 Control 13 | |
| 3515 | */ | |
| 3516 | #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_0_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */ | |
| 3517 | #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_0_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */ | |
| 3518 | #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_0_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */ | |
| 3519 | ||
| 3520 | /* | |
| 3521 | * R2832 (0xB10) - DSP2 Control 14 | |
| 3522 | */ | |
| 3523 | #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_1_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */ | |
| 3524 | #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_1_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */ | |
| 3525 | #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_1_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */ | |
| 3526 | ||
| 3527 | /* | |
| 3528 | * R2833 (0xB11) - DSP2 Control 15 | |
| 3529 | */ | |
| 3530 | #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_2_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */ | |
| 3531 | #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_2_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */ | |
| 3532 | #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_2_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */ | |
| 3533 | ||
| 3534 | /* | |
| 3535 | * R2834 (0xB12) - DSP2 Control 16 | |
| 3536 | */ | |
| 3537 | #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_3_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */ | |
| 3538 | #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_3_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */ | |
| 3539 | #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_3_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */ | |
| 3540 | ||
| 3541 | /* | |
| 3542 | * R2835 (0xB13) - DSP2 Control 17 | |
| 3543 | */ | |
| 3544 | #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_4_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */ | |
| 3545 | #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_4_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */ | |
| 3546 | #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_4_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */ | |
| 3547 | ||
| 3548 | /* | |
| 3549 | * R2836 (0xB14) - DSP2 Control 18 | |
| 3550 | */ | |
| 3551 | #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_5_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */ | |
| 3552 | #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_5_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */ | |
| 3553 | #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_5_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */ | |
| 3554 | ||
| 3555 | /* | |
| 3556 | * R2838 (0xB16) - DSP2 Control 19 | |
| 3557 | */ | |
| 3558 | #define WM2200_DSP2_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP2_WDMA_BUFFER_LENGTH - [7:0] */ | |
| 3559 | #define WM2200_DSP2_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP2_WDMA_BUFFER_LENGTH - [7:0] */ | |
| 3560 | #define WM2200_DSP2_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP2_WDMA_BUFFER_LENGTH - [7:0] */ | |
| 3561 | ||
| 3562 | /* | |
| 3563 | * R2839 (0xB17) - DSP2 Control 20 | |
| 3564 | */ | |
| 3565 | #define WM2200_DSP2_WDMA_CHANNEL_ENABLE_MASK 0x00FF /* DSP2_WDMA_CHANNEL_ENABLE - [7:0] */ | |
| 3566 | #define WM2200_DSP2_WDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP2_WDMA_CHANNEL_ENABLE - [7:0] */ | |
| 3567 | #define WM2200_DSP2_WDMA_CHANNEL_ENABLE_WIDTH 8 /* DSP2_WDMA_CHANNEL_ENABLE - [7:0] */ | |
| 3568 | ||
| 3569 | /* | |
| 3570 | * R2840 (0xB18) - DSP2 Control 21 | |
| 3571 | */ | |
| 3572 | #define WM2200_DSP2_RDMA_CHANNEL_ENABLE_MASK 0x003F /* DSP2_RDMA_CHANNEL_ENABLE - [5:0] */ | |
| 3573 | #define WM2200_DSP2_RDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP2_RDMA_CHANNEL_ENABLE - [5:0] */ | |
| 3574 | #define WM2200_DSP2_RDMA_CHANNEL_ENABLE_WIDTH 6 /* DSP2_RDMA_CHANNEL_ENABLE - [5:0] */ | |
| 3575 | ||
| 3576 | /* | |
| 3577 | * R2842 (0xB1A) - DSP2 Control 22 | |
| 3578 | */ | |
| 3579 | #define WM2200_DSP2_DM_SIZE_MASK 0xFFFF /* DSP2_DM_SIZE - [15:0] */ | |
| 3580 | #define WM2200_DSP2_DM_SIZE_SHIFT 0 /* DSP2_DM_SIZE - [15:0] */ | |
| 3581 | #define WM2200_DSP2_DM_SIZE_WIDTH 16 /* DSP2_DM_SIZE - [15:0] */ | |
| 3582 | ||
| 3583 | /* | |
| 3584 | * R2843 (0xB1B) - DSP2 Control 23 | |
| 3585 | */ | |
| 3586 | #define WM2200_DSP2_PM_SIZE_MASK 0xFFFF /* DSP2_PM_SIZE - [15:0] */ | |
| 3587 | #define WM2200_DSP2_PM_SIZE_SHIFT 0 /* DSP2_PM_SIZE - [15:0] */ | |
| 3588 | #define WM2200_DSP2_PM_SIZE_WIDTH 16 /* DSP2_PM_SIZE - [15:0] */ | |
| 3589 | ||
| 3590 | /* | |
| 3591 | * R2844 (0xB1C) - DSP2 Control 24 | |
| 3592 | */ | |
| 3593 | #define WM2200_DSP2_ZM_SIZE_MASK 0xFFFF /* DSP2_ZM_SIZE - [15:0] */ | |
| 3594 | #define WM2200_DSP2_ZM_SIZE_SHIFT 0 /* DSP2_ZM_SIZE - [15:0] */ | |
| 3595 | #define WM2200_DSP2_ZM_SIZE_WIDTH 16 /* DSP2_ZM_SIZE - [15:0] */ | |
| 3596 | ||
| 3597 | /* | |
| 3598 | * R2846 (0xB1E) - DSP2 Control 25 | |
| 3599 | */ | |
| 3600 | #define WM2200_DSP2_PING_FULL 0x8000 /* DSP2_PING_FULL */ | |
| 3601 | #define WM2200_DSP2_PING_FULL_MASK 0x8000 /* DSP2_PING_FULL */ | |
| 3602 | #define WM2200_DSP2_PING_FULL_SHIFT 15 /* DSP2_PING_FULL */ | |
| 3603 | #define WM2200_DSP2_PING_FULL_WIDTH 1 /* DSP2_PING_FULL */ | |
| 3604 | #define WM2200_DSP2_PONG_FULL 0x4000 /* DSP2_PONG_FULL */ | |
| 3605 | #define WM2200_DSP2_PONG_FULL_MASK 0x4000 /* DSP2_PONG_FULL */ | |
| 3606 | #define WM2200_DSP2_PONG_FULL_SHIFT 14 /* DSP2_PONG_FULL */ | |
| 3607 | #define WM2200_DSP2_PONG_FULL_WIDTH 1 /* DSP2_PONG_FULL */ | |
| 3608 | #define WM2200_DSP2_WDMA_ACTIVE_CHANNELS_MASK 0x00FF /* DSP2_WDMA_ACTIVE_CHANNELS - [7:0] */ | |
| 3609 | #define WM2200_DSP2_WDMA_ACTIVE_CHANNELS_SHIFT 0 /* DSP2_WDMA_ACTIVE_CHANNELS - [7:0] */ | |
| 3610 | #define WM2200_DSP2_WDMA_ACTIVE_CHANNELS_WIDTH 8 /* DSP2_WDMA_ACTIVE_CHANNELS - [7:0] */ | |
| 3611 | ||
| 3612 | /* | |
| 3613 | * R2848 (0xB20) - DSP2 Control 26 | |
| 3614 | */ | |
| 3615 | #define WM2200_DSP2_SCRATCH_0_MASK 0xFFFF /* DSP2_SCRATCH_0 - [15:0] */ | |
| 3616 | #define WM2200_DSP2_SCRATCH_0_SHIFT 0 /* DSP2_SCRATCH_0 - [15:0] */ | |
| 3617 | #define WM2200_DSP2_SCRATCH_0_WIDTH 16 /* DSP2_SCRATCH_0 - [15:0] */ | |
| 3618 | ||
| 3619 | /* | |
| 3620 | * R2849 (0xB21) - DSP2 Control 27 | |
| 3621 | */ | |
| 3622 | #define WM2200_DSP2_SCRATCH_1_MASK 0xFFFF /* DSP2_SCRATCH_1 - [15:0] */ | |
| 3623 | #define WM2200_DSP2_SCRATCH_1_SHIFT 0 /* DSP2_SCRATCH_1 - [15:0] */ | |
| 3624 | #define WM2200_DSP2_SCRATCH_1_WIDTH 16 /* DSP2_SCRATCH_1 - [15:0] */ | |
| 3625 | ||
| 3626 | /* | |
| 3627 | * R2850 (0xB22) - DSP2 Control 28 | |
| 3628 | */ | |
| 3629 | #define WM2200_DSP2_SCRATCH_2_MASK 0xFFFF /* DSP2_SCRATCH_2 - [15:0] */ | |
| 3630 | #define WM2200_DSP2_SCRATCH_2_SHIFT 0 /* DSP2_SCRATCH_2 - [15:0] */ | |
| 3631 | #define WM2200_DSP2_SCRATCH_2_WIDTH 16 /* DSP2_SCRATCH_2 - [15:0] */ | |
| 3632 | ||
| 3633 | /* | |
| 3634 | * R2851 (0xB23) - DSP2 Control 29 | |
| 3635 | */ | |
| 3636 | #define WM2200_DSP2_SCRATCH_3_MASK 0xFFFF /* DSP2_SCRATCH_3 - [15:0] */ | |
| 3637 | #define WM2200_DSP2_SCRATCH_3_SHIFT 0 /* DSP2_SCRATCH_3 - [15:0] */ | |
| 3638 | #define WM2200_DSP2_SCRATCH_3_WIDTH 16 /* DSP2_SCRATCH_3 - [15:0] */ | |
| 3639 | ||
| 3640 | /* | |
| 3641 | * R2852 (0xB24) - DSP2 Control 30 | |
| 3642 | */ | |
| 3643 | #define WM2200_DSP2_DBG_CLK_ENA 0x0008 /* DSP2_DBG_CLK_ENA */ | |
| 3644 | #define WM2200_DSP2_DBG_CLK_ENA_MASK 0x0008 /* DSP2_DBG_CLK_ENA */ | |
| 3645 | #define WM2200_DSP2_DBG_CLK_ENA_SHIFT 3 /* DSP2_DBG_CLK_ENA */ | |
| 3646 | #define WM2200_DSP2_DBG_CLK_ENA_WIDTH 1 /* DSP2_DBG_CLK_ENA */ | |
| 3647 | #define WM2200_DSP2_SYS_ENA 0x0004 /* DSP2_SYS_ENA */ | |
| 3648 | #define WM2200_DSP2_SYS_ENA_MASK 0x0004 /* DSP2_SYS_ENA */ | |
| 3649 | #define WM2200_DSP2_SYS_ENA_SHIFT 2 /* DSP2_SYS_ENA */ | |
| 3650 | #define WM2200_DSP2_SYS_ENA_WIDTH 1 /* DSP2_SYS_ENA */ | |
| 3651 | #define WM2200_DSP2_CORE_ENA 0x0002 /* DSP2_CORE_ENA */ | |
| 3652 | #define WM2200_DSP2_CORE_ENA_MASK 0x0002 /* DSP2_CORE_ENA */ | |
| 3653 | #define WM2200_DSP2_CORE_ENA_SHIFT 1 /* DSP2_CORE_ENA */ | |
| 3654 | #define WM2200_DSP2_CORE_ENA_WIDTH 1 /* DSP2_CORE_ENA */ | |
| 3655 | #define WM2200_DSP2_START 0x0001 /* DSP2_START */ | |
| 3656 | #define WM2200_DSP2_START_MASK 0x0001 /* DSP2_START */ | |
| 3657 | #define WM2200_DSP2_START_SHIFT 0 /* DSP2_START */ | |
| 3658 | #define WM2200_DSP2_START_WIDTH 1 /* DSP2_START */ | |
| 3659 | ||
| 3660 | /* | |
| 3661 | * R2854 (0xB26) - DSP2 Control 31 | |
| 3662 | */ | |
| 3663 | #define WM2200_DSP2_CLK_RATE_MASK 0x0018 /* DSP2_CLK_RATE - [4:3] */ | |
| 3664 | #define WM2200_DSP2_CLK_RATE_SHIFT 3 /* DSP2_CLK_RATE - [4:3] */ | |
| 3665 | #define WM2200_DSP2_CLK_RATE_WIDTH 2 /* DSP2_CLK_RATE - [4:3] */ | |
| 3666 | #define WM2200_DSP2_CLK_AVAIL 0x0004 /* DSP2_CLK_AVAIL */ | |
| 3667 | #define WM2200_DSP2_CLK_AVAIL_MASK 0x0004 /* DSP2_CLK_AVAIL */ | |
| 3668 | #define WM2200_DSP2_CLK_AVAIL_SHIFT 2 /* DSP2_CLK_AVAIL */ | |
| 3669 | #define WM2200_DSP2_CLK_AVAIL_WIDTH 1 /* DSP2_CLK_AVAIL */ | |
| 3670 | #define WM2200_DSP2_CLK_REQ_MASK 0x0003 /* DSP2_CLK_REQ - [1:0] */ | |
| 3671 | #define WM2200_DSP2_CLK_REQ_SHIFT 0 /* DSP2_CLK_REQ - [1:0] */ | |
| 3672 | #define WM2200_DSP2_CLK_REQ_WIDTH 2 /* DSP2_CLK_REQ - [1:0] */ | |
| 3673 | ||
| 3674 | #endif |