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ASoC: UDA1380: change decimator/interpolator register handling
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / uda1380.c
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b7482f52
PZ		 1/*
2 * uda1380.c - Philips UDA1380 ALSA SoC audio driver
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Copyright (c) 2007 Philipp Zabel <philipp.zabel@gmail.com>
9 * Improved support for DAPM and audio routing/mixing capabilities,
10 * added TLV support.
11 *
12 * Modified by Richard Purdie <richard@openedhand.com> to fit into SoC
13 * codec model.
14 *
15 * Copyright (c) 2005 Giorgio Padrin <giorgio@mandarinlogiq.org>
16 * Copyright 2005 Openedhand Ltd.
17 */
18
19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/types.h>
22#include <linux/string.h>
23#include <linux/slab.h>
24#include <linux/errno.h>
25#include <linux/ioctl.h>
26#include <linux/delay.h>
27#include <linux/i2c.h>
ef9e5e5c 28#include <linux/workqueue.h>
b7482f52
PZ		 29#include <sound/core.h>
30#include <sound/control.h>
31#include <sound/initval.h>
32#include <sound/info.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/tlv.h>
36
37#include "uda1380.h"
38
ef9e5e5c
PZ		 39static struct work_struct uda1380_work;
40static struct snd_soc_codec *uda1380_codec;
41
b7482f52
PZ		 42/*
43 * uda1380 register cache
44 */
45static const u16 uda1380_reg[UDA1380_CACHEREGNUM] = {
46 0x0502, 0x0000, 0x0000, 0x3f3f,
47 0x0202, 0x0000, 0x0000, 0x0000,
48 0x0000, 0x0000, 0x0000, 0x0000,
49 0x0000, 0x0000, 0x0000, 0x0000,
50 0x0000, 0xff00, 0x0000, 0x4800,
51 0x0000, 0x0000, 0x0000, 0x0000,
52 0x0000, 0x0000, 0x0000, 0x0000,
53 0x0000, 0x0000, 0x0000, 0x0000,
54 0x0000, 0x8000, 0x0002, 0x0000,
55};
56
ef9e5e5c
PZ		 57static unsigned long uda1380_cache_dirty;
58
b7482f52
PZ		 59/*
60 * read uda1380 register cache
61 */
62static inline unsigned int uda1380_read_reg_cache(struct snd_soc_codec *codec,
63 unsigned int reg)
64{
65 u16 *cache = codec->reg_cache;
66 if (reg == UDA1380_RESET)
67 return 0;
68 if (reg >= UDA1380_CACHEREGNUM)
69 return -1;
70 return cache[reg];
71}
72
73/*
74 * write uda1380 register cache
75 */
76static inline void uda1380_write_reg_cache(struct snd_soc_codec *codec,
77 u16 reg, unsigned int value)
78{
79 u16 *cache = codec->reg_cache;
ef9e5e5c 80
b7482f52
PZ		 81 if (reg >= UDA1380_CACHEREGNUM)
82 return;
ef9e5e5c
PZ		 83 if ((reg >= 0x10) && (cache[reg] != value))
84 set_bit(reg - 0x10, &uda1380_cache_dirty);
b7482f52
PZ		 85 cache[reg] = value;
86}
87
88/*
89 * write to the UDA1380 register space
90 */
91static int uda1380_write(struct snd_soc_codec *codec, unsigned int reg,
92 unsigned int value)
93{
94 u8 data[3];
95
96 /* data is
97 * data[0] is register offset
98 * data[1] is MS byte
99 * data[2] is LS byte
100 */
101 data[0] = reg;
102 data[1] = (value & 0xff00) >> 8;
103 data[2] = value & 0x00ff;
104
105 uda1380_write_reg_cache(codec, reg, value);
106
107 /* the interpolator & decimator regs must only be written when the
108 * codec DAI is active.
109 */
110 if (!codec->active && (reg >= UDA1380_MVOL))
111 return 0;
112 pr_debug("uda1380: hw write %x val %x\n", reg, value);
113 if (codec->hw_write(codec->control_data, data, 3) == 3) {
114 unsigned int val;
115 i2c_master_send(codec->control_data, data, 1);
116 i2c_master_recv(codec->control_data, data, 2);
117 val = (data[0]<<8) | data[1];
118 if (val != value) {
119 pr_debug("uda1380: READ BACK VAL %x\n",
120 (data[0]<<8) | data[1]);
121 return -EIO;
122 }
ef9e5e5c
PZ		 123 if (reg >= 0x10)
124 clear_bit(reg - 0x10, &uda1380_cache_dirty);
b7482f52
PZ		 125 return 0;
126 } else
127 return -EIO;
128}
129
130#define uda1380_reset(c) uda1380_write(c, UDA1380_RESET, 0)
131
ef9e5e5c
PZ		 132static void uda1380_flush_work(struct work_struct *work)
133{
134 int bit, reg;
135
136 for_each_bit(bit, &uda1380_cache_dirty, UDA1380_CACHEREGNUM - 0x10) {
137 reg = 0x10 + bit;
138 pr_debug("uda1380: flush reg %x val %x:\n", reg,
139 uda1380_read_reg_cache(uda1380_codec, reg));
140 uda1380_write(uda1380_codec, reg,
141 uda1380_read_reg_cache(uda1380_codec, reg));
142 clear_bit(bit, &uda1380_cache_dirty);
143 }
144}
145
b7482f52
PZ		 146/* declarations of ALSA reg_elem_REAL controls */
147static const char *uda1380_deemp[] = {
148 "None",
149 "32kHz",
150 "44.1kHz",
151 "48kHz",
152 "96kHz",
153};
154static const char *uda1380_input_sel[] = {
155 "Line",
156 "Mic + Line R",
157 "Line L",
158 "Mic",
159};
160static const char *uda1380_output_sel[] = {
161 "DAC",
162 "Analog Mixer",
163};
164static const char *uda1380_spf_mode[] = {
165 "Flat",
166 "Minimum1",
167 "Minimum2",
168 "Maximum"
169};
170static const char *uda1380_capture_sel[] = {
171 "ADC",
172 "Digital Mixer"
173};
174static const char *uda1380_sel_ns[] = {
175 "3rd-order",
176 "5th-order"
177};
178static const char *uda1380_mix_control[] = {
179 "off",
180 "PCM only",
181 "before sound processing",
182 "after sound processing"
183};
184static const char *uda1380_sdet_setting[] = {
185 "3200",
186 "4800",
187 "9600",
188 "19200"
189};
190static const char *uda1380_os_setting[] = {
191 "single-speed",
192 "double-speed (no mixing)",
193 "quad-speed (no mixing)"
194};
195
196static const struct soc_enum uda1380_deemp_enum[] = {
197 SOC_ENUM_SINGLE(UDA1380_DEEMP, 8, 5, uda1380_deemp),
198 SOC_ENUM_SINGLE(UDA1380_DEEMP, 0, 5, uda1380_deemp),
199};
200static const struct soc_enum uda1380_input_sel_enum =
201 SOC_ENUM_SINGLE(UDA1380_ADC, 2, 4, uda1380_input_sel); /* SEL_MIC, SEL_LNA */
202static const struct soc_enum uda1380_output_sel_enum =
203 SOC_ENUM_SINGLE(UDA1380_PM, 7, 2, uda1380_output_sel); /* R02_EN_AVC */
204static const struct soc_enum uda1380_spf_enum =
205 SOC_ENUM_SINGLE(UDA1380_MODE, 14, 4, uda1380_spf_mode); /* M */
206static const struct soc_enum uda1380_capture_sel_enum =
207 SOC_ENUM_SINGLE(UDA1380_IFACE, 6, 2, uda1380_capture_sel); /* SEL_SOURCE */
208static const struct soc_enum uda1380_sel_ns_enum =
209 SOC_ENUM_SINGLE(UDA1380_MIXER, 14, 2, uda1380_sel_ns); /* SEL_NS */
210static const struct soc_enum uda1380_mix_enum =
211 SOC_ENUM_SINGLE(UDA1380_MIXER, 12, 4, uda1380_mix_control); /* MIX, MIX_POS */
212static const struct soc_enum uda1380_sdet_enum =
213 SOC_ENUM_SINGLE(UDA1380_MIXER, 4, 4, uda1380_sdet_setting); /* SD_VALUE */
214static const struct soc_enum uda1380_os_enum =
215 SOC_ENUM_SINGLE(UDA1380_MIXER, 0, 3, uda1380_os_setting); /* OS */
216
217/*
218 * from -48 dB in 1.5 dB steps (mute instead of -49.5 dB)
219 */
220static DECLARE_TLV_DB_SCALE(amix_tlv, -4950, 150, 1);
221
222/*
223 * from -78 dB in 1 dB steps (3 dB steps, really. LSB are ignored),
224 * from -66 dB in 0.5 dB steps (2 dB steps, really) and
225 * from -52 dB in 0.25 dB steps
226 */
227static const unsigned int mvol_tlv[] = {
228 TLV_DB_RANGE_HEAD(3),
229 0, 15, TLV_DB_SCALE_ITEM(-8200, 100, 1),
230 16, 43, TLV_DB_SCALE_ITEM(-6600, 50, 0),
231 44, 252, TLV_DB_SCALE_ITEM(-5200, 25, 0),
232};
233
234/*
235 * from -72 dB in 1.5 dB steps (6 dB steps really),
236 * from -66 dB in 0.75 dB steps (3 dB steps really),
237 * from -60 dB in 0.5 dB steps (2 dB steps really) and
238 * from -46 dB in 0.25 dB steps
239 */
240static const unsigned int vc_tlv[] = {
241 TLV_DB_RANGE_HEAD(4),
242 0, 7, TLV_DB_SCALE_ITEM(-7800, 150, 1),
243 8, 15, TLV_DB_SCALE_ITEM(-6600, 75, 0),
244 16, 43, TLV_DB_SCALE_ITEM(-6000, 50, 0),
245 44, 228, TLV_DB_SCALE_ITEM(-4600, 25, 0),
246};
247
248/* from 0 to 6 dB in 2 dB steps if SPF mode != flat */
249static DECLARE_TLV_DB_SCALE(tr_tlv, 0, 200, 0);
250
251/* from 0 to 24 dB in 2 dB steps, if SPF mode == maximum, otherwise cuts
252 * off at 18 dB max) */
253static DECLARE_TLV_DB_SCALE(bb_tlv, 0, 200, 0);
254
255/* from -63 to 24 dB in 0.5 dB steps (-128...48) */
256static DECLARE_TLV_DB_SCALE(dec_tlv, -6400, 50, 1);
257
258/* from 0 to 24 dB in 3 dB steps */
259static DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0);
260
261/* from 0 to 30 dB in 2 dB steps */
262static DECLARE_TLV_DB_SCALE(vga_tlv, 0, 200, 0);
263
264static const struct snd_kcontrol_new uda1380_snd_controls[] = {
265 SOC_DOUBLE_TLV("Analog Mixer Volume", UDA1380_AMIX, 0, 8, 44, 1, amix_tlv), /* AVCR, AVCL */
266 SOC_DOUBLE_TLV("Master Playback Volume", UDA1380_MVOL, 0, 8, 252, 1, mvol_tlv), /* MVCL, MVCR */
267 SOC_SINGLE_TLV("ADC Playback Volume", UDA1380_MIXVOL, 8, 228, 1, vc_tlv), /* VC2 */
268 SOC_SINGLE_TLV("PCM Playback Volume", UDA1380_MIXVOL, 0, 228, 1, vc_tlv), /* VC1 */
269 SOC_ENUM("Sound Processing Filter", uda1380_spf_enum), /* M */
270 SOC_DOUBLE_TLV("Tone Control - Treble", UDA1380_MODE, 4, 12, 3, 0, tr_tlv), /* TRL, TRR */
271 SOC_DOUBLE_TLV("Tone Control - Bass", UDA1380_MODE, 0, 8, 15, 0, bb_tlv), /* BBL, BBR */
272/**/ SOC_SINGLE("Master Playback Switch", UDA1380_DEEMP, 14, 1, 1), /* MTM */
273 SOC_SINGLE("ADC Playback Switch", UDA1380_DEEMP, 11, 1, 1), /* MT2 from decimation filter */
274 SOC_ENUM("ADC Playback De-emphasis", uda1380_deemp_enum[0]), /* DE2 */
275 SOC_SINGLE("PCM Playback Switch", UDA1380_DEEMP, 3, 1, 1), /* MT1, from digital data input */
276 SOC_ENUM("PCM Playback De-emphasis", uda1380_deemp_enum[1]), /* DE1 */
277 SOC_SINGLE("DAC Polarity inverting Switch", UDA1380_MIXER, 15, 1, 0), /* DA_POL_INV */
278 SOC_ENUM("Noise Shaper", uda1380_sel_ns_enum), /* SEL_NS */
279 SOC_ENUM("Digital Mixer Signal Control", uda1380_mix_enum), /* MIX_POS, MIX */
b7482f52
PZ		 280 SOC_SINGLE("Silence Detector Switch", UDA1380_MIXER, 6, 1, 0), /* SDET_ON */
281 SOC_ENUM("Silence Detector Setting", uda1380_sdet_enum), /* SD_VALUE */
282 SOC_ENUM("Oversampling Input", uda1380_os_enum), /* OS */
283 SOC_DOUBLE_S8_TLV("ADC Capture Volume", UDA1380_DEC, -128, 48, dec_tlv), /* ML_DEC, MR_DEC */
284/**/ SOC_SINGLE("ADC Capture Switch", UDA1380_PGA, 15, 1, 1), /* MT_ADC */
285 SOC_DOUBLE_TLV("Line Capture Volume", UDA1380_PGA, 0, 8, 8, 0, pga_tlv), /* PGA_GAINCTRLL, PGA_GAINCTRLR */
286 SOC_SINGLE("ADC Polarity inverting Switch", UDA1380_ADC, 12, 1, 0), /* ADCPOL_INV */
287 SOC_SINGLE_TLV("Mic Capture Volume", UDA1380_ADC, 8, 15, 0, vga_tlv), /* VGA_CTRL */
288 SOC_SINGLE("DC Filter Bypass Switch", UDA1380_ADC, 1, 1, 0), /* SKIP_DCFIL (before decimator) */
289 SOC_SINGLE("DC Filter Enable Switch", UDA1380_ADC, 0, 1, 0), /* EN_DCFIL (at output of decimator) */
290 SOC_SINGLE("AGC Timing", UDA1380_AGC, 8, 7, 0), /* TODO: enum, see table 62 */
291 SOC_SINGLE("AGC Target level", UDA1380_AGC, 2, 3, 1), /* AGC_LEVEL */
292 /* -5.5, -8, -11.5, -14 dBFS */
293 SOC_SINGLE("AGC Switch", UDA1380_AGC, 0, 1, 0),
294};
295
b7482f52
PZ		 296/* Input mux */
297static const struct snd_kcontrol_new uda1380_input_mux_control =
298 SOC_DAPM_ENUM("Route", uda1380_input_sel_enum);
299
300/* Output mux */
301static const struct snd_kcontrol_new uda1380_output_mux_control =
302 SOC_DAPM_ENUM("Route", uda1380_output_sel_enum);
303
304/* Capture mux */
305static const struct snd_kcontrol_new uda1380_capture_mux_control =
306 SOC_DAPM_ENUM("Route", uda1380_capture_sel_enum);
307
308
309static const struct snd_soc_dapm_widget uda1380_dapm_widgets[] = {
310 SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,
311 &uda1380_input_mux_control),
312 SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM, 0, 0,
313 &uda1380_output_mux_control),
314 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0,
315 &uda1380_capture_mux_control),
316 SND_SOC_DAPM_PGA("Left PGA", UDA1380_PM, 3, 0, NULL, 0),
317 SND_SOC_DAPM_PGA("Right PGA", UDA1380_PM, 1, 0, NULL, 0),
318 SND_SOC_DAPM_PGA("Mic LNA", UDA1380_PM, 4, 0, NULL, 0),
319 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", UDA1380_PM, 2, 0),
320 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", UDA1380_PM, 0, 0),
321 SND_SOC_DAPM_INPUT("VINM"),
322 SND_SOC_DAPM_INPUT("VINL"),
323 SND_SOC_DAPM_INPUT("VINR"),
324 SND_SOC_DAPM_MIXER("Analog Mixer", UDA1380_PM, 6, 0, NULL, 0),
325 SND_SOC_DAPM_OUTPUT("VOUTLHP"),
326 SND_SOC_DAPM_OUTPUT("VOUTRHP"),
327 SND_SOC_DAPM_OUTPUT("VOUTL"),
328 SND_SOC_DAPM_OUTPUT("VOUTR"),
329 SND_SOC_DAPM_DAC("DAC", "Playback", UDA1380_PM, 10, 0),
330 SND_SOC_DAPM_PGA("HeadPhone Driver", UDA1380_PM, 13, 0, NULL, 0),
331};
332
333static const struct snd_soc_dapm_route audio_map[] = {
334
335 /* output mux */
336 {"HeadPhone Driver", NULL, "Output Mux"},
337 {"VOUTR", NULL, "Output Mux"},
338 {"VOUTL", NULL, "Output Mux"},
339
340 {"Analog Mixer", NULL, "VINR"},
341 {"Analog Mixer", NULL, "VINL"},
342 {"Analog Mixer", NULL, "DAC"},
343
344 {"Output Mux", "DAC", "DAC"},
345 {"Output Mux", "Analog Mixer", "Analog Mixer"},
346
347 /* {"DAC", "Digital Mixer", "I2S" } */
348
349 /* headphone driver */
350 {"VOUTLHP", NULL, "HeadPhone Driver"},
351 {"VOUTRHP", NULL, "HeadPhone Driver"},
352
353 /* input mux */
354 {"Left ADC", NULL, "Input Mux"},
355 {"Input Mux", "Mic", "Mic LNA"},
356 {"Input Mux", "Mic + Line R", "Mic LNA"},
357 {"Input Mux", "Line L", "Left PGA"},
358 {"Input Mux", "Line", "Left PGA"},
359
360 /* right input */
361 {"Right ADC", "Mic + Line R", "Right PGA"},
362 {"Right ADC", "Line", "Right PGA"},
363
364 /* inputs */
365 {"Mic LNA", NULL, "VINM"},
366 {"Left PGA", NULL, "VINL"},
367 {"Right PGA", NULL, "VINR"},
368};
369
370static int uda1380_add_widgets(struct snd_soc_codec *codec)
371{
372 snd_soc_dapm_new_controls(codec, uda1380_dapm_widgets,
373 ARRAY_SIZE(uda1380_dapm_widgets));
374
375 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
376
377 snd_soc_dapm_new_widgets(codec);
378 return 0;
379}
380
5b247442 381static int uda1380_set_dai_fmt_both(struct snd_soc_dai *codec_dai,
b7482f52
PZ		 382 unsigned int fmt)
383{
384 struct snd_soc_codec *codec = codec_dai->codec;
385 int iface;
386
387 /* set up DAI based upon fmt */
388 iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
389 iface &= ~(R01_SFORI_MASK | R01_SIM | R01_SFORO_MASK);
390
b7482f52
PZ		 391 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
392 case SND_SOC_DAIFMT_I2S:
393 iface |= R01_SFORI_I2S | R01_SFORO_I2S;
394 break;
395 case SND_SOC_DAIFMT_LSB:
5b247442 396 iface |= R01_SFORI_LSB16 | R01_SFORO_LSB16;
b7482f52
PZ		 397 break;
398 case SND_SOC_DAIFMT_MSB:
5b247442
PZ		 399 iface |= R01_SFORI_MSB | R01_SFORO_MSB;
400 }
401
402 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBM_CFM)
403 iface |= R01_SIM;
404
405 uda1380_write(codec, UDA1380_IFACE, iface);
406
407 return 0;
408}
409
410static int uda1380_set_dai_fmt_playback(struct snd_soc_dai *codec_dai,
411 unsigned int fmt)
412{
413 struct snd_soc_codec *codec = codec_dai->codec;
414 int iface;
415
416 /* set up DAI based upon fmt */
417 iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
418 iface &= ~R01_SFORI_MASK;
419
420 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
421 case SND_SOC_DAIFMT_I2S:
422 iface |= R01_SFORI_I2S;
423 break;
424 case SND_SOC_DAIFMT_LSB:
425 iface |= R01_SFORI_LSB16;
426 break;
427 case SND_SOC_DAIFMT_MSB:
428 iface |= R01_SFORI_MSB;
429 }
430
431 uda1380_write(codec, UDA1380_IFACE, iface);
432
433 return 0;
434}
435
436static int uda1380_set_dai_fmt_capture(struct snd_soc_dai *codec_dai,
437 unsigned int fmt)
438{
439 struct snd_soc_codec *codec = codec_dai->codec;
440 int iface;
441
442 /* set up DAI based upon fmt */
443 iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
444 iface &= ~(R01_SIM | R01_SFORO_MASK);
445
446 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
447 case SND_SOC_DAIFMT_I2S:
448 iface |= R01_SFORO_I2S;
449 break;
450 case SND_SOC_DAIFMT_LSB:
451 iface |= R01_SFORO_LSB16;
452 break;
453 case SND_SOC_DAIFMT_MSB:
454 iface |= R01_SFORO_MSB;
b7482f52
PZ		 455 }
456
457 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBM_CFM)
458 iface |= R01_SIM;
459
460 uda1380_write(codec, UDA1380_IFACE, iface);
461
462 return 0;
463}
464
ef9e5e5c
PZ		 465static int uda1380_trigger(struct snd_pcm_substream *substream, int cmd,
466 struct snd_soc_dai *dai)
b7482f52
PZ		 467{
468 struct snd_soc_pcm_runtime *rtd = substream->private_data;
469 struct snd_soc_device *socdev = rtd->socdev;
6627a653 470 struct snd_soc_codec *codec = socdev->card->codec;
ef9e5e5c
PZ		 471 int mixer = uda1380_read_reg_cache(codec, UDA1380_MIXER);
472
473 switch (cmd) {
474 case SNDRV_PCM_TRIGGER_START:
475 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
476 uda1380_write_reg_cache(codec, UDA1380_MIXER,
477 mixer & ~R14_SILENCE);
478 schedule_work(&uda1380_work);
479 break;
480 case SNDRV_PCM_TRIGGER_STOP:
481 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
482 uda1380_write_reg_cache(codec, UDA1380_MIXER,
483 mixer | R14_SILENCE);
484 schedule_work(&uda1380_work);
485 break;
b7482f52 486 }
b7482f52
PZ		 487 return 0;
488}
489
490static int uda1380_pcm_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 491 struct snd_pcm_hw_params *params,
492 struct snd_soc_dai *dai)
b7482f52
PZ		 493{
494 struct snd_soc_pcm_runtime *rtd = substream->private_data;
495 struct snd_soc_device *socdev = rtd->socdev;
6627a653 496 struct snd_soc_codec *codec = socdev->card->codec;
b7482f52
PZ		 497 u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
498
499 /* set WSPLL power and divider if running from this clock */
500 if (clk & R00_DAC_CLK) {
501 int rate = params_rate(params);
502 u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM);
503 clk &= ~0x3; /* clear SEL_LOOP_DIV */
504 switch (rate) {
505 case 6250 ... 12500:
506 clk |= 0x0;
507 break;
508 case 12501 ... 25000:
509 clk |= 0x1;
510 break;
511 case 25001 ... 50000:
512 clk |= 0x2;
513 break;
514 case 50001 ... 100000:
515 clk |= 0x3;
516 break;
517 }
518 uda1380_write(codec, UDA1380_PM, R02_PON_PLL | pm);
519 }
520
521 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
522 clk |= R00_EN_DAC | R00_EN_INT;
523 else
524 clk |= R00_EN_ADC | R00_EN_DEC;
525
526 uda1380_write(codec, UDA1380_CLK, clk);
527 return 0;
528}
529
dee89c4d
MB		 530static void uda1380_pcm_shutdown(struct snd_pcm_substream *substream,
531 struct snd_soc_dai *dai)
b7482f52
PZ		 532{
533 struct snd_soc_pcm_runtime *rtd = substream->private_data;
534 struct snd_soc_device *socdev = rtd->socdev;
6627a653 535 struct snd_soc_codec *codec = socdev->card->codec;
b7482f52
PZ		 536 u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
537
538 /* shut down WSPLL power if running from this clock */
539 if (clk & R00_DAC_CLK) {
540 u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM);
541 uda1380_write(codec, UDA1380_PM, ~R02_PON_PLL & pm);
542 }
543
544 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
545 clk &= ~(R00_EN_DAC | R00_EN_INT);
546 else
547 clk &= ~(R00_EN_ADC | R00_EN_DEC);
548
549 uda1380_write(codec, UDA1380_CLK, clk);
550}
551
b7482f52
PZ		 552static int uda1380_set_bias_level(struct snd_soc_codec *codec,
553 enum snd_soc_bias_level level)
554{
555 int pm = uda1380_read_reg_cache(codec, UDA1380_PM);
556
557 switch (level) {
558 case SND_SOC_BIAS_ON:
559 case SND_SOC_BIAS_PREPARE:
560 uda1380_write(codec, UDA1380_PM, R02_PON_BIAS | pm);
561 break;
562 case SND_SOC_BIAS_STANDBY:
563 uda1380_write(codec, UDA1380_PM, R02_PON_BIAS);
564 break;
565 case SND_SOC_BIAS_OFF:
566 uda1380_write(codec, UDA1380_PM, 0x0);
567 break;
568 }
569 codec->bias_level = level;
570 return 0;
571}
572
573#define UDA1380_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
574 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
575 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
576
e550e17f 577struct snd_soc_dai uda1380_dai[] = {
b7482f52
PZ		 578{
579 .name = "UDA1380",
580 .playback = {
581 .stream_name = "Playback",
582 .channels_min = 1,
583 .channels_max = 2,
584 .rates = UDA1380_RATES,
585 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
586 .capture = {
587 .stream_name = "Capture",
588 .channels_min = 1,
589 .channels_max = 2,
590 .rates = UDA1380_RATES,
591 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
592 .ops = {
ef9e5e5c 593 .trigger = uda1380_trigger,
b7482f52
PZ		 594 .hw_params = uda1380_pcm_hw_params,
595 .shutdown = uda1380_pcm_shutdown,
5b247442 596 .set_fmt = uda1380_set_dai_fmt_both,
b7482f52
PZ		 597 },
598},
599{ /* playback only - dual interface */
600 .name = "UDA1380",
601 .playback = {
602 .stream_name = "Playback",
603 .channels_min = 1,
604 .channels_max = 2,
605 .rates = UDA1380_RATES,
606 .formats = SNDRV_PCM_FMTBIT_S16_LE,
607 },
608 .ops = {
ef9e5e5c 609 .trigger = uda1380_trigger,
b7482f52
PZ		 610 .hw_params = uda1380_pcm_hw_params,
611 .shutdown = uda1380_pcm_shutdown,
5b247442 612 .set_fmt = uda1380_set_dai_fmt_playback,
b7482f52
PZ		 613 },
614},
615{ /* capture only - dual interface*/
616 .name = "UDA1380",
617 .capture = {
618 .stream_name = "Capture",
619 .channels_min = 1,
620 .channels_max = 2,
621 .rates = UDA1380_RATES,
622 .formats = SNDRV_PCM_FMTBIT_S16_LE,
623 },
624 .ops = {
ef9e5e5c 625 .trigger = uda1380_trigger,
b7482f52
PZ		 626 .hw_params = uda1380_pcm_hw_params,
627 .shutdown = uda1380_pcm_shutdown,
5b247442 628 .set_fmt = uda1380_set_dai_fmt_capture,
b7482f52
PZ		 629 },
630},
631};
632EXPORT_SYMBOL_GPL(uda1380_dai);
633
634static int uda1380_suspend(struct platform_device *pdev, pm_message_t state)
635{
636 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 637 struct snd_soc_codec *codec = socdev->card->codec;
b7482f52
PZ		 638
639 uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
640 return 0;
641}
642
643static int uda1380_resume(struct platform_device *pdev)
644{
645 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 646 struct snd_soc_codec *codec = socdev->card->codec;
b7482f52
PZ		 647 int i;
648 u8 data[2];
649 u16 *cache = codec->reg_cache;
650
651 /* Sync reg_cache with the hardware */
652 for (i = 0; i < ARRAY_SIZE(uda1380_reg); i++) {
653 data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
654 data[1] = cache[i] & 0x00ff;
655 codec->hw_write(codec->control_data, data, 2);
656 }
657 uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
658 uda1380_set_bias_level(codec, codec->suspend_bias_level);
659 return 0;
660}
661
662/*
663 * initialise the UDA1380 driver
664 * register mixer and dsp interfaces with the kernel
665 */
666static int uda1380_init(struct snd_soc_device *socdev, int dac_clk)
667{
6627a653 668 struct snd_soc_codec *codec = socdev->card->codec;
b7482f52
PZ		 669 int ret = 0;
670
671 codec->name = "UDA1380";
672 codec->owner = THIS_MODULE;
673 codec->read = uda1380_read_reg_cache;
674 codec->write = uda1380_write;
675 codec->set_bias_level = uda1380_set_bias_level;
676 codec->dai = uda1380_dai;
677 codec->num_dai = ARRAY_SIZE(uda1380_dai);
678 codec->reg_cache = kmemdup(uda1380_reg, sizeof(uda1380_reg),
679 GFP_KERNEL);
680 if (codec->reg_cache == NULL)
681 return -ENOMEM;
8ddd4407
MB		 682 codec->reg_cache_size = ARRAY_SIZE(uda1380_reg);
683 codec->reg_cache_step = 1;
b7482f52
PZ		 684 uda1380_reset(codec);
685
ef9e5e5c
PZ		 686 uda1380_codec = codec;
687 INIT_WORK(&uda1380_work, uda1380_flush_work);
688
b7482f52
PZ		 689 /* register pcms */
690 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
691 if (ret < 0) {
692 pr_err("uda1380: failed to create pcms\n");
693 goto pcm_err;
694 }
695
696 /* power on device */
697 uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
698 /* set clock input */
699 switch (dac_clk) {
700 case UDA1380_DAC_CLK_SYSCLK:
701 uda1380_write(codec, UDA1380_CLK, 0);
702 break;
703 case UDA1380_DAC_CLK_WSPLL:
704 uda1380_write(codec, UDA1380_CLK, R00_DAC_CLK);
705 break;
706 }
707
708 /* uda1380 init */
3e8e1952
IM		 709 snd_soc_add_controls(codec, uda1380_snd_controls,
710 ARRAY_SIZE(uda1380_snd_controls));
b7482f52 711 uda1380_add_widgets(codec);
968a6025 712 ret = snd_soc_init_card(socdev);
b7482f52
PZ		 713 if (ret < 0) {
714 pr_err("uda1380: failed to register card\n");
715 goto card_err;
716 }
717
718 return ret;
719
720card_err:
721 snd_soc_free_pcms(socdev);
722 snd_soc_dapm_free(socdev);
723pcm_err:
724 kfree(codec->reg_cache);
725 return ret;
726}
727
728static struct snd_soc_device *uda1380_socdev;
729
730#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
731
88fc39d7
JD		 732static int uda1380_i2c_probe(struct i2c_client *i2c,
733 const struct i2c_device_id *id)
b7482f52
PZ		 734{
735 struct snd_soc_device *socdev = uda1380_socdev;
736 struct uda1380_setup_data *setup = socdev->codec_data;
6627a653 737 struct snd_soc_codec *codec = socdev->card->codec;
b7482f52
PZ		 738 int ret;
739
b7482f52
PZ		 740 i2c_set_clientdata(i2c, codec);
741 codec->control_data = i2c;
742
b7482f52 743 ret = uda1380_init(socdev, setup->dac_clk);
88fc39d7 744 if (ret < 0)
b7482f52 745 pr_err("uda1380: failed to initialise UDA1380\n");
b7482f52 746
b7482f52
PZ		 747 return ret;
748}
749
88fc39d7 750static int uda1380_i2c_remove(struct i2c_client *client)
b7482f52
PZ		 751{
752 struct snd_soc_codec *codec = i2c_get_clientdata(client);
b7482f52 753 kfree(codec->reg_cache);
b7482f52
PZ		 754 return 0;
755}
756
88fc39d7
JD		 757static const struct i2c_device_id uda1380_i2c_id[] = {
758 { "uda1380", 0 },
759 { }
760};
761MODULE_DEVICE_TABLE(i2c, uda1380_i2c_id);
b7482f52
PZ		 762
763static struct i2c_driver uda1380_i2c_driver = {
764 .driver = {
765 .name = "UDA1380 I2C Codec",
766 .owner = THIS_MODULE,
767 },
88fc39d7
JD		 768 .probe = uda1380_i2c_probe,
769 .remove = uda1380_i2c_remove,
770 .id_table = uda1380_i2c_id,
b7482f52
PZ		 771};
772
88fc39d7
JD		 773static int uda1380_add_i2c_device(struct platform_device *pdev,
774 const struct uda1380_setup_data *setup)
775{
776 struct i2c_board_info info;
777 struct i2c_adapter *adapter;
778 struct i2c_client *client;
779 int ret;
780
781 ret = i2c_add_driver(&uda1380_i2c_driver);
782 if (ret != 0) {
783 dev_err(&pdev->dev, "can't add i2c driver\n");
784 return ret;
785 }
786
787 memset(&info, 0, sizeof(struct i2c_board_info));
788 info.addr = setup->i2c_address;
789 strlcpy(info.type, "uda1380", I2C_NAME_SIZE);
790
791 adapter = i2c_get_adapter(setup->i2c_bus);
792 if (!adapter) {
793 dev_err(&pdev->dev, "can't get i2c adapter %d\n",
794 setup->i2c_bus);
795 goto err_driver;
796 }
797
798 client = i2c_new_device(adapter, &info);
799 i2c_put_adapter(adapter);
800 if (!client) {
801 dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
802 (unsigned int)info.addr);
803 goto err_driver;
804 }
805
806 return 0;
807
808err_driver:
809 i2c_del_driver(&uda1380_i2c_driver);
810 return -ENODEV;
811}
b7482f52
PZ		 812#endif
813
814static int uda1380_probe(struct platform_device *pdev)
815{
816 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
817 struct uda1380_setup_data *setup;
818 struct snd_soc_codec *codec;
b7c9d852 819 int ret;
b7482f52 820
b7482f52
PZ		 821 setup = socdev->codec_data;
822 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
823 if (codec == NULL)
824 return -ENOMEM;
825
6627a653 826 socdev->card->codec = codec;
b7482f52
PZ		 827 mutex_init(&codec->mutex);
828 INIT_LIST_HEAD(&codec->dapm_widgets);
829 INIT_LIST_HEAD(&codec->dapm_paths);
830
831 uda1380_socdev = socdev;
b7c9d852
MB		 832 ret = -ENODEV;
833
b7482f52
PZ		 834#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
835 if (setup->i2c_address) {
b7482f52 836 codec->hw_write = (hw_write_t)i2c_master_send;
88fc39d7 837 ret = uda1380_add_i2c_device(pdev, setup);
b7482f52 838 }
b7482f52 839#endif
3051e41a
JD		 840
841 if (ret != 0)
842 kfree(codec);
b7482f52
PZ		 843 return ret;
844}
845
846/* power down chip */
847static int uda1380_remove(struct platform_device *pdev)
848{
849 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 850 struct snd_soc_codec *codec = socdev->card->codec;
b7482f52
PZ		 851
852 if (codec->control_data)
853 uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
854
855 snd_soc_free_pcms(socdev);
856 snd_soc_dapm_free(socdev);
857#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
88fc39d7 858 i2c_unregister_device(codec->control_data);
b7482f52
PZ		 859 i2c_del_driver(&uda1380_i2c_driver);
860#endif
861 kfree(codec);
862
863 return 0;
864}
865
866struct snd_soc_codec_device soc_codec_dev_uda1380 = {
867 .probe = uda1380_probe,
868 .remove = uda1380_remove,
869 .suspend = uda1380_suspend,
870 .resume = uda1380_resume,
871};
872EXPORT_SYMBOL_GPL(soc_codec_dev_uda1380);
873
c9b3a40f 874static int __init uda1380_modinit(void)
64089b84
MB		 875{
876 return snd_soc_register_dais(uda1380_dai, ARRAY_SIZE(uda1380_dai));
877}
878module_init(uda1380_modinit);
879
880static void __exit uda1380_exit(void)
881{
882 snd_soc_unregister_dais(uda1380_dai, ARRAY_SIZE(uda1380_dai));
883}
884module_exit(uda1380_exit);
885
b7482f52
PZ		 886MODULE_AUTHOR("Giorgio Padrin");
887MODULE_DESCRIPTION("Audio support for codec Philips UDA1380");
888MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)