projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / uda1380.c
CommitLineData
b7482f52
PZ		 1/*
2 * uda1380.c - Philips UDA1380 ALSA SoC audio driver
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
1abd9184 8 * Copyright (c) 2007-2009 Philipp Zabel <philipp.zabel@gmail.com>
b7482f52
PZ		 9 *
10 * Modified by Richard Purdie <richard@openedhand.com> to fit into SoC
11 * codec model.
12 *
13 * Copyright (c) 2005 Giorgio Padrin <giorgio@mandarinlogiq.org>
14 * Copyright 2005 Openedhand Ltd.
15 */
16
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/types.h>
b7482f52
PZ		 20#include <linux/slab.h>
21#include <linux/errno.h>
1abd9184 22#include <linux/gpio.h>
b7482f52
PZ		 23#include <linux/delay.h>
24#include <linux/i2c.h>
ef9e5e5c 25#include <linux/workqueue.h>
b7482f52
PZ		 26#include <sound/core.h>
27#include <sound/control.h>
28#include <sound/initval.h>
b7482f52 29#include <sound/soc.h>
b7482f52 30#include <sound/tlv.h>
1abd9184 31#include <sound/uda1380.h>
b7482f52
PZ		 32
33#include "uda1380.h"
34
1abd9184
PZ		 35/* codec private data */
36struct uda1380_priv {
f0fba2ad 37 struct snd_soc_codec *codec;
1abd9184
PZ		 38 unsigned int dac_clk;
39 struct work_struct work;
8614d310 40 void *control_data;
1abd9184
PZ		 41};
42
b7482f52
PZ		 43/*
44 * uda1380 register cache
45 */
46static const u16 uda1380_reg[UDA1380_CACHEREGNUM] = {
47 0x0502, 0x0000, 0x0000, 0x3f3f,
48 0x0202, 0x0000, 0x0000, 0x0000,
49 0x0000, 0x0000, 0x0000, 0x0000,
50 0x0000, 0x0000, 0x0000, 0x0000,
51 0x0000, 0xff00, 0x0000, 0x4800,
52 0x0000, 0x0000, 0x0000, 0x0000,
53 0x0000, 0x0000, 0x0000, 0x0000,
54 0x0000, 0x0000, 0x0000, 0x0000,
55 0x0000, 0x8000, 0x0002, 0x0000,
56};
57
ef9e5e5c
PZ		 58static unsigned long uda1380_cache_dirty;
59
b7482f52
PZ		 60/*
61 * read uda1380 register cache
62 */
63static inline unsigned int uda1380_read_reg_cache(struct snd_soc_codec *codec,
64 unsigned int reg)
65{
66 u16 *cache = codec->reg_cache;
67 if (reg == UDA1380_RESET)
68 return 0;
69 if (reg >= UDA1380_CACHEREGNUM)
70 return -1;
71 return cache[reg];
72}
73
74/*
75 * write uda1380 register cache
76 */
77static inline void uda1380_write_reg_cache(struct snd_soc_codec *codec,
78 u16 reg, unsigned int value)
79{
80 u16 *cache = codec->reg_cache;
ef9e5e5c 81
b7482f52
PZ		 82 if (reg >= UDA1380_CACHEREGNUM)
83 return;
ef9e5e5c
PZ		 84 if ((reg >= 0x10) && (cache[reg] != value))
85 set_bit(reg - 0x10, &uda1380_cache_dirty);
b7482f52
PZ		 86 cache[reg] = value;
87}
88
89/*
90 * write to the UDA1380 register space
91 */
92static int uda1380_write(struct snd_soc_codec *codec, unsigned int reg,
93 unsigned int value)
94{
95 u8 data[3];
96
97 /* data is
98 * data[0] is register offset
99 * data[1] is MS byte
100 * data[2] is LS byte
101 */
102 data[0] = reg;
103 data[1] = (value & 0xff00) >> 8;
104 data[2] = value & 0x00ff;
105
106 uda1380_write_reg_cache(codec, reg, value);
107
108 /* the interpolator & decimator regs must only be written when the
109 * codec DAI is active.
110 */
111 if (!codec->active && (reg >= UDA1380_MVOL))
112 return 0;
113 pr_debug("uda1380: hw write %x val %x\n", reg, value);
114 if (codec->hw_write(codec->control_data, data, 3) == 3) {
115 unsigned int val;
116 i2c_master_send(codec->control_data, data, 1);
117 i2c_master_recv(codec->control_data, data, 2);
118 val = (data[0]<<8) | data[1];
119 if (val != value) {
120 pr_debug("uda1380: READ BACK VAL %x\n",
121 (data[0]<<8) | data[1]);
122 return -EIO;
123 }
ef9e5e5c
PZ		 124 if (reg >= 0x10)
125 clear_bit(reg - 0x10, &uda1380_cache_dirty);
b7482f52
PZ		 126 return 0;
127 } else
128 return -EIO;
129}
130
8614d310
VK		 131static void uda1380_sync_cache(struct snd_soc_codec *codec)
132{
133 int reg;
134 u8 data[3];
135 u16 *cache = codec->reg_cache;
136
137 /* Sync reg_cache with the hardware */
138 for (reg = 0; reg < UDA1380_MVOL; reg++) {
139 data[0] = reg;
140 data[1] = (cache[reg] & 0xff00) >> 8;
141 data[2] = cache[reg] & 0x00ff;
142 if (codec->hw_write(codec->control_data, data, 3) != 3)
143 dev_err(codec->dev, "%s: write to reg 0x%x failed\n",
144 __func__, reg);
145 }
146}
147
148static int uda1380_reset(struct snd_soc_codec *codec)
149{
150 struct uda1380_platform_data *pdata = codec->dev->platform_data;
151
152 if (gpio_is_valid(pdata->gpio_reset)) {
153 gpio_set_value(pdata->gpio_reset, 1);
154 mdelay(1);
155 gpio_set_value(pdata->gpio_reset, 0);
156 } else {
157 u8 data[3];
158
159 data[0] = UDA1380_RESET;
160 data[1] = 0;
161 data[2] = 0;
162
163 if (codec->hw_write(codec->control_data, data, 3) != 3) {
164 dev_err(codec->dev, "%s: failed\n", __func__);
165 return -EIO;
166 }
167 }
168
169 return 0;
170}
b7482f52 171
ef9e5e5c
PZ		 172static void uda1380_flush_work(struct work_struct *work)
173{
f0fba2ad
LG		 174 struct uda1380_priv *uda1380 = container_of(work, struct uda1380_priv, work);
175 struct snd_soc_codec *uda1380_codec = uda1380->codec;
ef9e5e5c
PZ		 176 int bit, reg;
177
984b3f57 178 for_each_set_bit(bit, &uda1380_cache_dirty, UDA1380_CACHEREGNUM - 0x10) {
ef9e5e5c
PZ		 179 reg = 0x10 + bit;
180 pr_debug("uda1380: flush reg %x val %x:\n", reg,
181 uda1380_read_reg_cache(uda1380_codec, reg));
182 uda1380_write(uda1380_codec, reg,
183 uda1380_read_reg_cache(uda1380_codec, reg));
184 clear_bit(bit, &uda1380_cache_dirty);
185 }
f0fba2ad 186
ef9e5e5c
PZ		 187}
188
b7482f52
PZ		 189/* declarations of ALSA reg_elem_REAL controls */
190static const char *uda1380_deemp[] = {
191 "None",
192 "32kHz",
193 "44.1kHz",
194 "48kHz",
195 "96kHz",
196};
197static const char *uda1380_input_sel[] = {
198 "Line",
199 "Mic + Line R",
200 "Line L",
201 "Mic",
202};
203static const char *uda1380_output_sel[] = {
204 "DAC",
205 "Analog Mixer",
206};
207static const char *uda1380_spf_mode[] = {
208 "Flat",
209 "Minimum1",
210 "Minimum2",
211 "Maximum"
212};
213static const char *uda1380_capture_sel[] = {
214 "ADC",
215 "Digital Mixer"
216};
217static const char *uda1380_sel_ns[] = {
218 "3rd-order",
219 "5th-order"
220};
221static const char *uda1380_mix_control[] = {
222 "off",
223 "PCM only",
224 "before sound processing",
225 "after sound processing"
226};
227static const char *uda1380_sdet_setting[] = {
228 "3200",
229 "4800",
230 "9600",
231 "19200"
232};
233static const char *uda1380_os_setting[] = {
234 "single-speed",
235 "double-speed (no mixing)",
236 "quad-speed (no mixing)"
237};
238
239static const struct soc_enum uda1380_deemp_enum[] = {
240 SOC_ENUM_SINGLE(UDA1380_DEEMP, 8, 5, uda1380_deemp),
241 SOC_ENUM_SINGLE(UDA1380_DEEMP, 0, 5, uda1380_deemp),
242};
243static const struct soc_enum uda1380_input_sel_enum =
244 SOC_ENUM_SINGLE(UDA1380_ADC, 2, 4, uda1380_input_sel); /* SEL_MIC, SEL_LNA */
245static const struct soc_enum uda1380_output_sel_enum =
246 SOC_ENUM_SINGLE(UDA1380_PM, 7, 2, uda1380_output_sel); /* R02_EN_AVC */
247static const struct soc_enum uda1380_spf_enum =
248 SOC_ENUM_SINGLE(UDA1380_MODE, 14, 4, uda1380_spf_mode); /* M */
249static const struct soc_enum uda1380_capture_sel_enum =
250 SOC_ENUM_SINGLE(UDA1380_IFACE, 6, 2, uda1380_capture_sel); /* SEL_SOURCE */
251static const struct soc_enum uda1380_sel_ns_enum =
252 SOC_ENUM_SINGLE(UDA1380_MIXER, 14, 2, uda1380_sel_ns); /* SEL_NS */
253static const struct soc_enum uda1380_mix_enum =
254 SOC_ENUM_SINGLE(UDA1380_MIXER, 12, 4, uda1380_mix_control); /* MIX, MIX_POS */
255static const struct soc_enum uda1380_sdet_enum =
256 SOC_ENUM_SINGLE(UDA1380_MIXER, 4, 4, uda1380_sdet_setting); /* SD_VALUE */
257static const struct soc_enum uda1380_os_enum =
258 SOC_ENUM_SINGLE(UDA1380_MIXER, 0, 3, uda1380_os_setting); /* OS */
259
260/*
261 * from -48 dB in 1.5 dB steps (mute instead of -49.5 dB)
262 */
263static DECLARE_TLV_DB_SCALE(amix_tlv, -4950, 150, 1);
264
265/*
266 * from -78 dB in 1 dB steps (3 dB steps, really. LSB are ignored),
267 * from -66 dB in 0.5 dB steps (2 dB steps, really) and
268 * from -52 dB in 0.25 dB steps
269 */
270static const unsigned int mvol_tlv[] = {
271 TLV_DB_RANGE_HEAD(3),
272 0, 15, TLV_DB_SCALE_ITEM(-8200, 100, 1),
273 16, 43, TLV_DB_SCALE_ITEM(-6600, 50, 0),
274 44, 252, TLV_DB_SCALE_ITEM(-5200, 25, 0),
275};
276
277/*
278 * from -72 dB in 1.5 dB steps (6 dB steps really),
279 * from -66 dB in 0.75 dB steps (3 dB steps really),
280 * from -60 dB in 0.5 dB steps (2 dB steps really) and
281 * from -46 dB in 0.25 dB steps
282 */
283static const unsigned int vc_tlv[] = {
284 TLV_DB_RANGE_HEAD(4),
285 0, 7, TLV_DB_SCALE_ITEM(-7800, 150, 1),
286 8, 15, TLV_DB_SCALE_ITEM(-6600, 75, 0),
287 16, 43, TLV_DB_SCALE_ITEM(-6000, 50, 0),
288 44, 228, TLV_DB_SCALE_ITEM(-4600, 25, 0),
289};
290
291/* from 0 to 6 dB in 2 dB steps if SPF mode != flat */
292static DECLARE_TLV_DB_SCALE(tr_tlv, 0, 200, 0);
293
294/* from 0 to 24 dB in 2 dB steps, if SPF mode == maximum, otherwise cuts
295 * off at 18 dB max) */
296static DECLARE_TLV_DB_SCALE(bb_tlv, 0, 200, 0);
297
298/* from -63 to 24 dB in 0.5 dB steps (-128...48) */
299static DECLARE_TLV_DB_SCALE(dec_tlv, -6400, 50, 1);
300
301/* from 0 to 24 dB in 3 dB steps */
302static DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0);
303
304/* from 0 to 30 dB in 2 dB steps */
305static DECLARE_TLV_DB_SCALE(vga_tlv, 0, 200, 0);
306
307static const struct snd_kcontrol_new uda1380_snd_controls[] = {
308 SOC_DOUBLE_TLV("Analog Mixer Volume", UDA1380_AMIX, 0, 8, 44, 1, amix_tlv), /* AVCR, AVCL */
309 SOC_DOUBLE_TLV("Master Playback Volume", UDA1380_MVOL, 0, 8, 252, 1, mvol_tlv), /* MVCL, MVCR */
310 SOC_SINGLE_TLV("ADC Playback Volume", UDA1380_MIXVOL, 8, 228, 1, vc_tlv), /* VC2 */
311 SOC_SINGLE_TLV("PCM Playback Volume", UDA1380_MIXVOL, 0, 228, 1, vc_tlv), /* VC1 */
312 SOC_ENUM("Sound Processing Filter", uda1380_spf_enum), /* M */
313 SOC_DOUBLE_TLV("Tone Control - Treble", UDA1380_MODE, 4, 12, 3, 0, tr_tlv), /* TRL, TRR */
314 SOC_DOUBLE_TLV("Tone Control - Bass", UDA1380_MODE, 0, 8, 15, 0, bb_tlv), /* BBL, BBR */
315/**/ SOC_SINGLE("Master Playback Switch", UDA1380_DEEMP, 14, 1, 1), /* MTM */
316 SOC_SINGLE("ADC Playback Switch", UDA1380_DEEMP, 11, 1, 1), /* MT2 from decimation filter */
317 SOC_ENUM("ADC Playback De-emphasis", uda1380_deemp_enum[0]), /* DE2 */
318 SOC_SINGLE("PCM Playback Switch", UDA1380_DEEMP, 3, 1, 1), /* MT1, from digital data input */
319 SOC_ENUM("PCM Playback De-emphasis", uda1380_deemp_enum[1]), /* DE1 */
320 SOC_SINGLE("DAC Polarity inverting Switch", UDA1380_MIXER, 15, 1, 0), /* DA_POL_INV */
321 SOC_ENUM("Noise Shaper", uda1380_sel_ns_enum), /* SEL_NS */
322 SOC_ENUM("Digital Mixer Signal Control", uda1380_mix_enum), /* MIX_POS, MIX */
b7482f52
PZ		 323 SOC_SINGLE("Silence Detector Switch", UDA1380_MIXER, 6, 1, 0), /* SDET_ON */
324 SOC_ENUM("Silence Detector Setting", uda1380_sdet_enum), /* SD_VALUE */
325 SOC_ENUM("Oversampling Input", uda1380_os_enum), /* OS */
326 SOC_DOUBLE_S8_TLV("ADC Capture Volume", UDA1380_DEC, -128, 48, dec_tlv), /* ML_DEC, MR_DEC */
327/**/ SOC_SINGLE("ADC Capture Switch", UDA1380_PGA, 15, 1, 1), /* MT_ADC */
328 SOC_DOUBLE_TLV("Line Capture Volume", UDA1380_PGA, 0, 8, 8, 0, pga_tlv), /* PGA_GAINCTRLL, PGA_GAINCTRLR */
329 SOC_SINGLE("ADC Polarity inverting Switch", UDA1380_ADC, 12, 1, 0), /* ADCPOL_INV */
330 SOC_SINGLE_TLV("Mic Capture Volume", UDA1380_ADC, 8, 15, 0, vga_tlv), /* VGA_CTRL */
331 SOC_SINGLE("DC Filter Bypass Switch", UDA1380_ADC, 1, 1, 0), /* SKIP_DCFIL (before decimator) */
332 SOC_SINGLE("DC Filter Enable Switch", UDA1380_ADC, 0, 1, 0), /* EN_DCFIL (at output of decimator) */
333 SOC_SINGLE("AGC Timing", UDA1380_AGC, 8, 7, 0), /* TODO: enum, see table 62 */
334 SOC_SINGLE("AGC Target level", UDA1380_AGC, 2, 3, 1), /* AGC_LEVEL */
335 /* -5.5, -8, -11.5, -14 dBFS */
336 SOC_SINGLE("AGC Switch", UDA1380_AGC, 0, 1, 0),
337};
338
b7482f52
PZ		 339/* Input mux */
340static const struct snd_kcontrol_new uda1380_input_mux_control =
341 SOC_DAPM_ENUM("Route", uda1380_input_sel_enum);
342
343/* Output mux */
344static const struct snd_kcontrol_new uda1380_output_mux_control =
345 SOC_DAPM_ENUM("Route", uda1380_output_sel_enum);
346
347/* Capture mux */
348static const struct snd_kcontrol_new uda1380_capture_mux_control =
349 SOC_DAPM_ENUM("Route", uda1380_capture_sel_enum);
350
351
352static const struct snd_soc_dapm_widget uda1380_dapm_widgets[] = {
353 SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,
354 &uda1380_input_mux_control),
355 SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM, 0, 0,
356 &uda1380_output_mux_control),
357 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0,
358 &uda1380_capture_mux_control),
359 SND_SOC_DAPM_PGA("Left PGA", UDA1380_PM, 3, 0, NULL, 0),
360 SND_SOC_DAPM_PGA("Right PGA", UDA1380_PM, 1, 0, NULL, 0),
361 SND_SOC_DAPM_PGA("Mic LNA", UDA1380_PM, 4, 0, NULL, 0),
362 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", UDA1380_PM, 2, 0),
363 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", UDA1380_PM, 0, 0),
364 SND_SOC_DAPM_INPUT("VINM"),
365 SND_SOC_DAPM_INPUT("VINL"),
366 SND_SOC_DAPM_INPUT("VINR"),
367 SND_SOC_DAPM_MIXER("Analog Mixer", UDA1380_PM, 6, 0, NULL, 0),
368 SND_SOC_DAPM_OUTPUT("VOUTLHP"),
369 SND_SOC_DAPM_OUTPUT("VOUTRHP"),
370 SND_SOC_DAPM_OUTPUT("VOUTL"),
371 SND_SOC_DAPM_OUTPUT("VOUTR"),
372 SND_SOC_DAPM_DAC("DAC", "Playback", UDA1380_PM, 10, 0),
373 SND_SOC_DAPM_PGA("HeadPhone Driver", UDA1380_PM, 13, 0, NULL, 0),
374};
375
58fa8e45 376static const struct snd_soc_dapm_route uda1380_dapm_routes[] = {
b7482f52
PZ		 377
378 /* output mux */
379 {"HeadPhone Driver", NULL, "Output Mux"},
380 {"VOUTR", NULL, "Output Mux"},
381 {"VOUTL", NULL, "Output Mux"},
382
383 {"Analog Mixer", NULL, "VINR"},
384 {"Analog Mixer", NULL, "VINL"},
385 {"Analog Mixer", NULL, "DAC"},
386
387 {"Output Mux", "DAC", "DAC"},
388 {"Output Mux", "Analog Mixer", "Analog Mixer"},
389
390 /* {"DAC", "Digital Mixer", "I2S" } */
391
392 /* headphone driver */
393 {"VOUTLHP", NULL, "HeadPhone Driver"},
394 {"VOUTRHP", NULL, "HeadPhone Driver"},
395
396 /* input mux */
397 {"Left ADC", NULL, "Input Mux"},
398 {"Input Mux", "Mic", "Mic LNA"},
399 {"Input Mux", "Mic + Line R", "Mic LNA"},
400 {"Input Mux", "Line L", "Left PGA"},
401 {"Input Mux", "Line", "Left PGA"},
402
403 /* right input */
404 {"Right ADC", "Mic + Line R", "Right PGA"},
405 {"Right ADC", "Line", "Right PGA"},
406
407 /* inputs */
408 {"Mic LNA", NULL, "VINM"},
409 {"Left PGA", NULL, "VINL"},
410 {"Right PGA", NULL, "VINR"},
411};
412
5b247442 413static int uda1380_set_dai_fmt_both(struct snd_soc_dai *codec_dai,
b7482f52
PZ		 414 unsigned int fmt)
415{
416 struct snd_soc_codec *codec = codec_dai->codec;
417 int iface;
418
419 /* set up DAI based upon fmt */
420 iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
421 iface &= ~(R01_SFORI_MASK | R01_SIM | R01_SFORO_MASK);
422
b7482f52
PZ		 423 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
424 case SND_SOC_DAIFMT_I2S:
425 iface |= R01_SFORI_I2S | R01_SFORO_I2S;
426 break;
427 case SND_SOC_DAIFMT_LSB:
5b247442 428 iface |= R01_SFORI_LSB16 | R01_SFORO_LSB16;
b7482f52
PZ		 429 break;
430 case SND_SOC_DAIFMT_MSB:
5b247442
PZ		 431 iface |= R01_SFORI_MSB | R01_SFORO_MSB;
432 }
433
5f2a9384
PZ		 434 /* DATAI is slave only, so in single-link mode, this has to be slave */
435 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
436 return -EINVAL;
5b247442
PZ		 437
438 uda1380_write(codec, UDA1380_IFACE, iface);
439
440 return 0;
441}
442
443static int uda1380_set_dai_fmt_playback(struct snd_soc_dai *codec_dai,
444 unsigned int fmt)
445{
446 struct snd_soc_codec *codec = codec_dai->codec;
447 int iface;
448
449 /* set up DAI based upon fmt */
450 iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
451 iface &= ~R01_SFORI_MASK;
452
453 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
454 case SND_SOC_DAIFMT_I2S:
455 iface |= R01_SFORI_I2S;
456 break;
457 case SND_SOC_DAIFMT_LSB:
458 iface |= R01_SFORI_LSB16;
459 break;
460 case SND_SOC_DAIFMT_MSB:
461 iface |= R01_SFORI_MSB;
462 }
463
5f2a9384
PZ		 464 /* DATAI is slave only, so this has to be slave */
465 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
466 return -EINVAL;
467
5b247442
PZ		 468 uda1380_write(codec, UDA1380_IFACE, iface);
469
470 return 0;
471}
472
473static int uda1380_set_dai_fmt_capture(struct snd_soc_dai *codec_dai,
474 unsigned int fmt)
475{
476 struct snd_soc_codec *codec = codec_dai->codec;
477 int iface;
478
479 /* set up DAI based upon fmt */
480 iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
481 iface &= ~(R01_SIM | R01_SFORO_MASK);
482
483 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
484 case SND_SOC_DAIFMT_I2S:
485 iface |= R01_SFORO_I2S;
486 break;
487 case SND_SOC_DAIFMT_LSB:
488 iface |= R01_SFORO_LSB16;
489 break;
490 case SND_SOC_DAIFMT_MSB:
491 iface |= R01_SFORO_MSB;
b7482f52
PZ		 492 }
493
494 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBM_CFM)
495 iface |= R01_SIM;
496
497 uda1380_write(codec, UDA1380_IFACE, iface);
498
499 return 0;
500}
501
ef9e5e5c
PZ		 502static int uda1380_trigger(struct snd_pcm_substream *substream, int cmd,
503 struct snd_soc_dai *dai)
b7482f52 504{
e6968a17 505 struct snd_soc_codec *codec = dai->codec;
b2c812e2 506 struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec);
ef9e5e5c
PZ		 507 int mixer = uda1380_read_reg_cache(codec, UDA1380_MIXER);
508
509 switch (cmd) {
510 case SNDRV_PCM_TRIGGER_START:
511 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
512 uda1380_write_reg_cache(codec, UDA1380_MIXER,
513 mixer & ~R14_SILENCE);
1abd9184 514 schedule_work(&uda1380->work);
ef9e5e5c
PZ		 515 break;
516 case SNDRV_PCM_TRIGGER_STOP:
517 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
518 uda1380_write_reg_cache(codec, UDA1380_MIXER,
519 mixer | R14_SILENCE);
1abd9184 520 schedule_work(&uda1380->work);
ef9e5e5c 521 break;
b7482f52 522 }
b7482f52
PZ		 523 return 0;
524}
525
526static int uda1380_pcm_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 527 struct snd_pcm_hw_params *params,
528 struct snd_soc_dai *dai)
b7482f52 529{
e6968a17 530 struct snd_soc_codec *codec = dai->codec;
b7482f52
PZ		 531 u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
532
533 /* set WSPLL power and divider if running from this clock */
534 if (clk & R00_DAC_CLK) {
535 int rate = params_rate(params);
536 u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM);
537 clk &= ~0x3; /* clear SEL_LOOP_DIV */
538 switch (rate) {
539 case 6250 ... 12500:
540 clk |= 0x0;
541 break;
542 case 12501 ... 25000:
543 clk |= 0x1;
544 break;
545 case 25001 ... 50000:
546 clk |= 0x2;
547 break;
548 case 50001 ... 100000:
549 clk |= 0x3;
550 break;
551 }
552 uda1380_write(codec, UDA1380_PM, R02_PON_PLL | pm);
553 }
554
555 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
556 clk |= R00_EN_DAC | R00_EN_INT;
557 else
558 clk |= R00_EN_ADC | R00_EN_DEC;
559
560 uda1380_write(codec, UDA1380_CLK, clk);
561 return 0;
562}
563
dee89c4d
MB		 564static void uda1380_pcm_shutdown(struct snd_pcm_substream *substream,
565 struct snd_soc_dai *dai)
b7482f52
PZ		 566{
567 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 568 struct snd_soc_codec *codec = rtd->codec;
b7482f52
PZ		 569 u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
570
571 /* shut down WSPLL power if running from this clock */
572 if (clk & R00_DAC_CLK) {
573 u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM);
574 uda1380_write(codec, UDA1380_PM, ~R02_PON_PLL & pm);
575 }
576
577 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
578 clk &= ~(R00_EN_DAC | R00_EN_INT);
579 else
580 clk &= ~(R00_EN_ADC | R00_EN_DEC);
581
582 uda1380_write(codec, UDA1380_CLK, clk);
583}
584
b7482f52
PZ		 585static int uda1380_set_bias_level(struct snd_soc_codec *codec,
586 enum snd_soc_bias_level level)
587{
588 int pm = uda1380_read_reg_cache(codec, UDA1380_PM);
8614d310
VK		 589 int reg;
590 struct uda1380_platform_data *pdata = codec->dev->platform_data;
591
ce6120cc 592 if (codec->dapm.bias_level == level)
8614d310 593 return 0;
b7482f52
PZ		 594
595 switch (level) {
596 case SND_SOC_BIAS_ON:
597 case SND_SOC_BIAS_PREPARE:
8614d310 598 /* ADC, DAC on */
b7482f52
PZ		 599 uda1380_write(codec, UDA1380_PM, R02_PON_BIAS | pm);
600 break;
601 case SND_SOC_BIAS_STANDBY:
ce6120cc 602 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8614d310
VK		 603 if (gpio_is_valid(pdata->gpio_power)) {
604 gpio_set_value(pdata->gpio_power, 1);
8e3dce4d 605 mdelay(1);
8614d310
VK		 606 uda1380_reset(codec);
607 }
608
609 uda1380_sync_cache(codec);
610 }
b7482f52
PZ		 611 uda1380_write(codec, UDA1380_PM, 0x0);
612 break;
8614d310
VK		 613 case SND_SOC_BIAS_OFF:
614 if (!gpio_is_valid(pdata->gpio_power))
615 break;
616
617 gpio_set_value(pdata->gpio_power, 0);
618
619 /* Mark mixer regs cache dirty to sync them with
620 * codec regs on power on.
621 */
622 for (reg = UDA1380_MVOL; reg < UDA1380_CACHEREGNUM; reg++)
623 set_bit(reg - 0x10, &uda1380_cache_dirty);
b7482f52 624 }
ce6120cc 625 codec->dapm.bias_level = level;
b7482f52
PZ		 626 return 0;
627}
628
629#define UDA1380_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
630 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
631 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
632
85e7652d 633static const struct snd_soc_dai_ops uda1380_dai_ops = {
6335d055
EM		 634 .hw_params = uda1380_pcm_hw_params,
635 .shutdown = uda1380_pcm_shutdown,
65ec1cd1 636 .trigger = uda1380_trigger,
6335d055
EM		 637 .set_fmt = uda1380_set_dai_fmt_both,
638};
639
85e7652d 640static const struct snd_soc_dai_ops uda1380_dai_ops_playback = {
6335d055
EM		 641 .hw_params = uda1380_pcm_hw_params,
642 .shutdown = uda1380_pcm_shutdown,
65ec1cd1 643 .trigger = uda1380_trigger,
6335d055
EM		 644 .set_fmt = uda1380_set_dai_fmt_playback,
645};
646
85e7652d 647static const struct snd_soc_dai_ops uda1380_dai_ops_capture = {
6335d055
EM		 648 .hw_params = uda1380_pcm_hw_params,
649 .shutdown = uda1380_pcm_shutdown,
65ec1cd1 650 .trigger = uda1380_trigger,
6335d055
EM		 651 .set_fmt = uda1380_set_dai_fmt_capture,
652};
653
f0fba2ad 654static struct snd_soc_dai_driver uda1380_dai[] = {
b7482f52 655{
f0fba2ad 656 .name = "uda1380-hifi",
b7482f52
PZ		 657 .playback = {
658 .stream_name = "Playback",
659 .channels_min = 1,
660 .channels_max = 2,
661 .rates = UDA1380_RATES,
662 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
663 .capture = {
664 .stream_name = "Capture",
665 .channels_min = 1,
666 .channels_max = 2,
667 .rates = UDA1380_RATES,
668 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
6335d055 669 .ops = &uda1380_dai_ops,
b7482f52
PZ		 670},
671{ /* playback only - dual interface */
f0fba2ad 672 .name = "uda1380-hifi-playback",
b7482f52
PZ		 673 .playback = {
674 .stream_name = "Playback",
675 .channels_min = 1,
676 .channels_max = 2,
677 .rates = UDA1380_RATES,
678 .formats = SNDRV_PCM_FMTBIT_S16_LE,
679 },
6335d055 680 .ops = &uda1380_dai_ops_playback,
b7482f52
PZ		 681},
682{ /* capture only - dual interface*/
f0fba2ad 683 .name = "uda1380-hifi-capture",
b7482f52
PZ		 684 .capture = {
685 .stream_name = "Capture",
686 .channels_min = 1,
687 .channels_max = 2,
688 .rates = UDA1380_RATES,
689 .formats = SNDRV_PCM_FMTBIT_S16_LE,
690 },
6335d055 691 .ops = &uda1380_dai_ops_capture,
b7482f52
PZ		 692},
693};
b7482f52 694
84b315ee 695static int uda1380_suspend(struct snd_soc_codec *codec)
b7482f52 696{
b7482f52
PZ		 697 uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
698 return 0;
699}
700
f0fba2ad 701static int uda1380_resume(struct snd_soc_codec *codec)
b7482f52 702{
b7482f52 703 uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
b7482f52
PZ		 704 return 0;
705}
706
f0fba2ad 707static int uda1380_probe(struct snd_soc_codec *codec)
88fc39d7 708{
f0fba2ad
LG		 709 struct uda1380_platform_data *pdata =codec->dev->platform_data;
710 struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec);
711 int ret;
88fc39d7 712
8614d310
VK		 713 uda1380->codec = codec;
714
f0fba2ad 715 codec->hw_write = (hw_write_t)i2c_master_send;
8614d310 716 codec->control_data = uda1380->control_data;
1abd9184 717
8614d310 718 if (!pdata)
1abd9184
PZ		 719 return -EINVAL;
720
8614d310 721 if (gpio_is_valid(pdata->gpio_reset)) {
68020db8
AL		 722 ret = gpio_request_one(pdata->gpio_reset, GPIOF_OUT_INIT_LOW,
723 "uda1380 reset");
8614d310
VK		 724 if (ret)
725 goto err_out;
8614d310 726 }
1abd9184 727
8614d310 728 if (gpio_is_valid(pdata->gpio_power)) {
68020db8
AL		 729 ret = gpio_request_one(pdata->gpio_power, GPIOF_OUT_INIT_LOW,
730 "uda1380 power");
8614d310 731 if (ret)
68020db8 732 goto err_free_gpio;
8614d310
VK		 733 } else {
734 ret = uda1380_reset(codec);
68020db8
AL		 735 if (ret)
736 goto err_free_gpio;
88fc39d7
JD		 737 }
738
1abd9184
PZ		 739 INIT_WORK(&uda1380->work, uda1380_flush_work);
740
f0fba2ad
LG		 741 /* power on device */
742 uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
743 /* set clock input */
744 switch (pdata->dac_clk) {
745 case UDA1380_DAC_CLK_SYSCLK:
8614d310 746 uda1380_write_reg_cache(codec, UDA1380_CLK, 0);
f0fba2ad
LG		 747 break;
748 case UDA1380_DAC_CLK_WSPLL:
8614d310
VK		 749 uda1380_write_reg_cache(codec, UDA1380_CLK,
750 R00_DAC_CLK);
f0fba2ad 751 break;
88fc39d7
JD		 752 }
753
88fc39d7
JD		 754 return 0;
755
68020db8 756err_free_gpio:
8614d310
VK		 757 if (gpio_is_valid(pdata->gpio_reset))
758 gpio_free(pdata->gpio_reset);
759err_out:
1abd9184 760 return ret;
88fc39d7 761}
b7482f52 762
f0fba2ad
LG		 763/* power down chip */
764static int uda1380_remove(struct snd_soc_codec *codec)
b7482f52 765{
f0fba2ad 766 struct uda1380_platform_data *pdata =codec->dev->platform_data;
1abd9184 767
f0fba2ad 768 uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
1abd9184 769
1abd9184
PZ		 770 gpio_free(pdata->gpio_reset);
771 gpio_free(pdata->gpio_power);
772
f0fba2ad 773 return 0;
1abd9184
PZ		 774}
775
f0fba2ad
LG		 776static struct snd_soc_codec_driver soc_codec_dev_uda1380 = {
777 .probe = uda1380_probe,
778 .remove = uda1380_remove,
779 .suspend = uda1380_suspend,
780 .resume = uda1380_resume,
8614d310
VK		 781 .read = uda1380_read_reg_cache,
782 .write = uda1380_write,
f0fba2ad
LG		 783 .set_bias_level = uda1380_set_bias_level,
784 .reg_cache_size = ARRAY_SIZE(uda1380_reg),
785 .reg_word_size = sizeof(u16),
786 .reg_cache_default = uda1380_reg,
787 .reg_cache_step = 1,
58fa8e45
AL		 788
789 .controls = uda1380_snd_controls,
790 .num_controls = ARRAY_SIZE(uda1380_snd_controls),
791 .dapm_widgets = uda1380_dapm_widgets,
792 .num_dapm_widgets = ARRAY_SIZE(uda1380_dapm_widgets),
793 .dapm_routes = uda1380_dapm_routes,
794 .num_dapm_routes = ARRAY_SIZE(uda1380_dapm_routes),
f0fba2ad
LG		 795};
796
1abd9184 797#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
7a79e94e
BP		 798static int uda1380_i2c_probe(struct i2c_client *i2c,
799 const struct i2c_device_id *id)
1abd9184
PZ		 800{
801 struct uda1380_priv *uda1380;
b7c9d852 802 int ret;
b7482f52 803
6ce91ad4
AL		 804 uda1380 = devm_kzalloc(&i2c->dev, sizeof(struct uda1380_priv),
805 GFP_KERNEL);
1abd9184 806 if (uda1380 == NULL)
b7482f52
PZ		 807 return -ENOMEM;
808
1abd9184 809 i2c_set_clientdata(i2c, uda1380);
8614d310 810 uda1380->control_data = i2c;
3051e41a 811
f0fba2ad
LG		 812 ret = snd_soc_register_codec(&i2c->dev,
813 &soc_codec_dev_uda1380, uda1380_dai, ARRAY_SIZE(uda1380_dai));
b7482f52
PZ		 814 return ret;
815}
816
7a79e94e 817static int uda1380_i2c_remove(struct i2c_client *i2c)
b7482f52 818{
f0fba2ad 819 snd_soc_unregister_codec(&i2c->dev);
b7482f52
PZ		 820 return 0;
821}
822
1abd9184
PZ		 823static const struct i2c_device_id uda1380_i2c_id[] = {
824 { "uda1380", 0 },
825 { }
b7482f52 826};
1abd9184
PZ		 827MODULE_DEVICE_TABLE(i2c, uda1380_i2c_id);
828
829static struct i2c_driver uda1380_i2c_driver = {
830 .driver = {
f0fba2ad 831 .name = "uda1380-codec",
1abd9184
PZ		 832 .owner = THIS_MODULE,
833 },
834 .probe = uda1380_i2c_probe,
7a79e94e 835 .remove = uda1380_i2c_remove,
1abd9184
PZ		 836 .id_table = uda1380_i2c_id,
837};
838#endif
b7482f52 839
c9b3a40f 840static int __init uda1380_modinit(void)
64089b84 841{
ef149770 842 int ret = 0;
1abd9184
PZ		 843#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
844 ret = i2c_add_driver(&uda1380_i2c_driver);
845 if (ret != 0)
846 pr_err("Failed to register UDA1380 I2C driver: %d\n", ret);
847#endif
ef149770 848 return ret;
64089b84
MB		 849}
850module_init(uda1380_modinit);
851
852static void __exit uda1380_exit(void)
853{
1abd9184
PZ		 854#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
855 i2c_del_driver(&uda1380_i2c_driver);
856#endif
64089b84
MB		 857}
858module_exit(uda1380_exit);
859
b7482f52
PZ		 860MODULE_AUTHOR("Giorgio Padrin");
861MODULE_DESCRIPTION("Audio support for codec Philips UDA1380");
862MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)