[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / uda134x.c

/*
 * uda134x.c  --  UDA134X ALSA SoC Codec driver
 *
 * Modifications by Christian Pellegrin <chripell@evolware.org>
 *
 * Copyright 2007 Dension Audio Systems Ltd.
 * Author: Zoltan Devai
 *
 * Based on the WM87xx drivers by Liam Girdwood and Richard Purdie
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>

#include <sound/uda134x.h>
#include <sound/l3.h>

#include "uda134x.h"


#define UDA134X_RATES SNDRV_PCM_RATE_8000_48000
#define UDA134X_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
		SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE)

struct uda134x_priv {
	int sysclk;
	int dai_fmt;

	struct snd_pcm_substream *master_substream;
	struct snd_pcm_substream *slave_substream;
};

/* In-data addresses are hard-coded into the reg-cache values */
static const char uda134x_reg[UDA134X_REGS_NUM] = {
	/* Extended address registers */
	0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
	/* Status, data regs */
	0x00, 0x83, 0x00, 0x40, 0x80, 0xC0, 0x00,
};

/*
 * The codec has no support for reading its registers except for peak level...
 */
static inline unsigned int uda134x_read_reg_cache(struct snd_soc_codec *codec,
	unsigned int reg)
{
	u8 *cache = codec->reg_cache;

	if (reg >= UDA134X_REGS_NUM)
		return -1;
	return cache[reg];
}

/*
 * Write the register cache
 */
static inline void uda134x_write_reg_cache(struct snd_soc_codec *codec,
	u8 reg, unsigned int value)
{
	u8 *cache = codec->reg_cache;

	if (reg >= UDA134X_REGS_NUM)
		return;
	cache[reg] = value;
}

/*
 * Write to the uda134x registers
 *
 */
static int uda134x_write(struct snd_soc_codec *codec, unsigned int reg,
	unsigned int value)
{
	int ret;
	u8 addr;
	u8 data = value;
	struct uda134x_platform_data *pd = codec->control_data;

	pr_debug("%s reg: %02X, value:%02X\n", __func__, reg, value);

	if (reg >= UDA134X_REGS_NUM) {
		printk(KERN_ERR "%s unknown register: reg: %u",
		       __func__, reg);
		return -EINVAL;
	}

	uda134x_write_reg_cache(codec, reg, value);

	switch (reg) {
	case UDA134X_STATUS0:
	case UDA134X_STATUS1:
		addr = UDA134X_STATUS_ADDR;
		break;
	case UDA134X_DATA000:
	case UDA134X_DATA001:
	case UDA134X_DATA010:
	case UDA134X_DATA011:
		addr = UDA134X_DATA0_ADDR;
		break;
	case UDA134X_DATA1:
		addr = UDA134X_DATA1_ADDR;
		break;
	default:
		/* It's an extended address register */
		addr =  (reg | UDA134X_EXTADDR_PREFIX);

		ret = l3_write(&pd->l3,
			       UDA134X_DATA0_ADDR, &addr, 1);
		if (ret != 1)
			return -EIO;

		addr = UDA134X_DATA0_ADDR;
		data = (value | UDA134X_EXTDATA_PREFIX);
		break;
	}

	ret = l3_write(&pd->l3,
		       addr, &data, 1);
	if (ret != 1)
		return -EIO;

	return 0;
}

static inline void uda134x_reset(struct snd_soc_codec *codec)
{
	u8 reset_reg = uda134x_read_reg_cache(codec, UDA134X_STATUS0);
	uda134x_write(codec, UDA134X_STATUS0, reset_reg | (1<<6));
	msleep(1);
	uda134x_write(codec, UDA134X_STATUS0, reset_reg & ~(1<<6));
}

static int uda134x_mute(struct snd_soc_dai *dai, int mute)
{
	struct snd_soc_codec *codec = dai->codec;
	u8 mute_reg = uda134x_read_reg_cache(codec, UDA134X_DATA010);

	pr_debug("%s mute: %d\n", __func__, mute);

	if (mute)
		mute_reg |= (1<<2);
	else
		mute_reg &= ~(1<<2);

	uda134x_write(codec, UDA134X_DATA010, mute_reg);

	return 0;
}

static int uda134x_startup(struct snd_pcm_substream *substream,
	struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_codec *codec =rtd->codec;
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
	struct snd_pcm_runtime *master_runtime;

	if (uda134x->master_substream) {
		master_runtime = uda134x->master_substream->runtime;

		pr_debug("%s constraining to %d bits at %d\n", __func__,
			 master_runtime->sample_bits,
			 master_runtime->rate);

		snd_pcm_hw_constraint_minmax(substream->runtime,
					     SNDRV_PCM_HW_PARAM_RATE,
					     master_runtime->rate,
					     master_runtime->rate);

		snd_pcm_hw_constraint_minmax(substream->runtime,
					     SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
					     master_runtime->sample_bits,
					     master_runtime->sample_bits);

		uda134x->slave_substream = substream;
	} else
		uda134x->master_substream = substream;

	return 0;
}

static void uda134x_shutdown(struct snd_pcm_substream *substream,
	struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_codec *codec = rtd->codec;
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);

	if (uda134x->master_substream == substream)
		uda134x->master_substream = uda134x->slave_substream;

	uda134x->slave_substream = NULL;
}

static int uda134x_hw_params(struct snd_pcm_substream *substream,
	struct snd_pcm_hw_params *params,
	struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_codec *codec = rtd->codec;
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
	u8 hw_params;

	if (substream == uda134x->slave_substream) {
		pr_debug("%s ignoring hw_params for slave substream\n",
			 __func__);
		return 0;
	}

	hw_params = uda134x_read_reg_cache(codec, UDA134X_STATUS0);
	hw_params &= STATUS0_SYSCLK_MASK;
	hw_params &= STATUS0_DAIFMT_MASK;

	pr_debug("%s sysclk: %d, rate:%d\n", __func__,
		 uda134x->sysclk, params_rate(params));

	/* set SYSCLK / fs ratio */
	switch (uda134x->sysclk / params_rate(params)) {
	case 512:
		break;
	case 384:
		hw_params |= (1<<4);
		break;
	case 256:
		hw_params |= (1<<5);
		break;
	default:
		printk(KERN_ERR "%s unsupported fs\n", __func__);
		return -EINVAL;
	}

	pr_debug("%s dai_fmt: %d, params_format:%d\n", __func__,
		 uda134x->dai_fmt, params_format(params));

	/* set DAI format and word length */
	switch (uda134x->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		break;
	case SND_SOC_DAIFMT_RIGHT_J:
		switch (params_format(params)) {
		case SNDRV_PCM_FORMAT_S16_LE:
			hw_params |= (1<<1);
			break;
		case SNDRV_PCM_FORMAT_S18_3LE:
			hw_params |= (1<<2);
			break;
		case SNDRV_PCM_FORMAT_S20_3LE:
			hw_params |= ((1<<2) | (1<<1));
			break;
		default:
			printk(KERN_ERR "%s unsupported format (right)\n",
			       __func__);
			return -EINVAL;
		}
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		hw_params |= (1<<3);
		break;
	default:
		printk(KERN_ERR "%s unsupported format\n", __func__);
		return -EINVAL;
	}

	uda134x_write(codec, UDA134X_STATUS0, hw_params);

	return 0;
}

static int uda134x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
				  int clk_id, unsigned int freq, int dir)
{
	struct snd_soc_codec *codec = codec_dai->codec;
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);

	pr_debug("%s clk_id: %d, freq: %u, dir: %d\n", __func__,
		 clk_id, freq, dir);

	/* Anything between 256fs*8Khz and 512fs*48Khz should be acceptable
	   because the codec is slave. Of course limitations of the clock
	   master (the IIS controller) apply.
	   We'll error out on set_hw_params if it's not OK */
	if ((freq >= (256 * 8000)) && (freq <= (512 * 48000))) {
		uda134x->sysclk = freq;
		return 0;
	}

	printk(KERN_ERR "%s unsupported sysclk\n", __func__);
	return -EINVAL;
}

static int uda134x_set_dai_fmt(struct snd_soc_dai *codec_dai,
			       unsigned int fmt)
{
	struct snd_soc_codec *codec = codec_dai->codec;
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);

	pr_debug("%s fmt: %08X\n", __func__, fmt);

	/* codec supports only full slave mode */
	if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) {
		printk(KERN_ERR "%s unsupported slave mode\n", __func__);
		return -EINVAL;
	}

	/* no support for clock inversion */
	if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) {
		printk(KERN_ERR "%s unsupported clock inversion\n", __func__);
		return -EINVAL;
	}

	/* We can't setup DAI format here as it depends on the word bit num */
	/* so let's just store the value for later */
	uda134x->dai_fmt = fmt;

	return 0;
}

static int uda134x_set_bias_level(struct snd_soc_codec *codec,
				  enum snd_soc_bias_level level)
{
	u8 reg;
	struct uda134x_platform_data *pd = codec->control_data;
	int i;
	u8 *cache = codec->reg_cache;

	pr_debug("%s bias level %d\n", __func__, level);

	switch (level) {
	case SND_SOC_BIAS_ON:
		/* ADC, DAC on */
		switch (pd->model) {
		case UDA134X_UDA1340:
		case UDA134X_UDA1344:
		case UDA134X_UDA1345:
			reg = uda134x_read_reg_cache(codec, UDA134X_DATA011);
			uda134x_write(codec, UDA134X_DATA011, reg | 0x03);
			break;
		case UDA134X_UDA1341:
			reg = uda134x_read_reg_cache(codec, UDA134X_STATUS1);
			uda134x_write(codec, UDA134X_STATUS1, reg | 0x03);
			break;
		default:
			printk(KERN_ERR "UDA134X SoC codec: "
			       "unsupported model %d\n", pd->model);
			return -EINVAL;
		}
		break;
	case SND_SOC_BIAS_PREPARE:
		/* power on */
		if (pd->power) {
			pd->power(1);
			/* Sync reg_cache with the hardware */
			for (i = 0; i < ARRAY_SIZE(uda134x_reg); i++)
				codec->driver->write(codec, i, *cache++);
		}
		break;
	case SND_SOC_BIAS_STANDBY:
		/* ADC, DAC power off */
		switch (pd->model) {
		case UDA134X_UDA1340:
		case UDA134X_UDA1344:
		case UDA134X_UDA1345:
			reg = uda134x_read_reg_cache(codec, UDA134X_DATA011);
			uda134x_write(codec, UDA134X_DATA011, reg & ~(0x03));
			break;
		case UDA134X_UDA1341:
			reg = uda134x_read_reg_cache(codec, UDA134X_STATUS1);
			uda134x_write(codec, UDA134X_STATUS1, reg & ~(0x03));
			break;
		default:
			printk(KERN_ERR "UDA134X SoC codec: "
			       "unsupported model %d\n", pd->model);
			return -EINVAL;
		}
		break;
	case SND_SOC_BIAS_OFF:
		/* power off */
		if (pd->power)
			pd->power(0);
		break;
	}
	codec->dapm.bias_level = level;
	return 0;
}

static const char *uda134x_dsp_setting[] = {"Flat", "Minimum1",
					    "Minimum2", "Maximum"};
static const char *uda134x_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
static const char *uda134x_mixmode[] = {"Differential", "Analog1",
					"Analog2", "Both"};

static const struct soc_enum uda134x_mixer_enum[] = {
SOC_ENUM_SINGLE(UDA134X_DATA010, 0, 0x04, uda134x_dsp_setting),
SOC_ENUM_SINGLE(UDA134X_DATA010, 3, 0x04, uda134x_deemph),
SOC_ENUM_SINGLE(UDA134X_EA010, 0, 0x04, uda134x_mixmode),
};

static const struct snd_kcontrol_new uda1341_snd_controls[] = {
SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
SOC_SINGLE("Capture Volume", UDA134X_EA010, 2, 0x07, 0),
SOC_SINGLE("Analog1 Volume", UDA134X_EA000, 0, 0x1F, 1),
SOC_SINGLE("Analog2 Volume", UDA134X_EA001, 0, 0x1F, 1),

SOC_SINGLE("Mic Sensitivity", UDA134X_EA010, 2, 7, 0),
SOC_SINGLE("Mic Volume", UDA134X_EA101, 0, 0x1F, 0),

SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),

SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
SOC_ENUM("Input Mux", uda134x_mixer_enum[2]),

SOC_SINGLE("AGC Switch", UDA134X_EA100, 4, 1, 0),
SOC_SINGLE("AGC Target Volume", UDA134X_EA110, 0, 0x03, 1),
SOC_SINGLE("AGC Timing", UDA134X_EA110, 2, 0x07, 0),

SOC_SINGLE("DAC +6dB Switch", UDA134X_STATUS1, 6, 1, 0),
SOC_SINGLE("ADC +6dB Switch", UDA134X_STATUS1, 5, 1, 0),
SOC_SINGLE("ADC Polarity Switch", UDA134X_STATUS1, 4, 1, 0),
SOC_SINGLE("DAC Polarity Switch", UDA134X_STATUS1, 3, 1, 0),
SOC_SINGLE("Double Speed Playback Switch", UDA134X_STATUS1, 2, 1, 0),
SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
};

static const struct snd_kcontrol_new uda1340_snd_controls[] = {
SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),

SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),

SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),

SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
};

static const struct snd_kcontrol_new uda1345_snd_controls[] = {
SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),

SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),

SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
};

static const struct snd_soc_dai_ops uda134x_dai_ops = {
	.startup	= uda134x_startup,
	.shutdown	= uda134x_shutdown,
	.hw_params	= uda134x_hw_params,
	.digital_mute	= uda134x_mute,
	.set_sysclk	= uda134x_set_dai_sysclk,
	.set_fmt	= uda134x_set_dai_fmt,
};

static struct snd_soc_dai_driver uda134x_dai = {
	.name = "uda134x-hifi",
	/* playback capabilities */
	.playback = {
		.stream_name = "Playback",
		.channels_min = 1,
		.channels_max = 2,
		.rates = UDA134X_RATES,
		.formats = UDA134X_FORMATS,
	},
	/* capture capabilities */
	.capture = {
		.stream_name = "Capture",
		.channels_min = 1,
		.channels_max = 2,
		.rates = UDA134X_RATES,
		.formats = UDA134X_FORMATS,
	},
	/* pcm operations */
	.ops = &uda134x_dai_ops,
};

static int uda134x_soc_probe(struct snd_soc_codec *codec)
{
	struct uda134x_priv *uda134x;
	struct uda134x_platform_data *pd = codec->card->dev->platform_data;

	int ret;

	printk(KERN_INFO "UDA134X SoC Audio Codec\n");

	if (!pd) {
		printk(KERN_ERR "UDA134X SoC codec: "
		       "missing L3 bitbang function\n");
		return -ENODEV;
	}

	switch (pd->model) {
	case UDA134X_UDA1340:
	case UDA134X_UDA1341:
	case UDA134X_UDA1344:
	case UDA134X_UDA1345:
		break;
	default:
		printk(KERN_ERR "UDA134X SoC codec: "
		       "unsupported model %d\n",
			pd->model);
		return -EINVAL;
	}

	uda134x = kzalloc(sizeof(struct uda134x_priv), GFP_KERNEL);
	if (uda134x == NULL)
		return -ENOMEM;
	snd_soc_codec_set_drvdata(codec, uda134x);

	codec->control_data = pd;

	if (pd->power)
		pd->power(1);

	uda134x_reset(codec);

	if (pd->is_powered_on_standby)
		uda134x_set_bias_level(codec, SND_SOC_BIAS_ON);
	else
		uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);

	switch (pd->model) {
	case UDA134X_UDA1340:
	case UDA134X_UDA1344:
		ret = snd_soc_add_controls(codec, uda1340_snd_controls,
					ARRAY_SIZE(uda1340_snd_controls));
	break;
	case UDA134X_UDA1341:
		ret = snd_soc_add_controls(codec, uda1341_snd_controls,
					ARRAY_SIZE(uda1341_snd_controls));
	break;
	case UDA134X_UDA1345:
		ret = snd_soc_add_controls(codec, uda1345_snd_controls,
					ARRAY_SIZE(uda1345_snd_controls));
	break;
	default:
		printk(KERN_ERR "%s unknown codec type: %d",
			__func__, pd->model);
		kfree(uda134x);
		return -EINVAL;
	}

	if (ret < 0) {
		printk(KERN_ERR "UDA134X: failed to register controls\n");
		kfree(uda134x);
		return ret;
	}

	return 0;
}

/* power down chip */
static int uda134x_soc_remove(struct snd_soc_codec *codec)
{
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);

	uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
	uda134x_set_bias_level(codec, SND_SOC_BIAS_OFF);

	kfree(uda134x);
	return 0;
}

#if defined(CONFIG_PM)
static int uda134x_soc_suspend(struct snd_soc_codec *codec)
{
	uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
	uda134x_set_bias_level(codec, SND_SOC_BIAS_OFF);
	return 0;
}

static int uda134x_soc_resume(struct snd_soc_codec *codec)
{
	uda134x_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
	uda134x_set_bias_level(codec, SND_SOC_BIAS_ON);
	return 0;
}
#else
#define uda134x_soc_suspend NULL
#define uda134x_soc_resume NULL
#endif /* CONFIG_PM */

static struct snd_soc_codec_driver soc_codec_dev_uda134x = {
	.probe =        uda134x_soc_probe,
	.remove =       uda134x_soc_remove,
	.suspend =      uda134x_soc_suspend,
	.resume =       uda134x_soc_resume,
	.reg_cache_size = sizeof(uda134x_reg),
	.reg_word_size = sizeof(u8),
	.reg_cache_default = uda134x_reg,
	.reg_cache_step = 1,
	.read = uda134x_read_reg_cache,
	.write = uda134x_write,
	.set_bias_level = uda134x_set_bias_level,
};

static int __devinit uda134x_codec_probe(struct platform_device *pdev)
{
	return snd_soc_register_codec(&pdev->dev,
			&soc_codec_dev_uda134x, &uda134x_dai, 1);
}

static int __devexit uda134x_codec_remove(struct platform_device *pdev)
{
	snd_soc_unregister_codec(&pdev->dev);
	return 0;
}

static struct platform_driver uda134x_codec_driver = {
	.driver = {
		.name = "uda134x-codec",
		.owner = THIS_MODULE,
	},
	.probe = uda134x_codec_probe,
	.remove = __devexit_p(uda134x_codec_remove),
};

module_platform_driver(uda134x_codec_driver);

MODULE_DESCRIPTION("UDA134X ALSA soc codec driver");
MODULE_AUTHOR("Zoltan Devai, Christian Pellegrin <chripell@evolware.org>");
MODULE_LICENSE("GPL");
Commit	Line	Data
1cad1de1 CP	1	/*
	2	* uda134x.c -- UDA134X ALSA SoC Codec driver
	3	*
	4	* Modifications by Christian Pellegrin <chripell@evolware.org>
	5	*
	6	* Copyright 2007 Dension Audio Systems Ltd.
	7	* Author: Zoltan Devai
	8	*
	9	* Based on the WM87xx drivers by Liam Girdwood and Richard Purdie
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/module.h>
	17	#include <linux/delay.h>
5a0e3ad6	18	#include <linux/slab.h>
1cad1de1 CP	19	#include <sound/pcm.h>
	20	#include <sound/pcm_params.h>
	21	#include <sound/soc.h>
1cad1de1 CP	22	#include <sound/initval.h>
	23
	24	#include <sound/uda134x.h>
	25	#include <sound/l3.h>
	26
72f2b894	27	#include "uda134x.h"
1cad1de1 CP	28
1cad1de1 CP	29
1cad1de1 CP	30	#define UDA134X_RATES SNDRV_PCM_RATE_8000_48000
	31	#define UDA134X_FORMATS (SNDRV_PCM_FMTBIT_S8 \| SNDRV_PCM_FMTBIT_S16_LE \| \
	32	SNDRV_PCM_FMTBIT_S18_3LE \| SNDRV_PCM_FMTBIT_S20_3LE)
	33
	34	struct uda134x_priv {
	35	int sysclk;
	36	int dai_fmt;
	37
	38	struct snd_pcm_substream *master_substream;
	39	struct snd_pcm_substream *slave_substream;
	40	};
	41
	42	/* In-data addresses are hard-coded into the reg-cache values */
	43	static const char uda134x_reg[UDA134X_REGS_NUM] = {
	44	/* Extended address registers */
	45	0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
	46	/* Status, data regs */
ed632ad3	47	0x00, 0x83, 0x00, 0x40, 0x80, 0xC0, 0x00,
1cad1de1 CP	48	};
	49
	50	/*
	51	* The codec has no support for reading its registers except for peak level...
	52	*/
	53	static inline unsigned int uda134x_read_reg_cache(struct snd_soc_codec *codec,
	54	unsigned int reg)
	55	{
	56	u8 *cache = codec->reg_cache;
	57
	58	if (reg >= UDA134X_REGS_NUM)
	59	return -1;
	60	return cache[reg];
	61	}
	62
	63	/*
	64	* Write the register cache
	65	*/
	66	static inline void uda134x_write_reg_cache(struct snd_soc_codec *codec,
	67	u8 reg, unsigned int value)
	68	{
	69	u8 *cache = codec->reg_cache;
	70
	71	if (reg >= UDA134X_REGS_NUM)
	72	return;
	73	cache[reg] = value;
	74	}
	75
	76	/*
	77	* Write to the uda134x registers
	78	*
	79	*/
	80	static int uda134x_write(struct snd_soc_codec *codec, unsigned int reg,
	81	unsigned int value)
	82	{
	83	int ret;
	84	u8 addr;
	85	u8 data = value;
	86	struct uda134x_platform_data *pd = codec->control_data;
	87
	88	pr_debug("%s reg: %02X, value:%02X\n", __func__, reg, value);
	89
	90	if (reg >= UDA134X_REGS_NUM) {
af901ca1	91	printk(KERN_ERR "%s unknown register: reg: %u",
1cad1de1 CP	92	__func__, reg);
	93	return -EINVAL;
	94	}
	95
	96	uda134x_write_reg_cache(codec, reg, value);
	97
	98	switch (reg) {
	99	case UDA134X_STATUS0:
	100	case UDA134X_STATUS1:
	101	addr = UDA134X_STATUS_ADDR;
	102	break;
	103	case UDA134X_DATA000:
	104	case UDA134X_DATA001:
	105	case UDA134X_DATA010:
ed632ad3	106	case UDA134X_DATA011:
1cad1de1 CP	107	addr = UDA134X_DATA0_ADDR;
	108	break;
	109	case UDA134X_DATA1:
	110	addr = UDA134X_DATA1_ADDR;
	111	break;
	112	default:
	113	/* It's an extended address register */
	114	addr = (reg \| UDA134X_EXTADDR_PREFIX);
	115
	116	ret = l3_write(&pd->l3,
	117	UDA134X_DATA0_ADDR, &addr, 1);
	118	if (ret != 1)
	119	return -EIO;
	120
	121	addr = UDA134X_DATA0_ADDR;
	122	data = (value \| UDA134X_EXTDATA_PREFIX);
	123	break;
	124	}
	125
	126	ret = l3_write(&pd->l3,
	127	addr, &data, 1);
	128	if (ret != 1)
	129	return -EIO;
	130
	131	return 0;
	132	}
	133
	134	static inline void uda134x_reset(struct snd_soc_codec *codec)
	135	{
	136	u8 reset_reg = uda134x_read_reg_cache(codec, UDA134X_STATUS0);
	137	uda134x_write(codec, UDA134X_STATUS0, reset_reg \| (1<<6));
	138	msleep(1);
	139	uda134x_write(codec, UDA134X_STATUS0, reset_reg & ~(1<<6));
	140	}
	141
	142	static int uda134x_mute(struct snd_soc_dai *dai, int mute)
	143	{
	144	struct snd_soc_codec *codec = dai->codec;
	145	u8 mute_reg = uda134x_read_reg_cache(codec, UDA134X_DATA010);
	146
	147	pr_debug("%s mute: %d\n", __func__, mute);
	148
	149	if (mute)
	150	mute_reg \|= (1<<2);
	151	else
	152	mute_reg &= ~(1<<2);
	153
0c093fb5	154	uda134x_write(codec, UDA134X_DATA010, mute_reg);
1cad1de1 CP	155
	156	return 0;
	157	}
	158
dee89c4d MB	159	static int uda134x_startup(struct snd_pcm_substream *substream,
dee89c4d MB	160	struct snd_soc_dai *dai)
1cad1de1 CP	161	{
1cad1de1 CP	162	struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad	163	struct snd_soc_codec *codec =rtd->codec;
b2c812e2	164	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
1cad1de1 CP	165	struct snd_pcm_runtime *master_runtime;
	166
	167	if (uda134x->master_substream) {
	168	master_runtime = uda134x->master_substream->runtime;
	169
	170	pr_debug("%s constraining to %d bits at %d\n", __func__,
	171	master_runtime->sample_bits,
	172	master_runtime->rate);
	173
	174	snd_pcm_hw_constraint_minmax(substream->runtime,
	175	SNDRV_PCM_HW_PARAM_RATE,
	176	master_runtime->rate,
	177	master_runtime->rate);
	178
	179	snd_pcm_hw_constraint_minmax(substream->runtime,
	180	SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
	181	master_runtime->sample_bits,
	182	master_runtime->sample_bits);
	183
	184	uda134x->slave_substream = substream;
	185	} else
	186	uda134x->master_substream = substream;
	187
	188	return 0;
	189	}
	190
dee89c4d MB	191	static void uda134x_shutdown(struct snd_pcm_substream *substream,
dee89c4d MB	192	struct snd_soc_dai *dai)
1cad1de1 CP	193	{
1cad1de1 CP	194	struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad	195	struct snd_soc_codec *codec = rtd->codec;
b2c812e2	196	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
1cad1de1 CP	197
	198	if (uda134x->master_substream == substream)
	199	uda134x->master_substream = uda134x->slave_substream;
	200
	201	uda134x->slave_substream = NULL;
	202	}
	203
	204	static int uda134x_hw_params(struct snd_pcm_substream *substream,
dee89c4d MB	205	struct snd_pcm_hw_params *params,
dee89c4d MB	206	struct snd_soc_dai *dai)
1cad1de1 CP	207	{
1cad1de1 CP	208	struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad	209	struct snd_soc_codec *codec = rtd->codec;
b2c812e2	210	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
1cad1de1 CP	211	u8 hw_params;
	212
	213	if (substream == uda134x->slave_substream) {
	214	pr_debug("%s ignoring hw_params for slave substream\n",
	215	__func__);
	216	return 0;
	217	}
	218
	219	hw_params = uda134x_read_reg_cache(codec, UDA134X_STATUS0);
	220	hw_params &= STATUS0_SYSCLK_MASK;
	221	hw_params &= STATUS0_DAIFMT_MASK;
	222
	223	pr_debug("%s sysclk: %d, rate:%d\n", __func__,
	224	uda134x->sysclk, params_rate(params));
	225
	226	/* set SYSCLK / fs ratio */
	227	switch (uda134x->sysclk / params_rate(params)) {
	228	case 512:
	229	break;
	230	case 384:
	231	hw_params \|= (1<<4);
	232	break;
	233	case 256:
	234	hw_params \|= (1<<5);
	235	break;
	236	default:
	237	printk(KERN_ERR "%s unsupported fs\n", __func__);
	238	return -EINVAL;
	239	}
	240
	241	pr_debug("%s dai_fmt: %d, params_format:%d\n", __func__,
	242	uda134x->dai_fmt, params_format(params));
	243
	244	/* set DAI format and word length */
	245	switch (uda134x->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	246	case SND_SOC_DAIFMT_I2S:
	247	break;
	248	case SND_SOC_DAIFMT_RIGHT_J:
	249	switch (params_format(params)) {
	250	case SNDRV_PCM_FORMAT_S16_LE:
	251	hw_params \|= (1<<1);
	252	break;
	253	case SNDRV_PCM_FORMAT_S18_3LE:
	254	hw_params \|= (1<<2);
	255	break;
	256	case SNDRV_PCM_FORMAT_S20_3LE:
	257	hw_params \|= ((1<<2) \| (1<<1));
	258	break;
	259	default:
	260	printk(KERN_ERR "%s unsupported format (right)\n",
	261	__func__);
	262	return -EINVAL;
	263	}
	264	break;
	265	case SND_SOC_DAIFMT_LEFT_J:
	266	hw_params \|= (1<<3);
	267	break;
	268	default:
	269	printk(KERN_ERR "%s unsupported format\n", __func__);
	270	return -EINVAL;
	271	}
	272
	273	uda134x_write(codec, UDA134X_STATUS0, hw_params);
	274
275	return 0;
276	}
277
278	static int uda134x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
279	int clk_id, unsigned int freq, int dir)
280	{
281	struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2	282	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
1cad1de1	283
449bd54d	284	pr_debug("%s clk_id: %d, freq: %u, dir: %d\n", __func__,
1cad1de1 CP	285	clk_id, freq, dir);
	286
	287	/* Anything between 256fs8Khz and 512fs48Khz should be acceptable
	288	because the codec is slave. Of course limitations of the clock
	289	master (the IIS controller) apply.
	290	We'll error out on set_hw_params if it's not OK */
	291	if ((freq >= (256 * 8000)) && (freq <= (512 * 48000))) {
	292	uda134x->sysclk = freq;
	293	return 0;
	294	}
	295
	296	printk(KERN_ERR "%s unsupported sysclk\n", __func__);
	297	return -EINVAL;
	298	}
	299
	300	static int uda134x_set_dai_fmt(struct snd_soc_dai *codec_dai,
	301	unsigned int fmt)
	302	{
	303	struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2	304	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
1cad1de1 CP	305
	306	pr_debug("%s fmt: %08X\n", __func__, fmt);
	307
	308	/* codec supports only full slave mode */
	309	if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) {
	310	printk(KERN_ERR "%s unsupported slave mode\n", __func__);
	311	return -EINVAL;
	312	}
	313
	314	/* no support for clock inversion */
	315	if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) {
	316	printk(KERN_ERR "%s unsupported clock inversion\n", __func__);
	317	return -EINVAL;
	318	}
	319
	320	/* We can't setup DAI format here as it depends on the word bit num */
	321	/* so let's just store the value for later */
	322	uda134x->dai_fmt = fmt;
	323
	324	return 0;
	325	}
	326
	327	static int uda134x_set_bias_level(struct snd_soc_codec *codec,
	328	enum snd_soc_bias_level level)
	329	{
	330	u8 reg;
	331	struct uda134x_platform_data *pd = codec->control_data;
	332	int i;
	333	u8 *cache = codec->reg_cache;
	334
	335	pr_debug("%s bias level %d\n", __func__, level);
	336
	337	switch (level) {
	338	case SND_SOC_BIAS_ON:
	339	/* ADC, DAC on */
338de9d9 VZ	340	switch (pd->model) {
	341	case UDA134X_UDA1340:
	342	case UDA134X_UDA1344:
	343	case UDA134X_UDA1345:
	344	reg = uda134x_read_reg_cache(codec, UDA134X_DATA011);
	345	uda134x_write(codec, UDA134X_DATA011, reg \| 0x03);
	346	break;
	347	case UDA134X_UDA1341:
	348	reg = uda134x_read_reg_cache(codec, UDA134X_STATUS1);
	349	uda134x_write(codec, UDA134X_STATUS1, reg \| 0x03);
	350	break;
	351	default:
	352	printk(KERN_ERR "UDA134X SoC codec: "
	353	"unsupported model %d\n", pd->model);
	354	return -EINVAL;
	355	}
1cad1de1 CP	356	break;
	357	case SND_SOC_BIAS_PREPARE:
	358	/* power on */
	359	if (pd->power) {
	360	pd->power(1);
	361	/* Sync reg_cache with the hardware */
	362	for (i = 0; i < ARRAY_SIZE(uda134x_reg); i++)
f0fba2ad	363	codec->driver->write(codec, i, *cache++);
1cad1de1 CP	364	}
	365	break;
	366	case SND_SOC_BIAS_STANDBY:
	367	/* ADC, DAC power off */
338de9d9 VZ	368	switch (pd->model) {
	369	case UDA134X_UDA1340:
	370	case UDA134X_UDA1344:
	371	case UDA134X_UDA1345:
	372	reg = uda134x_read_reg_cache(codec, UDA134X_DATA011);
	373	uda134x_write(codec, UDA134X_DATA011, reg & ~(0x03));
	374	break;
	375	case UDA134X_UDA1341:
	376	reg = uda134x_read_reg_cache(codec, UDA134X_STATUS1);
	377	uda134x_write(codec, UDA134X_STATUS1, reg & ~(0x03));
	378	break;
	379	default:
	380	printk(KERN_ERR "UDA134X SoC codec: "
	381	"unsupported model %d\n", pd->model);
	382	return -EINVAL;
	383	}
1cad1de1 CP	384	break;
	385	case SND_SOC_BIAS_OFF:
	386	/* power off */
	387	if (pd->power)
	388	pd->power(0);
	389	break;
	390	}
ce6120cc	391	codec->dapm.bias_level = level;
1cad1de1 CP	392	return 0;
	393	}
	394
	395	static const char *uda134x_dsp_setting[] = {"Flat", "Minimum1",
	396	"Minimum2", "Maximum"};
	397	static const char *uda134x_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
	398	static const char *uda134x_mixmode[] = {"Differential", "Analog1",
	399	"Analog2", "Both"};
	400
	401	static const struct soc_enum uda134x_mixer_enum[] = {
	402	SOC_ENUM_SINGLE(UDA134X_DATA010, 0, 0x04, uda134x_dsp_setting),
	403	SOC_ENUM_SINGLE(UDA134X_DATA010, 3, 0x04, uda134x_deemph),
	404	SOC_ENUM_SINGLE(UDA134X_EA010, 0, 0x04, uda134x_mixmode),
	405	};
	406
	407	static const struct snd_kcontrol_new uda1341_snd_controls[] = {
	408	SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
	409	SOC_SINGLE("Capture Volume", UDA134X_EA010, 2, 0x07, 0),
	410	SOC_SINGLE("Analog1 Volume", UDA134X_EA000, 0, 0x1F, 1),
	411	SOC_SINGLE("Analog2 Volume", UDA134X_EA001, 0, 0x1F, 1),
	412
	413	SOC_SINGLE("Mic Sensitivity", UDA134X_EA010, 2, 7, 0),
	414	SOC_SINGLE("Mic Volume", UDA134X_EA101, 0, 0x1F, 0),
	415
	416	SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
	417	SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),
	418
	419	SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
	420	SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
	421	SOC_ENUM("Input Mux", uda134x_mixer_enum[2]),
	422
	423	SOC_SINGLE("AGC Switch", UDA134X_EA100, 4, 1, 0),
	424	SOC_SINGLE("AGC Target Volume", UDA134X_EA110, 0, 0x03, 1),
	425	SOC_SINGLE("AGC Timing", UDA134X_EA110, 2, 0x07, 0),
	426
	427	SOC_SINGLE("DAC +6dB Switch", UDA134X_STATUS1, 6, 1, 0),
	428	SOC_SINGLE("ADC +6dB Switch", UDA134X_STATUS1, 5, 1, 0),
	429	SOC_SINGLE("ADC Polarity Switch", UDA134X_STATUS1, 4, 1, 0),
	430	SOC_SINGLE("DAC Polarity Switch", UDA134X_STATUS1, 3, 1, 0),
	431	SOC_SINGLE("Double Speed Playback Switch", UDA134X_STATUS1, 2, 1, 0),
	432	SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
	433	};
	434
	435	static const struct snd_kcontrol_new uda1340_snd_controls[] = {
	436	SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
	437
	438	SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
	439	SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),
	440
	441	SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
	442	SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
	443
	444	SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
	445	};
	446
b28528a1 VZ	447	static const struct snd_kcontrol_new uda1345_snd_controls[] = {
	448	SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
	449
	450	SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
	451
	452	SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
	453	};
	454
85e7652d	455	static const struct snd_soc_dai_ops uda134x_dai_ops = {
6335d055 EM	456	.startup = uda134x_startup,
	457	.shutdown = uda134x_shutdown,
	458	.hw_params = uda134x_hw_params,
	459	.digital_mute = uda134x_mute,
	460	.set_sysclk = uda134x_set_dai_sysclk,
	461	.set_fmt = uda134x_set_dai_fmt,
	462	};
	463
f0fba2ad LG	464	static struct snd_soc_dai_driver uda134x_dai = {
f0fba2ad LG	465	.name = "uda134x-hifi",
1cad1de1 CP	466	/* playback capabilities */
	467	.playback = {
	468	.stream_name = "Playback",
	469	.channels_min = 1,
	470	.channels_max = 2,
	471	.rates = UDA134X_RATES,
	472	.formats = UDA134X_FORMATS,
	473	},
	474	/* capture capabilities */
	475	.capture = {
	476	.stream_name = "Capture",
	477	.channels_min = 1,
	478	.channels_max = 2,
	479	.rates = UDA134X_RATES,
	480	.formats = UDA134X_FORMATS,
	481	},
	482	/* pcm operations */
6335d055	483	.ops = &uda134x_dai_ops,
1cad1de1	484	};
1cad1de1	485
f0fba2ad	486	static int uda134x_soc_probe(struct snd_soc_codec *codec)
1cad1de1	487	{
1cad1de1	488	struct uda134x_priv *uda134x;
a110f4ef MB	489	struct uda134x_platform_data *pd = codec->card->dev->platform_data;
a110f4ef MB	490
f0fba2ad	491	int ret;
1cad1de1 CP	492
	493	printk(KERN_INFO "UDA134X SoC Audio Codec\n");
	494
f0fba2ad	495	if (!pd) {
1cad1de1 CP	496	printk(KERN_ERR "UDA134X SoC codec: "
	497	"missing L3 bitbang function\n");
	498	return -ENODEV;
	499	}
	500
1cad1de1 CP	501	switch (pd->model) {
	502	case UDA134X_UDA1340:
	503	case UDA134X_UDA1341:
	504	case UDA134X_UDA1344:
b28528a1	505	case UDA134X_UDA1345:
1cad1de1 CP	506	break;
	507	default:
	508	printk(KERN_ERR "UDA134X SoC codec: "
	509	"unsupported model %d\n",
	510	pd->model);
	511	return -EINVAL;
	512	}
	513
1cad1de1 CP	514	uda134x = kzalloc(sizeof(struct uda134x_priv), GFP_KERNEL);
1cad1de1 CP	515	if (uda134x == NULL)
f0fba2ad	516	return -ENOMEM;
b2c812e2	517	snd_soc_codec_set_drvdata(codec, uda134x);
1cad1de1	518
f0fba2ad	519	codec->control_data = pd;
1cad1de1 CP	520
	521	if (pd->power)
	522	pd->power(1);
	523
	524	uda134x_reset(codec);
	525
f0fba2ad	526	if (pd->is_powered_on_standby)
e4295b40	527	uda134x_set_bias_level(codec, SND_SOC_BIAS_ON);
f0fba2ad	528	else
e4295b40	529	uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1cad1de1	530
3e8e1952 IM	531	switch (pd->model) {
	532	case UDA134X_UDA1340:
	533	case UDA134X_UDA1344:
	534	ret = snd_soc_add_controls(codec, uda1340_snd_controls,
	535	ARRAY_SIZE(uda1340_snd_controls));
	536	break;
	537	case UDA134X_UDA1341:
	538	ret = snd_soc_add_controls(codec, uda1341_snd_controls,
	539	ARRAY_SIZE(uda1341_snd_controls));
	540	break;
b28528a1 VZ	541	case UDA134X_UDA1345:
	542	ret = snd_soc_add_controls(codec, uda1345_snd_controls,
	543	ARRAY_SIZE(uda1345_snd_controls));
	544	break;
3e8e1952	545	default:
af901ca1	546	printk(KERN_ERR "%s unknown codec type: %d",
3e8e1952	547	__func__, pd->model);
f0fba2ad LG	548	kfree(uda134x);
f0fba2ad LG	549	return -EINVAL;
3e8e1952 IM	550	}
3e8e1952 IM	551
1cad1de1 CP	552	if (ret < 0) {
1cad1de1 CP	553	printk(KERN_ERR "UDA134X: failed to register controls\n");
f0fba2ad LG	554	kfree(uda134x);
f0fba2ad LG	555	return ret;
1cad1de1 CP	556	}
1cad1de1 CP	557
1cad1de1	558	return 0;
1cad1de1 CP	559	}
	560
	561	/* power down chip */
f0fba2ad	562	static int uda134x_soc_remove(struct snd_soc_codec *codec)
1cad1de1	563	{
f0fba2ad	564	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
1cad1de1 CP	565
	566	uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
	567	uda134x_set_bias_level(codec, SND_SOC_BIAS_OFF);
	568
f0fba2ad	569	kfree(uda134x);
1cad1de1 CP	570	return 0;
	571	}
	572
	573	#if defined(CONFIG_PM)
84b315ee	574	static int uda134x_soc_suspend(struct snd_soc_codec *codec)
1cad1de1	575	{
1cad1de1 CP	576	uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
	577	uda134x_set_bias_level(codec, SND_SOC_BIAS_OFF);
	578	return 0;
	579	}
	580
f0fba2ad	581	static int uda134x_soc_resume(struct snd_soc_codec *codec)
1cad1de1	582	{
1cad1de1 CP	583	uda134x_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
	584	uda134x_set_bias_level(codec, SND_SOC_BIAS_ON);
	585	return 0;
	586	}
	587	#else
	588	#define uda134x_soc_suspend NULL
	589	#define uda134x_soc_resume NULL
	590	#endif /* CONFIG_PM */
	591
f0fba2ad	592	static struct snd_soc_codec_driver soc_codec_dev_uda134x = {
1cad1de1 CP	593	.probe = uda134x_soc_probe,
	594	.remove = uda134x_soc_remove,
	595	.suspend = uda134x_soc_suspend,
	596	.resume = uda134x_soc_resume,
f0fba2ad LG	597	.reg_cache_size = sizeof(uda134x_reg),
f0fba2ad LG	598	.reg_word_size = sizeof(u8),
2811fe2b	599	.reg_cache_default = uda134x_reg,
f0fba2ad LG	600	.reg_cache_step = 1,
	601	.read = uda134x_read_reg_cache,
	602	.write = uda134x_write,
f0fba2ad	603	.set_bias_level = uda134x_set_bias_level,
f0fba2ad LG	604	};
	605
	606	static int __devinit uda134x_codec_probe(struct platform_device *pdev)
	607	{
	608	return snd_soc_register_codec(&pdev->dev,
	609	&soc_codec_dev_uda134x, &uda134x_dai, 1);
	610	}
	611
	612	static int __devexit uda134x_codec_remove(struct platform_device *pdev)
	613	{
	614	snd_soc_unregister_codec(&pdev->dev);
	615	return 0;
	616	}
	617
	618	static struct platform_driver uda134x_codec_driver = {
	619	.driver = {
	620	.name = "uda134x-codec",
	621	.owner = THIS_MODULE,
	622	},
	623	.probe = uda134x_codec_probe,
	624	.remove = __devexit_p(uda134x_codec_remove),
1cad1de1	625	};
1cad1de1	626
5bbcc3c0	627	module_platform_driver(uda134x_codec_driver);
64089b84	628
1cad1de1 CP	629	MODULE_DESCRIPTION("UDA134X ALSA soc codec driver");
	630	MODULE_AUTHOR("Zoltan Devai, Christian Pellegrin <chripell@evolware.org>");
	631	MODULE_LICENSE("GPL");