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ASoC: Fix copyright statements on Simtec files
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
db04e2c5 45 0x91, /* REG_CODEC_MODE (0x1) */
cc17557e
SS		 46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
118};
119
7393958f
PU		 120/* codec private data */
121struct twl4030_priv {
122 unsigned int bypass_state;
123 unsigned int codec_powered;
124 unsigned int codec_muted;
125};
126
cc17557e
SS		 127/*
128 * read twl4030 register cache
129 */
130static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
131 unsigned int reg)
132{
133 u8 *cache = codec->reg_cache;
134
91432e97
IM		 135 if (reg >= TWL4030_CACHEREGNUM)
136 return -EIO;
137
cc17557e
SS		 138 return cache[reg];
139}
140
141/*
142 * write twl4030 register cache
143 */
144static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
145 u8 reg, u8 value)
146{
147 u8 *cache = codec->reg_cache;
148
149 if (reg >= TWL4030_CACHEREGNUM)
150 return;
151 cache[reg] = value;
152}
153
154/*
155 * write to the twl4030 register space
156 */
157static int twl4030_write(struct snd_soc_codec *codec,
158 unsigned int reg, unsigned int value)
159{
160 twl4030_write_reg_cache(codec, reg, value);
161 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
162}
163
db04e2c5 164static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 165{
7393958f 166 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 167 u8 mode;
168
7393958f
PU		 169 if (enable == twl4030->codec_powered)
170 return;
171
cc17557e 172 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
db04e2c5
PU		 173 if (enable)
174 mode |= TWL4030_CODECPDZ;
175 else
176 mode &= ~TWL4030_CODECPDZ;
cc17557e 177
db04e2c5 178 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
7393958f 179 twl4030->codec_powered = enable;
cc17557e
SS		 180
181 /* REVISIT: this delay is present in TI sample drivers */
182 /* but there seems to be no TRM requirement for it */
183 udelay(10);
184}
185
186static void twl4030_init_chip(struct snd_soc_codec *codec)
187{
188 int i;
189
190 /* clear CODECPDZ prior to setting register defaults */
db04e2c5 191 twl4030_codec_enable(codec, 0);
cc17557e
SS		 192
193 /* set all audio section registers to reasonable defaults */
194 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
195 twl4030_write(codec, i, twl4030_reg[i]);
196
197}
198
7393958f
PU		 199static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
200{
201 struct twl4030_priv *twl4030 = codec->private_data;
202 u8 reg_val;
203
204 if (mute == twl4030->codec_muted)
205 return;
206
207 if (mute) {
208 /* Bypass the reg_cache and mute the volumes
209 * Headset mute is done in it's own event handler
210 * Things to mute: Earpiece, PreDrivL/R, CarkitL/R
211 */
212 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL);
213 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
214 reg_val & (~TWL4030_EAR_GAIN),
215 TWL4030_REG_EAR_CTL);
216
217 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL);
218 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
219 reg_val & (~TWL4030_PREDL_GAIN),
220 TWL4030_REG_PREDL_CTL);
221 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL);
222 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
223 reg_val & (~TWL4030_PREDR_GAIN),
224 TWL4030_REG_PREDL_CTL);
225
226 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL);
227 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
228 reg_val & (~TWL4030_PRECKL_GAIN),
229 TWL4030_REG_PRECKL_CTL);
230 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL);
231 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
232 reg_val & (~TWL4030_PRECKL_GAIN),
233 TWL4030_REG_PRECKR_CTL);
234
235 /* Disable PLL */
236 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
237 reg_val &= ~TWL4030_APLL_EN;
238 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
239 } else {
240 /* Restore the volumes
241 * Headset mute is done in it's own event handler
242 * Things to restore: Earpiece, PreDrivL/R, CarkitL/R
243 */
244 twl4030_write(codec, TWL4030_REG_EAR_CTL,
245 twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL));
246
247 twl4030_write(codec, TWL4030_REG_PREDL_CTL,
248 twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL));
249 twl4030_write(codec, TWL4030_REG_PREDR_CTL,
250 twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL));
251
252 twl4030_write(codec, TWL4030_REG_PRECKL_CTL,
253 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL));
254 twl4030_write(codec, TWL4030_REG_PRECKR_CTL,
255 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL));
256
257 /* Enable PLL */
258 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
259 reg_val |= TWL4030_APLL_EN;
260 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
261 }
262
263 twl4030->codec_muted = mute;
264}
265
006f367e
PU		 266static void twl4030_power_up(struct snd_soc_codec *codec)
267{
7393958f 268 struct twl4030_priv *twl4030 = codec->private_data;
006f367e
PU		 269 u8 anamicl, regmisc1, byte;
270 int i = 0;
271
7393958f
PU		 272 if (twl4030->codec_powered)
273 return;
274
006f367e
PU		 275 /* set CODECPDZ to turn on codec */
276 twl4030_codec_enable(codec, 1);
277
278 /* initiate offset cancellation */
279 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
280 twl4030_write(codec, TWL4030_REG_ANAMICL,
281 anamicl | TWL4030_CNCL_OFFSET_START);
282
283 /* wait for offset cancellation to complete */
284 do {
285 /* this takes a little while, so don't slam i2c */
286 udelay(2000);
287 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
288 TWL4030_REG_ANAMICL);
289 } while ((i++ < 100) &&
290 ((byte & TWL4030_CNCL_OFFSET_START) ==
291 TWL4030_CNCL_OFFSET_START));
292
293 /* Make sure that the reg_cache has the same value as the HW */
294 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
295
296 /* anti-pop when changing analog gain */
297 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
298 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
299 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
300
301 /* toggle CODECPDZ as per TRM */
302 twl4030_codec_enable(codec, 0);
303 twl4030_codec_enable(codec, 1);
304}
305
7393958f
PU		 306/*
307 * Unconditional power down
308 */
006f367e
PU		 309static void twl4030_power_down(struct snd_soc_codec *codec)
310{
311 /* power down */
312 twl4030_codec_enable(codec, 0);
313}
314
5e98a464
PU		 315/* Earpiece */
316static const char *twl4030_earpiece_texts[] =
2f423577 317 {"Off", "DACL1", "DACL2", "DACR1"};
5e98a464 318
2f423577
PU		 319static const unsigned int twl4030_earpiece_values[] =
320 {0x0, 0x1, 0x2, 0x4};
321
cb1ace04 322static const struct soc_enum twl4030_earpiece_enum =
2f423577 323 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1, 0x7,
5e98a464 324 ARRAY_SIZE(twl4030_earpiece_texts),
2f423577
PU		 325 twl4030_earpiece_texts,
326 twl4030_earpiece_values);
5e98a464
PU		 327
328static const struct snd_kcontrol_new twl4030_dapm_earpiece_control =
2f423577 329SOC_DAPM_VALUE_ENUM("Route", twl4030_earpiece_enum);
5e98a464 330
2a6f5c58
PU		 331/* PreDrive Left */
332static const char *twl4030_predrivel_texts[] =
2f423577
PU		 333 {"Off", "DACL1", "DACL2", "DACR2"};
334
335static const unsigned int twl4030_predrivel_values[] =
336 {0x0, 0x1, 0x2, 0x4};
2a6f5c58 337
cb1ace04 338static const struct soc_enum twl4030_predrivel_enum =
2f423577 339 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDL_CTL, 1, 0x7,
2a6f5c58 340 ARRAY_SIZE(twl4030_predrivel_texts),
2f423577
PU		 341 twl4030_predrivel_texts,
342 twl4030_predrivel_values);
2a6f5c58
PU		 343
344static const struct snd_kcontrol_new twl4030_dapm_predrivel_control =
2f423577 345SOC_DAPM_VALUE_ENUM("Route", twl4030_predrivel_enum);
2a6f5c58
PU		 346
347/* PreDrive Right */
348static const char *twl4030_predriver_texts[] =
2f423577 349 {"Off", "DACR1", "DACR2", "DACL2"};
2a6f5c58 350
2f423577
PU		 351static const unsigned int twl4030_predriver_values[] =
352 {0x0, 0x1, 0x2, 0x4};
353
cb1ace04 354static const struct soc_enum twl4030_predriver_enum =
2f423577 355 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDR_CTL, 1, 0x7,
2a6f5c58 356 ARRAY_SIZE(twl4030_predriver_texts),
2f423577
PU		 357 twl4030_predriver_texts,
358 twl4030_predriver_values);
2a6f5c58
PU		 359
360static const struct snd_kcontrol_new twl4030_dapm_predriver_control =
2f423577 361SOC_DAPM_VALUE_ENUM("Route", twl4030_predriver_enum);
2a6f5c58 362
dfad21a2
PU		 363/* Headset Left */
364static const char *twl4030_hsol_texts[] =
365 {"Off", "DACL1", "DACL2"};
366
367static const struct soc_enum twl4030_hsol_enum =
368 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 1,
369 ARRAY_SIZE(twl4030_hsol_texts),
370 twl4030_hsol_texts);
371
372static const struct snd_kcontrol_new twl4030_dapm_hsol_control =
373SOC_DAPM_ENUM("Route", twl4030_hsol_enum);
374
375/* Headset Right */
376static const char *twl4030_hsor_texts[] =
377 {"Off", "DACR1", "DACR2"};
378
379static const struct soc_enum twl4030_hsor_enum =
380 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 4,
381 ARRAY_SIZE(twl4030_hsor_texts),
382 twl4030_hsor_texts);
383
384static const struct snd_kcontrol_new twl4030_dapm_hsor_control =
385SOC_DAPM_ENUM("Route", twl4030_hsor_enum);
386
5152d8c2
PU		 387/* Carkit Left */
388static const char *twl4030_carkitl_texts[] =
389 {"Off", "DACL1", "DACL2"};
390
391static const struct soc_enum twl4030_carkitl_enum =
392 SOC_ENUM_SINGLE(TWL4030_REG_PRECKL_CTL, 1,
393 ARRAY_SIZE(twl4030_carkitl_texts),
394 twl4030_carkitl_texts);
395
396static const struct snd_kcontrol_new twl4030_dapm_carkitl_control =
397SOC_DAPM_ENUM("Route", twl4030_carkitl_enum);
398
399/* Carkit Right */
400static const char *twl4030_carkitr_texts[] =
401 {"Off", "DACR1", "DACR2"};
402
403static const struct soc_enum twl4030_carkitr_enum =
404 SOC_ENUM_SINGLE(TWL4030_REG_PRECKR_CTL, 1,
405 ARRAY_SIZE(twl4030_carkitr_texts),
406 twl4030_carkitr_texts);
407
408static const struct snd_kcontrol_new twl4030_dapm_carkitr_control =
409SOC_DAPM_ENUM("Route", twl4030_carkitr_enum);
410
df339804
PU		 411/* Handsfree Left */
412static const char *twl4030_handsfreel_texts[] =
413 {"Voice", "DACL1", "DACL2", "DACR2"};
414
415static const struct soc_enum twl4030_handsfreel_enum =
416 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
417 ARRAY_SIZE(twl4030_handsfreel_texts),
418 twl4030_handsfreel_texts);
419
420static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
421SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
422
423/* Handsfree Right */
424static const char *twl4030_handsfreer_texts[] =
425 {"Voice", "DACR1", "DACR2", "DACL2"};
426
427static const struct soc_enum twl4030_handsfreer_enum =
428 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
429 ARRAY_SIZE(twl4030_handsfreer_texts),
430 twl4030_handsfreer_texts);
431
432static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
433SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
434
276c6222
PU		 435/* Left analog microphone selection */
436static const char *twl4030_analoglmic_texts[] =
2f423577
PU		 437 {"Off", "Main mic", "Headset mic", "AUXL", "Carkit mic"};
438
439static const unsigned int twl4030_analoglmic_values[] =
440 {0x0, 0x1, 0x2, 0x4, 0x8};
276c6222 441
cb1ace04 442static const struct soc_enum twl4030_analoglmic_enum =
2f423577 443 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICL, 0, 0xf,
276c6222 444 ARRAY_SIZE(twl4030_analoglmic_texts),
2f423577
PU		 445 twl4030_analoglmic_texts,
446 twl4030_analoglmic_values);
276c6222
PU		 447
448static const struct snd_kcontrol_new twl4030_dapm_analoglmic_control =
2f423577 449SOC_DAPM_VALUE_ENUM("Route", twl4030_analoglmic_enum);
276c6222
PU		 450
451/* Right analog microphone selection */
452static const char *twl4030_analogrmic_texts[] =
2f423577 453 {"Off", "Sub mic", "AUXR"};
276c6222 454
2f423577
PU		 455static const unsigned int twl4030_analogrmic_values[] =
456 {0x0, 0x1, 0x4};
457
cb1ace04 458static const struct soc_enum twl4030_analogrmic_enum =
2f423577 459 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICR, 0, 0x5,
276c6222 460 ARRAY_SIZE(twl4030_analogrmic_texts),
2f423577
PU		 461 twl4030_analogrmic_texts,
462 twl4030_analogrmic_values);
276c6222
PU		 463
464static const struct snd_kcontrol_new twl4030_dapm_analogrmic_control =
2f423577 465SOC_DAPM_VALUE_ENUM("Route", twl4030_analogrmic_enum);
276c6222
PU		 466
467/* TX1 L/R Analog/Digital microphone selection */
468static const char *twl4030_micpathtx1_texts[] =
469 {"Analog", "Digimic0"};
470
471static const struct soc_enum twl4030_micpathtx1_enum =
472 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
473 ARRAY_SIZE(twl4030_micpathtx1_texts),
474 twl4030_micpathtx1_texts);
475
476static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
477SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
478
479/* TX2 L/R Analog/Digital microphone selection */
480static const char *twl4030_micpathtx2_texts[] =
481 {"Analog", "Digimic1"};
482
483static const struct soc_enum twl4030_micpathtx2_enum =
484 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
485 ARRAY_SIZE(twl4030_micpathtx2_texts),
486 twl4030_micpathtx2_texts);
487
488static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
489SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
490
7393958f
PU		 491/* Analog bypass for AudioR1 */
492static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
493 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
494
495/* Analog bypass for AudioL1 */
496static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
497 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
498
499/* Analog bypass for AudioR2 */
500static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
501 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
502
503/* Analog bypass for AudioL2 */
504static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
505 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
506
6bab83fd
PU		 507/* Digital bypass gain, 0 mutes the bypass */
508static const unsigned int twl4030_dapm_dbypass_tlv[] = {
509 TLV_DB_RANGE_HEAD(2),
510 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
511 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
512};
513
514/* Digital bypass left (TX1L -> RX2L) */
515static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
516 SOC_DAPM_SINGLE_TLV("Volume",
517 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
518 twl4030_dapm_dbypass_tlv);
519
520/* Digital bypass right (TX1R -> RX2R) */
521static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
522 SOC_DAPM_SINGLE_TLV("Volume",
523 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
524 twl4030_dapm_dbypass_tlv);
525
276c6222
PU		 526static int micpath_event(struct snd_soc_dapm_widget *w,
527 struct snd_kcontrol *kcontrol, int event)
528{
529 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
530 unsigned char adcmicsel, micbias_ctl;
531
532 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
533 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
534 /* Prepare the bits for the given TX path:
535 * shift_l == 0: TX1 microphone path
536 * shift_l == 2: TX2 microphone path */
537 if (e->shift_l) {
538 /* TX2 microphone path */
539 if (adcmicsel & TWL4030_TX2IN_SEL)
540 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
541 else
542 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
543 } else {
544 /* TX1 microphone path */
545 if (adcmicsel & TWL4030_TX1IN_SEL)
546 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
547 else
548 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
549 }
550
551 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
552
553 return 0;
554}
555
49d92c7d
SM		 556static int handsfree_event(struct snd_soc_dapm_widget *w,
557 struct snd_kcontrol *kcontrol, int event)
558{
559 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
560 unsigned char hs_ctl;
561
562 hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
563
564 if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
565 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
566 twl4030_write(w->codec, e->reg, hs_ctl);
567 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
568 twl4030_write(w->codec, e->reg, hs_ctl);
569 hs_ctl |= TWL4030_HF_CTL_HB_EN;
570 twl4030_write(w->codec, e->reg, hs_ctl);
571 } else {
572 hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
573 | TWL4030_HF_CTL_HB_EN);
574 twl4030_write(w->codec, e->reg, hs_ctl);
575 }
576
577 return 0;
578}
579
aad749e5
PU		 580static int headsetl_event(struct snd_soc_dapm_widget *w,
581 struct snd_kcontrol *kcontrol, int event)
582{
583 unsigned char hs_gain, hs_pop;
584
585 /* Save the current volume */
586 hs_gain = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_GAIN_SET);
587
588 switch (event) {
589 case SND_SOC_DAPM_POST_PMU:
590 /* Do the anti-pop/bias ramp enable according to the TRM */
591 hs_pop = TWL4030_RAMP_DELAY_645MS;
592 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
593 hs_pop |= TWL4030_VMID_EN;
594 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
595 /* Is this needed? Can we just use whatever gain here? */
596 twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET,
597 (hs_gain & (~0x0f)) | 0x0a);
598 hs_pop |= TWL4030_RAMP_EN;
599 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
600
601 /* Restore the original volume */
602 twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
603 break;
604 case SND_SOC_DAPM_POST_PMD:
605 /* Do the anti-pop/bias ramp disable according to the TRM */
606 hs_pop = twl4030_read_reg_cache(w->codec,
607 TWL4030_REG_HS_POPN_SET);
608 hs_pop &= ~TWL4030_RAMP_EN;
609 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
610 /* Bypass the reg_cache to mute the headset */
611 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
612 hs_gain & (~0x0f),
613 TWL4030_REG_HS_GAIN_SET);
614 hs_pop &= ~TWL4030_VMID_EN;
615 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
616 break;
617 }
618 return 0;
619}
620
7393958f
PU		 621static int bypass_event(struct snd_soc_dapm_widget *w,
622 struct snd_kcontrol *kcontrol, int event)
623{
624 struct soc_mixer_control *m =
625 (struct soc_mixer_control *)w->kcontrols->private_value;
626 struct twl4030_priv *twl4030 = w->codec->private_data;
627 unsigned char reg;
628
629 reg = twl4030_read_reg_cache(w->codec, m->reg);
6bab83fd
PU		 630
631 if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
632 /* Analog bypass */
633 if (reg & (1 << m->shift))
634 twl4030->bypass_state |=
635 (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
636 else
637 twl4030->bypass_state &=
638 ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
639 } else {
640 /* Digital bypass */
641 if (reg & (0x7 << m->shift))
642 twl4030->bypass_state |= (1 << (m->shift ? 5 : 4));
643 else
644 twl4030->bypass_state &= ~(1 << (m->shift ? 5 : 4));
645 }
7393958f
PU		 646
647 if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
648 if (twl4030->bypass_state)
649 twl4030_codec_mute(w->codec, 0);
650 else
651 twl4030_codec_mute(w->codec, 1);
652 }
653 return 0;
654}
655
b0bd53a7
PU		 656/*
657 * Some of the gain controls in TWL (mostly those which are associated with
658 * the outputs) are implemented in an interesting way:
659 * 0x0 : Power down (mute)
660 * 0x1 : 6dB
661 * 0x2 : 0 dB
662 * 0x3 : -6 dB
663 * Inverting not going to help with these.
664 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
665 */
666#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
667 xinvert, tlv_array) \
668{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
669 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
670 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
671 .tlv.p = (tlv_array), \
672 .info = snd_soc_info_volsw, \
673 .get = snd_soc_get_volsw_twl4030, \
674 .put = snd_soc_put_volsw_twl4030, \
675 .private_value = (unsigned long)&(struct soc_mixer_control) \
676 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
677 .max = xmax, .invert = xinvert} }
678#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
679 xinvert, tlv_array) \
680{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
681 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
682 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
683 .tlv.p = (tlv_array), \
684 .info = snd_soc_info_volsw_2r, \
685 .get = snd_soc_get_volsw_r2_twl4030,\
686 .put = snd_soc_put_volsw_r2_twl4030, \
687 .private_value = (unsigned long)&(struct soc_mixer_control) \
688 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 689 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 690#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
691 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
692 xinvert, tlv_array)
693
694static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
695 struct snd_ctl_elem_value *ucontrol)
696{
697 struct soc_mixer_control *mc =
698 (struct soc_mixer_control *)kcontrol->private_value;
699 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
700 unsigned int reg = mc->reg;
701 unsigned int shift = mc->shift;
702 unsigned int rshift = mc->rshift;
703 int max = mc->max;
704 int mask = (1 << fls(max)) - 1;
705
706 ucontrol->value.integer.value[0] =
707 (snd_soc_read(codec, reg) >> shift) & mask;
708 if (ucontrol->value.integer.value[0])
709 ucontrol->value.integer.value[0] =
710 max + 1 - ucontrol->value.integer.value[0];
711
712 if (shift != rshift) {
713 ucontrol->value.integer.value[1] =
714 (snd_soc_read(codec, reg) >> rshift) & mask;
715 if (ucontrol->value.integer.value[1])
716 ucontrol->value.integer.value[1] =
717 max + 1 - ucontrol->value.integer.value[1];
718 }
719
720 return 0;
721}
722
723static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
724 struct snd_ctl_elem_value *ucontrol)
725{
726 struct soc_mixer_control *mc =
727 (struct soc_mixer_control *)kcontrol->private_value;
728 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
729 unsigned int reg = mc->reg;
730 unsigned int shift = mc->shift;
731 unsigned int rshift = mc->rshift;
732 int max = mc->max;
733 int mask = (1 << fls(max)) - 1;
734 unsigned short val, val2, val_mask;
735
736 val = (ucontrol->value.integer.value[0] & mask);
737
738 val_mask = mask << shift;
739 if (val)
740 val = max + 1 - val;
741 val = val << shift;
742 if (shift != rshift) {
743 val2 = (ucontrol->value.integer.value[1] & mask);
744 val_mask |= mask << rshift;
745 if (val2)
746 val2 = max + 1 - val2;
747 val |= val2 << rshift;
748 }
749 return snd_soc_update_bits(codec, reg, val_mask, val);
750}
751
752static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
753 struct snd_ctl_elem_value *ucontrol)
754{
755 struct soc_mixer_control *mc =
756 (struct soc_mixer_control *)kcontrol->private_value;
757 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
758 unsigned int reg = mc->reg;
759 unsigned int reg2 = mc->rreg;
760 unsigned int shift = mc->shift;
761 int max = mc->max;
762 int mask = (1<<fls(max))-1;
763
764 ucontrol->value.integer.value[0] =
765 (snd_soc_read(codec, reg) >> shift) & mask;
766 ucontrol->value.integer.value[1] =
767 (snd_soc_read(codec, reg2) >> shift) & mask;
768
769 if (ucontrol->value.integer.value[0])
770 ucontrol->value.integer.value[0] =
771 max + 1 - ucontrol->value.integer.value[0];
772 if (ucontrol->value.integer.value[1])
773 ucontrol->value.integer.value[1] =
774 max + 1 - ucontrol->value.integer.value[1];
775
776 return 0;
777}
778
779static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
780 struct snd_ctl_elem_value *ucontrol)
781{
782 struct soc_mixer_control *mc =
783 (struct soc_mixer_control *)kcontrol->private_value;
784 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
785 unsigned int reg = mc->reg;
786 unsigned int reg2 = mc->rreg;
787 unsigned int shift = mc->shift;
788 int max = mc->max;
789 int mask = (1 << fls(max)) - 1;
790 int err;
791 unsigned short val, val2, val_mask;
792
793 val_mask = mask << shift;
794 val = (ucontrol->value.integer.value[0] & mask);
795 val2 = (ucontrol->value.integer.value[1] & mask);
796
797 if (val)
798 val = max + 1 - val;
799 if (val2)
800 val2 = max + 1 - val2;
801
802 val = val << shift;
803 val2 = val2 << shift;
804
805 err = snd_soc_update_bits(codec, reg, val_mask, val);
806 if (err < 0)
807 return err;
808
809 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
810 return err;
811}
812
c10b82cf
PU		 813/*
814 * FGAIN volume control:
815 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
816 */
d889a72c 817static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 818
0d33ea0b
PU		 819/*
820 * CGAIN volume control:
821 * 0 dB to 12 dB in 6 dB steps
822 * value 2 and 3 means 12 dB
823 */
d889a72c
PU		 824static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
825
826/*
827 * Analog playback gain
828 * -24 dB to 12 dB in 2 dB steps
829 */
830static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 831
4290239c
PU		 832/*
833 * Gain controls tied to outputs
834 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
835 */
836static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
837
381a22b5
PU		 838/*
839 * Capture gain after the ADCs
840 * from 0 dB to 31 dB in 1 dB steps
841 */
842static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
843
5920b453
GI		 844/*
845 * Gain control for input amplifiers
846 * 0 dB to 30 dB in 6 dB steps
847 */
848static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
849
cc17557e 850static const struct snd_kcontrol_new twl4030_snd_controls[] = {
d889a72c
PU		 851 /* Common playback gain controls */
852 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
853 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
854 0, 0x3f, 0, digital_fine_tlv),
855 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
856 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
857 0, 0x3f, 0, digital_fine_tlv),
858
859 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
860 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
861 6, 0x2, 0, digital_coarse_tlv),
862 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
863 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
864 6, 0x2, 0, digital_coarse_tlv),
865
866 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
867 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
868 3, 0x12, 1, analog_tlv),
869 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
870 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
871 3, 0x12, 1, analog_tlv),
44c55870
PU		 872 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
873 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
874 1, 1, 0),
875 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
876 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
877 1, 1, 0),
381a22b5 878
4290239c
PU		 879 /* Separate output gain controls */
880 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
881 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
882 4, 3, 0, output_tvl),
883
884 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
885 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
886
887 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
888 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
889 4, 3, 0, output_tvl),
890
891 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
892 TWL4030_REG_EAR_CTL, 4, 3, 0, output_tvl),
893
381a22b5 894 /* Common capture gain controls */
276c6222 895 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 896 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
897 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 898 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
899 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
900 0, 0x1f, 0, digital_capture_tlv),
5920b453 901
276c6222 902 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 903 0, 3, 5, 0, input_gain_tlv),
cc17557e
SS		 904};
905
cc17557e 906static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 907 /* Left channel inputs */
908 SND_SOC_DAPM_INPUT("MAINMIC"),
909 SND_SOC_DAPM_INPUT("HSMIC"),
910 SND_SOC_DAPM_INPUT("AUXL"),
911 SND_SOC_DAPM_INPUT("CARKITMIC"),
912 /* Right channel inputs */
913 SND_SOC_DAPM_INPUT("SUBMIC"),
914 SND_SOC_DAPM_INPUT("AUXR"),
915 /* Digital microphones (Stereo) */
916 SND_SOC_DAPM_INPUT("DIGIMIC0"),
917 SND_SOC_DAPM_INPUT("DIGIMIC1"),
918
919 /* Outputs */
cc17557e
SS		 920 SND_SOC_DAPM_OUTPUT("OUTL"),
921 SND_SOC_DAPM_OUTPUT("OUTR"),
5e98a464 922 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 923 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
924 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 925 SND_SOC_DAPM_OUTPUT("HSOL"),
926 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 927 SND_SOC_DAPM_OUTPUT("CARKITL"),
928 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 929 SND_SOC_DAPM_OUTPUT("HFL"),
930 SND_SOC_DAPM_OUTPUT("HFR"),
cc17557e 931
53b5047d 932 /* DACs */
1e5fa31f 933 SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
7393958f 934 SND_SOC_NOPM, 0, 0),
1e5fa31f 935 SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
7393958f 936 SND_SOC_NOPM, 0, 0),
1e5fa31f 937 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
7393958f 938 SND_SOC_NOPM, 0, 0),
1e5fa31f 939 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
7393958f 940 SND_SOC_NOPM, 0, 0),
cc17557e 941
44c55870
PU		 942 /* Analog PGAs */
943 SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
944 0, 0, NULL, 0),
945 SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
946 0, 0, NULL, 0),
947 SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
948 0, 0, NULL, 0),
949 SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
950 0, 0, NULL, 0),
951
7393958f
PU		 952 /* Analog bypasses */
953 SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
954 &twl4030_dapm_abypassr1_control, bypass_event,
955 SND_SOC_DAPM_POST_REG),
956 SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
957 &twl4030_dapm_abypassl1_control,
958 bypass_event, SND_SOC_DAPM_POST_REG),
959 SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
960 &twl4030_dapm_abypassr2_control,
961 bypass_event, SND_SOC_DAPM_POST_REG),
962 SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
963 &twl4030_dapm_abypassl2_control,
964 bypass_event, SND_SOC_DAPM_POST_REG),
965
6bab83fd
PU		 966 /* Digital bypasses */
967 SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
968 &twl4030_dapm_dbypassl_control, bypass_event,
969 SND_SOC_DAPM_POST_REG),
970 SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
971 &twl4030_dapm_dbypassr_control, bypass_event,
972 SND_SOC_DAPM_POST_REG),
973
7393958f
PU		 974 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
975 0, 0, NULL, 0),
976 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
977 1, 0, NULL, 0),
978 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
979 2, 0, NULL, 0),
980 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
981 3, 0, NULL, 0),
982
5e98a464
PU		 983 /* Output MUX controls */
984 /* Earpiece */
2f423577
PU		 985 SND_SOC_DAPM_VALUE_MUX("Earpiece Mux", SND_SOC_NOPM, 0, 0,
986 &twl4030_dapm_earpiece_control),
2a6f5c58 987 /* PreDrivL/R */
2f423577
PU		 988 SND_SOC_DAPM_VALUE_MUX("PredriveL Mux", SND_SOC_NOPM, 0, 0,
989 &twl4030_dapm_predrivel_control),
990 SND_SOC_DAPM_VALUE_MUX("PredriveR Mux", SND_SOC_NOPM, 0, 0,
991 &twl4030_dapm_predriver_control),
dfad21a2 992 /* HeadsetL/R */
aad749e5
PU		 993 SND_SOC_DAPM_MUX_E("HeadsetL Mux", SND_SOC_NOPM, 0, 0,
994 &twl4030_dapm_hsol_control, headsetl_event,
995 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
dfad21a2
PU		 996 SND_SOC_DAPM_MUX("HeadsetR Mux", SND_SOC_NOPM, 0, 0,
997 &twl4030_dapm_hsor_control),
5152d8c2
PU		 998 /* CarkitL/R */
999 SND_SOC_DAPM_MUX("CarkitL Mux", SND_SOC_NOPM, 0, 0,
1000 &twl4030_dapm_carkitl_control),
1001 SND_SOC_DAPM_MUX("CarkitR Mux", SND_SOC_NOPM, 0, 0,
1002 &twl4030_dapm_carkitr_control),
df339804 1003 /* HandsfreeL/R */
49d92c7d
SM		 1004 SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
1005 &twl4030_dapm_handsfreel_control, handsfree_event,
1006 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1007 SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
1008 &twl4030_dapm_handsfreer_control, handsfree_event,
1009 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5e98a464 1010
276c6222
PU		 1011 /* Introducing four virtual ADC, since TWL4030 have four channel for
1012 capture */
1013 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1014 SND_SOC_NOPM, 0, 0),
1015 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1016 SND_SOC_NOPM, 0, 0),
1017 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1018 SND_SOC_NOPM, 0, 0),
1019 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1020 SND_SOC_NOPM, 0, 0),
1021
1022 /* Analog/Digital mic path selection.
1023 TX1 Left/Right: either analog Left/Right or Digimic0
1024 TX2 Left/Right: either analog Left/Right or Digimic1 */
1025 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1026 &twl4030_dapm_micpathtx1_control, micpath_event,
1027 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1028 SND_SOC_DAPM_POST_REG),
1029 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1030 &twl4030_dapm_micpathtx2_control, micpath_event,
1031 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1032 SND_SOC_DAPM_POST_REG),
1033
fb2a2f84 1034 /* Analog input muxes with switch for the capture amplifiers */
2f423577 1035 SND_SOC_DAPM_VALUE_MUX("Analog Left Capture Route",
fb2a2f84 1036 TWL4030_REG_ANAMICL, 4, 0, &twl4030_dapm_analoglmic_control),
2f423577 1037 SND_SOC_DAPM_VALUE_MUX("Analog Right Capture Route",
fb2a2f84 1038 TWL4030_REG_ANAMICR, 4, 0, &twl4030_dapm_analogrmic_control),
276c6222 1039
fb2a2f84
PU		 1040 SND_SOC_DAPM_PGA("ADC Physical Left",
1041 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1042 SND_SOC_DAPM_PGA("ADC Physical Right",
1043 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222
PU		 1044
1045 SND_SOC_DAPM_PGA("Digimic0 Enable",
1046 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1047 SND_SOC_DAPM_PGA("Digimic1 Enable",
1048 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1049
1050 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1051 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1052 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
7393958f 1053
cc17557e
SS		 1054};
1055
1056static const struct snd_soc_dapm_route intercon[] = {
7393958f
PU		 1057 {"Analog L1 Playback Mixer", NULL, "DAC Left1"},
1058 {"Analog R1 Playback Mixer", NULL, "DAC Right1"},
1059 {"Analog L2 Playback Mixer", NULL, "DAC Left2"},
1060 {"Analog R2 Playback Mixer", NULL, "DAC Right2"},
1061
1062 {"ARXL1_APGA", NULL, "Analog L1 Playback Mixer"},
1063 {"ARXR1_APGA", NULL, "Analog R1 Playback Mixer"},
1064 {"ARXL2_APGA", NULL, "Analog L2 Playback Mixer"},
1065 {"ARXR2_APGA", NULL, "Analog R2 Playback Mixer"},
44c55870 1066
5e98a464
PU		 1067 /* Internal playback routings */
1068 /* Earpiece */
1069 {"Earpiece Mux", "DACL1", "ARXL1_APGA"},
1070 {"Earpiece Mux", "DACL2", "ARXL2_APGA"},
1071 {"Earpiece Mux", "DACR1", "ARXR1_APGA"},
2a6f5c58
PU		 1072 /* PreDrivL */
1073 {"PredriveL Mux", "DACL1", "ARXL1_APGA"},
1074 {"PredriveL Mux", "DACL2", "ARXL2_APGA"},
1075 {"PredriveL Mux", "DACR2", "ARXR2_APGA"},
1076 /* PreDrivR */
1077 {"PredriveR Mux", "DACR1", "ARXR1_APGA"},
1078 {"PredriveR Mux", "DACR2", "ARXR2_APGA"},
1079 {"PredriveR Mux", "DACL2", "ARXL2_APGA"},
dfad21a2
PU		 1080 /* HeadsetL */
1081 {"HeadsetL Mux", "DACL1", "ARXL1_APGA"},
1082 {"HeadsetL Mux", "DACL2", "ARXL2_APGA"},
1083 /* HeadsetR */
1084 {"HeadsetR Mux", "DACR1", "ARXR1_APGA"},
1085 {"HeadsetR Mux", "DACR2", "ARXR2_APGA"},
5152d8c2
PU		 1086 /* CarkitL */
1087 {"CarkitL Mux", "DACL1", "ARXL1_APGA"},
1088 {"CarkitL Mux", "DACL2", "ARXL2_APGA"},
1089 /* CarkitR */
1090 {"CarkitR Mux", "DACR1", "ARXR1_APGA"},
1091 {"CarkitR Mux", "DACR2", "ARXR2_APGA"},
df339804
PU		 1092 /* HandsfreeL */
1093 {"HandsfreeL Mux", "DACL1", "ARXL1_APGA"},
1094 {"HandsfreeL Mux", "DACL2", "ARXL2_APGA"},
1095 {"HandsfreeL Mux", "DACR2", "ARXR2_APGA"},
1096 /* HandsfreeR */
1097 {"HandsfreeR Mux", "DACR1", "ARXR1_APGA"},
1098 {"HandsfreeR Mux", "DACR2", "ARXR2_APGA"},
1099 {"HandsfreeR Mux", "DACL2", "ARXL2_APGA"},
5e98a464 1100
cc17557e 1101 /* outputs */
44c55870
PU		 1102 {"OUTL", NULL, "ARXL2_APGA"},
1103 {"OUTR", NULL, "ARXR2_APGA"},
5e98a464 1104 {"EARPIECE", NULL, "Earpiece Mux"},
2a6f5c58
PU		 1105 {"PREDRIVEL", NULL, "PredriveL Mux"},
1106 {"PREDRIVER", NULL, "PredriveR Mux"},
dfad21a2
PU		 1107 {"HSOL", NULL, "HeadsetL Mux"},
1108 {"HSOR", NULL, "HeadsetR Mux"},
5152d8c2
PU		 1109 {"CARKITL", NULL, "CarkitL Mux"},
1110 {"CARKITR", NULL, "CarkitR Mux"},
df339804
PU		 1111 {"HFL", NULL, "HandsfreeL Mux"},
1112 {"HFR", NULL, "HandsfreeR Mux"},
cc17557e 1113
276c6222
PU		 1114 /* Capture path */
1115 {"Analog Left Capture Route", "Main mic", "MAINMIC"},
1116 {"Analog Left Capture Route", "Headset mic", "HSMIC"},
1117 {"Analog Left Capture Route", "AUXL", "AUXL"},
1118 {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
1119
1120 {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
1121 {"Analog Right Capture Route", "AUXR", "AUXR"},
1122
fb2a2f84
PU		 1123 {"ADC Physical Left", NULL, "Analog Left Capture Route"},
1124 {"ADC Physical Right", NULL, "Analog Right Capture Route"},
276c6222
PU		 1125
1126 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1127 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1128
1129 /* TX1 Left capture path */
fb2a2f84 1130 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1131 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1132 /* TX1 Right capture path */
fb2a2f84 1133 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1134 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1135 /* TX2 Left capture path */
fb2a2f84 1136 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1137 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1138 /* TX2 Right capture path */
fb2a2f84 1139 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1140 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1141
1142 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1143 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1144 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1145 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1146
7393958f
PU		 1147 /* Analog bypass routes */
1148 {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
1149 {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
1150 {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
1151 {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
1152
1153 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1154 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1155 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1156 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
1157
6bab83fd
PU		 1158 /* Digital bypass routes */
1159 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1160 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
1161
1162 {"Analog R2 Playback Mixer", NULL, "Right Digital Loopback"},
1163 {"Analog L2 Playback Mixer", NULL, "Left Digital Loopback"},
1164
cc17557e
SS		 1165};
1166
1167static int twl4030_add_widgets(struct snd_soc_codec *codec)
1168{
1169 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1170 ARRAY_SIZE(twl4030_dapm_widgets));
1171
1172 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1173
1174 snd_soc_dapm_new_widgets(codec);
1175 return 0;
1176}
1177
cc17557e
SS		 1178static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1179 enum snd_soc_bias_level level)
1180{
7393958f
PU		 1181 struct twl4030_priv *twl4030 = codec->private_data;
1182
cc17557e
SS		 1183 switch (level) {
1184 case SND_SOC_BIAS_ON:
7393958f 1185 twl4030_codec_mute(codec, 0);
cc17557e
SS		 1186 break;
1187 case SND_SOC_BIAS_PREPARE:
7393958f
PU		 1188 twl4030_power_up(codec);
1189 if (twl4030->bypass_state)
1190 twl4030_codec_mute(codec, 0);
1191 else
1192 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1193 break;
1194 case SND_SOC_BIAS_STANDBY:
7393958f
PU		 1195 twl4030_power_up(codec);
1196 if (twl4030->bypass_state)
1197 twl4030_codec_mute(codec, 0);
1198 else
1199 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1200 break;
1201 case SND_SOC_BIAS_OFF:
1202 twl4030_power_down(codec);
1203 break;
1204 }
1205 codec->bias_level = level;
1206
1207 return 0;
1208}
1209
1210static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1211 struct snd_pcm_hw_params *params,
1212 struct snd_soc_dai *dai)
cc17557e
SS		 1213{
1214 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1215 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1216 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1217 u8 mode, old_mode, format, old_format;
1218
cc17557e
SS		 1219 /* bit rate */
1220 old_mode = twl4030_read_reg_cache(codec,
1221 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1222 mode = old_mode & ~TWL4030_APLL_RATE;
1223
1224 switch (params_rate(params)) {
1225 case 8000:
1226 mode |= TWL4030_APLL_RATE_8000;
1227 break;
1228 case 11025:
1229 mode |= TWL4030_APLL_RATE_11025;
1230 break;
1231 case 12000:
1232 mode |= TWL4030_APLL_RATE_12000;
1233 break;
1234 case 16000:
1235 mode |= TWL4030_APLL_RATE_16000;
1236 break;
1237 case 22050:
1238 mode |= TWL4030_APLL_RATE_22050;
1239 break;
1240 case 24000:
1241 mode |= TWL4030_APLL_RATE_24000;
1242 break;
1243 case 32000:
1244 mode |= TWL4030_APLL_RATE_32000;
1245 break;
1246 case 44100:
1247 mode |= TWL4030_APLL_RATE_44100;
1248 break;
1249 case 48000:
1250 mode |= TWL4030_APLL_RATE_48000;
1251 break;
1252 default:
1253 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1254 params_rate(params));
1255 return -EINVAL;
1256 }
1257
1258 if (mode != old_mode) {
1259 /* change rate and set CODECPDZ */
7393958f 1260 twl4030_codec_enable(codec, 0);
cc17557e 1261 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
db04e2c5 1262 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1263 }
1264
1265 /* sample size */
1266 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1267 format = old_format;
1268 format &= ~TWL4030_DATA_WIDTH;
1269 switch (params_format(params)) {
1270 case SNDRV_PCM_FORMAT_S16_LE:
1271 format |= TWL4030_DATA_WIDTH_16S_16W;
1272 break;
1273 case SNDRV_PCM_FORMAT_S24_LE:
1274 format |= TWL4030_DATA_WIDTH_32S_24W;
1275 break;
1276 default:
1277 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1278 params_format(params));
1279 return -EINVAL;
1280 }
1281
1282 if (format != old_format) {
1283
1284 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1285 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1286
1287 /* change format */
1288 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1289
1290 /* set CODECPDZ afterwards */
db04e2c5 1291 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1292 }
1293 return 0;
1294}
1295
1296static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1297 int clk_id, unsigned int freq, int dir)
1298{
1299 struct snd_soc_codec *codec = codec_dai->codec;
1300 u8 infreq;
1301
1302 switch (freq) {
1303 case 19200000:
1304 infreq = TWL4030_APLL_INFREQ_19200KHZ;
1305 break;
1306 case 26000000:
1307 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1308 break;
1309 case 38400000:
1310 infreq = TWL4030_APLL_INFREQ_38400KHZ;
1311 break;
1312 default:
1313 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1314 freq);
1315 return -EINVAL;
1316 }
1317
1318 infreq |= TWL4030_APLL_EN;
1319 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1320
1321 return 0;
1322}
1323
1324static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1325 unsigned int fmt)
1326{
1327 struct snd_soc_codec *codec = codec_dai->codec;
1328 u8 old_format, format;
1329
1330 /* get format */
1331 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1332 format = old_format;
1333
1334 /* set master/slave audio interface */
1335 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1336 case SND_SOC_DAIFMT_CBM_CFM:
1337 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1338 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1339 break;
1340 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1341 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1342 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1343 break;
1344 default:
1345 return -EINVAL;
1346 }
1347
1348 /* interface format */
1349 format &= ~TWL4030_AIF_FORMAT;
1350 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1351 case SND_SOC_DAIFMT_I2S:
1352 format |= TWL4030_AIF_FORMAT_CODEC;
1353 break;
1354 default:
1355 return -EINVAL;
1356 }
1357
1358 if (format != old_format) {
1359
1360 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1361 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1362
1363 /* change format */
1364 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1365
1366 /* set CODECPDZ afterwards */
db04e2c5 1367 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1368 }
1369
1370 return 0;
1371}
1372
bbba9444 1373#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 1374#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
1375
1376struct snd_soc_dai twl4030_dai = {
1377 .name = "twl4030",
1378 .playback = {
1379 .stream_name = "Playback",
1380 .channels_min = 2,
1381 .channels_max = 2,
1382 .rates = TWL4030_RATES,
1383 .formats = TWL4030_FORMATS,},
1384 .capture = {
1385 .stream_name = "Capture",
1386 .channels_min = 2,
1387 .channels_max = 2,
1388 .rates = TWL4030_RATES,
1389 .formats = TWL4030_FORMATS,},
1390 .ops = {
1391 .hw_params = twl4030_hw_params,
cc17557e
SS		 1392 .set_sysclk = twl4030_set_dai_sysclk,
1393 .set_fmt = twl4030_set_dai_fmt,
1394 }
1395};
1396EXPORT_SYMBOL_GPL(twl4030_dai);
1397
1398static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
1399{
1400 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1401 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1402
1403 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
1404
1405 return 0;
1406}
1407
1408static int twl4030_resume(struct platform_device *pdev)
1409{
1410 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1411 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1412
1413 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1414 twl4030_set_bias_level(codec, codec->suspend_bias_level);
1415 return 0;
1416}
1417
1418/*
1419 * initialize the driver
1420 * register the mixer and dsp interfaces with the kernel
1421 */
1422
1423static int twl4030_init(struct snd_soc_device *socdev)
1424{
6627a653 1425 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1426 int ret = 0;
1427
1428 printk(KERN_INFO "TWL4030 Audio Codec init \n");
1429
1430 codec->name = "twl4030";
1431 codec->owner = THIS_MODULE;
1432 codec->read = twl4030_read_reg_cache;
1433 codec->write = twl4030_write;
1434 codec->set_bias_level = twl4030_set_bias_level;
1435 codec->dai = &twl4030_dai;
1436 codec->num_dai = 1;
1437 codec->reg_cache_size = sizeof(twl4030_reg);
1438 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
1439 GFP_KERNEL);
1440 if (codec->reg_cache == NULL)
1441 return -ENOMEM;
1442
1443 /* register pcms */
1444 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1445 if (ret < 0) {
1446 printk(KERN_ERR "twl4030: failed to create pcms\n");
1447 goto pcm_err;
1448 }
1449
1450 twl4030_init_chip(codec);
1451
1452 /* power on device */
1453 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1454
3e8e1952
IM		 1455 snd_soc_add_controls(codec, twl4030_snd_controls,
1456 ARRAY_SIZE(twl4030_snd_controls));
cc17557e
SS		 1457 twl4030_add_widgets(codec);
1458
968a6025 1459 ret = snd_soc_init_card(socdev);
cc17557e
SS		 1460 if (ret < 0) {
1461 printk(KERN_ERR "twl4030: failed to register card\n");
1462 goto card_err;
1463 }
1464
1465 return ret;
1466
1467card_err:
1468 snd_soc_free_pcms(socdev);
1469 snd_soc_dapm_free(socdev);
1470pcm_err:
1471 kfree(codec->reg_cache);
1472 return ret;
1473}
1474
1475static struct snd_soc_device *twl4030_socdev;
1476
1477static int twl4030_probe(struct platform_device *pdev)
1478{
1479 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1480 struct snd_soc_codec *codec;
7393958f 1481 struct twl4030_priv *twl4030;
cc17557e
SS		 1482
1483 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1484 if (codec == NULL)
1485 return -ENOMEM;
1486
7393958f
PU		 1487 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
1488 if (twl4030 == NULL) {
1489 kfree(codec);
1490 return -ENOMEM;
1491 }
1492
1493 codec->private_data = twl4030;
6627a653 1494 socdev->card->codec = codec;
cc17557e
SS		 1495 mutex_init(&codec->mutex);
1496 INIT_LIST_HEAD(&codec->dapm_widgets);
1497 INIT_LIST_HEAD(&codec->dapm_paths);
1498
1499 twl4030_socdev = socdev;
1500 twl4030_init(socdev);
1501
1502 return 0;
1503}
1504
1505static int twl4030_remove(struct platform_device *pdev)
1506{
1507 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1508 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1509
1510 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
7393958f 1511 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
c6d1662b
PU		 1512 snd_soc_free_pcms(socdev);
1513 snd_soc_dapm_free(socdev);
7393958f 1514 kfree(codec->private_data);
cc17557e
SS		 1515 kfree(codec);
1516
1517 return 0;
1518}
1519
1520struct snd_soc_codec_device soc_codec_dev_twl4030 = {
1521 .probe = twl4030_probe,
1522 .remove = twl4030_remove,
1523 .suspend = twl4030_suspend,
1524 .resume = twl4030_resume,
1525};
1526EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
1527
24e07db8 1528static int __init twl4030_modinit(void)
64089b84
MB		 1529{
1530 return snd_soc_register_dai(&twl4030_dai);
1531}
24e07db8 1532module_init(twl4030_modinit);
64089b84
MB		 1533
1534static void __exit twl4030_exit(void)
1535{
1536 snd_soc_unregister_dai(&twl4030_dai);
1537}
1538module_exit(twl4030_exit);
1539
cc17557e
SS		 1540MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
1541MODULE_AUTHOR("Steve Sakoman");
1542MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)