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Merge branch 'topic/hda' into for-linus
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / tlv320dac33.c
CommitLineData
c8bf93f0
PU		 1/*
2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
3 *
93864cf0 4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
c8bf93f0
PU		 5 *
6 * Copyright: (C) 2009 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/init.h>
27#include <linux/delay.h>
28#include <linux/pm.h>
29#include <linux/i2c.h>
30#include <linux/platform_device.h>
31#include <linux/interrupt.h>
32#include <linux/gpio.h>
3a7aaed7 33#include <linux/regulator/consumer.h>
5a0e3ad6 34#include <linux/slab.h>
c8bf93f0
PU		 35#include <sound/core.h>
36#include <sound/pcm.h>
37#include <sound/pcm_params.h>
38#include <sound/soc.h>
c8bf93f0
PU		 39#include <sound/initval.h>
40#include <sound/tlv.h>
41
42#include <sound/tlv320dac33-plat.h>
43#include "tlv320dac33.h"
44
549675ed
PU		 45/*
46 * The internal FIFO is 24576 bytes long
47 * It can be configured to hold 16bit or 24bit samples
48 * In 16bit configuration the FIFO can hold 6144 stereo samples
49 * In 24bit configuration the FIFO can hold 4096 stereo samples
50 */
51#define DAC33_FIFO_SIZE_16BIT 6144
52#define DAC33_FIFO_SIZE_24BIT 4096
53#define DAC33_MODE7_MARGIN 10 /* Safety margin for FIFO in Mode7 */
4260393e 54
76f47127
PU		 55#define BURST_BASEFREQ_HZ 49152000
56
f57d2cfa
PU		 57#define SAMPLES_TO_US(rate, samples) \
58 (1000000000 / ((rate * 1000) / samples))
59
60#define US_TO_SAMPLES(rate, us) \
d54e1f4f 61 (rate / (1000000 / (us < 1000000 ? us : 1000000)))
f57d2cfa 62
a577b318
PU		 63#define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
64 ((samples * 5000) / ((burstrate * 5000) / (burstrate - playrate)))
65
ad05c03b
PU		 66static void dac33_calculate_times(struct snd_pcm_substream *substream);
67static int dac33_prepare_chip(struct snd_pcm_substream *substream);
f57d2cfa 68
c8bf93f0
PU		 69enum dac33_state {
70 DAC33_IDLE = 0,
71 DAC33_PREFILL,
72 DAC33_PLAYBACK,
73 DAC33_FLUSH,
74};
75
7427b4b9
PU		 76enum dac33_fifo_modes {
77 DAC33_FIFO_BYPASS = 0,
78 DAC33_FIFO_MODE1,
28e05d98 79 DAC33_FIFO_MODE7,
7427b4b9
PU		 80 DAC33_FIFO_LAST_MODE,
81};
82
3a7aaed7
IK		 83#define DAC33_NUM_SUPPLIES 3
84static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
85 "AVDD",
86 "DVDD",
87 "IOVDD",
88};
89
c8bf93f0
PU		 90struct tlv320dac33_priv {
91 struct mutex mutex;
92 struct workqueue_struct *dac33_wq;
93 struct work_struct work;
f0fba2ad 94 struct snd_soc_codec *codec;
3a7aaed7 95 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
0b61d2b9 96 struct snd_pcm_substream *substream;
c8bf93f0
PU		 97 int power_gpio;
98 int chip_power;
99 int irq;
100 unsigned int refclk;
101
102 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
7427b4b9 103 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
549675ed 104 unsigned int fifo_size; /* Size of the FIFO in samples */
c8bf93f0 105 unsigned int nsample; /* burst read amount from host */
f430a27f
PU		 106 int mode1_latency; /* latency caused by the i2c writes in
107 * us */
6aceabb4 108 u8 burst_bclkdiv; /* BCLK divider value in burst mode */
76f47127 109 unsigned int burst_rate; /* Interface speed in Burst modes */
c8bf93f0 110
eeb309a8
PU		 111 int keep_bclk; /* Keep the BCLK continuously running
112 * in FIFO modes */
f57d2cfa
PU		 113 spinlock_t lock;
114 unsigned long long t_stamp1; /* Time stamp for FIFO modes to */
115 unsigned long long t_stamp2; /* calculate the FIFO caused delay */
116
117 unsigned int mode1_us_burst; /* Time to burst read n number of
118 * samples */
119 unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */
c8bf93f0 120
9d7db2b2
PU		 121 unsigned int uthr;
122
c8bf93f0 123 enum dac33_state state;
f0fba2ad
LG		 124 enum snd_soc_control_type control_type;
125 void *control_data;
c8bf93f0
PU		 126};
127
128static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
1290x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
1300x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
1310x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
1320x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
1330x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
1340x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
1350x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
1360x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
1370x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
1380x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
1390x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
1400x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
1410x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
1420x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
1430x00, 0x00, /* 0x38 - 0x39 */
144/* Registers 0x3a - 0x3f are reserved */
145 0x00, 0x00, /* 0x3a - 0x3b */
1460x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
147
1480x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
1490x00, 0x80, /* 0x44 - 0x45 */
150/* Registers 0x46 - 0x47 are reserved */
151 0x80, 0x80, /* 0x46 - 0x47 */
152
1530x80, 0x00, 0x00, /* 0x48 - 0x4a */
154/* Registers 0x4b - 0x7c are reserved */
155 0x00, /* 0x4b */
1560x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
1570x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
1580x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
1590x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
1600x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
1610x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
1620x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
1630x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
1640x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
1650x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
1660x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
1670x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
1680x00, /* 0x7c */
169
170 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
171};
172
173/* Register read and write */
174static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
175 unsigned reg)
176{
177 u8 *cache = codec->reg_cache;
178 if (reg >= DAC33_CACHEREGNUM)
179 return 0;
180
181 return cache[reg];
182}
183
184static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
185 u8 reg, u8 value)
186{
187 u8 *cache = codec->reg_cache;
188 if (reg >= DAC33_CACHEREGNUM)
189 return;
190
191 cache[reg] = value;
192}
193
194static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
195 u8 *value)
196{
b2c812e2 197 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
911a0f0b 198 int val, ret = 0;
c8bf93f0
PU		 199
200 *value = reg & 0xff;
201
202 /* If powered off, return the cached value */
203 if (dac33->chip_power) {
204 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
205 if (val < 0) {
206 dev_err(codec->dev, "Read failed (%d)\n", val);
207 value[0] = dac33_read_reg_cache(codec, reg);
911a0f0b 208 ret = val;
c8bf93f0
PU		 209 } else {
210 value[0] = val;
211 dac33_write_reg_cache(codec, reg, val);
212 }
213 } else {
214 value[0] = dac33_read_reg_cache(codec, reg);
215 }
216
911a0f0b 217 return ret;
c8bf93f0
PU		 218}
219
220static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
221 unsigned int value)
222{
b2c812e2 223 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 224 u8 data[2];
225 int ret = 0;
226
227 /*
228 * data is
229 * D15..D8 dac33 register offset
230 * D7...D0 register data
231 */
232 data[0] = reg & 0xff;
233 data[1] = value & 0xff;
234
235 dac33_write_reg_cache(codec, data[0], data[1]);
236 if (dac33->chip_power) {
237 ret = codec->hw_write(codec->control_data, data, 2);
238 if (ret != 2)
239 dev_err(codec->dev, "Write failed (%d)\n", ret);
240 else
241 ret = 0;
242 }
243
244 return ret;
245}
246
247static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
248 unsigned int value)
249{
b2c812e2 250 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 251 int ret;
252
253 mutex_lock(&dac33->mutex);
254 ret = dac33_write(codec, reg, value);
255 mutex_unlock(&dac33->mutex);
256
257 return ret;
258}
259
260#define DAC33_I2C_ADDR_AUTOINC 0x80
261static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
262 unsigned int value)
263{
b2c812e2 264 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 265 u8 data[3];
266 int ret = 0;
267
268 /*
269 * data is
270 * D23..D16 dac33 register offset
271 * D15..D8 register data MSB
272 * D7...D0 register data LSB
273 */
274 data[0] = reg & 0xff;
275 data[1] = (value >> 8) & 0xff;
276 data[2] = value & 0xff;
277
278 dac33_write_reg_cache(codec, data[0], data[1]);
279 dac33_write_reg_cache(codec, data[0] + 1, data[2]);
280
281 if (dac33->chip_power) {
282 /* We need to set autoincrement mode for 16 bit writes */
283 data[0] |= DAC33_I2C_ADDR_AUTOINC;
284 ret = codec->hw_write(codec->control_data, data, 3);
285 if (ret != 3)
286 dev_err(codec->dev, "Write failed (%d)\n", ret);
287 else
288 ret = 0;
289 }
290
291 return ret;
292}
293
ef909d67 294static void dac33_init_chip(struct snd_soc_codec *codec)
c8bf93f0 295{
b2c812e2 296 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 297
ef909d67 298 if (unlikely(!dac33->chip_power))
c8bf93f0
PU		 299 return;
300
ef909d67
PU		 301 /* A : DAC sample rate Fsref/1.5 */
302 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
303 /* B : DAC src=normal, not muted */
304 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
305 DAC33_DACSRCL_LEFT);
306 /* C : (defaults) */
307 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
308
ef909d67
PU		 309 /* 73 : volume soft stepping control,
310 clock source = internal osc (?) */
311 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
312
ef909d67
PU		 313 /* Restore only selected registers (gains mostly) */
314 dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
315 dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
316 dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
317 dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
318
319 dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
320 dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
321 dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
322 dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
399b82e4
PU		 323
324 dac33_write(codec, DAC33_OUT_AMP_CTRL,
325 dac33_read_reg_cache(codec, DAC33_OUT_AMP_CTRL));
326
56a3536c
PU		 327 dac33_write(codec, DAC33_LDAC_PWR_CTRL,
328 dac33_read_reg_cache(codec, DAC33_LDAC_PWR_CTRL));
329 dac33_write(codec, DAC33_RDAC_PWR_CTRL,
330 dac33_read_reg_cache(codec, DAC33_RDAC_PWR_CTRL));
c8bf93f0
PU		 331}
332
911a0f0b 333static inline int dac33_read_id(struct snd_soc_codec *codec)
239fe55c 334{
911a0f0b 335 int i, ret = 0;
239fe55c
PU		 336 u8 reg;
337
911a0f0b
PU		 338 for (i = 0; i < 3; i++) {
339 ret = dac33_read(codec, DAC33_DEVICE_ID_MSB + i, &reg);
340 if (ret < 0)
341 break;
342 }
343
344 return ret;
c8bf93f0
PU		 345}
346
347static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
348{
349 u8 reg;
350
351 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
352 if (power)
353 reg |= DAC33_PDNALLB;
354 else
c3746a07
PU		 355 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
356 DAC33_DACRPDNB | DAC33_DACLPDNB);
c8bf93f0
PU		 357 dac33_write(codec, DAC33_PWR_CTRL, reg);
358}
359
a6cea965
PU		 360static inline void dac33_disable_digital(struct snd_soc_codec *codec)
361{
362 u8 reg;
363
364 /* Stop the DAI clock */
365 reg = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
366 reg &= ~DAC33_BCLKON;
367 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, reg);
368
369 /* Power down the Oscillator, and DACs */
370 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
371 reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB);
372 dac33_write(codec, DAC33_PWR_CTRL, reg);
373}
374
3a7aaed7 375static int dac33_hard_power(struct snd_soc_codec *codec, int power)
c8bf93f0 376{
b2c812e2 377 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
ad05c03b 378 int ret = 0;
c8bf93f0
PU		 379
380 mutex_lock(&dac33->mutex);
ad05c03b
PU		 381
382 /* Safety check */
383 if (unlikely(power == dac33->chip_power)) {
7fd1d74b 384 dev_dbg(codec->dev, "Trying to set the same power state: %s\n",
ad05c03b
PU		 385 power ? "ON" : "OFF");
386 goto exit;
387 }
388
c8bf93f0 389 if (power) {
3a7aaed7
IK		 390 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
391 dac33->supplies);
392 if (ret != 0) {
393 dev_err(codec->dev,
394 "Failed to enable supplies: %d\n", ret);
395 goto exit;
c8bf93f0 396 }
3a7aaed7
IK		 397
398 if (dac33->power_gpio >= 0)
399 gpio_set_value(dac33->power_gpio, 1);
400
401 dac33->chip_power = 1;
c8bf93f0
PU		 402 } else {
403 dac33_soft_power(codec, 0);
3a7aaed7 404 if (dac33->power_gpio >= 0)
c8bf93f0 405 gpio_set_value(dac33->power_gpio, 0);
3a7aaed7
IK		 406
407 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
408 dac33->supplies);
409 if (ret != 0) {
410 dev_err(codec->dev,
411 "Failed to disable supplies: %d\n", ret);
412 goto exit;
c8bf93f0 413 }
3a7aaed7
IK		 414
415 dac33->chip_power = 0;
c8bf93f0 416 }
c8bf93f0 417
3a7aaed7
IK		 418exit:
419 mutex_unlock(&dac33->mutex);
420 return ret;
c8bf93f0
PU		 421}
422
a6cea965 423static int dac33_playback_event(struct snd_soc_dapm_widget *w,
ad05c03b
PU		 424 struct snd_kcontrol *kcontrol, int event)
425{
426 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec);
427
428 switch (event) {
429 case SND_SOC_DAPM_PRE_PMU:
430 if (likely(dac33->substream)) {
431 dac33_calculate_times(dac33->substream);
432 dac33_prepare_chip(dac33->substream);
433 }
434 break;
a6cea965
PU		 435 case SND_SOC_DAPM_POST_PMD:
436 dac33_disable_digital(w->codec);
437 break;
ad05c03b
PU		 438 }
439 return 0;
440}
441
7427b4b9 442static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 443 struct snd_ctl_elem_value *ucontrol)
444{
445 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 446 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 447
7427b4b9 448 ucontrol->value.integer.value[0] = dac33->fifo_mode;
c8bf93f0
PU		 449
450 return 0;
451}
452
7427b4b9 453static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 454 struct snd_ctl_elem_value *ucontrol)
455{
456 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 457 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 458 int ret = 0;
459
7427b4b9 460 if (dac33->fifo_mode == ucontrol->value.integer.value[0])
c8bf93f0
PU		 461 return 0;
462 /* Do not allow changes while stream is running*/
463 if (codec->active)
464 return -EPERM;
465
466 if (ucontrol->value.integer.value[0] < 0 ||
7427b4b9 467 ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
c8bf93f0
PU		 468 ret = -EINVAL;
469 else
7427b4b9 470 dac33->fifo_mode = ucontrol->value.integer.value[0];
c8bf93f0
PU		 471
472 return ret;
473}
474
7427b4b9
PU		 475/* Codec operation modes */
476static const char *dac33_fifo_mode_texts[] = {
28e05d98 477 "Bypass", "Mode 1", "Mode 7"
7427b4b9
PU		 478};
479
480static const struct soc_enum dac33_fifo_mode_enum =
481 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
482 dac33_fifo_mode_texts);
483
cf4bb698
PU		 484/* L/R Line Output Gain */
485static const char *lr_lineout_gain_texts[] = {
486 "Line -12dB DAC 0dB", "Line -6dB DAC 6dB",
487 "Line 0dB DAC 12dB", "Line 6dB DAC 18dB",
488};
489
490static const struct soc_enum l_lineout_gain_enum =
491 SOC_ENUM_SINGLE(DAC33_LDAC_PWR_CTRL, 0,
492 ARRAY_SIZE(lr_lineout_gain_texts),
493 lr_lineout_gain_texts);
494
495static const struct soc_enum r_lineout_gain_enum =
496 SOC_ENUM_SINGLE(DAC33_RDAC_PWR_CTRL, 0,
497 ARRAY_SIZE(lr_lineout_gain_texts),
498 lr_lineout_gain_texts);
499
c8bf93f0
PU		 500/*
501 * DACL/R digital volume control:
502 * from 0 dB to -63.5 in 0.5 dB steps
503 * Need to be inverted later on:
504 * 0x00 == 0 dB
505 * 0x7f == -63.5 dB
506 */
507static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
508
509static const struct snd_kcontrol_new dac33_snd_controls[] = {
510 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
511 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
512 0, 0x7f, 1, dac_digivol_tlv),
513 SOC_DOUBLE_R("DAC Digital Playback Switch",
514 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
515 SOC_DOUBLE_R("Line to Line Out Volume",
516 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
cf4bb698
PU		 517 SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum),
518 SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum),
c8bf93f0
PU		 519};
520
a577b318
PU		 521static const struct snd_kcontrol_new dac33_mode_snd_controls[] = {
522 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
523 dac33_get_fifo_mode, dac33_set_fifo_mode),
524};
525
c8bf93f0
PU		 526/* Analog bypass */
527static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
528 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
529
530static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
531 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
532
399b82e4
PU		 533/* LOP L/R invert selection */
534static const char *dac33_lr_lom_texts[] = {"DAC", "LOP"};
535
536static const struct soc_enum dac33_left_lom_enum =
537 SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL, 3,
538 ARRAY_SIZE(dac33_lr_lom_texts),
539 dac33_lr_lom_texts);
540
541static const struct snd_kcontrol_new dac33_dapm_left_lom_control =
542SOC_DAPM_ENUM("Route", dac33_left_lom_enum);
543
544static const struct soc_enum dac33_right_lom_enum =
545 SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL, 2,
546 ARRAY_SIZE(dac33_lr_lom_texts),
547 dac33_lr_lom_texts);
548
549static const struct snd_kcontrol_new dac33_dapm_right_lom_control =
550SOC_DAPM_ENUM("Route", dac33_right_lom_enum);
551
c8bf93f0
PU		 552static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
553 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
554 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
555
556 SND_SOC_DAPM_INPUT("LINEL"),
557 SND_SOC_DAPM_INPUT("LINER"),
558
76eac39c
PU		 559 SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0),
560 SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0),
c8bf93f0
PU		 561
562 /* Analog bypass */
563 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
564 &dac33_dapm_abypassl_control),
565 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
566 &dac33_dapm_abypassr_control),
567
399b82e4
PU		 568 SND_SOC_DAPM_MUX("Left LOM Inverted From", SND_SOC_NOPM, 0, 0,
569 &dac33_dapm_left_lom_control),
570 SND_SOC_DAPM_MUX("Right LOM Inverted From", SND_SOC_NOPM, 0, 0,
571 &dac33_dapm_right_lom_control),
572 /*
573 * For DAPM path, when only the anlog bypass path is enabled, and the
574 * LOP inverted from the corresponding DAC side.
575 * This is needed, so we can attach the DAC power supply in this case.
576 */
577 SND_SOC_DAPM_PGA("Left Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
578 SND_SOC_DAPM_PGA("Right Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
579
9e87186f 580 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier",
c8bf93f0 581 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
9e87186f 582 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier",
c8bf93f0 583 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
ad05c03b 584
76eac39c
PU		 585 SND_SOC_DAPM_SUPPLY("Left DAC Power",
586 DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0),
587 SND_SOC_DAPM_SUPPLY("Right DAC Power",
588 DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0),
589
4b8ffdb9
PU		 590 SND_SOC_DAPM_SUPPLY("Codec Power",
591 DAC33_PWR_CTRL, 4, 0, NULL, 0),
592
a6cea965
PU		 593 SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event),
594 SND_SOC_DAPM_POST("Post Playback", dac33_playback_event),
c8bf93f0
PU		 595};
596
597static const struct snd_soc_dapm_route audio_map[] = {
598 /* Analog bypass */
599 {"Analog Left Bypass", "Switch", "LINEL"},
600 {"Analog Right Bypass", "Switch", "LINER"},
601
9e87186f
PU		 602 {"Output Left Amplifier", NULL, "DACL"},
603 {"Output Right Amplifier", NULL, "DACR"},
c8bf93f0 604
399b82e4
PU		 605 {"Left Bypass PGA", NULL, "Analog Left Bypass"},
606 {"Right Bypass PGA", NULL, "Analog Right Bypass"},
607
608 {"Left LOM Inverted From", "DAC", "Left Bypass PGA"},
609 {"Right LOM Inverted From", "DAC", "Right Bypass PGA"},
610 {"Left LOM Inverted From", "LOP", "Analog Left Bypass"},
611 {"Right LOM Inverted From", "LOP", "Analog Right Bypass"},
612
613 {"Output Left Amplifier", NULL, "Left LOM Inverted From"},
614 {"Output Right Amplifier", NULL, "Right LOM Inverted From"},
615
616 {"DACL", NULL, "Left DAC Power"},
617 {"DACR", NULL, "Right DAC Power"},
c8bf93f0 618
399b82e4
PU		 619 {"Left Bypass PGA", NULL, "Left DAC Power"},
620 {"Right Bypass PGA", NULL, "Right DAC Power"},
76eac39c 621
c8bf93f0 622 /* output */
9e87186f
PU		 623 {"LEFT_LO", NULL, "Output Left Amplifier"},
624 {"RIGHT_LO", NULL, "Output Right Amplifier"},
4b8ffdb9
PU		 625
626 {"LEFT_LO", NULL, "Codec Power"},
627 {"RIGHT_LO", NULL, "Codec Power"},
c8bf93f0
PU		 628};
629
630static int dac33_add_widgets(struct snd_soc_codec *codec)
631{
ce6120cc 632 struct snd_soc_dapm_context *dapm = &codec->dapm;
c8bf93f0 633
ce6120cc
LG		 634 snd_soc_dapm_new_controls(dapm, dac33_dapm_widgets,
635 ARRAY_SIZE(dac33_dapm_widgets));
c8bf93f0 636 /* set up audio path interconnects */
ce6120cc 637 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
c8bf93f0
PU		 638
639 return 0;
640}
641
642static int dac33_set_bias_level(struct snd_soc_codec *codec,
643 enum snd_soc_bias_level level)
644{
3a7aaed7
IK		 645 int ret;
646
c8bf93f0
PU		 647 switch (level) {
648 case SND_SOC_BIAS_ON:
c8bf93f0
PU		 649 break;
650 case SND_SOC_BIAS_PREPARE:
651 break;
652 case SND_SOC_BIAS_STANDBY:
ce6120cc 653 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
ad05c03b 654 /* Coming from OFF, switch on the codec */
3a7aaed7
IK		 655 ret = dac33_hard_power(codec, 1);
656 if (ret != 0)
657 return ret;
3a7aaed7 658
ad05c03b
PU		 659 dac33_init_chip(codec);
660 }
c8bf93f0
PU		 661 break;
662 case SND_SOC_BIAS_OFF:
2d4cdd6f 663 /* Do not power off, when the codec is already off */
ce6120cc 664 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
2d4cdd6f 665 return 0;
3a7aaed7
IK		 666 ret = dac33_hard_power(codec, 0);
667 if (ret != 0)
668 return ret;
c8bf93f0
PU		 669 break;
670 }
ce6120cc 671 codec->dapm.bias_level = level;
c8bf93f0
PU		 672
673 return 0;
674}
675
d4f102d4
PU		 676static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
677{
f0fba2ad 678 struct snd_soc_codec *codec = dac33->codec;
84eae18c 679 unsigned int delay;
a3b55791 680 unsigned long flags;
d4f102d4
PU		 681
682 switch (dac33->fifo_mode) {
683 case DAC33_FIFO_MODE1:
684 dac33_write16(codec, DAC33_NSAMPLE_MSB,
f430a27f 685 DAC33_THRREG(dac33->nsample));
f57d2cfa
PU		 686
687 /* Take the timestamps */
a3b55791 688 spin_lock_irqsave(&dac33->lock, flags);
f57d2cfa
PU		 689 dac33->t_stamp2 = ktime_to_us(ktime_get());
690 dac33->t_stamp1 = dac33->t_stamp2;
a3b55791 691 spin_unlock_irqrestore(&dac33->lock, flags);
f57d2cfa 692
d4f102d4
PU		 693 dac33_write16(codec, DAC33_PREFILL_MSB,
694 DAC33_THRREG(dac33->alarm_threshold));
f4d59328 695 /* Enable Alarm Threshold IRQ with a delay */
84eae18c
PU		 696 delay = SAMPLES_TO_US(dac33->burst_rate,
697 dac33->alarm_threshold) + 1000;
698 usleep_range(delay, delay + 500);
f4d59328 699 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
d4f102d4 700 break;
28e05d98 701 case DAC33_FIFO_MODE7:
f57d2cfa 702 /* Take the timestamp */
a3b55791 703 spin_lock_irqsave(&dac33->lock, flags);
f57d2cfa
PU		 704 dac33->t_stamp1 = ktime_to_us(ktime_get());
705 /* Move back the timestamp with drain time */
706 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
a3b55791 707 spin_unlock_irqrestore(&dac33->lock, flags);
f57d2cfa 708
28e05d98 709 dac33_write16(codec, DAC33_PREFILL_MSB,
549675ed 710 DAC33_THRREG(DAC33_MODE7_MARGIN));
f57d2cfa
PU		 711
712 /* Enable Upper Threshold IRQ */
713 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
28e05d98 714 break;
d4f102d4
PU		 715 default:
716 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
717 dac33->fifo_mode);
718 break;
719 }
720}
721
722static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
723{
f0fba2ad 724 struct snd_soc_codec *codec = dac33->codec;
a3b55791 725 unsigned long flags;
d4f102d4
PU		 726
727 switch (dac33->fifo_mode) {
728 case DAC33_FIFO_MODE1:
f57d2cfa 729 /* Take the timestamp */
a3b55791 730 spin_lock_irqsave(&dac33->lock, flags);
f57d2cfa 731 dac33->t_stamp2 = ktime_to_us(ktime_get());
a3b55791 732 spin_unlock_irqrestore(&dac33->lock, flags);
f57d2cfa 733
d4f102d4
PU		 734 dac33_write16(codec, DAC33_NSAMPLE_MSB,
735 DAC33_THRREG(dac33->nsample));
736 break;
28e05d98
PU		 737 case DAC33_FIFO_MODE7:
738 /* At the moment we are not using interrupts in mode7 */
739 break;
d4f102d4
PU		 740 default:
741 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
742 dac33->fifo_mode);
743 break;
744 }
745}
746
c8bf93f0
PU		 747static void dac33_work(struct work_struct *work)
748{
749 struct snd_soc_codec *codec;
750 struct tlv320dac33_priv *dac33;
751 u8 reg;
752
753 dac33 = container_of(work, struct tlv320dac33_priv, work);
f0fba2ad 754 codec = dac33->codec;
c8bf93f0
PU		 755
756 mutex_lock(&dac33->mutex);
757 switch (dac33->state) {
758 case DAC33_PREFILL:
759 dac33->state = DAC33_PLAYBACK;
d4f102d4 760 dac33_prefill_handler(dac33);
c8bf93f0
PU		 761 break;
762 case DAC33_PLAYBACK:
d4f102d4 763 dac33_playback_handler(dac33);
c8bf93f0
PU		 764 break;
765 case DAC33_IDLE:
766 break;
767 case DAC33_FLUSH:
768 dac33->state = DAC33_IDLE;
769 /* Mask all interrupts from dac33 */
770 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
771
772 /* flush fifo */
773 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
774 reg |= DAC33_FIFOFLUSH;
775 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
776 break;
777 }
778 mutex_unlock(&dac33->mutex);
779}
780
781static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
782{
783 struct snd_soc_codec *codec = dev;
b2c812e2 784 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
a3b55791 785 unsigned long flags;
c8bf93f0 786
a3b55791 787 spin_lock_irqsave(&dac33->lock, flags);
f57d2cfa 788 dac33->t_stamp1 = ktime_to_us(ktime_get());
a3b55791 789 spin_unlock_irqrestore(&dac33->lock, flags);
c8bf93f0 790
f57d2cfa
PU		 791 /* Do not schedule the workqueue in Mode7 */
792 if (dac33->fifo_mode != DAC33_FIFO_MODE7)
793 queue_work(dac33->dac33_wq, &dac33->work);
c8bf93f0 794
c8bf93f0 795 return IRQ_HANDLED;
c8bf93f0
PU		 796}
797
798static void dac33_oscwait(struct snd_soc_codec *codec)
799{
84eae18c 800 int timeout = 60;
c8bf93f0
PU		 801 u8 reg;
802
803 do {
84eae18c 804 usleep_range(1000, 2000);
c8bf93f0
PU		 805 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
806 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
807 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
808 dev_err(codec->dev,
809 "internal oscillator calibration failed\n");
810}
811
0b61d2b9
PU		 812static int dac33_startup(struct snd_pcm_substream *substream,
813 struct snd_soc_dai *dai)
814{
815 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 816 struct snd_soc_codec *codec = rtd->codec;
0b61d2b9
PU		 817 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
818
819 /* Stream started, save the substream pointer */
820 dac33->substream = substream;
821
0d99d2b0
PU		 822 snd_pcm_hw_constraint_msbits(substream->runtime, 0, 32, 24);
823
0b61d2b9
PU		 824 return 0;
825}
826
827static void dac33_shutdown(struct snd_pcm_substream *substream,
828 struct snd_soc_dai *dai)
829{
830 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 831 struct snd_soc_codec *codec = rtd->codec;
0b61d2b9
PU		 832 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
833
834 dac33->substream = NULL;
835}
836
549675ed
PU		 837#define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \
838 (BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample)
c8bf93f0
PU		 839static int dac33_hw_params(struct snd_pcm_substream *substream,
840 struct snd_pcm_hw_params *params,
841 struct snd_soc_dai *dai)
842{
843 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 844 struct snd_soc_codec *codec = rtd->codec;
549675ed 845 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 846
847 /* Check parameters for validity */
848 switch (params_rate(params)) {
849 case 44100:
850 case 48000:
851 break;
852 default:
853 dev_err(codec->dev, "unsupported rate %d\n",
854 params_rate(params));
855 return -EINVAL;
856 }
857
858 switch (params_format(params)) {
859 case SNDRV_PCM_FORMAT_S16_LE:
549675ed
PU		 860 dac33->fifo_size = DAC33_FIFO_SIZE_16BIT;
861 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 32);
c8bf93f0 862 break;
0d99d2b0
PU		 863 case SNDRV_PCM_FORMAT_S32_LE:
864 dac33->fifo_size = DAC33_FIFO_SIZE_24BIT;
865 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 64);
866 break;
c8bf93f0
PU		 867 default:
868 dev_err(codec->dev, "unsupported format %d\n",
869 params_format(params));
870 return -EINVAL;
871 }
872
873 return 0;
874}
875
876#define CALC_OSCSET(rate, refclk) ( \
7833ae0e 877 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
c8bf93f0
PU		 878#define CALC_RATIOSET(rate, refclk) ( \
879 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
880
881/*
882 * tlv320dac33 is strict on the sequence of the register writes, if the register
883 * writes happens in different order, than dac33 might end up in unknown state.
884 * Use the known, working sequence of register writes to initialize the dac33.
885 */
886static int dac33_prepare_chip(struct snd_pcm_substream *substream)
887{
888 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 889 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 890 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 891 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
aec242dc 892 u8 aictrl_a, aictrl_b, fifoctrl_a;
c8bf93f0
PU		 893
894 switch (substream->runtime->rate) {
895 case 44100:
896 case 48000:
897 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
898 ratioset = CALC_RATIOSET(substream->runtime->rate,
899 dac33->refclk);
900 break;
901 default:
902 dev_err(codec->dev, "unsupported rate %d\n",
903 substream->runtime->rate);
904 return -EINVAL;
905 }
906
907
908 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
909 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
e5e878c1 910 /* Read FIFO control A, and clear FIFO flush bit */
c8bf93f0 911 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
e5e878c1
PU		 912 fifoctrl_a &= ~DAC33_FIFOFLUSH;
913
c8bf93f0
PU		 914 fifoctrl_a &= ~DAC33_WIDTH;
915 switch (substream->runtime->format) {
916 case SNDRV_PCM_FORMAT_S16_LE:
917 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
918 fifoctrl_a |= DAC33_WIDTH;
919 break;
0d99d2b0
PU		 920 case SNDRV_PCM_FORMAT_S32_LE:
921 aictrl_a |= (DAC33_NCYCL_32 | DAC33_WLEN_24);
922 break;
c8bf93f0
PU		 923 default:
924 dev_err(codec->dev, "unsupported format %d\n",
925 substream->runtime->format);
926 return -EINVAL;
927 }
928
929 mutex_lock(&dac33->mutex);
ad05c03b
PU		 930
931 if (!dac33->chip_power) {
932 /*
933 * Chip is not powered yet.
934 * Do the init in the dac33_set_bias_level later.
935 */
936 mutex_unlock(&dac33->mutex);
937 return 0;
938 }
939
c3746a07 940 dac33_soft_power(codec, 0);
c8bf93f0
PU		 941 dac33_soft_power(codec, 1);
942
943 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
944 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
945
946 /* Write registers 0x08 and 0x09 (MSB, LSB) */
947 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
948
82a58a8b
PU		 949 /* OSC calibration time */
950 dac33_write(codec, DAC33_CALIB_TIME, 96);
c8bf93f0
PU		 951
952 /* adjustment treshold & step */
953 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
954 DAC33_ADJSTEP(1));
955
956 /* div=4 / gain=1 / div */
957 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
958
959 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
960 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
961 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
962
963 dac33_oscwait(codec);
964
7427b4b9 965 if (dac33->fifo_mode) {
aec242dc 966 /* Generic for all FIFO modes */
c8bf93f0 967 /* 50-51 : ASRC Control registers */
fdb6b1e1 968 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
c8bf93f0
PU		 969 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
970
971 /* Write registers 0x34 and 0x35 (MSB, LSB) */
972 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
973
974 /* Set interrupts to high active */
975 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
c8bf93f0 976 } else {
aec242dc 977 /* FIFO bypass mode */
c8bf93f0
PU		 978 /* 50-51 : ASRC Control registers */
979 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
980 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
981 }
982
aec242dc
PU		 983 /* Interrupt behaviour configuration */
984 switch (dac33->fifo_mode) {
985 case DAC33_FIFO_MODE1:
986 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
987 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
aec242dc 988 break;
28e05d98 989 case DAC33_FIFO_MODE7:
f57d2cfa
PU		 990 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
991 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
28e05d98 992 break;
aec242dc
PU		 993 default:
994 /* in FIFO bypass mode, the interrupts are not used */
995 break;
996 }
997
998 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
999
1000 switch (dac33->fifo_mode) {
1001 case DAC33_FIFO_MODE1:
1002 /*
1003 * For mode1:
1004 * Disable the FIFO bypass (Enable the use of FIFO)
1005 * Select nSample mode
1006 * BCLK is only running when data is needed by DAC33
1007 */
c8bf93f0 1008 fifoctrl_a &= ~DAC33_FBYPAS;
aec242dc 1009 fifoctrl_a &= ~DAC33_FAUTO;
eeb309a8
PU		 1010 if (dac33->keep_bclk)
1011 aictrl_b |= DAC33_BCLKON;
1012 else
1013 aictrl_b &= ~DAC33_BCLKON;
aec242dc 1014 break;
28e05d98
PU		 1015 case DAC33_FIFO_MODE7:
1016 /*
1017 * For mode1:
1018 * Disable the FIFO bypass (Enable the use of FIFO)
1019 * Select Threshold mode
1020 * BCLK is only running when data is needed by DAC33
1021 */
1022 fifoctrl_a &= ~DAC33_FBYPAS;
1023 fifoctrl_a |= DAC33_FAUTO;
eeb309a8
PU		 1024 if (dac33->keep_bclk)
1025 aictrl_b |= DAC33_BCLKON;
1026 else
1027 aictrl_b &= ~DAC33_BCLKON;
28e05d98 1028 break;
aec242dc
PU		 1029 default:
1030 /*
1031 * For FIFO bypass mode:
1032 * Enable the FIFO bypass (Disable the FIFO use)
25985edc 1033 * Set the BCLK as continuous
aec242dc 1034 */
c8bf93f0 1035 fifoctrl_a |= DAC33_FBYPAS;
aec242dc
PU		 1036 aictrl_b |= DAC33_BCLKON;
1037 break;
1038 }
c8bf93f0 1039
aec242dc 1040 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
c8bf93f0 1041 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
aec242dc 1042 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
c8bf93f0 1043
6aceabb4
PU		 1044 /*
1045 * BCLK divide ratio
1046 * 0: 1.5
1047 * 1: 1
1048 * 2: 2
1049 * ...
1050 * 254: 254
1051 * 255: 255
1052 */
6cd6cede 1053 if (dac33->fifo_mode)
6aceabb4
PU		 1054 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
1055 dac33->burst_bclkdiv);
6cd6cede 1056 else
0d99d2b0
PU		 1057 if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE)
1058 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
1059 else
1060 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 16);
c8bf93f0 1061
6cd6cede
PU		 1062 switch (dac33->fifo_mode) {
1063 case DAC33_FIFO_MODE1:
c8bf93f0
PU		 1064 dac33_write16(codec, DAC33_ATHR_MSB,
1065 DAC33_THRREG(dac33->alarm_threshold));
aec242dc 1066 break;
28e05d98
PU		 1067 case DAC33_FIFO_MODE7:
1068 /*
1069 * Configure the threshold levels, and leave 10 sample space
1070 * at the bottom, and also at the top of the FIFO
1071 */
9d7db2b2 1072 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
549675ed
PU		 1073 dac33_write16(codec, DAC33_LTHR_MSB,
1074 DAC33_THRREG(DAC33_MODE7_MARGIN));
28e05d98 1075 break;
aec242dc 1076 default:
aec242dc 1077 break;
c8bf93f0
PU		 1078 }
1079
1080 mutex_unlock(&dac33->mutex);
1081
1082 return 0;
1083}
1084
1085static void dac33_calculate_times(struct snd_pcm_substream *substream)
1086{
1087 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1088 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 1089 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
f430a27f
PU		 1090 unsigned int period_size = substream->runtime->period_size;
1091 unsigned int rate = substream->runtime->rate;
c8bf93f0
PU		 1092 unsigned int nsample_limit;
1093
55abb59c
PU		 1094 /* In bypass mode we don't need to calculate */
1095 if (!dac33->fifo_mode)
1096 return;
1097
f57d2cfa
PU		 1098 switch (dac33->fifo_mode) {
1099 case DAC33_FIFO_MODE1:
f430a27f
PU		 1100 /* Number of samples under i2c latency */
1101 dac33->alarm_threshold = US_TO_SAMPLES(rate,
1102 dac33->mode1_latency);
549675ed 1103 nsample_limit = dac33->fifo_size - dac33->alarm_threshold;
1bc13b2e 1104
3591f4cd 1105 if (period_size <= dac33->alarm_threshold)
a577b318 1106 /*
3591f4cd
PU		 1107 * Configure nSamaple to number of periods,
1108 * which covers the latency requironment.
a577b318 1109 */
3591f4cd
PU		 1110 dac33->nsample = period_size *
1111 ((dac33->alarm_threshold / period_size) +
1112 (dac33->alarm_threshold % period_size ?
1113 1 : 0));
1114 else if (period_size > nsample_limit)
1115 dac33->nsample = nsample_limit;
1116 else
1117 dac33->nsample = period_size;
f430a27f 1118
f57d2cfa
PU		 1119 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1120 dac33->nsample);
1121 dac33->t_stamp1 = 0;
1122 dac33->t_stamp2 = 0;
1123 break;
1124 case DAC33_FIFO_MODE7:
3591f4cd
PU		 1125 dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate,
1126 dac33->burst_rate) + 9;
549675ed
PU		 1127 if (dac33->uthr > (dac33->fifo_size - DAC33_MODE7_MARGIN))
1128 dac33->uthr = dac33->fifo_size - DAC33_MODE7_MARGIN;
1129 if (dac33->uthr < (DAC33_MODE7_MARGIN + 10))
1130 dac33->uthr = (DAC33_MODE7_MARGIN + 10);
3591f4cd 1131
f57d2cfa 1132 dac33->mode7_us_to_lthr =
9d7db2b2 1133 SAMPLES_TO_US(substream->runtime->rate,
549675ed 1134 dac33->uthr - DAC33_MODE7_MARGIN + 1);
f57d2cfa
PU		 1135 dac33->t_stamp1 = 0;
1136 break;
1137 default:
1138 break;
1139 }
c8bf93f0 1140
c8bf93f0
PU		 1141}
1142
1143static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1144 struct snd_soc_dai *dai)
1145{
1146 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1147 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 1148 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1149 int ret = 0;
1150
1151 switch (cmd) {
1152 case SNDRV_PCM_TRIGGER_START:
1153 case SNDRV_PCM_TRIGGER_RESUME:
1154 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
7427b4b9 1155 if (dac33->fifo_mode) {
c8bf93f0
PU		 1156 dac33->state = DAC33_PREFILL;
1157 queue_work(dac33->dac33_wq, &dac33->work);
1158 }
1159 break;
1160 case SNDRV_PCM_TRIGGER_STOP:
1161 case SNDRV_PCM_TRIGGER_SUSPEND:
1162 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
7427b4b9 1163 if (dac33->fifo_mode) {
c8bf93f0
PU		 1164 dac33->state = DAC33_FLUSH;
1165 queue_work(dac33->dac33_wq, &dac33->work);
1166 }
1167 break;
1168 default:
1169 ret = -EINVAL;
1170 }
1171
1172 return ret;
1173}
1174
f57d2cfa
PU		 1175static snd_pcm_sframes_t dac33_dai_delay(
1176 struct snd_pcm_substream *substream,
1177 struct snd_soc_dai *dai)
1178{
1179 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1180 struct snd_soc_codec *codec = rtd->codec;
f57d2cfa
PU		 1181 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1182 unsigned long long t0, t1, t_now;
9d7db2b2 1183 unsigned int time_delta, uthr;
f57d2cfa
PU		 1184 int samples_out, samples_in, samples;
1185 snd_pcm_sframes_t delay = 0;
a3b55791 1186 unsigned long flags;
f57d2cfa
PU		 1187
1188 switch (dac33->fifo_mode) {
1189 case DAC33_FIFO_BYPASS:
1190 break;
1191 case DAC33_FIFO_MODE1:
a3b55791 1192 spin_lock_irqsave(&dac33->lock, flags);
f57d2cfa
PU		 1193 t0 = dac33->t_stamp1;
1194 t1 = dac33->t_stamp2;
a3b55791 1195 spin_unlock_irqrestore(&dac33->lock, flags);
f57d2cfa
PU		 1196 t_now = ktime_to_us(ktime_get());
1197
1198 /* We have not started to fill the FIFO yet, delay is 0 */
1199 if (!t1)
1200 goto out;
1201
1202 if (t0 > t1) {
1203 /*
1204 * Phase 1:
1205 * After Alarm threshold, and before nSample write
1206 */
1207 time_delta = t_now - t0;
1208 samples_out = time_delta ? US_TO_SAMPLES(
1209 substream->runtime->rate,
1210 time_delta) : 0;
1211
1212 if (likely(dac33->alarm_threshold > samples_out))
1213 delay = dac33->alarm_threshold - samples_out;
1214 else
1215 delay = 0;
1216 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1217 /*
1218 * Phase 2:
1219 * After nSample write (during burst operation)
1220 */
1221 time_delta = t_now - t0;
1222 samples_out = time_delta ? US_TO_SAMPLES(
1223 substream->runtime->rate,
1224 time_delta) : 0;
1225
1226 time_delta = t_now - t1;
1227 samples_in = time_delta ? US_TO_SAMPLES(
1228 dac33->burst_rate,
1229 time_delta) : 0;
1230
1231 samples = dac33->alarm_threshold;
1232 samples += (samples_in - samples_out);
1233
1234 if (likely(samples > 0))
1235 delay = samples;
1236 else
1237 delay = 0;
1238 } else {
1239 /*
1240 * Phase 3:
1241 * After burst operation, before next alarm threshold
1242 */
1243 time_delta = t_now - t0;
1244 samples_out = time_delta ? US_TO_SAMPLES(
1245 substream->runtime->rate,
1246 time_delta) : 0;
1247
1248 samples_in = dac33->nsample;
1249 samples = dac33->alarm_threshold;
1250 samples += (samples_in - samples_out);
1251
1252 if (likely(samples > 0))
549675ed
PU		 1253 delay = samples > dac33->fifo_size ?
1254 dac33->fifo_size : samples;
f57d2cfa
PU		 1255 else
1256 delay = 0;
1257 }
1258 break;
1259 case DAC33_FIFO_MODE7:
a3b55791 1260 spin_lock_irqsave(&dac33->lock, flags);
f57d2cfa 1261 t0 = dac33->t_stamp1;
9d7db2b2 1262 uthr = dac33->uthr;
a3b55791 1263 spin_unlock_irqrestore(&dac33->lock, flags);
f57d2cfa
PU		 1264 t_now = ktime_to_us(ktime_get());
1265
1266 /* We have not started to fill the FIFO yet, delay is 0 */
1267 if (!t0)
1268 goto out;
1269
1270 if (t_now <= t0) {
1271 /*
1272 * Either the timestamps are messed or equal. Report
1273 * maximum delay
1274 */
9d7db2b2 1275 delay = uthr;
f57d2cfa
PU		 1276 goto out;
1277 }
1278
1279 time_delta = t_now - t0;
1280 if (time_delta <= dac33->mode7_us_to_lthr) {
1281 /*
1282 * Phase 1:
1283 * After burst (draining phase)
1284 */
1285 samples_out = US_TO_SAMPLES(
1286 substream->runtime->rate,
1287 time_delta);
1288
9d7db2b2
PU		 1289 if (likely(uthr > samples_out))
1290 delay = uthr - samples_out;
f57d2cfa
PU		 1291 else
1292 delay = 0;
1293 } else {
1294 /*
1295 * Phase 2:
1296 * During burst operation
1297 */
1298 time_delta = time_delta - dac33->mode7_us_to_lthr;
1299
1300 samples_out = US_TO_SAMPLES(
1301 substream->runtime->rate,
1302 time_delta);
1303 samples_in = US_TO_SAMPLES(
1304 dac33->burst_rate,
1305 time_delta);
549675ed 1306 delay = DAC33_MODE7_MARGIN + samples_in - samples_out;
f57d2cfa 1307
9d7db2b2
PU		 1308 if (unlikely(delay > uthr))
1309 delay = uthr;
f57d2cfa
PU		 1310 }
1311 break;
1312 default:
1313 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1314 dac33->fifo_mode);
1315 break;
1316 }
1317out:
1318 return delay;
1319}
1320
c8bf93f0
PU		 1321static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1322 int clk_id, unsigned int freq, int dir)
1323{
1324 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1325 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1326 u8 ioc_reg, asrcb_reg;
1327
1328 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1329 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1330 switch (clk_id) {
1331 case TLV320DAC33_MCLK:
1332 ioc_reg |= DAC33_REFSEL;
1333 asrcb_reg |= DAC33_SRCREFSEL;
1334 break;
1335 case TLV320DAC33_SLEEPCLK:
1336 ioc_reg &= ~DAC33_REFSEL;
1337 asrcb_reg &= ~DAC33_SRCREFSEL;
1338 break;
1339 default:
1340 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1341 break;
1342 }
1343 dac33->refclk = freq;
1344
1345 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1346 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1347
1348 return 0;
1349}
1350
1351static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1352 unsigned int fmt)
1353{
1354 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1355 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1356 u8 aictrl_a, aictrl_b;
1357
1358 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1359 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1360 /* set master/slave audio interface */
1361 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1362 case SND_SOC_DAIFMT_CBM_CFM:
1363 /* Codec Master */
1364 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1365 break;
1366 case SND_SOC_DAIFMT_CBS_CFS:
1367 /* Codec Slave */
adcb8bc0
PU		 1368 if (dac33->fifo_mode) {
1369 dev_err(codec->dev, "FIFO mode requires master mode\n");
1370 return -EINVAL;
1371 } else
1372 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
c8bf93f0
PU		 1373 break;
1374 default:
1375 return -EINVAL;
1376 }
1377
1378 aictrl_a &= ~DAC33_AFMT_MASK;
1379 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1380 case SND_SOC_DAIFMT_I2S:
1381 aictrl_a |= DAC33_AFMT_I2S;
1382 break;
1383 case SND_SOC_DAIFMT_DSP_A:
1384 aictrl_a |= DAC33_AFMT_DSP;
1385 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
44f497b4 1386 aictrl_b |= DAC33_DATA_DELAY(0);
c8bf93f0
PU		 1387 break;
1388 case SND_SOC_DAIFMT_RIGHT_J:
1389 aictrl_a |= DAC33_AFMT_RIGHT_J;
1390 break;
1391 case SND_SOC_DAIFMT_LEFT_J:
1392 aictrl_a |= DAC33_AFMT_LEFT_J;
1393 break;
1394 default:
1395 dev_err(codec->dev, "Unsupported format (%u)\n",
1396 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1397 return -EINVAL;
1398 }
1399
1400 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1401 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1402
1403 return 0;
1404}
1405
f0fba2ad 1406static int dac33_soc_probe(struct snd_soc_codec *codec)
c8bf93f0 1407{
f0fba2ad 1408 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1409 int ret = 0;
1410
f0fba2ad
LG		 1411 codec->control_data = dac33->control_data;
1412 codec->hw_write = (hw_write_t) i2c_master_send;
ce6120cc 1413 codec->dapm.idle_bias_off = 1;
f0fba2ad 1414 dac33->codec = codec;
c8bf93f0 1415
f0fba2ad
LG		 1416 /* Read the tlv320dac33 ID registers */
1417 ret = dac33_hard_power(codec, 1);
1418 if (ret != 0) {
1419 dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
1420 goto err_power;
1421 }
911a0f0b 1422 ret = dac33_read_id(codec);
f0fba2ad 1423 dac33_hard_power(codec, 0);
c8bf93f0 1424
911a0f0b
PU		 1425 if (ret < 0) {
1426 dev_err(codec->dev, "Failed to read chip ID: %d\n", ret);
1427 ret = -ENODEV;
1428 goto err_power;
1429 }
1430
f0fba2ad
LG		 1431 /* Check if the IRQ number is valid and request it */
1432 if (dac33->irq >= 0) {
1433 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1434 IRQF_TRIGGER_RISING | IRQF_DISABLED,
1435 codec->name, codec);
1436 if (ret < 0) {
1437 dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1438 dac33->irq, ret);
1439 dac33->irq = -1;
1440 }
1441 if (dac33->irq != -1) {
1442 /* Setup work queue */
1443 dac33->dac33_wq =
1444 create_singlethread_workqueue("tlv320dac33");
1445 if (dac33->dac33_wq == NULL) {
1446 free_irq(dac33->irq, codec);
1447 return -ENOMEM;
1448 }
1449
1450 INIT_WORK(&dac33->work, dac33_work);
1451 }
c8bf93f0
PU		 1452 }
1453
1454 snd_soc_add_controls(codec, dac33_snd_controls,
1455 ARRAY_SIZE(dac33_snd_controls));
a577b318 1456 /* Only add the FIFO controls, if we have valid IRQ number */
3591f4cd 1457 if (dac33->irq >= 0)
a577b318
PU		 1458 snd_soc_add_controls(codec, dac33_mode_snd_controls,
1459 ARRAY_SIZE(dac33_mode_snd_controls));
3591f4cd 1460
c8bf93f0
PU		 1461 dac33_add_widgets(codec);
1462
f0fba2ad 1463err_power:
c8bf93f0
PU		 1464 return ret;
1465}
1466
f0fba2ad 1467static int dac33_soc_remove(struct snd_soc_codec *codec)
c8bf93f0 1468{
f0fba2ad 1469 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1470
1471 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1472
f0fba2ad
LG		 1473 if (dac33->irq >= 0) {
1474 free_irq(dac33->irq, dac33->codec);
1475 destroy_workqueue(dac33->dac33_wq);
1476 }
c8bf93f0
PU		 1477 return 0;
1478}
1479
f0fba2ad 1480static int dac33_soc_suspend(struct snd_soc_codec *codec, pm_message_t state)
c8bf93f0 1481{
c8bf93f0
PU		 1482 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1483
1484 return 0;
1485}
1486
f0fba2ad 1487static int dac33_soc_resume(struct snd_soc_codec *codec)
c8bf93f0 1488{
c8bf93f0 1489 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
c8bf93f0
PU		 1490
1491 return 0;
1492}
1493
f0fba2ad
LG		 1494static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = {
1495 .read = dac33_read_reg_cache,
1496 .write = dac33_write_locked,
1497 .set_bias_level = dac33_set_bias_level,
1498 .reg_cache_size = ARRAY_SIZE(dac33_reg),
1499 .reg_word_size = sizeof(u8),
1500 .reg_cache_default = dac33_reg,
c8bf93f0
PU		 1501 .probe = dac33_soc_probe,
1502 .remove = dac33_soc_remove,
1503 .suspend = dac33_soc_suspend,
1504 .resume = dac33_soc_resume,
1505};
c8bf93f0
PU		 1506
1507#define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1508 SNDRV_PCM_RATE_48000)
0d99d2b0 1509#define DAC33_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
c8bf93f0
PU		 1510
1511static struct snd_soc_dai_ops dac33_dai_ops = {
0b61d2b9 1512 .startup = dac33_startup,
c8bf93f0
PU		 1513 .shutdown = dac33_shutdown,
1514 .hw_params = dac33_hw_params,
c8bf93f0 1515 .trigger = dac33_pcm_trigger,
f57d2cfa 1516 .delay = dac33_dai_delay,
c8bf93f0
PU		 1517 .set_sysclk = dac33_set_dai_sysclk,
1518 .set_fmt = dac33_set_dai_fmt,
1519};
1520
f0fba2ad
LG		 1521static struct snd_soc_dai_driver dac33_dai = {
1522 .name = "tlv320dac33-hifi",
c8bf93f0
PU		 1523 .playback = {
1524 .stream_name = "Playback",
1525 .channels_min = 2,
1526 .channels_max = 2,
1527 .rates = DAC33_RATES,
1528 .formats = DAC33_FORMATS,},
1529 .ops = &dac33_dai_ops,
1530};
c8bf93f0 1531
735fe4cf
MB		 1532static int __devinit dac33_i2c_probe(struct i2c_client *client,
1533 const struct i2c_device_id *id)
c8bf93f0
PU		 1534{
1535 struct tlv320dac33_platform_data *pdata;
1536 struct tlv320dac33_priv *dac33;
3a7aaed7 1537 int ret, i;
c8bf93f0
PU		 1538
1539 if (client->dev.platform_data == NULL) {
1540 dev_err(&client->dev, "Platform data not set\n");
1541 return -ENODEV;
1542 }
1543 pdata = client->dev.platform_data;
1544
1545 dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1546 if (dac33 == NULL)
1547 return -ENOMEM;
1548
f0fba2ad 1549 dac33->control_data = client;
c8bf93f0 1550 mutex_init(&dac33->mutex);
f57d2cfa 1551 spin_lock_init(&dac33->lock);
c8bf93f0
PU		 1552
1553 i2c_set_clientdata(client, dac33);
1554
1555 dac33->power_gpio = pdata->power_gpio;
6aceabb4 1556 dac33->burst_bclkdiv = pdata->burst_bclkdiv;
eeb309a8 1557 dac33->keep_bclk = pdata->keep_bclk;
f430a27f
PU		 1558 dac33->mode1_latency = pdata->mode1_latency;
1559 if (!dac33->mode1_latency)
1560 dac33->mode1_latency = 10000; /* 10ms */
c8bf93f0 1561 dac33->irq = client->irq;
c8bf93f0 1562 /* Disable FIFO use by default */
7427b4b9 1563 dac33->fifo_mode = DAC33_FIFO_BYPASS;
c8bf93f0 1564
c8bf93f0
PU		 1565 /* Check if the reset GPIO number is valid and request it */
1566 if (dac33->power_gpio >= 0) {
1567 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1568 if (ret < 0) {
f0fba2ad 1569 dev_err(&client->dev,
c8bf93f0
PU		 1570 "Failed to request reset GPIO (%d)\n",
1571 dac33->power_gpio);
f0fba2ad 1572 goto err_gpio;
c8bf93f0
PU		 1573 }
1574 gpio_direction_output(dac33->power_gpio, 0);
c8bf93f0
PU		 1575 }
1576
3a7aaed7
IK		 1577 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1578 dac33->supplies[i].supply = dac33_supply_names[i];
1579
f0fba2ad 1580 ret = regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies),
3a7aaed7
IK		 1581 dac33->supplies);
1582
1583 if (ret != 0) {
f0fba2ad 1584 dev_err(&client->dev, "Failed to request supplies: %d\n", ret);
3a7aaed7
IK		 1585 goto err_get;
1586 }
1587
f0fba2ad
LG		 1588 ret = snd_soc_register_codec(&client->dev,
1589 &soc_codec_dev_tlv320dac33, &dac33_dai, 1);
1590 if (ret < 0)
1591 goto err_register;
c8bf93f0 1592
c8bf93f0 1593 return ret;
f0fba2ad 1594err_register:
3a7aaed7
IK		 1595 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1596err_get:
c8bf93f0
PU		 1597 if (dac33->power_gpio >= 0)
1598 gpio_free(dac33->power_gpio);
f0fba2ad 1599err_gpio:
c8bf93f0 1600 kfree(dac33);
c8bf93f0
PU		 1601 return ret;
1602}
1603
735fe4cf 1604static int __devexit dac33_i2c_remove(struct i2c_client *client)
c8bf93f0 1605{
f0fba2ad 1606 struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client);
239fe55c
PU		 1607
1608 if (unlikely(dac33->chip_power))
f0fba2ad 1609 dac33_hard_power(dac33->codec, 0);
c8bf93f0
PU		 1610
1611 if (dac33->power_gpio >= 0)
1612 gpio_free(dac33->power_gpio);
c8bf93f0 1613
3a7aaed7
IK		 1614 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1615
f0fba2ad 1616 snd_soc_unregister_codec(&client->dev);
c8bf93f0 1617 kfree(dac33);
c8bf93f0
PU		 1618
1619 return 0;
1620}
1621
1622static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1623 {
1624 .name = "tlv320dac33",
1625 .driver_data = 0,
1626 },
1627 { },
1628};
573f26e3 1629MODULE_DEVICE_TABLE(i2c, tlv320dac33_i2c_id);
c8bf93f0
PU		 1630
1631static struct i2c_driver tlv320dac33_i2c_driver = {
1632 .driver = {
f0fba2ad 1633 .name = "tlv320dac33-codec",
c8bf93f0
PU		 1634 .owner = THIS_MODULE,
1635 },
1636 .probe = dac33_i2c_probe,
1637 .remove = __devexit_p(dac33_i2c_remove),
1638 .id_table = tlv320dac33_i2c_id,
1639};
1640
1641static int __init dac33_module_init(void)
1642{
1643 int r;
1644 r = i2c_add_driver(&tlv320dac33_i2c_driver);
1645 if (r < 0) {
1646 printk(KERN_ERR "DAC33: driver registration failed\n");
1647 return r;
1648 }
1649 return 0;
1650}
1651module_init(dac33_module_init);
1652
1653static void __exit dac33_module_exit(void)
1654{
1655 i2c_del_driver(&tlv320dac33_i2c_driver);
1656}
1657module_exit(dac33_module_exit);
1658
1659
1660MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
93864cf0 1661MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
c8bf93f0 1662MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)