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Merge branch 'for-2.6.33' into for-2.6.34
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / tlv320dac33.c
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c8bf93f0
PU		 1/*
2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
3 *
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
5 *
6 * Copyright: (C) 2009 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/init.h>
27#include <linux/delay.h>
28#include <linux/pm.h>
29#include <linux/i2c.h>
30#include <linux/platform_device.h>
31#include <linux/interrupt.h>
32#include <linux/gpio.h>
33#include <sound/core.h>
34#include <sound/pcm.h>
35#include <sound/pcm_params.h>
36#include <sound/soc.h>
37#include <sound/soc-dapm.h>
38#include <sound/initval.h>
39#include <sound/tlv.h>
40
41#include <sound/tlv320dac33-plat.h>
42#include "tlv320dac33.h"
43
44#define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words,
45 * 6144 stereo */
46#define DAC33_BUFFER_SIZE_SAMPLES 6144
47
48#define NSAMPLE_MAX 5700
49
50#define LATENCY_TIME_MS 20
51
52static struct snd_soc_codec *tlv320dac33_codec;
53
54enum dac33_state {
55 DAC33_IDLE = 0,
56 DAC33_PREFILL,
57 DAC33_PLAYBACK,
58 DAC33_FLUSH,
59};
60
61struct tlv320dac33_priv {
62 struct mutex mutex;
63 struct workqueue_struct *dac33_wq;
64 struct work_struct work;
65 struct snd_soc_codec codec;
66 int power_gpio;
67 int chip_power;
68 int irq;
69 unsigned int refclk;
70
71 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
72 unsigned int nsample_min; /* nsample should not be lower than
73 * this */
74 unsigned int nsample_max; /* nsample should not be higher than
75 * this */
76 unsigned int nsample_switch; /* Use FIFO or bypass FIFO switch */
77 unsigned int nsample; /* burst read amount from host */
78
79 enum dac33_state state;
80};
81
82static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
830x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
840x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
850x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
860x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
870x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
880x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
890x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
900x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
910x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
920x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
930x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
940x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
950x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
960x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
970x00, 0x00, /* 0x38 - 0x39 */
98/* Registers 0x3a - 0x3f are reserved */
99 0x00, 0x00, /* 0x3a - 0x3b */
1000x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
101
1020x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
1030x00, 0x80, /* 0x44 - 0x45 */
104/* Registers 0x46 - 0x47 are reserved */
105 0x80, 0x80, /* 0x46 - 0x47 */
106
1070x80, 0x00, 0x00, /* 0x48 - 0x4a */
108/* Registers 0x4b - 0x7c are reserved */
109 0x00, /* 0x4b */
1100x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
1110x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
1120x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
1130x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
1140x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
1150x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
1160x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
1170x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
1180x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
1190x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
1200x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
1210x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
1220x00, /* 0x7c */
123
124 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
125};
126
127/* Register read and write */
128static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
129 unsigned reg)
130{
131 u8 *cache = codec->reg_cache;
132 if (reg >= DAC33_CACHEREGNUM)
133 return 0;
134
135 return cache[reg];
136}
137
138static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
139 u8 reg, u8 value)
140{
141 u8 *cache = codec->reg_cache;
142 if (reg >= DAC33_CACHEREGNUM)
143 return;
144
145 cache[reg] = value;
146}
147
148static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
149 u8 *value)
150{
151 struct tlv320dac33_priv *dac33 = codec->private_data;
152 int val;
153
154 *value = reg & 0xff;
155
156 /* If powered off, return the cached value */
157 if (dac33->chip_power) {
158 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
159 if (val < 0) {
160 dev_err(codec->dev, "Read failed (%d)\n", val);
161 value[0] = dac33_read_reg_cache(codec, reg);
162 } else {
163 value[0] = val;
164 dac33_write_reg_cache(codec, reg, val);
165 }
166 } else {
167 value[0] = dac33_read_reg_cache(codec, reg);
168 }
169
170 return 0;
171}
172
173static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
174 unsigned int value)
175{
176 struct tlv320dac33_priv *dac33 = codec->private_data;
177 u8 data[2];
178 int ret = 0;
179
180 /*
181 * data is
182 * D15..D8 dac33 register offset
183 * D7...D0 register data
184 */
185 data[0] = reg & 0xff;
186 data[1] = value & 0xff;
187
188 dac33_write_reg_cache(codec, data[0], data[1]);
189 if (dac33->chip_power) {
190 ret = codec->hw_write(codec->control_data, data, 2);
191 if (ret != 2)
192 dev_err(codec->dev, "Write failed (%d)\n", ret);
193 else
194 ret = 0;
195 }
196
197 return ret;
198}
199
200static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
201 unsigned int value)
202{
203 struct tlv320dac33_priv *dac33 = codec->private_data;
204 int ret;
205
206 mutex_lock(&dac33->mutex);
207 ret = dac33_write(codec, reg, value);
208 mutex_unlock(&dac33->mutex);
209
210 return ret;
211}
212
213#define DAC33_I2C_ADDR_AUTOINC 0x80
214static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
215 unsigned int value)
216{
217 struct tlv320dac33_priv *dac33 = codec->private_data;
218 u8 data[3];
219 int ret = 0;
220
221 /*
222 * data is
223 * D23..D16 dac33 register offset
224 * D15..D8 register data MSB
225 * D7...D0 register data LSB
226 */
227 data[0] = reg & 0xff;
228 data[1] = (value >> 8) & 0xff;
229 data[2] = value & 0xff;
230
231 dac33_write_reg_cache(codec, data[0], data[1]);
232 dac33_write_reg_cache(codec, data[0] + 1, data[2]);
233
234 if (dac33->chip_power) {
235 /* We need to set autoincrement mode for 16 bit writes */
236 data[0] |= DAC33_I2C_ADDR_AUTOINC;
237 ret = codec->hw_write(codec->control_data, data, 3);
238 if (ret != 3)
239 dev_err(codec->dev, "Write failed (%d)\n", ret);
240 else
241 ret = 0;
242 }
243
244 return ret;
245}
246
247static void dac33_restore_regs(struct snd_soc_codec *codec)
248{
249 struct tlv320dac33_priv *dac33 = codec->private_data;
250 u8 *cache = codec->reg_cache;
251 u8 data[2];
252 int i, ret;
253
254 if (!dac33->chip_power)
255 return;
256
257 for (i = DAC33_PWR_CTRL; i <= DAC33_INTP_CTRL_B; i++) {
258 data[0] = i;
259 data[1] = cache[i];
260 /* Skip the read only registers */
261 if ((i >= DAC33_INT_OSC_STATUS &&
262 i <= DAC33_INT_OSC_FREQ_RAT_READ_B) ||
263 (i >= DAC33_FIFO_WPTR_MSB && i <= DAC33_FIFO_IRQ_FLAG) ||
264 i == DAC33_DAC_STATUS_FLAGS ||
265 i == DAC33_SRC_EST_REF_CLK_RATIO_A ||
266 i == DAC33_SRC_EST_REF_CLK_RATIO_B)
267 continue;
268 ret = codec->hw_write(codec->control_data, data, 2);
269 if (ret != 2)
270 dev_err(codec->dev, "Write failed (%d)\n", ret);
271 }
272 for (i = DAC33_LDAC_PWR_CTRL; i <= DAC33_LINEL_TO_LLO_VOL; i++) {
273 data[0] = i;
274 data[1] = cache[i];
275 ret = codec->hw_write(codec->control_data, data, 2);
276 if (ret != 2)
277 dev_err(codec->dev, "Write failed (%d)\n", ret);
278 }
279 for (i = DAC33_LINER_TO_RLO_VOL; i <= DAC33_OSC_TRIM; i++) {
280 data[0] = i;
281 data[1] = cache[i];
282 ret = codec->hw_write(codec->control_data, data, 2);
283 if (ret != 2)
284 dev_err(codec->dev, "Write failed (%d)\n", ret);
285 }
286}
287
288static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
289{
290 u8 reg;
291
292 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
293 if (power)
294 reg |= DAC33_PDNALLB;
295 else
296 reg &= ~DAC33_PDNALLB;
297 dac33_write(codec, DAC33_PWR_CTRL, reg);
298}
299
300static void dac33_hard_power(struct snd_soc_codec *codec, int power)
301{
302 struct tlv320dac33_priv *dac33 = codec->private_data;
303
304 mutex_lock(&dac33->mutex);
305 if (power) {
306 if (dac33->power_gpio >= 0) {
307 gpio_set_value(dac33->power_gpio, 1);
308 dac33->chip_power = 1;
309 /* Restore registers */
310 dac33_restore_regs(codec);
311 }
312 dac33_soft_power(codec, 1);
313 } else {
314 dac33_soft_power(codec, 0);
315 if (dac33->power_gpio >= 0) {
316 gpio_set_value(dac33->power_gpio, 0);
317 dac33->chip_power = 0;
318 }
319 }
320 mutex_unlock(&dac33->mutex);
321
322}
323
324static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
325 struct snd_ctl_elem_value *ucontrol)
326{
327 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
328 struct tlv320dac33_priv *dac33 = codec->private_data;
329
330 ucontrol->value.integer.value[0] = dac33->nsample;
331
332 return 0;
333}
334
335static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
336 struct snd_ctl_elem_value *ucontrol)
337{
338 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
339 struct tlv320dac33_priv *dac33 = codec->private_data;
340 int ret = 0;
341
342 if (dac33->nsample == ucontrol->value.integer.value[0])
343 return 0;
344
345 if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
346 ucontrol->value.integer.value[0] > dac33->nsample_max)
347 ret = -EINVAL;
348 else
349 dac33->nsample = ucontrol->value.integer.value[0];
350
351 return ret;
352}
353
354static int dac33_get_nsample_switch(struct snd_kcontrol *kcontrol,
355 struct snd_ctl_elem_value *ucontrol)
356{
357 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
358 struct tlv320dac33_priv *dac33 = codec->private_data;
359
360 ucontrol->value.integer.value[0] = dac33->nsample_switch;
361
362 return 0;
363}
364
365static int dac33_set_nsample_switch(struct snd_kcontrol *kcontrol,
366 struct snd_ctl_elem_value *ucontrol)
367{
368 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
369 struct tlv320dac33_priv *dac33 = codec->private_data;
370 int ret = 0;
371
372 if (dac33->nsample_switch == ucontrol->value.integer.value[0])
373 return 0;
374 /* Do not allow changes while stream is running*/
375 if (codec->active)
376 return -EPERM;
377
378 if (ucontrol->value.integer.value[0] < 0 ||
379 ucontrol->value.integer.value[0] > 1)
380 ret = -EINVAL;
381 else
382 dac33->nsample_switch = ucontrol->value.integer.value[0];
383
384 return ret;
385}
386
387/*
388 * DACL/R digital volume control:
389 * from 0 dB to -63.5 in 0.5 dB steps
390 * Need to be inverted later on:
391 * 0x00 == 0 dB
392 * 0x7f == -63.5 dB
393 */
394static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
395
396static const struct snd_kcontrol_new dac33_snd_controls[] = {
397 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
398 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
399 0, 0x7f, 1, dac_digivol_tlv),
400 SOC_DOUBLE_R("DAC Digital Playback Switch",
401 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
402 SOC_DOUBLE_R("Line to Line Out Volume",
403 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
404};
405
406static const struct snd_kcontrol_new dac33_nsample_snd_controls[] = {
407 SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
408 dac33_get_nsample, dac33_set_nsample),
409 SOC_SINGLE_EXT("nSample Switch", 0, 0, 1, 0,
410 dac33_get_nsample_switch, dac33_set_nsample_switch),
411};
412
413/* Analog bypass */
414static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
415 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
416
417static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
418 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
419
420static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
421 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
422 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
423
424 SND_SOC_DAPM_INPUT("LINEL"),
425 SND_SOC_DAPM_INPUT("LINER"),
426
427 SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
428 SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
429
430 /* Analog bypass */
431 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
432 &dac33_dapm_abypassl_control),
433 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
434 &dac33_dapm_abypassr_control),
435
436 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
437 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
438 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
439 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
440};
441
442static const struct snd_soc_dapm_route audio_map[] = {
443 /* Analog bypass */
444 {"Analog Left Bypass", "Switch", "LINEL"},
445 {"Analog Right Bypass", "Switch", "LINER"},
446
447 {"Output Left Amp Power", NULL, "DACL"},
448 {"Output Right Amp Power", NULL, "DACR"},
449
450 {"Output Left Amp Power", NULL, "Analog Left Bypass"},
451 {"Output Right Amp Power", NULL, "Analog Right Bypass"},
452
453 /* output */
454 {"LEFT_LO", NULL, "Output Left Amp Power"},
455 {"RIGHT_LO", NULL, "Output Right Amp Power"},
456};
457
458static int dac33_add_widgets(struct snd_soc_codec *codec)
459{
460 snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
461 ARRAY_SIZE(dac33_dapm_widgets));
462
463 /* set up audio path interconnects */
464 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
c8bf93f0
PU		 465
466 return 0;
467}
468
469static int dac33_set_bias_level(struct snd_soc_codec *codec,
470 enum snd_soc_bias_level level)
471{
472 switch (level) {
473 case SND_SOC_BIAS_ON:
474 dac33_soft_power(codec, 1);
475 break;
476 case SND_SOC_BIAS_PREPARE:
477 break;
478 case SND_SOC_BIAS_STANDBY:
479 if (codec->bias_level == SND_SOC_BIAS_OFF)
480 dac33_hard_power(codec, 1);
481 dac33_soft_power(codec, 0);
482 break;
483 case SND_SOC_BIAS_OFF:
484 dac33_hard_power(codec, 0);
485 break;
486 }
487 codec->bias_level = level;
488
489 return 0;
490}
491
492static void dac33_work(struct work_struct *work)
493{
494 struct snd_soc_codec *codec;
495 struct tlv320dac33_priv *dac33;
496 u8 reg;
497
498 dac33 = container_of(work, struct tlv320dac33_priv, work);
499 codec = &dac33->codec;
500
501 mutex_lock(&dac33->mutex);
502 switch (dac33->state) {
503 case DAC33_PREFILL:
504 dac33->state = DAC33_PLAYBACK;
505 dac33_write16(codec, DAC33_NSAMPLE_MSB,
506 DAC33_THRREG(dac33->nsample));
507 dac33_write16(codec, DAC33_PREFILL_MSB,
508 DAC33_THRREG(dac33->alarm_threshold));
509 break;
510 case DAC33_PLAYBACK:
511 dac33_write16(codec, DAC33_NSAMPLE_MSB,
512 DAC33_THRREG(dac33->nsample));
513 break;
514 case DAC33_IDLE:
515 break;
516 case DAC33_FLUSH:
517 dac33->state = DAC33_IDLE;
518 /* Mask all interrupts from dac33 */
519 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
520
521 /* flush fifo */
522 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
523 reg |= DAC33_FIFOFLUSH;
524 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
525 break;
526 }
527 mutex_unlock(&dac33->mutex);
528}
529
530static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
531{
532 struct snd_soc_codec *codec = dev;
533 struct tlv320dac33_priv *dac33 = codec->private_data;
534
535 queue_work(dac33->dac33_wq, &dac33->work);
536
537 return IRQ_HANDLED;
538}
539
540static void dac33_shutdown(struct snd_pcm_substream *substream,
541 struct snd_soc_dai *dai)
542{
543 struct snd_soc_pcm_runtime *rtd = substream->private_data;
544 struct snd_soc_device *socdev = rtd->socdev;
545 struct snd_soc_codec *codec = socdev->card->codec;
546 struct tlv320dac33_priv *dac33 = codec->private_data;
547 unsigned int pwr_ctrl;
548
549 /* Stop pending workqueue */
550 if (dac33->nsample_switch)
551 cancel_work_sync(&dac33->work);
552
553 mutex_lock(&dac33->mutex);
554 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
555 pwr_ctrl &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB);
556 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
557 mutex_unlock(&dac33->mutex);
558}
559
560static void dac33_oscwait(struct snd_soc_codec *codec)
561{
562 int timeout = 20;
563 u8 reg;
564
565 do {
566 msleep(1);
567 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
568 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
569 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
570 dev_err(codec->dev,
571 "internal oscillator calibration failed\n");
572}
573
574static int dac33_hw_params(struct snd_pcm_substream *substream,
575 struct snd_pcm_hw_params *params,
576 struct snd_soc_dai *dai)
577{
578 struct snd_soc_pcm_runtime *rtd = substream->private_data;
579 struct snd_soc_device *socdev = rtd->socdev;
580 struct snd_soc_codec *codec = socdev->card->codec;
581
582 /* Check parameters for validity */
583 switch (params_rate(params)) {
584 case 44100:
585 case 48000:
586 break;
587 default:
588 dev_err(codec->dev, "unsupported rate %d\n",
589 params_rate(params));
590 return -EINVAL;
591 }
592
593 switch (params_format(params)) {
594 case SNDRV_PCM_FORMAT_S16_LE:
595 break;
596 default:
597 dev_err(codec->dev, "unsupported format %d\n",
598 params_format(params));
599 return -EINVAL;
600 }
601
602 return 0;
603}
604
605#define CALC_OSCSET(rate, refclk) ( \
606 ((((rate * 10000) / refclk) * 4096) + 5000) / 10000)
607#define CALC_RATIOSET(rate, refclk) ( \
608 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
609
610/*
611 * tlv320dac33 is strict on the sequence of the register writes, if the register
612 * writes happens in different order, than dac33 might end up in unknown state.
613 * Use the known, working sequence of register writes to initialize the dac33.
614 */
615static int dac33_prepare_chip(struct snd_pcm_substream *substream)
616{
617 struct snd_soc_pcm_runtime *rtd = substream->private_data;
618 struct snd_soc_device *socdev = rtd->socdev;
619 struct snd_soc_codec *codec = socdev->card->codec;
620 struct tlv320dac33_priv *dac33 = codec->private_data;
621 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
622 u8 aictrl_a, fifoctrl_a;
623
624 switch (substream->runtime->rate) {
625 case 44100:
626 case 48000:
627 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
628 ratioset = CALC_RATIOSET(substream->runtime->rate,
629 dac33->refclk);
630 break;
631 default:
632 dev_err(codec->dev, "unsupported rate %d\n",
633 substream->runtime->rate);
634 return -EINVAL;
635 }
636
637
638 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
639 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
640 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
641 fifoctrl_a &= ~DAC33_WIDTH;
642 switch (substream->runtime->format) {
643 case SNDRV_PCM_FORMAT_S16_LE:
644 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
645 fifoctrl_a |= DAC33_WIDTH;
646 break;
647 default:
648 dev_err(codec->dev, "unsupported format %d\n",
649 substream->runtime->format);
650 return -EINVAL;
651 }
652
653 mutex_lock(&dac33->mutex);
654 dac33_soft_power(codec, 1);
655
656 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
657 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
658
659 /* Write registers 0x08 and 0x09 (MSB, LSB) */
660 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
661
662 /* calib time: 128 is a nice number ;) */
663 dac33_write(codec, DAC33_CALIB_TIME, 128);
664
665 /* adjustment treshold & step */
666 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
667 DAC33_ADJSTEP(1));
668
669 /* div=4 / gain=1 / div */
670 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
671
672 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
673 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
674 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
675
676 dac33_oscwait(codec);
677
678 if (dac33->nsample_switch) {
679 /* 50-51 : ASRC Control registers */
680 dac33_write(codec, DAC33_ASRC_CTRL_A, (1 << 4)); /* div=2 */
681 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
682
683 /* Write registers 0x34 and 0x35 (MSB, LSB) */
684 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
685
686 /* Set interrupts to high active */
687 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
688
689 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
690 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
691 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
692 } else {
693 /* 50-51 : ASRC Control registers */
694 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
695 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
696 }
697
698 if (dac33->nsample_switch)
699 fifoctrl_a &= ~DAC33_FBYPAS;
700 else
701 fifoctrl_a |= DAC33_FBYPAS;
702 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
703
704 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
705 reg_tmp = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
706 if (dac33->nsample_switch)
707 reg_tmp &= ~DAC33_BCLKON;
708 else
709 reg_tmp |= DAC33_BCLKON;
710 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, reg_tmp);
711
712 if (dac33->nsample_switch) {
713 /* 20: BCLK divide ratio */
714 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 3);
715
716 dac33_write16(codec, DAC33_ATHR_MSB,
717 DAC33_THRREG(dac33->alarm_threshold));
718 } else {
719 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
720 }
721
722 mutex_unlock(&dac33->mutex);
723
724 return 0;
725}
726
727static void dac33_calculate_times(struct snd_pcm_substream *substream)
728{
729 struct snd_soc_pcm_runtime *rtd = substream->private_data;
730 struct snd_soc_device *socdev = rtd->socdev;
731 struct snd_soc_codec *codec = socdev->card->codec;
732 struct tlv320dac33_priv *dac33 = codec->private_data;
733 unsigned int nsample_limit;
734
735 /* Number of samples (16bit, stereo) in one period */
736 dac33->nsample_min = snd_pcm_lib_period_bytes(substream) / 4;
737
738 /* Number of samples (16bit, stereo) in ALSA buffer */
739 dac33->nsample_max = snd_pcm_lib_buffer_bytes(substream) / 4;
740 /* Subtract one period from the total */
741 dac33->nsample_max -= dac33->nsample_min;
742
743 /* Number of samples for LATENCY_TIME_MS / 2 */
744 dac33->alarm_threshold = substream->runtime->rate /
745 (1000 / (LATENCY_TIME_MS / 2));
746
747 /* Find and fix up the lowest nsmaple limit */
748 nsample_limit = substream->runtime->rate / (1000 / LATENCY_TIME_MS);
749
750 if (dac33->nsample_min < nsample_limit)
751 dac33->nsample_min = nsample_limit;
752
753 if (dac33->nsample < dac33->nsample_min)
754 dac33->nsample = dac33->nsample_min;
755
756 /*
757 * Find and fix up the highest nsmaple limit
758 * In order to not overflow the DAC33 buffer substract the
759 * alarm_threshold value from the size of the DAC33 buffer
760 */
761 nsample_limit = DAC33_BUFFER_SIZE_SAMPLES - dac33->alarm_threshold;
762
763 if (dac33->nsample_max > nsample_limit)
764 dac33->nsample_max = nsample_limit;
765
766 if (dac33->nsample > dac33->nsample_max)
767 dac33->nsample = dac33->nsample_max;
768}
769
770static int dac33_pcm_prepare(struct snd_pcm_substream *substream,
771 struct snd_soc_dai *dai)
772{
773 dac33_calculate_times(substream);
774 dac33_prepare_chip(substream);
775
776 return 0;
777}
778
779static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
780 struct snd_soc_dai *dai)
781{
782 struct snd_soc_pcm_runtime *rtd = substream->private_data;
783 struct snd_soc_device *socdev = rtd->socdev;
784 struct snd_soc_codec *codec = socdev->card->codec;
785 struct tlv320dac33_priv *dac33 = codec->private_data;
786 int ret = 0;
787
788 switch (cmd) {
789 case SNDRV_PCM_TRIGGER_START:
790 case SNDRV_PCM_TRIGGER_RESUME:
791 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
792 if (dac33->nsample_switch) {
793 dac33->state = DAC33_PREFILL;
794 queue_work(dac33->dac33_wq, &dac33->work);
795 }
796 break;
797 case SNDRV_PCM_TRIGGER_STOP:
798 case SNDRV_PCM_TRIGGER_SUSPEND:
799 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
800 if (dac33->nsample_switch) {
801 dac33->state = DAC33_FLUSH;
802 queue_work(dac33->dac33_wq, &dac33->work);
803 }
804 break;
805 default:
806 ret = -EINVAL;
807 }
808
809 return ret;
810}
811
812static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
813 int clk_id, unsigned int freq, int dir)
814{
815 struct snd_soc_codec *codec = codec_dai->codec;
816 struct tlv320dac33_priv *dac33 = codec->private_data;
817 u8 ioc_reg, asrcb_reg;
818
819 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
820 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
821 switch (clk_id) {
822 case TLV320DAC33_MCLK:
823 ioc_reg |= DAC33_REFSEL;
824 asrcb_reg |= DAC33_SRCREFSEL;
825 break;
826 case TLV320DAC33_SLEEPCLK:
827 ioc_reg &= ~DAC33_REFSEL;
828 asrcb_reg &= ~DAC33_SRCREFSEL;
829 break;
830 default:
831 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
832 break;
833 }
834 dac33->refclk = freq;
835
836 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
837 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
838
839 return 0;
840}
841
842static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
843 unsigned int fmt)
844{
845 struct snd_soc_codec *codec = codec_dai->codec;
846 u8 aictrl_a, aictrl_b;
847
848 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
849 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
850 /* set master/slave audio interface */
851 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
852 case SND_SOC_DAIFMT_CBM_CFM:
853 /* Codec Master */
854 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
855 break;
856 case SND_SOC_DAIFMT_CBS_CFS:
857 /* Codec Slave */
858 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
859 break;
860 default:
861 return -EINVAL;
862 }
863
864 aictrl_a &= ~DAC33_AFMT_MASK;
865 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
866 case SND_SOC_DAIFMT_I2S:
867 aictrl_a |= DAC33_AFMT_I2S;
868 break;
869 case SND_SOC_DAIFMT_DSP_A:
870 aictrl_a |= DAC33_AFMT_DSP;
871 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
872 aictrl_b |= DAC33_DATA_DELAY(1); /* 1 bit delay */
873 break;
874 case SND_SOC_DAIFMT_DSP_B:
875 aictrl_a |= DAC33_AFMT_DSP;
876 aictrl_b &= ~DAC33_DATA_DELAY_MASK; /* No delay */
877 break;
878 case SND_SOC_DAIFMT_RIGHT_J:
879 aictrl_a |= DAC33_AFMT_RIGHT_J;
880 break;
881 case SND_SOC_DAIFMT_LEFT_J:
882 aictrl_a |= DAC33_AFMT_LEFT_J;
883 break;
884 default:
885 dev_err(codec->dev, "Unsupported format (%u)\n",
886 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
887 return -EINVAL;
888 }
889
890 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
891 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
892
893 return 0;
894}
895
896static void dac33_init_chip(struct snd_soc_codec *codec)
897{
898 /* 44-46: DAC Control Registers */
899 /* A : DAC sample rate Fsref/1.5 */
900 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(1));
901 /* B : DAC src=normal, not muted */
902 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
903 DAC33_DACSRCL_LEFT);
904 /* C : (defaults) */
905 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
906
907 /* 64-65 : L&R DAC power control
908 Line In -> OUT 1V/V Gain, DAC -> OUT 4V/V Gain*/
909 dac33_write(codec, DAC33_LDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
910 dac33_write(codec, DAC33_RDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
911
912 /* 73 : volume soft stepping control,
913 clock source = internal osc (?) */
914 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
915
916 /* 66 : LOP/LOM Modes */
917 dac33_write(codec, DAC33_OUT_AMP_CM_CTRL, 0xff);
918
919 /* 68 : LOM inverted from LOP */
920 dac33_write(codec, DAC33_OUT_AMP_CTRL, (3<<2));
921
922 dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
923}
924
925static int dac33_soc_probe(struct platform_device *pdev)
926{
927 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
928 struct snd_soc_codec *codec;
929 struct tlv320dac33_priv *dac33;
930 int ret = 0;
931
932 BUG_ON(!tlv320dac33_codec);
933
934 codec = tlv320dac33_codec;
935 socdev->card->codec = codec;
936 dac33 = codec->private_data;
937
938 /* Power up the codec */
939 dac33_hard_power(codec, 1);
940 /* Set default configuration */
941 dac33_init_chip(codec);
942
943 /* register pcms */
944 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
945 if (ret < 0) {
946 dev_err(codec->dev, "failed to create pcms\n");
947 goto pcm_err;
948 }
949
950 snd_soc_add_controls(codec, dac33_snd_controls,
951 ARRAY_SIZE(dac33_snd_controls));
952 /* Only add the nSample controls, if we have valid IRQ number */
953 if (dac33->irq >= 0)
954 snd_soc_add_controls(codec, dac33_nsample_snd_controls,
955 ARRAY_SIZE(dac33_nsample_snd_controls));
956
957 dac33_add_widgets(codec);
958
959 /* power on device */
960 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
961
c8bf93f0 962 return 0;
fe3e78e0 963
c8bf93f0
PU		 964pcm_err:
965 dac33_hard_power(codec, 0);
966 return ret;
967}
968
969static int dac33_soc_remove(struct platform_device *pdev)
970{
971 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
972 struct snd_soc_codec *codec = socdev->card->codec;
973
974 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
975
976 snd_soc_free_pcms(socdev);
977 snd_soc_dapm_free(socdev);
978
979 return 0;
980}
981
982static int dac33_soc_suspend(struct platform_device *pdev, pm_message_t state)
983{
984 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
985 struct snd_soc_codec *codec = socdev->card->codec;
986
987 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
988
989 return 0;
990}
991
992static int dac33_soc_resume(struct platform_device *pdev)
993{
994 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
995 struct snd_soc_codec *codec = socdev->card->codec;
996
997 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
998 dac33_set_bias_level(codec, codec->suspend_bias_level);
999
1000 return 0;
1001}
1002
1003struct snd_soc_codec_device soc_codec_dev_tlv320dac33 = {
1004 .probe = dac33_soc_probe,
1005 .remove = dac33_soc_remove,
1006 .suspend = dac33_soc_suspend,
1007 .resume = dac33_soc_resume,
1008};
1009EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33);
1010
1011#define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1012 SNDRV_PCM_RATE_48000)
1013#define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1014
1015static struct snd_soc_dai_ops dac33_dai_ops = {
1016 .shutdown = dac33_shutdown,
1017 .hw_params = dac33_hw_params,
1018 .prepare = dac33_pcm_prepare,
1019 .trigger = dac33_pcm_trigger,
1020 .set_sysclk = dac33_set_dai_sysclk,
1021 .set_fmt = dac33_set_dai_fmt,
1022};
1023
1024struct snd_soc_dai dac33_dai = {
1025 .name = "tlv320dac33",
1026 .playback = {
1027 .stream_name = "Playback",
1028 .channels_min = 2,
1029 .channels_max = 2,
1030 .rates = DAC33_RATES,
1031 .formats = DAC33_FORMATS,},
1032 .ops = &dac33_dai_ops,
1033};
1034EXPORT_SYMBOL_GPL(dac33_dai);
1035
1036static int dac33_i2c_probe(struct i2c_client *client,
1037 const struct i2c_device_id *id)
1038{
1039 struct tlv320dac33_platform_data *pdata;
1040 struct tlv320dac33_priv *dac33;
1041 struct snd_soc_codec *codec;
1042 int ret = 0;
1043
1044 if (client->dev.platform_data == NULL) {
1045 dev_err(&client->dev, "Platform data not set\n");
1046 return -ENODEV;
1047 }
1048 pdata = client->dev.platform_data;
1049
1050 dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1051 if (dac33 == NULL)
1052 return -ENOMEM;
1053
1054 codec = &dac33->codec;
1055 codec->private_data = dac33;
1056 codec->control_data = client;
1057
1058 mutex_init(&codec->mutex);
1059 mutex_init(&dac33->mutex);
1060 INIT_LIST_HEAD(&codec->dapm_widgets);
1061 INIT_LIST_HEAD(&codec->dapm_paths);
1062
1063 codec->name = "tlv320dac33";
1064 codec->owner = THIS_MODULE;
1065 codec->read = dac33_read_reg_cache;
1066 codec->write = dac33_write_locked;
1067 codec->hw_write = (hw_write_t) i2c_master_send;
1068 codec->bias_level = SND_SOC_BIAS_OFF;
1069 codec->set_bias_level = dac33_set_bias_level;
1070 codec->dai = &dac33_dai;
1071 codec->num_dai = 1;
1072 codec->reg_cache_size = ARRAY_SIZE(dac33_reg);
1073 codec->reg_cache = kmemdup(dac33_reg, ARRAY_SIZE(dac33_reg),
1074 GFP_KERNEL);
1075 if (codec->reg_cache == NULL) {
1076 ret = -ENOMEM;
1077 goto error_reg;
1078 }
1079
1080 i2c_set_clientdata(client, dac33);
1081
1082 dac33->power_gpio = pdata->power_gpio;
1083 dac33->irq = client->irq;
1084 dac33->nsample = NSAMPLE_MAX;
1085 /* Disable FIFO use by default */
1086 dac33->nsample_switch = 0;
1087
1088 tlv320dac33_codec = codec;
1089
1090 codec->dev = &client->dev;
1091 dac33_dai.dev = codec->dev;
1092
1093 /* Check if the reset GPIO number is valid and request it */
1094 if (dac33->power_gpio >= 0) {
1095 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1096 if (ret < 0) {
1097 dev_err(codec->dev,
1098 "Failed to request reset GPIO (%d)\n",
1099 dac33->power_gpio);
1100 snd_soc_unregister_dai(&dac33_dai);
1101 snd_soc_unregister_codec(codec);
1102 goto error_gpio;
1103 }
1104 gpio_direction_output(dac33->power_gpio, 0);
1105 } else {
1106 dac33->chip_power = 1;
1107 }
1108
1109 /* Check if the IRQ number is valid and request it */
1110 if (dac33->irq >= 0) {
1111 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1112 IRQF_TRIGGER_RISING | IRQF_DISABLED,
1113 codec->name, codec);
1114 if (ret < 0) {
1115 dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1116 dac33->irq, ret);
1117 dac33->irq = -1;
1118 }
1119 if (dac33->irq != -1) {
1120 /* Setup work queue */
74ea23aa
PU		 1121 dac33->dac33_wq =
1122 create_singlethread_workqueue("tlv320dac33");
c8bf93f0
PU		 1123 if (dac33->dac33_wq == NULL) {
1124 free_irq(dac33->irq, &dac33->codec);
1125 ret = -ENOMEM;
1126 goto error_wq;
1127 }
1128
1129 INIT_WORK(&dac33->work, dac33_work);
1130 }
1131 }
1132
1133 ret = snd_soc_register_codec(codec);
1134 if (ret != 0) {
1135 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1136 goto error_codec;
1137 }
1138
1139 ret = snd_soc_register_dai(&dac33_dai);
1140 if (ret != 0) {
1141 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1142 snd_soc_unregister_codec(codec);
1143 goto error_codec;
1144 }
1145
1146 /* Shut down the codec for now */
1147 dac33_hard_power(codec, 0);
1148
1149 return ret;
1150
1151error_codec:
1152 if (dac33->irq >= 0) {
1153 free_irq(dac33->irq, &dac33->codec);
1154 destroy_workqueue(dac33->dac33_wq);
1155 }
1156error_wq:
1157 if (dac33->power_gpio >= 0)
1158 gpio_free(dac33->power_gpio);
1159error_gpio:
1160 kfree(codec->reg_cache);
1161error_reg:
1162 tlv320dac33_codec = NULL;
1163 kfree(dac33);
1164
1165 return ret;
1166}
1167
1168static int dac33_i2c_remove(struct i2c_client *client)
1169{
1170 struct tlv320dac33_priv *dac33;
1171
1172 dac33 = i2c_get_clientdata(client);
1173 dac33_hard_power(&dac33->codec, 0);
1174
1175 if (dac33->power_gpio >= 0)
1176 gpio_free(dac33->power_gpio);
1177 if (dac33->irq >= 0)
1178 free_irq(dac33->irq, &dac33->codec);
1179
1180 destroy_workqueue(dac33->dac33_wq);
1181 snd_soc_unregister_dai(&dac33_dai);
1182 snd_soc_unregister_codec(&dac33->codec);
1183 kfree(dac33->codec.reg_cache);
1184 kfree(dac33);
1185 tlv320dac33_codec = NULL;
1186
1187 return 0;
1188}
1189
1190static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1191 {
1192 .name = "tlv320dac33",
1193 .driver_data = 0,
1194 },
1195 { },
1196};
1197
1198static struct i2c_driver tlv320dac33_i2c_driver = {
1199 .driver = {
1200 .name = "tlv320dac33",
1201 .owner = THIS_MODULE,
1202 },
1203 .probe = dac33_i2c_probe,
1204 .remove = __devexit_p(dac33_i2c_remove),
1205 .id_table = tlv320dac33_i2c_id,
1206};
1207
1208static int __init dac33_module_init(void)
1209{
1210 int r;
1211 r = i2c_add_driver(&tlv320dac33_i2c_driver);
1212 if (r < 0) {
1213 printk(KERN_ERR "DAC33: driver registration failed\n");
1214 return r;
1215 }
1216 return 0;
1217}
1218module_init(dac33_module_init);
1219
1220static void __exit dac33_module_exit(void)
1221{
1222 i2c_del_driver(&tlv320dac33_i2c_driver);
1223}
1224module_exit(dac33_module_exit);
1225
1226
1227MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1228MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1229MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)