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ASoC: TWL4030: Capture route DAPM event fix
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / tlv320dac33.c
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c8bf93f0
PU		 1/*
2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
3 *
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
5 *
6 * Copyright: (C) 2009 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/init.h>
27#include <linux/delay.h>
28#include <linux/pm.h>
29#include <linux/i2c.h>
30#include <linux/platform_device.h>
31#include <linux/interrupt.h>
32#include <linux/gpio.h>
3a7aaed7 33#include <linux/regulator/consumer.h>
5a0e3ad6 34#include <linux/slab.h>
c8bf93f0
PU		 35#include <sound/core.h>
36#include <sound/pcm.h>
37#include <sound/pcm_params.h>
38#include <sound/soc.h>
39#include <sound/soc-dapm.h>
40#include <sound/initval.h>
41#include <sound/tlv.h>
42
43#include <sound/tlv320dac33-plat.h>
44#include "tlv320dac33.h"
45
46#define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words,
47 * 6144 stereo */
48#define DAC33_BUFFER_SIZE_SAMPLES 6144
49
50#define NSAMPLE_MAX 5700
51
52#define LATENCY_TIME_MS 20
53
4260393e
PU		 54#define MODE7_LTHR 10
55#define MODE7_UTHR (DAC33_BUFFER_SIZE_SAMPLES - 10)
56
76f47127
PU		 57#define BURST_BASEFREQ_HZ 49152000
58
f57d2cfa
PU		 59#define SAMPLES_TO_US(rate, samples) \
60 (1000000000 / ((rate * 1000) / samples))
61
62#define US_TO_SAMPLES(rate, us) \
63 (rate / (1000000 / us))
64
ad05c03b
PU		 65static void dac33_calculate_times(struct snd_pcm_substream *substream);
66static int dac33_prepare_chip(struct snd_pcm_substream *substream);
f57d2cfa 67
c8bf93f0
PU		 68static struct snd_soc_codec *tlv320dac33_codec;
69
70enum dac33_state {
71 DAC33_IDLE = 0,
72 DAC33_PREFILL,
73 DAC33_PLAYBACK,
74 DAC33_FLUSH,
75};
76
7427b4b9
PU		 77enum dac33_fifo_modes {
78 DAC33_FIFO_BYPASS = 0,
79 DAC33_FIFO_MODE1,
28e05d98 80 DAC33_FIFO_MODE7,
7427b4b9
PU		 81 DAC33_FIFO_LAST_MODE,
82};
83
3a7aaed7
IK		 84#define DAC33_NUM_SUPPLIES 3
85static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
86 "AVDD",
87 "DVDD",
88 "IOVDD",
89};
90
c8bf93f0
PU		 91struct tlv320dac33_priv {
92 struct mutex mutex;
93 struct workqueue_struct *dac33_wq;
94 struct work_struct work;
95 struct snd_soc_codec codec;
3a7aaed7 96 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
0b61d2b9 97 struct snd_pcm_substream *substream;
c8bf93f0
PU		 98 int power_gpio;
99 int chip_power;
100 int irq;
101 unsigned int refclk;
102
103 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
104 unsigned int nsample_min; /* nsample should not be lower than
105 * this */
106 unsigned int nsample_max; /* nsample should not be higher than
107 * this */
7427b4b9 108 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
c8bf93f0 109 unsigned int nsample; /* burst read amount from host */
6aceabb4 110 u8 burst_bclkdiv; /* BCLK divider value in burst mode */
76f47127 111 unsigned int burst_rate; /* Interface speed in Burst modes */
c8bf93f0 112
eeb309a8
PU		 113 int keep_bclk; /* Keep the BCLK continuously running
114 * in FIFO modes */
f57d2cfa
PU		 115 spinlock_t lock;
116 unsigned long long t_stamp1; /* Time stamp for FIFO modes to */
117 unsigned long long t_stamp2; /* calculate the FIFO caused delay */
118
119 unsigned int mode1_us_burst; /* Time to burst read n number of
120 * samples */
121 unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */
c8bf93f0 122
9d7db2b2
PU		 123 unsigned int uthr;
124
c8bf93f0
PU		 125 enum dac33_state state;
126};
127
128static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
1290x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
1300x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
1310x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
1320x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
1330x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
1340x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
1350x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
1360x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
1370x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
1380x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
1390x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
1400x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
1410x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
1420x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
1430x00, 0x00, /* 0x38 - 0x39 */
144/* Registers 0x3a - 0x3f are reserved */
145 0x00, 0x00, /* 0x3a - 0x3b */
1460x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
147
1480x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
1490x00, 0x80, /* 0x44 - 0x45 */
150/* Registers 0x46 - 0x47 are reserved */
151 0x80, 0x80, /* 0x46 - 0x47 */
152
1530x80, 0x00, 0x00, /* 0x48 - 0x4a */
154/* Registers 0x4b - 0x7c are reserved */
155 0x00, /* 0x4b */
1560x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
1570x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
1580x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
1590x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
1600x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
1610x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
1620x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
1630x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
1640x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
1650x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
1660x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
1670x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
1680x00, /* 0x7c */
169
170 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
171};
172
173/* Register read and write */
174static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
175 unsigned reg)
176{
177 u8 *cache = codec->reg_cache;
178 if (reg >= DAC33_CACHEREGNUM)
179 return 0;
180
181 return cache[reg];
182}
183
184static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
185 u8 reg, u8 value)
186{
187 u8 *cache = codec->reg_cache;
188 if (reg >= DAC33_CACHEREGNUM)
189 return;
190
191 cache[reg] = value;
192}
193
194static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
195 u8 *value)
196{
b2c812e2 197 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 198 int val;
199
200 *value = reg & 0xff;
201
202 /* If powered off, return the cached value */
203 if (dac33->chip_power) {
204 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
205 if (val < 0) {
206 dev_err(codec->dev, "Read failed (%d)\n", val);
207 value[0] = dac33_read_reg_cache(codec, reg);
208 } else {
209 value[0] = val;
210 dac33_write_reg_cache(codec, reg, val);
211 }
212 } else {
213 value[0] = dac33_read_reg_cache(codec, reg);
214 }
215
216 return 0;
217}
218
219static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
220 unsigned int value)
221{
b2c812e2 222 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 223 u8 data[2];
224 int ret = 0;
225
226 /*
227 * data is
228 * D15..D8 dac33 register offset
229 * D7...D0 register data
230 */
231 data[0] = reg & 0xff;
232 data[1] = value & 0xff;
233
234 dac33_write_reg_cache(codec, data[0], data[1]);
235 if (dac33->chip_power) {
236 ret = codec->hw_write(codec->control_data, data, 2);
237 if (ret != 2)
238 dev_err(codec->dev, "Write failed (%d)\n", ret);
239 else
240 ret = 0;
241 }
242
243 return ret;
244}
245
246static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
247 unsigned int value)
248{
b2c812e2 249 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 250 int ret;
251
252 mutex_lock(&dac33->mutex);
253 ret = dac33_write(codec, reg, value);
254 mutex_unlock(&dac33->mutex);
255
256 return ret;
257}
258
259#define DAC33_I2C_ADDR_AUTOINC 0x80
260static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
261 unsigned int value)
262{
b2c812e2 263 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 264 u8 data[3];
265 int ret = 0;
266
267 /*
268 * data is
269 * D23..D16 dac33 register offset
270 * D15..D8 register data MSB
271 * D7...D0 register data LSB
272 */
273 data[0] = reg & 0xff;
274 data[1] = (value >> 8) & 0xff;
275 data[2] = value & 0xff;
276
277 dac33_write_reg_cache(codec, data[0], data[1]);
278 dac33_write_reg_cache(codec, data[0] + 1, data[2]);
279
280 if (dac33->chip_power) {
281 /* We need to set autoincrement mode for 16 bit writes */
282 data[0] |= DAC33_I2C_ADDR_AUTOINC;
283 ret = codec->hw_write(codec->control_data, data, 3);
284 if (ret != 3)
285 dev_err(codec->dev, "Write failed (%d)\n", ret);
286 else
287 ret = 0;
288 }
289
290 return ret;
291}
292
ef909d67 293static void dac33_init_chip(struct snd_soc_codec *codec)
c8bf93f0 294{
b2c812e2 295 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 296
ef909d67 297 if (unlikely(!dac33->chip_power))
c8bf93f0
PU		 298 return;
299
ef909d67
PU		 300 /* 44-46: DAC Control Registers */
301 /* A : DAC sample rate Fsref/1.5 */
302 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
303 /* B : DAC src=normal, not muted */
304 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
305 DAC33_DACSRCL_LEFT);
306 /* C : (defaults) */
307 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
308
ef909d67
PU		 309 /* 73 : volume soft stepping control,
310 clock source = internal osc (?) */
311 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
312
ef909d67
PU		 313 dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
314
315 /* Restore only selected registers (gains mostly) */
316 dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
317 dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
318 dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
319 dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
320
321 dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
322 dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
323 dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
324 dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
c8bf93f0
PU		 325}
326
239fe55c
PU		 327static inline void dac33_read_id(struct snd_soc_codec *codec)
328{
329 u8 reg;
330
331 dac33_read(codec, DAC33_DEVICE_ID_MSB, &reg);
332 dac33_read(codec, DAC33_DEVICE_ID_LSB, &reg);
333 dac33_read(codec, DAC33_DEVICE_REV_ID, &reg);
c8bf93f0
PU		 334}
335
336static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
337{
338 u8 reg;
339
340 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
341 if (power)
342 reg |= DAC33_PDNALLB;
343 else
c3746a07
PU		 344 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
345 DAC33_DACRPDNB | DAC33_DACLPDNB);
c8bf93f0
PU		 346 dac33_write(codec, DAC33_PWR_CTRL, reg);
347}
348
3a7aaed7 349static int dac33_hard_power(struct snd_soc_codec *codec, int power)
c8bf93f0 350{
b2c812e2 351 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
ad05c03b 352 int ret = 0;
c8bf93f0
PU		 353
354 mutex_lock(&dac33->mutex);
ad05c03b
PU		 355
356 /* Safety check */
357 if (unlikely(power == dac33->chip_power)) {
7fd1d74b 358 dev_dbg(codec->dev, "Trying to set the same power state: %s\n",
ad05c03b
PU		 359 power ? "ON" : "OFF");
360 goto exit;
361 }
362
c8bf93f0 363 if (power) {
3a7aaed7
IK		 364 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
365 dac33->supplies);
366 if (ret != 0) {
367 dev_err(codec->dev,
368 "Failed to enable supplies: %d\n", ret);
369 goto exit;
c8bf93f0 370 }
3a7aaed7
IK		 371
372 if (dac33->power_gpio >= 0)
373 gpio_set_value(dac33->power_gpio, 1);
374
375 dac33->chip_power = 1;
c8bf93f0
PU		 376 } else {
377 dac33_soft_power(codec, 0);
3a7aaed7 378 if (dac33->power_gpio >= 0)
c8bf93f0 379 gpio_set_value(dac33->power_gpio, 0);
3a7aaed7
IK		 380
381 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
382 dac33->supplies);
383 if (ret != 0) {
384 dev_err(codec->dev,
385 "Failed to disable supplies: %d\n", ret);
386 goto exit;
c8bf93f0 387 }
3a7aaed7
IK		 388
389 dac33->chip_power = 0;
c8bf93f0 390 }
c8bf93f0 391
3a7aaed7
IK		 392exit:
393 mutex_unlock(&dac33->mutex);
394 return ret;
c8bf93f0
PU		 395}
396
ad05c03b
PU		 397static int playback_event(struct snd_soc_dapm_widget *w,
398 struct snd_kcontrol *kcontrol, int event)
399{
400 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec);
401
402 switch (event) {
403 case SND_SOC_DAPM_PRE_PMU:
404 if (likely(dac33->substream)) {
405 dac33_calculate_times(dac33->substream);
406 dac33_prepare_chip(dac33->substream);
407 }
408 break;
409 }
410 return 0;
411}
412
c8bf93f0
PU		 413static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
414 struct snd_ctl_elem_value *ucontrol)
415{
416 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 417 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 418
419 ucontrol->value.integer.value[0] = dac33->nsample;
420
421 return 0;
422}
423
424static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
425 struct snd_ctl_elem_value *ucontrol)
426{
427 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 428 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 429 int ret = 0;
430
431 if (dac33->nsample == ucontrol->value.integer.value[0])
432 return 0;
433
434 if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
f57d2cfa 435 ucontrol->value.integer.value[0] > dac33->nsample_max) {
c8bf93f0 436 ret = -EINVAL;
f57d2cfa 437 } else {
c8bf93f0 438 dac33->nsample = ucontrol->value.integer.value[0];
f57d2cfa
PU		 439 /* Re calculate the burst time */
440 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
441 dac33->nsample);
442 }
c8bf93f0
PU		 443
444 return ret;
445}
446
9d7db2b2
PU		 447static int dac33_get_uthr(struct snd_kcontrol *kcontrol,
448 struct snd_ctl_elem_value *ucontrol)
449{
450 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
451 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
452
453 ucontrol->value.integer.value[0] = dac33->uthr;
454
455 return 0;
456}
457
458static int dac33_set_uthr(struct snd_kcontrol *kcontrol,
459 struct snd_ctl_elem_value *ucontrol)
460{
461 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
462 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
463 int ret = 0;
464
465 if (dac33->substream)
466 return -EBUSY;
467
468 if (dac33->uthr == ucontrol->value.integer.value[0])
469 return 0;
470
471 if (ucontrol->value.integer.value[0] < (MODE7_LTHR + 10) ||
472 ucontrol->value.integer.value[0] > MODE7_UTHR)
473 ret = -EINVAL;
474 else
475 dac33->uthr = ucontrol->value.integer.value[0];
476
477 return ret;
478}
479
7427b4b9 480static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 481 struct snd_ctl_elem_value *ucontrol)
482{
483 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 484 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 485
7427b4b9 486 ucontrol->value.integer.value[0] = dac33->fifo_mode;
c8bf93f0
PU		 487
488 return 0;
489}
490
7427b4b9 491static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 492 struct snd_ctl_elem_value *ucontrol)
493{
494 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 495 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 496 int ret = 0;
497
7427b4b9 498 if (dac33->fifo_mode == ucontrol->value.integer.value[0])
c8bf93f0
PU		 499 return 0;
500 /* Do not allow changes while stream is running*/
501 if (codec->active)
502 return -EPERM;
503
504 if (ucontrol->value.integer.value[0] < 0 ||
7427b4b9 505 ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
c8bf93f0
PU		 506 ret = -EINVAL;
507 else
7427b4b9 508 dac33->fifo_mode = ucontrol->value.integer.value[0];
c8bf93f0
PU		 509
510 return ret;
511}
512
7427b4b9
PU		 513/* Codec operation modes */
514static const char *dac33_fifo_mode_texts[] = {
28e05d98 515 "Bypass", "Mode 1", "Mode 7"
7427b4b9
PU		 516};
517
518static const struct soc_enum dac33_fifo_mode_enum =
519 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
520 dac33_fifo_mode_texts);
521
c8bf93f0
PU		 522/*
523 * DACL/R digital volume control:
524 * from 0 dB to -63.5 in 0.5 dB steps
525 * Need to be inverted later on:
526 * 0x00 == 0 dB
527 * 0x7f == -63.5 dB
528 */
529static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
530
531static const struct snd_kcontrol_new dac33_snd_controls[] = {
532 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
533 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
534 0, 0x7f, 1, dac_digivol_tlv),
535 SOC_DOUBLE_R("DAC Digital Playback Switch",
536 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
537 SOC_DOUBLE_R("Line to Line Out Volume",
538 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
539};
540
541static const struct snd_kcontrol_new dac33_nsample_snd_controls[] = {
542 SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
543 dac33_get_nsample, dac33_set_nsample),
9d7db2b2
PU		 544 SOC_SINGLE_EXT("UTHR", 0, 0, MODE7_UTHR, 0,
545 dac33_get_uthr, dac33_set_uthr),
7427b4b9
PU		 546 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
547 dac33_get_fifo_mode, dac33_set_fifo_mode),
c8bf93f0
PU		 548};
549
550/* Analog bypass */
551static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
552 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
553
554static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
555 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
556
557static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
558 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
559 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
560
561 SND_SOC_DAPM_INPUT("LINEL"),
562 SND_SOC_DAPM_INPUT("LINER"),
563
564 SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
565 SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
566
567 /* Analog bypass */
568 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
569 &dac33_dapm_abypassl_control),
570 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
571 &dac33_dapm_abypassr_control),
572
573 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
574 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
575 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
576 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
ad05c03b
PU		 577
578 SND_SOC_DAPM_PRE("Prepare Playback", playback_event),
c8bf93f0
PU		 579};
580
581static const struct snd_soc_dapm_route audio_map[] = {
582 /* Analog bypass */
583 {"Analog Left Bypass", "Switch", "LINEL"},
584 {"Analog Right Bypass", "Switch", "LINER"},
585
586 {"Output Left Amp Power", NULL, "DACL"},
587 {"Output Right Amp Power", NULL, "DACR"},
588
589 {"Output Left Amp Power", NULL, "Analog Left Bypass"},
590 {"Output Right Amp Power", NULL, "Analog Right Bypass"},
591
592 /* output */
593 {"LEFT_LO", NULL, "Output Left Amp Power"},
594 {"RIGHT_LO", NULL, "Output Right Amp Power"},
595};
596
597static int dac33_add_widgets(struct snd_soc_codec *codec)
598{
599 snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
600 ARRAY_SIZE(dac33_dapm_widgets));
601
602 /* set up audio path interconnects */
603 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
c8bf93f0
PU		 604
605 return 0;
606}
607
608static int dac33_set_bias_level(struct snd_soc_codec *codec,
609 enum snd_soc_bias_level level)
610{
3a7aaed7
IK		 611 int ret;
612
c8bf93f0
PU		 613 switch (level) {
614 case SND_SOC_BIAS_ON:
615 dac33_soft_power(codec, 1);
616 break;
617 case SND_SOC_BIAS_PREPARE:
618 break;
619 case SND_SOC_BIAS_STANDBY:
3a7aaed7 620 if (codec->bias_level == SND_SOC_BIAS_OFF) {
ad05c03b 621 /* Coming from OFF, switch on the codec */
3a7aaed7
IK		 622 ret = dac33_hard_power(codec, 1);
623 if (ret != 0)
624 return ret;
3a7aaed7 625
ad05c03b
PU		 626 dac33_init_chip(codec);
627 }
c8bf93f0
PU		 628 break;
629 case SND_SOC_BIAS_OFF:
2d4cdd6f
PU		 630 /* Do not power off, when the codec is already off */
631 if (codec->bias_level == SND_SOC_BIAS_OFF)
632 return 0;
3a7aaed7
IK		 633 ret = dac33_hard_power(codec, 0);
634 if (ret != 0)
635 return ret;
c8bf93f0
PU		 636 break;
637 }
638 codec->bias_level = level;
639
640 return 0;
641}
642
d4f102d4
PU		 643static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
644{
645 struct snd_soc_codec *codec;
646
647 codec = &dac33->codec;
648
649 switch (dac33->fifo_mode) {
650 case DAC33_FIFO_MODE1:
651 dac33_write16(codec, DAC33_NSAMPLE_MSB,
f4d59328 652 DAC33_THRREG(dac33->nsample + dac33->alarm_threshold));
f57d2cfa
PU		 653
654 /* Take the timestamps */
655 spin_lock_irq(&dac33->lock);
656 dac33->t_stamp2 = ktime_to_us(ktime_get());
657 dac33->t_stamp1 = dac33->t_stamp2;
658 spin_unlock_irq(&dac33->lock);
659
d4f102d4
PU		 660 dac33_write16(codec, DAC33_PREFILL_MSB,
661 DAC33_THRREG(dac33->alarm_threshold));
f4d59328
PU		 662 /* Enable Alarm Threshold IRQ with a delay */
663 udelay(SAMPLES_TO_US(dac33->burst_rate,
664 dac33->alarm_threshold));
665 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
d4f102d4 666 break;
28e05d98 667 case DAC33_FIFO_MODE7:
f57d2cfa
PU		 668 /* Take the timestamp */
669 spin_lock_irq(&dac33->lock);
670 dac33->t_stamp1 = ktime_to_us(ktime_get());
671 /* Move back the timestamp with drain time */
672 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
673 spin_unlock_irq(&dac33->lock);
674
28e05d98 675 dac33_write16(codec, DAC33_PREFILL_MSB,
4260393e 676 DAC33_THRREG(MODE7_LTHR));
f57d2cfa
PU		 677
678 /* Enable Upper Threshold IRQ */
679 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
28e05d98 680 break;
d4f102d4
PU		 681 default:
682 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
683 dac33->fifo_mode);
684 break;
685 }
686}
687
688static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
689{
690 struct snd_soc_codec *codec;
691
692 codec = &dac33->codec;
693
694 switch (dac33->fifo_mode) {
695 case DAC33_FIFO_MODE1:
f57d2cfa
PU		 696 /* Take the timestamp */
697 spin_lock_irq(&dac33->lock);
698 dac33->t_stamp2 = ktime_to_us(ktime_get());
699 spin_unlock_irq(&dac33->lock);
700
d4f102d4
PU		 701 dac33_write16(codec, DAC33_NSAMPLE_MSB,
702 DAC33_THRREG(dac33->nsample));
703 break;
28e05d98
PU		 704 case DAC33_FIFO_MODE7:
705 /* At the moment we are not using interrupts in mode7 */
706 break;
d4f102d4
PU		 707 default:
708 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
709 dac33->fifo_mode);
710 break;
711 }
712}
713
c8bf93f0
PU		 714static void dac33_work(struct work_struct *work)
715{
716 struct snd_soc_codec *codec;
717 struct tlv320dac33_priv *dac33;
718 u8 reg;
719
720 dac33 = container_of(work, struct tlv320dac33_priv, work);
721 codec = &dac33->codec;
722
723 mutex_lock(&dac33->mutex);
724 switch (dac33->state) {
725 case DAC33_PREFILL:
726 dac33->state = DAC33_PLAYBACK;
d4f102d4 727 dac33_prefill_handler(dac33);
c8bf93f0
PU		 728 break;
729 case DAC33_PLAYBACK:
d4f102d4 730 dac33_playback_handler(dac33);
c8bf93f0
PU		 731 break;
732 case DAC33_IDLE:
733 break;
734 case DAC33_FLUSH:
735 dac33->state = DAC33_IDLE;
736 /* Mask all interrupts from dac33 */
737 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
738
739 /* flush fifo */
740 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
741 reg |= DAC33_FIFOFLUSH;
742 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
743 break;
744 }
745 mutex_unlock(&dac33->mutex);
746}
747
748static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
749{
750 struct snd_soc_codec *codec = dev;
b2c812e2 751 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 752
f57d2cfa
PU		 753 spin_lock(&dac33->lock);
754 dac33->t_stamp1 = ktime_to_us(ktime_get());
755 spin_unlock(&dac33->lock);
c8bf93f0 756
f57d2cfa
PU		 757 /* Do not schedule the workqueue in Mode7 */
758 if (dac33->fifo_mode != DAC33_FIFO_MODE7)
759 queue_work(dac33->dac33_wq, &dac33->work);
c8bf93f0 760
c8bf93f0 761 return IRQ_HANDLED;
c8bf93f0
PU		 762}
763
764static void dac33_oscwait(struct snd_soc_codec *codec)
765{
766 int timeout = 20;
767 u8 reg;
768
769 do {
770 msleep(1);
771 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
772 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
773 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
774 dev_err(codec->dev,
775 "internal oscillator calibration failed\n");
776}
777
0b61d2b9
PU		 778static int dac33_startup(struct snd_pcm_substream *substream,
779 struct snd_soc_dai *dai)
780{
781 struct snd_soc_pcm_runtime *rtd = substream->private_data;
782 struct snd_soc_device *socdev = rtd->socdev;
783 struct snd_soc_codec *codec = socdev->card->codec;
784 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
785
786 /* Stream started, save the substream pointer */
787 dac33->substream = substream;
788
789 return 0;
790}
791
792static void dac33_shutdown(struct snd_pcm_substream *substream,
793 struct snd_soc_dai *dai)
794{
795 struct snd_soc_pcm_runtime *rtd = substream->private_data;
796 struct snd_soc_device *socdev = rtd->socdev;
797 struct snd_soc_codec *codec = socdev->card->codec;
798 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
799
800 dac33->substream = NULL;
801}
802
c8bf93f0
PU		 803static int dac33_hw_params(struct snd_pcm_substream *substream,
804 struct snd_pcm_hw_params *params,
805 struct snd_soc_dai *dai)
806{
807 struct snd_soc_pcm_runtime *rtd = substream->private_data;
808 struct snd_soc_device *socdev = rtd->socdev;
809 struct snd_soc_codec *codec = socdev->card->codec;
810
811 /* Check parameters for validity */
812 switch (params_rate(params)) {
813 case 44100:
814 case 48000:
815 break;
816 default:
817 dev_err(codec->dev, "unsupported rate %d\n",
818 params_rate(params));
819 return -EINVAL;
820 }
821
822 switch (params_format(params)) {
823 case SNDRV_PCM_FORMAT_S16_LE:
824 break;
825 default:
826 dev_err(codec->dev, "unsupported format %d\n",
827 params_format(params));
828 return -EINVAL;
829 }
830
831 return 0;
832}
833
834#define CALC_OSCSET(rate, refclk) ( \
7833ae0e 835 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
c8bf93f0
PU		 836#define CALC_RATIOSET(rate, refclk) ( \
837 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
838
839/*
840 * tlv320dac33 is strict on the sequence of the register writes, if the register
841 * writes happens in different order, than dac33 might end up in unknown state.
842 * Use the known, working sequence of register writes to initialize the dac33.
843 */
844static int dac33_prepare_chip(struct snd_pcm_substream *substream)
845{
846 struct snd_soc_pcm_runtime *rtd = substream->private_data;
847 struct snd_soc_device *socdev = rtd->socdev;
848 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 849 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 850 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
aec242dc 851 u8 aictrl_a, aictrl_b, fifoctrl_a;
c8bf93f0
PU		 852
853 switch (substream->runtime->rate) {
854 case 44100:
855 case 48000:
856 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
857 ratioset = CALC_RATIOSET(substream->runtime->rate,
858 dac33->refclk);
859 break;
860 default:
861 dev_err(codec->dev, "unsupported rate %d\n",
862 substream->runtime->rate);
863 return -EINVAL;
864 }
865
866
867 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
868 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
e5e878c1 869 /* Read FIFO control A, and clear FIFO flush bit */
c8bf93f0 870 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
e5e878c1
PU		 871 fifoctrl_a &= ~DAC33_FIFOFLUSH;
872
c8bf93f0
PU		 873 fifoctrl_a &= ~DAC33_WIDTH;
874 switch (substream->runtime->format) {
875 case SNDRV_PCM_FORMAT_S16_LE:
876 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
877 fifoctrl_a |= DAC33_WIDTH;
878 break;
879 default:
880 dev_err(codec->dev, "unsupported format %d\n",
881 substream->runtime->format);
882 return -EINVAL;
883 }
884
885 mutex_lock(&dac33->mutex);
ad05c03b
PU		 886
887 if (!dac33->chip_power) {
888 /*
889 * Chip is not powered yet.
890 * Do the init in the dac33_set_bias_level later.
891 */
892 mutex_unlock(&dac33->mutex);
893 return 0;
894 }
895
c3746a07 896 dac33_soft_power(codec, 0);
c8bf93f0
PU		 897 dac33_soft_power(codec, 1);
898
899 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
900 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
901
902 /* Write registers 0x08 and 0x09 (MSB, LSB) */
903 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
904
905 /* calib time: 128 is a nice number ;) */
906 dac33_write(codec, DAC33_CALIB_TIME, 128);
907
908 /* adjustment treshold & step */
909 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
910 DAC33_ADJSTEP(1));
911
912 /* div=4 / gain=1 / div */
913 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
914
915 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
916 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
917 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
918
919 dac33_oscwait(codec);
920
7427b4b9 921 if (dac33->fifo_mode) {
aec242dc 922 /* Generic for all FIFO modes */
c8bf93f0 923 /* 50-51 : ASRC Control registers */
fdb6b1e1 924 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
c8bf93f0
PU		 925 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
926
927 /* Write registers 0x34 and 0x35 (MSB, LSB) */
928 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
929
930 /* Set interrupts to high active */
931 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
c8bf93f0 932 } else {
aec242dc 933 /* FIFO bypass mode */
c8bf93f0
PU		 934 /* 50-51 : ASRC Control registers */
935 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
936 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
937 }
938
aec242dc
PU		 939 /* Interrupt behaviour configuration */
940 switch (dac33->fifo_mode) {
941 case DAC33_FIFO_MODE1:
942 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
943 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
aec242dc 944 break;
28e05d98 945 case DAC33_FIFO_MODE7:
f57d2cfa
PU		 946 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
947 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
28e05d98 948 break;
aec242dc
PU		 949 default:
950 /* in FIFO bypass mode, the interrupts are not used */
951 break;
952 }
953
954 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
955
956 switch (dac33->fifo_mode) {
957 case DAC33_FIFO_MODE1:
958 /*
959 * For mode1:
960 * Disable the FIFO bypass (Enable the use of FIFO)
961 * Select nSample mode
962 * BCLK is only running when data is needed by DAC33
963 */
c8bf93f0 964 fifoctrl_a &= ~DAC33_FBYPAS;
aec242dc 965 fifoctrl_a &= ~DAC33_FAUTO;
eeb309a8
PU		 966 if (dac33->keep_bclk)
967 aictrl_b |= DAC33_BCLKON;
968 else
969 aictrl_b &= ~DAC33_BCLKON;
aec242dc 970 break;
28e05d98
PU		 971 case DAC33_FIFO_MODE7:
972 /*
973 * For mode1:
974 * Disable the FIFO bypass (Enable the use of FIFO)
975 * Select Threshold mode
976 * BCLK is only running when data is needed by DAC33
977 */
978 fifoctrl_a &= ~DAC33_FBYPAS;
979 fifoctrl_a |= DAC33_FAUTO;
eeb309a8
PU		 980 if (dac33->keep_bclk)
981 aictrl_b |= DAC33_BCLKON;
982 else
983 aictrl_b &= ~DAC33_BCLKON;
28e05d98 984 break;
aec242dc
PU		 985 default:
986 /*
987 * For FIFO bypass mode:
988 * Enable the FIFO bypass (Disable the FIFO use)
989 * Set the BCLK as continous
990 */
c8bf93f0 991 fifoctrl_a |= DAC33_FBYPAS;
aec242dc
PU		 992 aictrl_b |= DAC33_BCLKON;
993 break;
994 }
c8bf93f0 995
aec242dc 996 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
c8bf93f0 997 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
aec242dc 998 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
c8bf93f0 999
6aceabb4
PU		 1000 /*
1001 * BCLK divide ratio
1002 * 0: 1.5
1003 * 1: 1
1004 * 2: 2
1005 * ...
1006 * 254: 254
1007 * 255: 255
1008 */
6cd6cede 1009 if (dac33->fifo_mode)
6aceabb4
PU		 1010 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
1011 dac33->burst_bclkdiv);
6cd6cede
PU		 1012 else
1013 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
c8bf93f0 1014
6cd6cede
PU		 1015 switch (dac33->fifo_mode) {
1016 case DAC33_FIFO_MODE1:
c8bf93f0
PU		 1017 dac33_write16(codec, DAC33_ATHR_MSB,
1018 DAC33_THRREG(dac33->alarm_threshold));
aec242dc 1019 break;
28e05d98
PU		 1020 case DAC33_FIFO_MODE7:
1021 /*
1022 * Configure the threshold levels, and leave 10 sample space
1023 * at the bottom, and also at the top of the FIFO
1024 */
9d7db2b2 1025 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
4260393e 1026 dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR));
28e05d98 1027 break;
aec242dc 1028 default:
aec242dc 1029 break;
c8bf93f0
PU		 1030 }
1031
1032 mutex_unlock(&dac33->mutex);
1033
1034 return 0;
1035}
1036
1037static void dac33_calculate_times(struct snd_pcm_substream *substream)
1038{
1039 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1040 struct snd_soc_device *socdev = rtd->socdev;
1041 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 1042 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1043 unsigned int nsample_limit;
1044
55abb59c
PU		 1045 /* In bypass mode we don't need to calculate */
1046 if (!dac33->fifo_mode)
1047 return;
1048
c8bf93f0
PU		 1049 /* Number of samples (16bit, stereo) in one period */
1050 dac33->nsample_min = snd_pcm_lib_period_bytes(substream) / 4;
1051
1052 /* Number of samples (16bit, stereo) in ALSA buffer */
1053 dac33->nsample_max = snd_pcm_lib_buffer_bytes(substream) / 4;
1054 /* Subtract one period from the total */
1055 dac33->nsample_max -= dac33->nsample_min;
1056
1057 /* Number of samples for LATENCY_TIME_MS / 2 */
1058 dac33->alarm_threshold = substream->runtime->rate /
1059 (1000 / (LATENCY_TIME_MS / 2));
1060
1061 /* Find and fix up the lowest nsmaple limit */
1062 nsample_limit = substream->runtime->rate / (1000 / LATENCY_TIME_MS);
1063
1064 if (dac33->nsample_min < nsample_limit)
1065 dac33->nsample_min = nsample_limit;
1066
1067 if (dac33->nsample < dac33->nsample_min)
1068 dac33->nsample = dac33->nsample_min;
1069
1070 /*
1071 * Find and fix up the highest nsmaple limit
1072 * In order to not overflow the DAC33 buffer substract the
1073 * alarm_threshold value from the size of the DAC33 buffer
1074 */
1075 nsample_limit = DAC33_BUFFER_SIZE_SAMPLES - dac33->alarm_threshold;
1076
1077 if (dac33->nsample_max > nsample_limit)
1078 dac33->nsample_max = nsample_limit;
1079
1080 if (dac33->nsample > dac33->nsample_max)
1081 dac33->nsample = dac33->nsample_max;
c8bf93f0 1082
f57d2cfa
PU		 1083 switch (dac33->fifo_mode) {
1084 case DAC33_FIFO_MODE1:
1085 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1086 dac33->nsample);
1087 dac33->t_stamp1 = 0;
1088 dac33->t_stamp2 = 0;
1089 break;
1090 case DAC33_FIFO_MODE7:
1091 dac33->mode7_us_to_lthr =
9d7db2b2
PU		 1092 SAMPLES_TO_US(substream->runtime->rate,
1093 dac33->uthr - MODE7_LTHR + 1);
f57d2cfa
PU		 1094 dac33->t_stamp1 = 0;
1095 break;
1096 default:
1097 break;
1098 }
c8bf93f0 1099
c8bf93f0
PU		 1100}
1101
1102static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1103 struct snd_soc_dai *dai)
1104{
1105 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1106 struct snd_soc_device *socdev = rtd->socdev;
1107 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 1108 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1109 int ret = 0;
1110
1111 switch (cmd) {
1112 case SNDRV_PCM_TRIGGER_START:
1113 case SNDRV_PCM_TRIGGER_RESUME:
1114 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
7427b4b9 1115 if (dac33->fifo_mode) {
c8bf93f0
PU		 1116 dac33->state = DAC33_PREFILL;
1117 queue_work(dac33->dac33_wq, &dac33->work);
1118 }
1119 break;
1120 case SNDRV_PCM_TRIGGER_STOP:
1121 case SNDRV_PCM_TRIGGER_SUSPEND:
1122 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
7427b4b9 1123 if (dac33->fifo_mode) {
c8bf93f0
PU		 1124 dac33->state = DAC33_FLUSH;
1125 queue_work(dac33->dac33_wq, &dac33->work);
1126 }
1127 break;
1128 default:
1129 ret = -EINVAL;
1130 }
1131
1132 return ret;
1133}
1134
f57d2cfa
PU		 1135static snd_pcm_sframes_t dac33_dai_delay(
1136 struct snd_pcm_substream *substream,
1137 struct snd_soc_dai *dai)
1138{
1139 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1140 struct snd_soc_device *socdev = rtd->socdev;
1141 struct snd_soc_codec *codec = socdev->card->codec;
1142 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1143 unsigned long long t0, t1, t_now;
9d7db2b2 1144 unsigned int time_delta, uthr;
f57d2cfa
PU		 1145 int samples_out, samples_in, samples;
1146 snd_pcm_sframes_t delay = 0;
1147
1148 switch (dac33->fifo_mode) {
1149 case DAC33_FIFO_BYPASS:
1150 break;
1151 case DAC33_FIFO_MODE1:
1152 spin_lock(&dac33->lock);
1153 t0 = dac33->t_stamp1;
1154 t1 = dac33->t_stamp2;
1155 spin_unlock(&dac33->lock);
1156 t_now = ktime_to_us(ktime_get());
1157
1158 /* We have not started to fill the FIFO yet, delay is 0 */
1159 if (!t1)
1160 goto out;
1161
1162 if (t0 > t1) {
1163 /*
1164 * Phase 1:
1165 * After Alarm threshold, and before nSample write
1166 */
1167 time_delta = t_now - t0;
1168 samples_out = time_delta ? US_TO_SAMPLES(
1169 substream->runtime->rate,
1170 time_delta) : 0;
1171
1172 if (likely(dac33->alarm_threshold > samples_out))
1173 delay = dac33->alarm_threshold - samples_out;
1174 else
1175 delay = 0;
1176 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1177 /*
1178 * Phase 2:
1179 * After nSample write (during burst operation)
1180 */
1181 time_delta = t_now - t0;
1182 samples_out = time_delta ? US_TO_SAMPLES(
1183 substream->runtime->rate,
1184 time_delta) : 0;
1185
1186 time_delta = t_now - t1;
1187 samples_in = time_delta ? US_TO_SAMPLES(
1188 dac33->burst_rate,
1189 time_delta) : 0;
1190
1191 samples = dac33->alarm_threshold;
1192 samples += (samples_in - samples_out);
1193
1194 if (likely(samples > 0))
1195 delay = samples;
1196 else
1197 delay = 0;
1198 } else {
1199 /*
1200 * Phase 3:
1201 * After burst operation, before next alarm threshold
1202 */
1203 time_delta = t_now - t0;
1204 samples_out = time_delta ? US_TO_SAMPLES(
1205 substream->runtime->rate,
1206 time_delta) : 0;
1207
1208 samples_in = dac33->nsample;
1209 samples = dac33->alarm_threshold;
1210 samples += (samples_in - samples_out);
1211
1212 if (likely(samples > 0))
1213 delay = samples > DAC33_BUFFER_SIZE_SAMPLES ?
1214 DAC33_BUFFER_SIZE_SAMPLES : samples;
1215 else
1216 delay = 0;
1217 }
1218 break;
1219 case DAC33_FIFO_MODE7:
1220 spin_lock(&dac33->lock);
1221 t0 = dac33->t_stamp1;
9d7db2b2 1222 uthr = dac33->uthr;
f57d2cfa
PU		 1223 spin_unlock(&dac33->lock);
1224 t_now = ktime_to_us(ktime_get());
1225
1226 /* We have not started to fill the FIFO yet, delay is 0 */
1227 if (!t0)
1228 goto out;
1229
1230 if (t_now <= t0) {
1231 /*
1232 * Either the timestamps are messed or equal. Report
1233 * maximum delay
1234 */
9d7db2b2 1235 delay = uthr;
f57d2cfa
PU		 1236 goto out;
1237 }
1238
1239 time_delta = t_now - t0;
1240 if (time_delta <= dac33->mode7_us_to_lthr) {
1241 /*
1242 * Phase 1:
1243 * After burst (draining phase)
1244 */
1245 samples_out = US_TO_SAMPLES(
1246 substream->runtime->rate,
1247 time_delta);
1248
9d7db2b2
PU		 1249 if (likely(uthr > samples_out))
1250 delay = uthr - samples_out;
f57d2cfa
PU		 1251 else
1252 delay = 0;
1253 } else {
1254 /*
1255 * Phase 2:
1256 * During burst operation
1257 */
1258 time_delta = time_delta - dac33->mode7_us_to_lthr;
1259
1260 samples_out = US_TO_SAMPLES(
1261 substream->runtime->rate,
1262 time_delta);
1263 samples_in = US_TO_SAMPLES(
1264 dac33->burst_rate,
1265 time_delta);
1266 delay = MODE7_LTHR + samples_in - samples_out;
1267
9d7db2b2
PU		 1268 if (unlikely(delay > uthr))
1269 delay = uthr;
f57d2cfa
PU		 1270 }
1271 break;
1272 default:
1273 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1274 dac33->fifo_mode);
1275 break;
1276 }
1277out:
1278 return delay;
1279}
1280
c8bf93f0
PU		 1281static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1282 int clk_id, unsigned int freq, int dir)
1283{
1284 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1285 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1286 u8 ioc_reg, asrcb_reg;
1287
1288 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1289 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1290 switch (clk_id) {
1291 case TLV320DAC33_MCLK:
1292 ioc_reg |= DAC33_REFSEL;
1293 asrcb_reg |= DAC33_SRCREFSEL;
1294 break;
1295 case TLV320DAC33_SLEEPCLK:
1296 ioc_reg &= ~DAC33_REFSEL;
1297 asrcb_reg &= ~DAC33_SRCREFSEL;
1298 break;
1299 default:
1300 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1301 break;
1302 }
1303 dac33->refclk = freq;
1304
1305 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1306 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1307
1308 return 0;
1309}
1310
1311static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1312 unsigned int fmt)
1313{
1314 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1315 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1316 u8 aictrl_a, aictrl_b;
1317
1318 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1319 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1320 /* set master/slave audio interface */
1321 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1322 case SND_SOC_DAIFMT_CBM_CFM:
1323 /* Codec Master */
1324 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1325 break;
1326 case SND_SOC_DAIFMT_CBS_CFS:
1327 /* Codec Slave */
adcb8bc0
PU		 1328 if (dac33->fifo_mode) {
1329 dev_err(codec->dev, "FIFO mode requires master mode\n");
1330 return -EINVAL;
1331 } else
1332 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
c8bf93f0
PU		 1333 break;
1334 default:
1335 return -EINVAL;
1336 }
1337
1338 aictrl_a &= ~DAC33_AFMT_MASK;
1339 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1340 case SND_SOC_DAIFMT_I2S:
1341 aictrl_a |= DAC33_AFMT_I2S;
1342 break;
1343 case SND_SOC_DAIFMT_DSP_A:
1344 aictrl_a |= DAC33_AFMT_DSP;
1345 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
44f497b4 1346 aictrl_b |= DAC33_DATA_DELAY(0);
c8bf93f0
PU		 1347 break;
1348 case SND_SOC_DAIFMT_RIGHT_J:
1349 aictrl_a |= DAC33_AFMT_RIGHT_J;
1350 break;
1351 case SND_SOC_DAIFMT_LEFT_J:
1352 aictrl_a |= DAC33_AFMT_LEFT_J;
1353 break;
1354 default:
1355 dev_err(codec->dev, "Unsupported format (%u)\n",
1356 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1357 return -EINVAL;
1358 }
1359
1360 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1361 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1362
1363 return 0;
1364}
1365
c8bf93f0
PU		 1366static int dac33_soc_probe(struct platform_device *pdev)
1367{
1368 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1369 struct snd_soc_codec *codec;
1370 struct tlv320dac33_priv *dac33;
1371 int ret = 0;
1372
1373 BUG_ON(!tlv320dac33_codec);
1374
1375 codec = tlv320dac33_codec;
1376 socdev->card->codec = codec;
b2c812e2 1377 dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1378
1379 /* register pcms */
1380 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1381 if (ret < 0) {
1382 dev_err(codec->dev, "failed to create pcms\n");
1383 goto pcm_err;
1384 }
1385
1386 snd_soc_add_controls(codec, dac33_snd_controls,
1387 ARRAY_SIZE(dac33_snd_controls));
1388 /* Only add the nSample controls, if we have valid IRQ number */
1389 if (dac33->irq >= 0)
1390 snd_soc_add_controls(codec, dac33_nsample_snd_controls,
1391 ARRAY_SIZE(dac33_nsample_snd_controls));
1392
1393 dac33_add_widgets(codec);
1394
c8bf93f0 1395 return 0;
fe3e78e0 1396
c8bf93f0
PU		 1397pcm_err:
1398 dac33_hard_power(codec, 0);
1399 return ret;
1400}
1401
1402static int dac33_soc_remove(struct platform_device *pdev)
1403{
1404 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1405 struct snd_soc_codec *codec = socdev->card->codec;
1406
1407 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1408
1409 snd_soc_free_pcms(socdev);
1410 snd_soc_dapm_free(socdev);
1411
1412 return 0;
1413}
1414
1415static int dac33_soc_suspend(struct platform_device *pdev, pm_message_t state)
1416{
1417 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1418 struct snd_soc_codec *codec = socdev->card->codec;
1419
1420 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1421
1422 return 0;
1423}
1424
1425static int dac33_soc_resume(struct platform_device *pdev)
1426{
1427 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1428 struct snd_soc_codec *codec = socdev->card->codec;
1429
1430 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
c8bf93f0
PU		 1431
1432 return 0;
1433}
1434
1435struct snd_soc_codec_device soc_codec_dev_tlv320dac33 = {
1436 .probe = dac33_soc_probe,
1437 .remove = dac33_soc_remove,
1438 .suspend = dac33_soc_suspend,
1439 .resume = dac33_soc_resume,
1440};
1441EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33);
1442
1443#define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1444 SNDRV_PCM_RATE_48000)
1445#define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1446
1447static struct snd_soc_dai_ops dac33_dai_ops = {
0b61d2b9 1448 .startup = dac33_startup,
c8bf93f0
PU		 1449 .shutdown = dac33_shutdown,
1450 .hw_params = dac33_hw_params,
c8bf93f0 1451 .trigger = dac33_pcm_trigger,
f57d2cfa 1452 .delay = dac33_dai_delay,
c8bf93f0
PU		 1453 .set_sysclk = dac33_set_dai_sysclk,
1454 .set_fmt = dac33_set_dai_fmt,
1455};
1456
1457struct snd_soc_dai dac33_dai = {
1458 .name = "tlv320dac33",
1459 .playback = {
1460 .stream_name = "Playback",
1461 .channels_min = 2,
1462 .channels_max = 2,
1463 .rates = DAC33_RATES,
1464 .formats = DAC33_FORMATS,},
1465 .ops = &dac33_dai_ops,
1466};
1467EXPORT_SYMBOL_GPL(dac33_dai);
1468
735fe4cf
MB		 1469static int __devinit dac33_i2c_probe(struct i2c_client *client,
1470 const struct i2c_device_id *id)
c8bf93f0
PU		 1471{
1472 struct tlv320dac33_platform_data *pdata;
1473 struct tlv320dac33_priv *dac33;
1474 struct snd_soc_codec *codec;
3a7aaed7 1475 int ret, i;
c8bf93f0
PU		 1476
1477 if (client->dev.platform_data == NULL) {
1478 dev_err(&client->dev, "Platform data not set\n");
1479 return -ENODEV;
1480 }
1481 pdata = client->dev.platform_data;
1482
1483 dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1484 if (dac33 == NULL)
1485 return -ENOMEM;
1486
1487 codec = &dac33->codec;
b2c812e2 1488 snd_soc_codec_set_drvdata(codec, dac33);
c8bf93f0
PU		 1489 codec->control_data = client;
1490
1491 mutex_init(&codec->mutex);
1492 mutex_init(&dac33->mutex);
f57d2cfa 1493 spin_lock_init(&dac33->lock);
c8bf93f0
PU		 1494 INIT_LIST_HEAD(&codec->dapm_widgets);
1495 INIT_LIST_HEAD(&codec->dapm_paths);
1496
1497 codec->name = "tlv320dac33";
1498 codec->owner = THIS_MODULE;
1499 codec->read = dac33_read_reg_cache;
1500 codec->write = dac33_write_locked;
1501 codec->hw_write = (hw_write_t) i2c_master_send;
1502 codec->bias_level = SND_SOC_BIAS_OFF;
1503 codec->set_bias_level = dac33_set_bias_level;
ad05c03b 1504 codec->idle_bias_off = 1;
c8bf93f0
PU		 1505 codec->dai = &dac33_dai;
1506 codec->num_dai = 1;
1507 codec->reg_cache_size = ARRAY_SIZE(dac33_reg);
1508 codec->reg_cache = kmemdup(dac33_reg, ARRAY_SIZE(dac33_reg),
1509 GFP_KERNEL);
1510 if (codec->reg_cache == NULL) {
1511 ret = -ENOMEM;
1512 goto error_reg;
1513 }
1514
1515 i2c_set_clientdata(client, dac33);
1516
1517 dac33->power_gpio = pdata->power_gpio;
6aceabb4 1518 dac33->burst_bclkdiv = pdata->burst_bclkdiv;
76f47127
PU		 1519 /* Pre calculate the burst rate */
1520 dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32;
eeb309a8 1521 dac33->keep_bclk = pdata->keep_bclk;
c8bf93f0
PU		 1522 dac33->irq = client->irq;
1523 dac33->nsample = NSAMPLE_MAX;
55abb59c 1524 dac33->nsample_max = NSAMPLE_MAX;
9d7db2b2 1525 dac33->uthr = MODE7_UTHR;
c8bf93f0 1526 /* Disable FIFO use by default */
7427b4b9 1527 dac33->fifo_mode = DAC33_FIFO_BYPASS;
c8bf93f0
PU		 1528
1529 tlv320dac33_codec = codec;
1530
1531 codec->dev = &client->dev;
1532 dac33_dai.dev = codec->dev;
1533
1534 /* Check if the reset GPIO number is valid and request it */
1535 if (dac33->power_gpio >= 0) {
1536 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1537 if (ret < 0) {
1538 dev_err(codec->dev,
1539 "Failed to request reset GPIO (%d)\n",
1540 dac33->power_gpio);
1541 snd_soc_unregister_dai(&dac33_dai);
1542 snd_soc_unregister_codec(codec);
1543 goto error_gpio;
1544 }
1545 gpio_direction_output(dac33->power_gpio, 0);
c8bf93f0
PU		 1546 }
1547
1548 /* Check if the IRQ number is valid and request it */
1549 if (dac33->irq >= 0) {
1550 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1551 IRQF_TRIGGER_RISING | IRQF_DISABLED,
1552 codec->name, codec);
1553 if (ret < 0) {
1554 dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1555 dac33->irq, ret);
1556 dac33->irq = -1;
1557 }
1558 if (dac33->irq != -1) {
1559 /* Setup work queue */
74ea23aa
PU		 1560 dac33->dac33_wq =
1561 create_singlethread_workqueue("tlv320dac33");
c8bf93f0
PU		 1562 if (dac33->dac33_wq == NULL) {
1563 free_irq(dac33->irq, &dac33->codec);
1564 ret = -ENOMEM;
1565 goto error_wq;
1566 }
1567
1568 INIT_WORK(&dac33->work, dac33_work);
1569 }
1570 }
1571
3a7aaed7
IK		 1572 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1573 dac33->supplies[i].supply = dac33_supply_names[i];
1574
1575 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(dac33->supplies),
1576 dac33->supplies);
1577
1578 if (ret != 0) {
1579 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1580 goto err_get;
1581 }
1582
239fe55c
PU		 1583 /* Read the tlv320dac33 ID registers */
1584 ret = dac33_hard_power(codec, 1);
3a7aaed7 1585 if (ret != 0) {
239fe55c
PU		 1586 dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
1587 goto error_codec;
3a7aaed7 1588 }
239fe55c
PU		 1589 dac33_read_id(codec);
1590 dac33_hard_power(codec, 0);
3a7aaed7 1591
c8bf93f0
PU		 1592 ret = snd_soc_register_codec(codec);
1593 if (ret != 0) {
1594 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1595 goto error_codec;
1596 }
1597
1598 ret = snd_soc_register_dai(&dac33_dai);
1599 if (ret != 0) {
1600 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1601 snd_soc_unregister_codec(codec);
1602 goto error_codec;
1603 }
1604
c8bf93f0
PU		 1605 return ret;
1606
1607error_codec:
3a7aaed7
IK		 1608 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1609err_get:
c8bf93f0
PU		 1610 if (dac33->irq >= 0) {
1611 free_irq(dac33->irq, &dac33->codec);
1612 destroy_workqueue(dac33->dac33_wq);
1613 }
1614error_wq:
1615 if (dac33->power_gpio >= 0)
1616 gpio_free(dac33->power_gpio);
1617error_gpio:
1618 kfree(codec->reg_cache);
1619error_reg:
1620 tlv320dac33_codec = NULL;
1621 kfree(dac33);
1622
1623 return ret;
1624}
1625
735fe4cf 1626static int __devexit dac33_i2c_remove(struct i2c_client *client)
c8bf93f0
PU		 1627{
1628 struct tlv320dac33_priv *dac33;
1629
1630 dac33 = i2c_get_clientdata(client);
239fe55c
PU		 1631
1632 if (unlikely(dac33->chip_power))
1633 dac33_hard_power(&dac33->codec, 0);
c8bf93f0
PU		 1634
1635 if (dac33->power_gpio >= 0)
1636 gpio_free(dac33->power_gpio);
1637 if (dac33->irq >= 0)
1638 free_irq(dac33->irq, &dac33->codec);
1639
3a7aaed7
IK		 1640 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1641
c8bf93f0
PU		 1642 destroy_workqueue(dac33->dac33_wq);
1643 snd_soc_unregister_dai(&dac33_dai);
1644 snd_soc_unregister_codec(&dac33->codec);
1645 kfree(dac33->codec.reg_cache);
1646 kfree(dac33);
1647 tlv320dac33_codec = NULL;
1648
1649 return 0;
1650}
1651
1652static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1653 {
1654 .name = "tlv320dac33",
1655 .driver_data = 0,
1656 },
1657 { },
1658};
1659
1660static struct i2c_driver tlv320dac33_i2c_driver = {
1661 .driver = {
1662 .name = "tlv320dac33",
1663 .owner = THIS_MODULE,
1664 },
1665 .probe = dac33_i2c_probe,
1666 .remove = __devexit_p(dac33_i2c_remove),
1667 .id_table = tlv320dac33_i2c_id,
1668};
1669
1670static int __init dac33_module_init(void)
1671{
1672 int r;
1673 r = i2c_add_driver(&tlv320dac33_i2c_driver);
1674 if (r < 0) {
1675 printk(KERN_ERR "DAC33: driver registration failed\n");
1676 return r;
1677 }
1678 return 0;
1679}
1680module_init(dac33_module_init);
1681
1682static void __exit dac33_module_exit(void)
1683{
1684 i2c_del_driver(&tlv320dac33_i2c_driver);
1685}
1686module_exit(dac33_module_exit);
1687
1688
1689MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1690MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1691MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)