[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / tlv320aic3x.h

/*
 * ALSA SoC TLV320AIC3X codec driver
 *
 * Author:      Vladimir Barinov, <vbarinov@embeddedalley.com>
 * Copyright:   (C) 2007 MontaVista Software, Inc., <source@mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef _AIC3X_H
#define _AIC3X_H

/* AIC3X register space */
#define AIC3X_CACHEREGNUM		110

/* Page select register */
#define AIC3X_PAGE_SELECT		0
/* Software reset register */
#define AIC3X_RESET			1
/* Codec Sample rate select register */
#define AIC3X_SAMPLE_RATE_SEL_REG	2
/* PLL progrramming register A */
#define AIC3X_PLL_PROGA_REG		3
/* PLL progrramming register B */
#define AIC3X_PLL_PROGB_REG		4
/* PLL progrramming register C */
#define AIC3X_PLL_PROGC_REG		5
/* PLL progrramming register D */
#define AIC3X_PLL_PROGD_REG		6
/* Codec datapath setup register */
#define AIC3X_CODEC_DATAPATH_REG	7
/* Audio serial data interface control register A */
#define AIC3X_ASD_INTF_CTRLA		8
/* Audio serial data interface control register B */
#define AIC3X_ASD_INTF_CTRLB		9
/* Audio serial data interface control register C */
#define AIC3X_ASD_INTF_CTRLC		10
/* Audio overflow status and PLL R value programming register */
#define AIC3X_OVRF_STATUS_AND_PLLR_REG	11
/* Audio codec digital filter control register */
#define AIC3X_CODEC_DFILT_CTRL		12
/* Headset/button press detection register */
#define AIC3X_HEADSET_DETECT_CTRL_A	13
#define AIC3X_HEADSET_DETECT_CTRL_B	14
/* ADC PGA Gain control registers */
#define LADC_VOL			15
#define RADC_VOL			16
/* MIC3 control registers */
#define MIC3LR_2_LADC_CTRL		17
#define MIC3LR_2_RADC_CTRL		18
/* Line1 Input control registers */
#define LINE1L_2_LADC_CTRL		19
#define LINE1R_2_LADC_CTRL		21
#define LINE1R_2_RADC_CTRL		22
#define LINE1L_2_RADC_CTRL		24
/* Line2 Input control registers */
#define LINE2L_2_LADC_CTRL		20
#define LINE2R_2_RADC_CTRL		23
/* MICBIAS Control Register */
#define MICBIAS_CTRL			25

/* AGC Control Registers A, B, C */
#define LAGC_CTRL_A			26
#define LAGC_CTRL_B			27
#define LAGC_CTRL_C			28
#define RAGC_CTRL_A			29
#define RAGC_CTRL_B			30
#define RAGC_CTRL_C			31

/* DAC Power and Left High Power Output control registers */
#define DAC_PWR				37
#define HPLCOM_CFG			37
/* Right High Power Output control registers */
#define HPRCOM_CFG			38
/* High Power Output Stage Control Register */
#define HPOUT_SC			40
/* DAC Output Switching control registers */
#define DAC_LINE_MUX			41
/* High Power Output Driver Pop Reduction registers */
#define HPOUT_POP_REDUCTION		42
/* DAC Digital control registers */
#define LDAC_VOL			43
#define RDAC_VOL			44
/* Left High Power Output control registers */
#define LINE2L_2_HPLOUT_VOL		45
#define PGAL_2_HPLOUT_VOL		46
#define DACL1_2_HPLOUT_VOL		47
#define LINE2R_2_HPLOUT_VOL		48
#define PGAR_2_HPLOUT_VOL		49
#define DACR1_2_HPLOUT_VOL		50
#define HPLOUT_CTRL			51
/* Left High Power COM control registers */
#define LINE2L_2_HPLCOM_VOL		52
#define PGAL_2_HPLCOM_VOL		53
#define DACL1_2_HPLCOM_VOL		54
#define LINE2R_2_HPLCOM_VOL		55
#define PGAR_2_HPLCOM_VOL		56
#define DACR1_2_HPLCOM_VOL		57
#define HPLCOM_CTRL			58
/* Right High Power Output control registers */
#define LINE2L_2_HPROUT_VOL		59
#define PGAL_2_HPROUT_VOL		60
#define DACL1_2_HPROUT_VOL		61
#define LINE2R_2_HPROUT_VOL		62
#define PGAR_2_HPROUT_VOL		63
#define DACR1_2_HPROUT_VOL		64
#define HPROUT_CTRL			65
/* Right High Power COM control registers */
#define LINE2L_2_HPRCOM_VOL		66
#define PGAL_2_HPRCOM_VOL		67
#define DACL1_2_HPRCOM_VOL		68
#define LINE2R_2_HPRCOM_VOL		69
#define PGAR_2_HPRCOM_VOL		70
#define DACR1_2_HPRCOM_VOL		71
#define HPRCOM_CTRL			72
/* Mono Line Output Plus/Minus control registers */
#define LINE2L_2_MONOLOPM_VOL		73
#define PGAL_2_MONOLOPM_VOL		74
#define DACL1_2_MONOLOPM_VOL		75
#define LINE2R_2_MONOLOPM_VOL		76
#define PGAR_2_MONOLOPM_VOL		77
#define DACR1_2_MONOLOPM_VOL		78
#define MONOLOPM_CTRL			79
/* Class-D speaker driver on tlv320aic3007 */
#define CLASSD_CTRL			73
/* Left Line Output Plus/Minus control registers */
#define LINE2L_2_LLOPM_VOL		80
#define PGAL_2_LLOPM_VOL		81
#define DACL1_2_LLOPM_VOL		82
#define LINE2R_2_LLOPM_VOL		83
#define PGAR_2_LLOPM_VOL		84
#define DACR1_2_LLOPM_VOL		85
#define LLOPM_CTRL			86
/* Right Line Output Plus/Minus control registers */
#define LINE2L_2_RLOPM_VOL		87
#define PGAL_2_RLOPM_VOL		88
#define DACL1_2_RLOPM_VOL		89
#define LINE2R_2_RLOPM_VOL		90
#define PGAR_2_RLOPM_VOL		91
#define DACR1_2_RLOPM_VOL		92
#define RLOPM_CTRL			93
/* GPIO/IRQ registers */
#define AIC3X_STICKY_IRQ_FLAGS_REG	96
#define AIC3X_RT_IRQ_FLAGS_REG		97
#define AIC3X_GPIO1_REG			98
#define AIC3X_GPIO2_REG			99
#define AIC3X_GPIOA_REG			100
#define AIC3X_GPIOB_REG			101
/* Clock generation control register */
#define AIC3X_CLKGEN_CTRL_REG		102
/* New AGC registers */
#define LAGCN_ATTACK			103
#define LAGCN_DECAY			104
#define RAGCN_ATTACK			105
#define RAGCN_DECAY			106
/* New Programmable ADC Digital Path and I2C Bus Condition Register */
#define NEW_ADC_DIGITALPATH		107
/* Passive Analog Signal Bypass Selection During Powerdown Register */
#define PASSIVE_BYPASS			108
/* DAC Quiescent Current Adjustment Register */
#define DAC_ICC_ADJ			109

/* Page select register bits */
#define PAGE0_SELECT		0
#define PAGE1_SELECT		1

/* Audio serial data interface control register A bits */
#define BIT_CLK_MASTER          0x80
#define WORD_CLK_MASTER         0x40

/* Codec Datapath setup register 7 */
#define FSREF_44100		(1 << 7)
#define FSREF_48000		(0 << 7)
#define DUAL_RATE_MODE		((1 << 5) | (1 << 6))
#define LDAC2LCH		(0x1 << 3)
#define RDAC2RCH		(0x1 << 1)
#define LDAC2RCH		(0x2 << 3)
#define RDAC2LCH		(0x2 << 1)
#define LDAC2MONOMIX		(0x3 << 3)
#define RDAC2MONOMIX		(0x3 << 1)

/* PLL registers bitfields */
#define PLLP_SHIFT		0
#define PLLP_MASK		7
#define PLLQ_SHIFT		3
#define PLLR_SHIFT		0
#define PLLJ_SHIFT		2
#define PLLD_MSB_SHIFT		0
#define PLLD_LSB_SHIFT		2

/* Clock generation register bits */
#define CODEC_CLKIN_PLLDIV	0
#define CODEC_CLKIN_CLKDIV	1
#define PLL_CLKIN_SHIFT		4
#define MCLK_SOURCE		0x0
#define PLL_CLKDIV_SHIFT	0
#define PLLCLK_IN_MASK		0x30
#define PLLCLK_IN_SHIFT		4
#define CLKDIV_IN_MASK		0xc0
#define CLKDIV_IN_SHIFT		6
/* clock in source */
#define CLKIN_MCLK		0
#define CLKIN_GPIO2		1
#define CLKIN_BCLK		2

/* Software reset register bits */
#define SOFT_RESET		0x80

/* PLL progrramming register A bits */
#define PLL_ENABLE		0x80

/* Route bits */
#define ROUTE_ON		0x80

/* Mute bits */
#define UNMUTE			0x08
#define MUTE_ON			0x80

/* Power bits */
#define LADC_PWR_ON		0x04
#define RADC_PWR_ON		0x04
#define LDAC_PWR_ON		0x80
#define RDAC_PWR_ON		0x40
#define HPLOUT_PWR_ON		0x01
#define HPROUT_PWR_ON		0x01
#define HPLCOM_PWR_ON		0x01
#define HPRCOM_PWR_ON		0x01
#define MONOLOPM_PWR_ON		0x01
#define LLOPM_PWR_ON		0x01
#define RLOPM_PWR_ON	0x01

#define INVERT_VOL(val)   (0x7f - val)

/* Default output volume (inverted) */
#define DEFAULT_VOL     INVERT_VOL(0x50)
/* Default input volume */
#define DEFAULT_GAIN    0x20

/* MICBIAS Control Register */
#define MICBIAS_LEVEL_SHIFT	(6)
#define MICBIAS_LEVEL_MASK	(3 << 6)

/* headset detection / button API */

/* The AIC3x supports detection of stereo headsets (GND + left + right signal)
 * and cellular headsets (GND + speaker output + microphone input).
 * It is recommended to enable MIC bias for this function to work properly.
 * For more information, please refer to the datasheet. */
enum {
	AIC3X_HEADSET_DETECT_OFF	= 0,
	AIC3X_HEADSET_DETECT_STEREO	= 1,
	AIC3X_HEADSET_DETECT_CELLULAR   = 2,
	AIC3X_HEADSET_DETECT_BOTH	= 3
};

enum {
	AIC3X_HEADSET_DEBOUNCE_16MS	= 0,
	AIC3X_HEADSET_DEBOUNCE_32MS	= 1,
	AIC3X_HEADSET_DEBOUNCE_64MS	= 2,
	AIC3X_HEADSET_DEBOUNCE_128MS	= 3,
	AIC3X_HEADSET_DEBOUNCE_256MS	= 4,
	AIC3X_HEADSET_DEBOUNCE_512MS	= 5
};

enum {
	AIC3X_BUTTON_DEBOUNCE_0MS	= 0,
	AIC3X_BUTTON_DEBOUNCE_8MS	= 1,
	AIC3X_BUTTON_DEBOUNCE_16MS	= 2,
	AIC3X_BUTTON_DEBOUNCE_32MS	= 3
};

#define AIC3X_HEADSET_DETECT_ENABLED	0x80
#define AIC3X_HEADSET_DETECT_SHIFT	5
#define AIC3X_HEADSET_DETECT_MASK	3
#define AIC3X_HEADSET_DEBOUNCE_SHIFT	2
#define AIC3X_HEADSET_DEBOUNCE_MASK	7
#define AIC3X_BUTTON_DEBOUNCE_SHIFT 	0
#define AIC3X_BUTTON_DEBOUNCE_MASK	3

#endif /* _AIC3X_H */
Commit	Line	Data
44d0a879 VB	1	/*
	2	* ALSA SoC TLV320AIC3X codec driver
	3	*
d6b52039	4	* Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
44d0a879 VB	5	* Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#ifndef _AIC3X_H
	13	#define _AIC3X_H
	14
	15	/* AIC3X register space */
784a897e	16	#define AIC3X_CACHEREGNUM 110
44d0a879 VB	17
	18	/* Page select register */
	19	#define AIC3X_PAGE_SELECT 0
	20	/* Software reset register */
	21	#define AIC3X_RESET 1
	22	/* Codec Sample rate select register */
	23	#define AIC3X_SAMPLE_RATE_SEL_REG 2
	24	/* PLL progrramming register A */
	25	#define AIC3X_PLL_PROGA_REG 3
	26	/* PLL progrramming register B */
	27	#define AIC3X_PLL_PROGB_REG 4
	28	/* PLL progrramming register C */
	29	#define AIC3X_PLL_PROGC_REG 5
	30	/* PLL progrramming register D */
	31	#define AIC3X_PLL_PROGD_REG 6
	32	/* Codec datapath setup register */
	33	#define AIC3X_CODEC_DATAPATH_REG 7
	34	/* Audio serial data interface control register A */
	35	#define AIC3X_ASD_INTF_CTRLA 8
	36	/* Audio serial data interface control register B */
	37	#define AIC3X_ASD_INTF_CTRLB 9
a24f4f68 TK	38	/* Audio serial data interface control register C */
a24f4f68 TK	39	#define AIC3X_ASD_INTF_CTRLC 10
44d0a879 VB	40	/* Audio overflow status and PLL R value programming register */
44d0a879 VB	41	#define AIC3X_OVRF_STATUS_AND_PLLR_REG 11
4d20f70a JN	42	/* Audio codec digital filter control register */
4d20f70a JN	43	#define AIC3X_CODEC_DFILT_CTRL 12
6f2a974b DM	44	/* Headset/button press detection register */
	45	#define AIC3X_HEADSET_DETECT_CTRL_A 13
	46	#define AIC3X_HEADSET_DETECT_CTRL_B 14
44d0a879 VB	47	/* ADC PGA Gain control registers */
	48	#define LADC_VOL 15
	49	#define RADC_VOL 16
	50	/* MIC3 control registers */
	51	#define MIC3LR_2_LADC_CTRL 17
	52	#define MIC3LR_2_RADC_CTRL 18
	53	/* Line1 Input control registers */
	54	#define LINE1L_2_LADC_CTRL 19
54f01916	55	#define LINE1R_2_LADC_CTRL 21
44d0a879	56	#define LINE1R_2_RADC_CTRL 22
54f01916	57	#define LINE1L_2_RADC_CTRL 24
44d0a879 VB	58	/* Line2 Input control registers */
	59	#define LINE2L_2_LADC_CTRL 20
	60	#define LINE2R_2_RADC_CTRL 23
	61	/* MICBIAS Control Register */
	62	#define MICBIAS_CTRL 25
	63
	64	/* AGC Control Registers A, B, C */
	65	#define LAGC_CTRL_A 26
	66	#define LAGC_CTRL_B 27
	67	#define LAGC_CTRL_C 28
	68	#define RAGC_CTRL_A 29
	69	#define RAGC_CTRL_B 30
	70	#define RAGC_CTRL_C 31
	71
	72	/* DAC Power and Left High Power Output control registers */
	73	#define DAC_PWR 37
	74	#define HPLCOM_CFG 37
	75	/* Right High Power Output control registers */
	76	#define HPRCOM_CFG 38
784a897e JP	77	/* High Power Output Stage Control Register */
784a897e JP	78	#define HPOUT_SC 40
44d0a879 VB	79	/* DAC Output Switching control registers */
	80	#define DAC_LINE_MUX 41
	81	/* High Power Output Driver Pop Reduction registers */
	82	#define HPOUT_POP_REDUCTION 42
	83	/* DAC Digital control registers */
	84	#define LDAC_VOL 43
	85	#define RDAC_VOL 44
b2eaac20	86	/* Left High Power Output control registers */
44d0a879	87	#define LINE2L_2_HPLOUT_VOL 45
44d0a879	88	#define PGAL_2_HPLOUT_VOL 46
44d0a879	89	#define DACL1_2_HPLOUT_VOL 47
c3b79e05	90	#define LINE2R_2_HPLOUT_VOL 48
b2eaac20	91	#define PGAR_2_HPLOUT_VOL 49
c3b79e05	92	#define DACR1_2_HPLOUT_VOL 50
44d0a879	93	#define HPLOUT_CTRL 51
b2eaac20	94	/* Left High Power COM control registers */
44d0a879	95	#define LINE2L_2_HPLCOM_VOL 52
44d0a879	96	#define PGAL_2_HPLCOM_VOL 53
b2eaac20	97	#define DACL1_2_HPLCOM_VOL 54
c3b79e05	98	#define LINE2R_2_HPLCOM_VOL 55
54f01916	99	#define PGAR_2_HPLCOM_VOL 56
c3b79e05	100	#define DACR1_2_HPLCOM_VOL 57
b2eaac20 JN	101	#define HPLCOM_CTRL 58
b2eaac20 JN	102	/* Right High Power Output control registers */
c3b79e05	103	#define LINE2L_2_HPROUT_VOL 59
b2eaac20	104	#define PGAL_2_HPROUT_VOL 60
c3b79e05	105	#define DACL1_2_HPROUT_VOL 61
b2eaac20 JN	106	#define LINE2R_2_HPROUT_VOL 62
	107	#define PGAR_2_HPROUT_VOL 63
	108	#define DACR1_2_HPROUT_VOL 64
	109	#define HPROUT_CTRL 65
	110	/* Right High Power COM control registers */
c3b79e05	111	#define LINE2L_2_HPRCOM_VOL 66
54f01916	112	#define PGAL_2_HPRCOM_VOL 67
c3b79e05	113	#define DACL1_2_HPRCOM_VOL 68
b2eaac20	114	#define LINE2R_2_HPRCOM_VOL 69
44d0a879	115	#define PGAR_2_HPRCOM_VOL 70
44d0a879	116	#define DACR1_2_HPRCOM_VOL 71
44d0a879 VB	117	#define HPRCOM_CTRL 72
	118	/* Mono Line Output Plus/Minus control registers */
	119	#define LINE2L_2_MONOLOPM_VOL 73
44d0a879	120	#define PGAL_2_MONOLOPM_VOL 74
44d0a879	121	#define DACL1_2_MONOLOPM_VOL 75
b2eaac20 JN	122	#define LINE2R_2_MONOLOPM_VOL 76
b2eaac20 JN	123	#define PGAR_2_MONOLOPM_VOL 77
44d0a879 VB	124	#define DACR1_2_MONOLOPM_VOL 78
44d0a879 VB	125	#define MONOLOPM_CTRL 79
6184f105 RC	126	/* Class-D speaker driver on tlv320aic3007 */
6184f105 RC	127	#define CLASSD_CTRL 73
b2eaac20	128	/* Left Line Output Plus/Minus control registers */
44d0a879	129	#define LINE2L_2_LLOPM_VOL 80
44d0a879	130	#define PGAL_2_LLOPM_VOL 81
44d0a879	131	#define DACL1_2_LLOPM_VOL 82
b2eaac20 JN	132	#define LINE2R_2_LLOPM_VOL 83
b2eaac20 JN	133	#define PGAR_2_LLOPM_VOL 84
54f01916	134	#define DACR1_2_LLOPM_VOL 85
44d0a879	135	#define LLOPM_CTRL 86
b2eaac20 JN	136	/* Right Line Output Plus/Minus control registers */
	137	#define LINE2L_2_RLOPM_VOL 87
	138	#define PGAL_2_RLOPM_VOL 88
	139	#define DACL1_2_RLOPM_VOL 89
	140	#define LINE2R_2_RLOPM_VOL 90
	141	#define PGAR_2_RLOPM_VOL 91
	142	#define DACR1_2_RLOPM_VOL 92
44d0a879	143	#define RLOPM_CTRL 93
54e7e616 DM	144	/* GPIO/IRQ registers */
	145	#define AIC3X_STICKY_IRQ_FLAGS_REG 96
	146	#define AIC3X_RT_IRQ_FLAGS_REG 97
	147	#define AIC3X_GPIO1_REG 98
	148	#define AIC3X_GPIO2_REG 99
	149	#define AIC3X_GPIOA_REG 100
4f9c16cc	150	#define AIC3X_GPIOB_REG 101
54e7e616	151	/* Clock generation control register */
44d0a879	152	#define AIC3X_CLKGEN_CTRL_REG 102
784a897e JP	153	/* New AGC registers */
	154	#define LAGCN_ATTACK 103
	155	#define LAGCN_DECAY 104
	156	#define RAGCN_ATTACK 105
	157	#define RAGCN_DECAY 106
	158	/* New Programmable ADC Digital Path and I2C Bus Condition Register */
	159	#define NEW_ADC_DIGITALPATH 107
	160	/* Passive Analog Signal Bypass Selection During Powerdown Register */
	161	#define PASSIVE_BYPASS 108
	162	/* DAC Quiescent Current Adjustment Register */
	163	#define DAC_ICC_ADJ 109
44d0a879 VB	164
	165	/* Page select register bits */
	166	#define PAGE0_SELECT 0
	167	#define PAGE1_SELECT 1
	168
	169	/* Audio serial data interface control register A bits */
	170	#define BIT_CLK_MASTER 0x80
	171	#define WORD_CLK_MASTER 0x40
	172
	173	/* Codec Datapath setup register 7 */
	174	#define FSREF_44100 (1 << 7)
	175	#define FSREF_48000 (0 << 7)
	176	#define DUAL_RATE_MODE ((1 << 5) \| (1 << 6))
	177	#define LDAC2LCH (0x1 << 3)
	178	#define RDAC2RCH (0x1 << 1)
784a897e JP	179	#define LDAC2RCH (0x2 << 3)
	180	#define RDAC2LCH (0x2 << 1)
	181	#define LDAC2MONOMIX (0x3 << 3)
	182	#define RDAC2MONOMIX (0x3 << 1)
44d0a879 VB	183
	184	/* PLL registers bitfields */
	185	#define PLLP_SHIFT 0
c9fe573a	186	#define PLLP_MASK 7
4f9c16cc	187	#define PLLQ_SHIFT 3
44d0a879 VB	188	#define PLLR_SHIFT 0
	189	#define PLLJ_SHIFT 2
	190	#define PLLD_MSB_SHIFT 0
	191	#define PLLD_LSB_SHIFT 2
	192
	193	/* Clock generation register bits */
4f9c16cc DM	194	#define CODEC_CLKIN_PLLDIV 0
4f9c16cc DM	195	#define CODEC_CLKIN_CLKDIV 1
44d0a879 VB	196	#define PLL_CLKIN_SHIFT 4
	197	#define MCLK_SOURCE 0x0
	198	#define PLL_CLKDIV_SHIFT 0
a1f34af0 JP	199	#define PLLCLK_IN_MASK 0x30
	200	#define PLLCLK_IN_SHIFT 4
	201	#define CLKDIV_IN_MASK 0xc0
	202	#define CLKDIV_IN_SHIFT 6
	203	/* clock in source */
	204	#define CLKIN_MCLK 0
	205	#define CLKIN_GPIO2 1
	206	#define CLKIN_BCLK 2
44d0a879 VB	207
	208	/* Software reset register bits */
	209	#define SOFT_RESET 0x80
	210
	211	/* PLL progrramming register A bits */
	212	#define PLL_ENABLE 0x80
	213
	214	/* Route bits */
	215	#define ROUTE_ON 0x80
	216
	217	/* Mute bits */
	218	#define UNMUTE 0x08
	219	#define MUTE_ON 0x80
	220
	221	/* Power bits */
	222	#define LADC_PWR_ON 0x04
	223	#define RADC_PWR_ON 0x04
	224	#define LDAC_PWR_ON 0x80
	225	#define RDAC_PWR_ON 0x40
	226	#define HPLOUT_PWR_ON 0x01
	227	#define HPROUT_PWR_ON 0x01
	228	#define HPLCOM_PWR_ON 0x01
	229	#define HPRCOM_PWR_ON 0x01
	230	#define MONOLOPM_PWR_ON 0x01
	231	#define LLOPM_PWR_ON 0x01
	232	#define RLOPM_PWR_ON 0x01
	233
	234	#define INVERT_VOL(val) (0x7f - val)
	235
	236	/* Default output volume (inverted) */
	237	#define DEFAULT_VOL INVERT_VOL(0x50)
	238	/* Default input volume */
	239	#define DEFAULT_GAIN 0x20
	240
e2e8bfdf HG	241	/* MICBIAS Control Register */
	242	#define MICBIAS_LEVEL_SHIFT (6)
	243	#define MICBIAS_LEVEL_MASK (3 << 6)
	244
6f2a974b DM	245	/* headset detection / button API */
	246
	247	/* The AIC3x supports detection of stereo headsets (GND + left + right signal)
	248	* and cellular headsets (GND + speaker output + microphone input).
	249	* It is recommended to enable MIC bias for this function to work properly.
	250	* For more information, please refer to the datasheet. */
	251	enum {
	252	AIC3X_HEADSET_DETECT_OFF = 0,
	253	AIC3X_HEADSET_DETECT_STEREO = 1,
	254	AIC3X_HEADSET_DETECT_CELLULAR = 2,
	255	AIC3X_HEADSET_DETECT_BOTH = 3
	256	};
	257
	258	enum {
	259	AIC3X_HEADSET_DEBOUNCE_16MS = 0,
	260	AIC3X_HEADSET_DEBOUNCE_32MS = 1,
	261	AIC3X_HEADSET_DEBOUNCE_64MS = 2,
	262	AIC3X_HEADSET_DEBOUNCE_128MS = 3,
	263	AIC3X_HEADSET_DEBOUNCE_256MS = 4,
	264	AIC3X_HEADSET_DEBOUNCE_512MS = 5
	265	};
	266
	267	enum {
	268	AIC3X_BUTTON_DEBOUNCE_0MS = 0,
	269	AIC3X_BUTTON_DEBOUNCE_8MS = 1,
	270	AIC3X_BUTTON_DEBOUNCE_16MS = 2,
	271	AIC3X_BUTTON_DEBOUNCE_32MS = 3
	272	};
	273
	274	#define AIC3X_HEADSET_DETECT_ENABLED 0x80
	275	#define AIC3X_HEADSET_DETECT_SHIFT 5
	276	#define AIC3X_HEADSET_DETECT_MASK 3
	277	#define AIC3X_HEADSET_DEBOUNCE_SHIFT 2
	278	#define AIC3X_HEADSET_DEBOUNCE_MASK 7
	279	#define AIC3X_BUTTON_DEBOUNCE_SHIFT 0
	280	#define AIC3X_BUTTON_DEBOUNCE_MASK 3
	281
44d0a879	282	#endif /* _AIC3X_H */