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ASoC: core: Add support for DAI and machine kcontrols.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / tlv320aic3x.c
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44d0a879
VB		 1/*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
d6b52039 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
44d0a879
VB		 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
6184f105 15 * codecs aic31, aic32, aic33, aic3007.
44d0a879
VB		 16 *
17 * It supports full aic33 codec functionality.
6184f105
RC		 18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
44d0a879
VB		 20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
a5302181 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
44d0a879
VB		 33 */
34
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/pm.h>
40#include <linux/i2c.h>
5193d62f 41#include <linux/gpio.h>
07779fdd 42#include <linux/regulator/consumer.h>
5a0e3ad6 43#include <linux/slab.h>
44d0a879
VB		 44#include <sound/core.h>
45#include <sound/pcm.h>
46#include <sound/pcm_params.h>
47#include <sound/soc.h>
44d0a879 48#include <sound/initval.h>
7565fc38 49#include <sound/tlv.h>
5193d62f 50#include <sound/tlv320aic3x.h>
44d0a879
VB		 51
52#include "tlv320aic3x.h"
53
07779fdd
JN		 54#define AIC3X_NUM_SUPPLIES 4
55static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
56 "IOVDD", /* I/O Voltage */
57 "DVDD", /* Digital Core Voltage */
58 "AVDD", /* Analog DAC Voltage */
59 "DRVDD", /* ADC Analog and Output Driver Voltage */
60};
44d0a879 61
414c73ab
JN		 62static LIST_HEAD(reset_list);
63
5a895f8a
JN		 64struct aic3x_priv;
65
66struct aic3x_disable_nb {
67 struct notifier_block nb;
68 struct aic3x_priv *aic3x;
69};
70
44d0a879
VB		 71/* codec private data */
72struct aic3x_priv {
5a895f8a 73 struct snd_soc_codec *codec;
07779fdd 74 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
5a895f8a 75 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
f0fba2ad
LG		 76 enum snd_soc_control_type control_type;
77 struct aic3x_setup_data *setup;
44d0a879 78 unsigned int sysclk;
414c73ab 79 struct list_head list;
44d0a879 80 int master;
5193d62f 81 int gpio_reset;
6c1a7d40 82 int power;
6184f105
RC		 83#define AIC3X_MODEL_3X 0
84#define AIC3X_MODEL_33 1
85#define AIC3X_MODEL_3007 2
86 u16 model;
44d0a879
VB		 87};
88
89/*
90 * AIC3X register cache
91 * We can't read the AIC3X register space when we are
92 * using 2 wire for device control, so we cache them instead.
93 * There is no point in caching the reset register
94 */
95static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
96 0x00, 0x00, 0x00, 0x10, /* 0 */
97 0x04, 0x00, 0x00, 0x00, /* 4 */
98 0x00, 0x00, 0x00, 0x01, /* 8 */
99 0x00, 0x00, 0x00, 0x80, /* 12 */
100 0x80, 0xff, 0xff, 0x78, /* 16 */
101 0x78, 0x78, 0x78, 0x78, /* 20 */
102 0x78, 0x00, 0x00, 0xfe, /* 24 */
103 0x00, 0x00, 0xfe, 0x00, /* 28 */
104 0x18, 0x18, 0x00, 0x00, /* 32 */
105 0x00, 0x00, 0x00, 0x00, /* 36 */
106 0x00, 0x00, 0x00, 0x80, /* 40 */
107 0x80, 0x00, 0x00, 0x00, /* 44 */
108 0x00, 0x00, 0x00, 0x04, /* 48 */
109 0x00, 0x00, 0x00, 0x00, /* 52 */
110 0x00, 0x00, 0x04, 0x00, /* 56 */
111 0x00, 0x00, 0x00, 0x00, /* 60 */
112 0x00, 0x04, 0x00, 0x00, /* 64 */
113 0x00, 0x00, 0x00, 0x00, /* 68 */
114 0x04, 0x00, 0x00, 0x00, /* 72 */
115 0x00, 0x00, 0x00, 0x00, /* 76 */
116 0x00, 0x00, 0x00, 0x00, /* 80 */
117 0x00, 0x00, 0x00, 0x00, /* 84 */
118 0x00, 0x00, 0x00, 0x00, /* 88 */
119 0x00, 0x00, 0x00, 0x00, /* 92 */
120 0x00, 0x00, 0x00, 0x00, /* 96 */
121 0x00, 0x00, 0x02, /* 100 */
122};
123
124/*
9900daa8
JN		 125 * read from the aic3x register space. Only use for this function is if
126 * wanting to read volatile bits from those registers that has both read-only
127 * and read/write bits. All other cases should use snd_soc_read.
44d0a879 128 */
54e7e616
DM		 129static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
130 u8 *value)
44d0a879
VB		 131{
132 u8 *cache = codec->reg_cache;
44d0a879 133
5a895f8a
JN		 134 if (codec->cache_only)
135 return -EINVAL;
44d0a879 136 if (reg >= AIC3X_CACHEREGNUM)
9900daa8 137 return -1;
5f345346 138
38c436aa
AL		 139 codec->cache_bypass = 1;
140 *value = snd_soc_read(codec, reg);
141 codec->cache_bypass = 0;
142
9900daa8 143 cache[reg] = *value;
54e7e616 144
54e7e616
DM		 145 return 0;
146}
147
44d0a879
VB		 148#define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
149{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
150 .info = snd_soc_info_volsw, \
151 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
152 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
153
154/*
155 * All input lines are connected when !0xf and disconnected with 0xf bit field,
156 * so we have to use specific dapm_put call for input mixer
157 */
158static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
159 struct snd_ctl_elem_value *ucontrol)
160{
9d03545d
JN		 161 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
162 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
4453dba5
EN		 163 struct soc_mixer_control *mc =
164 (struct soc_mixer_control *)kcontrol->private_value;
165 unsigned int reg = mc->reg;
166 unsigned int shift = mc->shift;
167 int max = mc->max;
168 unsigned int mask = (1 << fls(max)) - 1;
169 unsigned int invert = mc->invert;
44d0a879
VB		 170 unsigned short val, val_mask;
171 int ret;
172 struct snd_soc_dapm_path *path;
173 int found = 0;
174
175 val = (ucontrol->value.integer.value[0] & mask);
176
177 mask = 0xf;
178 if (val)
179 val = mask;
180
181 if (invert)
182 val = mask - val;
183 val_mask = mask << shift;
184 val = val << shift;
185
186 mutex_lock(&widget->codec->mutex);
187
188 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
189 /* find dapm widget path assoc with kcontrol */
8ddab3f5 190 list_for_each_entry(path, &widget->dapm->card->paths, list) {
44d0a879
VB		 191 if (path->kcontrol != kcontrol)
192 continue;
193
194 /* found, now check type */
195 found = 1;
196 if (val)
197 /* new connection */
198 path->connect = invert ? 0 : 1;
199 else
200 /* old connection must be powered down */
201 path->connect = invert ? 1 : 0;
25c77c5f
MB		 202
203 dapm_mark_dirty(path->source, "tlv320aic3x source");
204 dapm_mark_dirty(path->sink, "tlv320aic3x sink");
205
44d0a879
VB		 206 break;
207 }
208
209 if (found)
ce6120cc 210 snd_soc_dapm_sync(widget->dapm);
44d0a879
VB		 211 }
212
213 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
214
215 mutex_unlock(&widget->codec->mutex);
216 return ret;
217}
218
219static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
220static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
221static const char *aic3x_left_hpcom_mux[] =
222 { "differential of HPLOUT", "constant VCM", "single-ended" };
223static const char *aic3x_right_hpcom_mux[] =
224 { "differential of HPROUT", "constant VCM", "single-ended",
225 "differential of HPLCOM", "external feedback" };
226static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
4d20f70a
JN		 227static const char *aic3x_adc_hpf[] =
228 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
44d0a879
VB		 229
230#define LDAC_ENUM 0
231#define RDAC_ENUM 1
232#define LHPCOM_ENUM 2
233#define RHPCOM_ENUM 3
404b5665
JN		 234#define LINE1L_2_L_ENUM 4
235#define LINE1L_2_R_ENUM 5
236#define LINE1R_2_L_ENUM 6
237#define LINE1R_2_R_ENUM 7
238#define LINE2L_ENUM 8
239#define LINE2R_ENUM 9
240#define ADC_HPF_ENUM 10
44d0a879
VB		 241
242static const struct soc_enum aic3x_enum[] = {
243 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
244 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
245 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
246 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
247 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
404b5665
JN		 248 SOC_ENUM_SINGLE(LINE1L_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
249 SOC_ENUM_SINGLE(LINE1R_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
44d0a879
VB		 250 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
251 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
252 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
4d20f70a 253 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
44d0a879
VB		 254};
255
7565fc38
JN		 256/*
257 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
258 */
259static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
260/* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
261static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
262/*
263 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
264 * Step size is approximately 0.5 dB over most of the scale but increasing
265 * near the very low levels.
266 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
267 * but having increasing dB difference below that (and where it doesn't count
268 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
269 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
270 */
271static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
272
44d0a879
VB		 273static const struct snd_kcontrol_new aic3x_snd_controls[] = {
274 /* Output */
7565fc38
JN		 275 SOC_DOUBLE_R_TLV("PCM Playback Volume",
276 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
44d0a879 277
098b1718
JN		 278 /*
279 * Output controls that map to output mixer switches. Note these are
280 * only for swapped L-to-R and R-to-L routes. See below stereo controls
281 * for direct L-to-L and R-to-R routes.
282 */
283 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
284 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
285 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
286 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
287 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
288 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
289
290 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
291 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
292 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
293 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
294 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
295 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
296
297 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
298 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
299 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
300 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
301 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
302 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
303
304 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
305 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
306 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
307 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
308 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
309 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
310
311 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
312 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
313 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
314 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
315 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
316 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
317
318 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
319 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
320 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
321 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
322 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
323 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
324
325 /* Stereo output controls for direct L-to-L and R-to-R routes */
326 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
327 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
328 0, 118, 1, output_stage_tlv),
329 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
330 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
331 0, 118, 1, output_stage_tlv),
7565fc38
JN		 332 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
333 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
334 0, 118, 1, output_stage_tlv),
098b1718
JN		 335
336 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
337 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
7565fc38 338 0, 118, 1, output_stage_tlv),
098b1718
JN		 339 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
340 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
7565fc38 341 0, 118, 1, output_stage_tlv),
7565fc38
JN		 342 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
343 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
344 0, 118, 1, output_stage_tlv),
098b1718
JN		 345
346 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
347 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
7565fc38 348 0, 118, 1, output_stage_tlv),
098b1718
JN		 349 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
350 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
7565fc38 351 0, 118, 1, output_stage_tlv),
7565fc38
JN		 352 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
353 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
354 0, 118, 1, output_stage_tlv),
098b1718
JN		 355
356 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
357 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
7565fc38 358 0, 118, 1, output_stage_tlv),
098b1718
JN		 359 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
360 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
7565fc38 361 0, 118, 1, output_stage_tlv),
7565fc38
JN		 362 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
363 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
364 0, 118, 1, output_stage_tlv),
098b1718
JN		 365
366 /* Output pin mute controls */
367 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
368 0x01, 0),
369 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
370 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
371 0x01, 0),
f9bc0297 372 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
44d0a879 373 0x01, 0),
44d0a879
VB		 374
375 /*
376 * Note: enable Automatic input Gain Controller with care. It can
377 * adjust PGA to max value when ADC is on and will never go back.
378 */
379 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
380
381 /* Input */
7565fc38
JN		 382 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
383 0, 119, 0, adc_tlv),
44d0a879 384 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
4d20f70a
JN		 385
386 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
44d0a879
VB		 387};
388
6184f105
RC		 389/*
390 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
391 */
392static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
393
394static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
395 SOC_DOUBLE_TLV("Class-D Amplifier Gain", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
396
44d0a879
VB		 397/* Left DAC Mux */
398static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
399SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
400
401/* Right DAC Mux */
402static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
403SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
404
405/* Left HPCOM Mux */
406static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
407SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
408
409/* Right HPCOM Mux */
410static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
411SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
412
c3b79e05
JN		 413/* Left Line Mixer */
414static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
415 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
416 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
417 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
418 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
419 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
420 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
44d0a879
VB		 421};
422
c3b79e05
JN		 423/* Right Line Mixer */
424static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
425 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
426 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
427 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
428 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
429 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
430 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
431};
432
433/* Mono Mixer */
434static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
435 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
436 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
437 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
438 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
439 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
440 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
441};
442
443/* Left HP Mixer */
444static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
445 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
446 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
447 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
448 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
449 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
450 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
451};
452
453/* Right HP Mixer */
454static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
455 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
456 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
457 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
458 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
459 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
460 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
461};
462
463/* Left HPCOM Mixer */
464static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
465 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
466 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
467 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
468 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
469 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
470 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
471};
472
473/* Right HPCOM Mixer */
474static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
475 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
476 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
477 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
478 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
479 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
480 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
44d0a879
VB		 481};
482
483/* Left PGA Mixer */
484static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
485 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
54f01916 486 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
44d0a879
VB		 487 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
488 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
54f01916 489 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
44d0a879
VB		 490};
491
492/* Right PGA Mixer */
493static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
494 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
54f01916 495 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
44d0a879 496 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
54f01916 497 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
44d0a879
VB		 498 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
499};
500
501/* Left Line1 Mux */
404b5665
JN		 502static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls =
503SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_L_ENUM]);
504static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls =
505SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_R_ENUM]);
44d0a879
VB		 506
507/* Right Line1 Mux */
404b5665
JN		 508static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls =
509SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_R_ENUM]);
510static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls =
511SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_L_ENUM]);
44d0a879
VB		 512
513/* Left Line2 Mux */
514static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
515SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
516
517/* Right Line2 Mux */
518static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
519SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
520
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VB		 521static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
522 /* Left DAC to Left Outputs */
523 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
524 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
525 &aic3x_left_dac_mux_controls),
44d0a879
VB		 526 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
527 &aic3x_left_hpcom_mux_controls),
528 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
529 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
530 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
531
532 /* Right DAC to Right Outputs */
533 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
534 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
535 &aic3x_right_dac_mux_controls),
44d0a879
VB		 536 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
537 &aic3x_right_hpcom_mux_controls),
538 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
539 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
540 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
541
542 /* Mono Output */
543 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
544
54f01916 545 /* Inputs to Left ADC */
44d0a879
VB		 546 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
547 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
548 &aic3x_left_pga_mixer_controls[0],
549 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
550 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
404b5665 551 &aic3x_left_line1l_mux_controls),
54f01916 552 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
404b5665 553 &aic3x_left_line1r_mux_controls),
44d0a879
VB		 554 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
555 &aic3x_left_line2_mux_controls),
556
54f01916 557 /* Inputs to Right ADC */
44d0a879
VB		 558 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
559 LINE1R_2_RADC_CTRL, 2, 0),
560 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
561 &aic3x_right_pga_mixer_controls[0],
562 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
54f01916 563 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
404b5665 564 &aic3x_right_line1l_mux_controls),
44d0a879 565 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
404b5665 566 &aic3x_right_line1r_mux_controls),
44d0a879
VB		 567 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
568 &aic3x_right_line2_mux_controls),
569
ee15ffdb
JN		 570 /*
571 * Not a real mic bias widget but similar function. This is for dynamic
572 * control of GPIO1 digital mic modulator clock output function when
573 * using digital mic.
574 */
575 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
576 AIC3X_GPIO1_REG, 4, 0xf,
577 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
578 AIC3X_GPIO1_FUNC_DISABLED),
579
580 /*
581 * Also similar function like mic bias. Selects digital mic with
582 * configurable oversampling rate instead of ADC converter.
583 */
584 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
585 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
586 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
587 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
588 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
589 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
590
44d0a879 591 /* Mic Bias */
0bd72a3d
JN		 592 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
593 MICBIAS_CTRL, 6, 3, 1, 0),
594 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
595 MICBIAS_CTRL, 6, 3, 2, 0),
596 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
597 MICBIAS_CTRL, 6, 3, 3, 0),
44d0a879 598
c3b79e05
JN		 599 /* Output mixers */
600 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
601 &aic3x_left_line_mixer_controls[0],
602 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
603 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
604 &aic3x_right_line_mixer_controls[0],
605 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
606 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
607 &aic3x_mono_mixer_controls[0],
608 ARRAY_SIZE(aic3x_mono_mixer_controls)),
609 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
610 &aic3x_left_hp_mixer_controls[0],
611 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
612 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
613 &aic3x_right_hp_mixer_controls[0],
614 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
615 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
616 &aic3x_left_hpcom_mixer_controls[0],
617 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
618 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
619 &aic3x_right_hpcom_mixer_controls[0],
620 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
44d0a879
VB		 621
622 SND_SOC_DAPM_OUTPUT("LLOUT"),
623 SND_SOC_DAPM_OUTPUT("RLOUT"),
624 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
625 SND_SOC_DAPM_OUTPUT("HPLOUT"),
626 SND_SOC_DAPM_OUTPUT("HPROUT"),
627 SND_SOC_DAPM_OUTPUT("HPLCOM"),
628 SND_SOC_DAPM_OUTPUT("HPRCOM"),
629
630 SND_SOC_DAPM_INPUT("MIC3L"),
631 SND_SOC_DAPM_INPUT("MIC3R"),
632 SND_SOC_DAPM_INPUT("LINE1L"),
633 SND_SOC_DAPM_INPUT("LINE1R"),
634 SND_SOC_DAPM_INPUT("LINE2L"),
635 SND_SOC_DAPM_INPUT("LINE2R"),
19f7ac50
JN		 636
637 /*
638 * Virtual output pin to detection block inside codec. This can be
639 * used to keep codec bias on if gpio or detection features are needed.
640 * Force pin on or construct a path with an input jack and mic bias
641 * widgets.
642 */
643 SND_SOC_DAPM_OUTPUT("Detection"),
44d0a879
VB		 644};
645
6184f105
RC		 646static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
647 /* Class-D outputs */
648 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
649 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
650
651 SND_SOC_DAPM_OUTPUT("SPOP"),
652 SND_SOC_DAPM_OUTPUT("SPOM"),
653};
654
d0cc0d3a 655static const struct snd_soc_dapm_route intercon[] = {
44d0a879
VB		 656 /* Left Input */
657 {"Left Line1L Mux", "single-ended", "LINE1L"},
658 {"Left Line1L Mux", "differential", "LINE1L"},
659
660 {"Left Line2L Mux", "single-ended", "LINE2L"},
661 {"Left Line2L Mux", "differential", "LINE2L"},
662
663 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
54f01916 664 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
44d0a879
VB		 665 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
666 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
54f01916 667 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
44d0a879
VB		 668
669 {"Left ADC", NULL, "Left PGA Mixer"},
ee15ffdb 670 {"Left ADC", NULL, "GPIO1 dmic modclk"},
44d0a879
VB		 671
672 /* Right Input */
673 {"Right Line1R Mux", "single-ended", "LINE1R"},
674 {"Right Line1R Mux", "differential", "LINE1R"},
675
676 {"Right Line2R Mux", "single-ended", "LINE2R"},
677 {"Right Line2R Mux", "differential", "LINE2R"},
678
54f01916 679 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
44d0a879
VB		 680 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
681 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
54f01916 682 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
44d0a879
VB		 683 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
684
685 {"Right ADC", NULL, "Right PGA Mixer"},
ee15ffdb 686 {"Right ADC", NULL, "GPIO1 dmic modclk"},
44d0a879 687
ee15ffdb
JN		 688 /*
689 * Logical path between digital mic enable and GPIO1 modulator clock
690 * output function
691 */
692 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
693 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
694 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
c3b79e05
JN		 695
696 /* Left DAC Output */
697 {"Left DAC Mux", "DAC_L1", "Left DAC"},
698 {"Left DAC Mux", "DAC_L2", "Left DAC"},
699 {"Left DAC Mux", "DAC_L3", "Left DAC"},
700
701 /* Right DAC Output */
702 {"Right DAC Mux", "DAC_R1", "Right DAC"},
703 {"Right DAC Mux", "DAC_R2", "Right DAC"},
704 {"Right DAC Mux", "DAC_R3", "Right DAC"},
705
706 /* Left Line Output */
707 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
708 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
709 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
710 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
711 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
712 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
713
714 {"Left Line Out", NULL, "Left Line Mixer"},
715 {"Left Line Out", NULL, "Left DAC Mux"},
716 {"LLOUT", NULL, "Left Line Out"},
717
718 /* Right Line Output */
719 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
720 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
721 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
722 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
723 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
724 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
725
726 {"Right Line Out", NULL, "Right Line Mixer"},
727 {"Right Line Out", NULL, "Right DAC Mux"},
728 {"RLOUT", NULL, "Right Line Out"},
729
730 /* Mono Output */
731 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
732 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
733 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
734 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
735 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
736 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
737
738 {"Mono Out", NULL, "Mono Mixer"},
739 {"MONO_LOUT", NULL, "Mono Out"},
740
741 /* Left HP Output */
742 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
743 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
744 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
745 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
746 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
747 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
748
749 {"Left HP Out", NULL, "Left HP Mixer"},
750 {"Left HP Out", NULL, "Left DAC Mux"},
751 {"HPLOUT", NULL, "Left HP Out"},
752
753 /* Right HP Output */
754 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
755 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
756 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
757 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
758 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
759 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
760
761 {"Right HP Out", NULL, "Right HP Mixer"},
762 {"Right HP Out", NULL, "Right DAC Mux"},
763 {"HPROUT", NULL, "Right HP Out"},
764
765 /* Left HPCOM Output */
766 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
767 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
768 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
769 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
770 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
771 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
772
773 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
774 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
775 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
776 {"Left HP Com", NULL, "Left HPCOM Mux"},
777 {"HPLCOM", NULL, "Left HP Com"},
778
779 /* Right HPCOM Output */
780 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
781 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
782 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
783 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
784 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
785 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
786
787 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
788 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
789 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
790 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
791 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
792 {"Right HP Com", NULL, "Right HPCOM Mux"},
793 {"HPRCOM", NULL, "Right HP Com"},
44d0a879
VB		 794};
795
6184f105
RC		 796static const struct snd_soc_dapm_route intercon_3007[] = {
797 /* Class-D outputs */
798 {"Left Class-D Out", NULL, "Left Line Out"},
799 {"Right Class-D Out", NULL, "Left Line Out"},
800 {"SPOP", NULL, "Left Class-D Out"},
801 {"SPOM", NULL, "Right Class-D Out"},
802};
803
44d0a879
VB		 804static int aic3x_add_widgets(struct snd_soc_codec *codec)
805{
6184f105 806 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
ce6120cc 807 struct snd_soc_dapm_context *dapm = &codec->dapm;
6184f105 808
ce6120cc 809 snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets,
d0cc0d3a 810 ARRAY_SIZE(aic3x_dapm_widgets));
44d0a879
VB		 811
812 /* set up audio path interconnects */
ce6120cc 813 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
44d0a879 814
6184f105 815 if (aic3x->model == AIC3X_MODEL_3007) {
ce6120cc 816 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
6184f105 817 ARRAY_SIZE(aic3007_dapm_widgets));
ce6120cc
LG		 818 snd_soc_dapm_add_routes(dapm, intercon_3007,
819 ARRAY_SIZE(intercon_3007));
6184f105
RC		 820 }
821
44d0a879
VB		 822 return 0;
823}
824
44d0a879 825static int aic3x_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 826 struct snd_pcm_hw_params *params,
827 struct snd_soc_dai *dai)
44d0a879
VB		 828{
829 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 830 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 831 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
4f9c16cc 832 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
255173b4
PM		 833 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
834 u16 d, pll_d = 1;
255173b4 835 int clk;
44d0a879 836
4f9c16cc 837 /* select data word length */
e18eca43 838 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
4f9c16cc
DM		 839 switch (params_format(params)) {
840 case SNDRV_PCM_FORMAT_S16_LE:
44d0a879 841 break;
4f9c16cc
DM		 842 case SNDRV_PCM_FORMAT_S20_3LE:
843 data |= (0x01 << 4);
44d0a879 844 break;
4f9c16cc
DM		 845 case SNDRV_PCM_FORMAT_S24_LE:
846 data |= (0x02 << 4);
44d0a879 847 break;
4f9c16cc
DM		 848 case SNDRV_PCM_FORMAT_S32_LE:
849 data |= (0x03 << 4);
44d0a879
VB		 850 break;
851 }
e18eca43 852 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data);
4f9c16cc
DM		 853
854 /* Fsref can be 44100 or 48000 */
855 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
856
857 /* Try to find a value for Q which allows us to bypass the PLL and
858 * generate CODEC_CLK directly. */
859 for (pll_q = 2; pll_q < 18; pll_q++)
860 if (aic3x->sysclk / (128 * pll_q) == fsref) {
861 bypass_pll = 1;
862 break;
863 }
864
865 if (bypass_pll) {
866 pll_q &= 0xf;
e18eca43
JN		 867 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
868 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
06c71282 869 /* disable PLL if it is bypassed */
9c173d15 870 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0);
06c71282
C		 871
872 } else {
e18eca43 873 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
06c71282 874 /* enable PLL when it is used */
9c173d15
AL		 875 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
876 PLL_ENABLE, PLL_ENABLE);
06c71282 877 }
4f9c16cc
DM		 878
879 /* Route Left DAC to left channel input and
880 * right DAC to right channel input */
881 data = (LDAC2LCH | RDAC2RCH);
882 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
883 if (params_rate(params) >= 64000)
884 data |= DUAL_RATE_MODE;
e18eca43 885 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
44d0a879
VB		 886
887 /* codec sample rate select */
4f9c16cc
DM		 888 data = (fsref * 20) / params_rate(params);
889 if (params_rate(params) < 64000)
890 data /= 2;
891 data /= 5;
892 data -= 2;
44d0a879 893 data |= (data << 4);
e18eca43 894 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
44d0a879 895
4f9c16cc
DM		 896 if (bypass_pll)
897 return 0;
898
25985edc 899 /* Use PLL, compute appropriate setup for j, d, r and p, the closest
255173b4
PM		 900 * one wins the game. Try with d==0 first, next with d!=0.
901 * Constraints for j are according to the datasheet.
4f9c16cc 902 * The sysclk is divided by 1000 to prevent integer overflows.
44d0a879 903 */
255173b4 904
4f9c16cc
DM		 905 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
906
907 for (r = 1; r <= 16; r++)
908 for (p = 1; p <= 8; p++) {
255173b4
PM		 909 for (j = 4; j <= 55; j++) {
910 /* This is actually 1000*((j+(d/10000))*r)/p
911 * The term had to be converted to get
912 * rid of the division by 10000; d = 0 here
913 */
5baf8315 914 int tmp_clk = (1000 * j * r) / p;
255173b4
PM		 915
916 /* Check whether this values get closer than
917 * the best ones we had before
918 */
5baf8315 919 if (abs(codec_clk - tmp_clk) <
255173b4
PM		 920 abs(codec_clk - last_clk)) {
921 pll_j = j; pll_d = 0;
922 pll_r = r; pll_p = p;
5baf8315 923 last_clk = tmp_clk;
255173b4
PM		 924 }
925
926 /* Early exit for exact matches */
5baf8315 927 if (tmp_clk == codec_clk)
255173b4
PM		 928 goto found;
929 }
930 }
4f9c16cc 931
255173b4
PM		 932 /* try with d != 0 */
933 for (p = 1; p <= 8; p++) {
934 j = codec_clk * p / 1000;
4f9c16cc 935
255173b4
PM		 936 if (j < 4 || j > 11)
937 continue;
4f9c16cc 938
255173b4
PM		 939 /* do not use codec_clk here since we'd loose precision */
940 d = ((2048 * p * fsref) - j * aic3x->sysclk)
941 * 100 / (aic3x->sysclk/100);
4f9c16cc 942
255173b4 943 clk = (10000 * j + d) / (10 * p);
4f9c16cc 944
255173b4
PM		 945 /* check whether this values get closer than the best
946 * ones we had before */
947 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
948 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
949 last_clk = clk;
4f9c16cc
DM		 950 }
951
255173b4
PM		 952 /* Early exit for exact matches */
953 if (clk == codec_clk)
954 goto found;
955 }
956
4f9c16cc
DM		 957 if (last_clk == 0) {
958 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
959 return -EINVAL;
960 }
44d0a879 961
255173b4 962found:
e18eca43
JN		 963 data = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
964 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
965 data | (pll_p << PLLP_SHIFT));
966 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
967 pll_r << PLLR_SHIFT);
968 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
969 snd_soc_write(codec, AIC3X_PLL_PROGC_REG,
970 (pll_d >> 6) << PLLD_MSB_SHIFT);
971 snd_soc_write(codec, AIC3X_PLL_PROGD_REG,
972 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
44d0a879 973
44d0a879
VB		 974 return 0;
975}
976
e550e17f 977static int aic3x_mute(struct snd_soc_dai *dai, int mute)
44d0a879
VB		 978{
979 struct snd_soc_codec *codec = dai->codec;
e18eca43
JN		 980 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON;
981 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON;
44d0a879
VB		 982
983 if (mute) {
e18eca43
JN		 984 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
985 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
44d0a879 986 } else {
e18eca43
JN		 987 snd_soc_write(codec, LDAC_VOL, ldac_reg);
988 snd_soc_write(codec, RDAC_VOL, rdac_reg);
44d0a879
VB		 989 }
990
991 return 0;
992}
993
e550e17f 994static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
44d0a879
VB		 995 int clk_id, unsigned int freq, int dir)
996{
997 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 998 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879 999
4f9c16cc
DM		 1000 aic3x->sysclk = freq;
1001 return 0;
44d0a879
VB		 1002}
1003
e550e17f 1004static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
44d0a879
VB		 1005 unsigned int fmt)
1006{
1007 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1008 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
81971a14 1009 u8 iface_areg, iface_breg;
a24f4f68 1010 int delay = 0;
81971a14 1011
e18eca43
JN		 1012 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1013 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
44d0a879
VB		 1014
1015 /* set master/slave audio interface */
1016 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1017 case SND_SOC_DAIFMT_CBM_CFM:
1018 aic3x->master = 1;
1019 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1020 break;
1021 case SND_SOC_DAIFMT_CBS_CFS:
1022 aic3x->master = 0;
68e47981 1023 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER);
44d0a879
VB		 1024 break;
1025 default:
1026 return -EINVAL;
1027 }
1028
4b7d2831
JN		 1029 /*
1030 * match both interface format and signal polarities since they
1031 * are fixed
1032 */
1033 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1034 SND_SOC_DAIFMT_INV_MASK)) {
1035 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
44d0a879 1036 break;
a24f4f68
TK		 1037 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1038 delay = 1;
4b7d2831 1039 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
44d0a879
VB		 1040 iface_breg |= (0x01 << 6);
1041 break;
4b7d2831 1042 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1043 iface_breg |= (0x02 << 6);
1044 break;
4b7d2831 1045 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1046 iface_breg |= (0x03 << 6);
1047 break;
1048 default:
1049 return -EINVAL;
1050 }
1051
1052 /* set iface */
e18eca43
JN		 1053 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1054 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1055 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
44d0a879
VB		 1056
1057 return 0;
1058}
1059
6c1a7d40
JN		 1060static int aic3x_init_3007(struct snd_soc_codec *codec)
1061{
1062 u8 tmp1, tmp2, *cache = codec->reg_cache;
1063
1064 /*
1065 * There is no need to cache writes to undocumented page 0xD but
1066 * respective page 0 register cache entries must be preserved
1067 */
1068 tmp1 = cache[0xD];
1069 tmp2 = cache[0x8];
1070 /* Class-D speaker driver init; datasheet p. 46 */
1071 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x0D);
1072 snd_soc_write(codec, 0xD, 0x0D);
1073 snd_soc_write(codec, 0x8, 0x5C);
1074 snd_soc_write(codec, 0x8, 0x5D);
1075 snd_soc_write(codec, 0x8, 0x5C);
1076 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x00);
1077 cache[0xD] = tmp1;
1078 cache[0x8] = tmp2;
1079
1080 return 0;
1081}
1082
5a895f8a
JN		 1083static int aic3x_regulator_event(struct notifier_block *nb,
1084 unsigned long event, void *data)
1085{
1086 struct aic3x_disable_nb *disable_nb =
1087 container_of(nb, struct aic3x_disable_nb, nb);
1088 struct aic3x_priv *aic3x = disable_nb->aic3x;
1089
1090 if (event & REGULATOR_EVENT_DISABLE) {
1091 /*
1092 * Put codec to reset and require cache sync as at least one
1093 * of the supplies was disabled
1094 */
79ee820d 1095 if (gpio_is_valid(aic3x->gpio_reset))
5a895f8a
JN		 1096 gpio_set_value(aic3x->gpio_reset, 0);
1097 aic3x->codec->cache_sync = 1;
1098 }
1099
1100 return 0;
1101}
1102
6c1a7d40
JN		 1103static int aic3x_set_power(struct snd_soc_codec *codec, int power)
1104{
1105 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1106 int i, ret;
1107 u8 *cache = codec->reg_cache;
1108
1109 if (power) {
1110 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1111 aic3x->supplies);
1112 if (ret)
1113 goto out;
1114 aic3x->power = 1;
5a895f8a
JN		 1115 /*
1116 * Reset release and cache sync is necessary only if some
1117 * supply was off or if there were cached writes
1118 */
1119 if (!codec->cache_sync)
1120 goto out;
1121
79ee820d 1122 if (gpio_is_valid(aic3x->gpio_reset)) {
6c1a7d40
JN		 1123 udelay(1);
1124 gpio_set_value(aic3x->gpio_reset, 1);
1125 }
1126
1127 /* Sync reg_cache with the hardware */
1128 codec->cache_only = 0;
508b7686 1129 for (i = AIC3X_SAMPLE_RATE_SEL_REG; i < ARRAY_SIZE(aic3x_reg); i++)
6c1a7d40
JN		 1130 snd_soc_write(codec, i, cache[i]);
1131 if (aic3x->model == AIC3X_MODEL_3007)
1132 aic3x_init_3007(codec);
1133 codec->cache_sync = 0;
1134 } else {
9fb352b1
JN		 1135 /*
1136 * Do soft reset to this codec instance in order to clear
1137 * possible VDD leakage currents in case the supply regulators
1138 * remain on
1139 */
1140 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
1141 codec->cache_sync = 1;
6c1a7d40 1142 aic3x->power = 0;
5a895f8a
JN		 1143 /* HW writes are needless when bias is off */
1144 codec->cache_only = 1;
6c1a7d40
JN		 1145 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1146 aic3x->supplies);
1147 }
1148out:
1149 return ret;
1150}
1151
0be9898a
MB		 1152static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1153 enum snd_soc_bias_level level)
44d0a879 1154{
b2c812e2 1155 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879 1156
0be9898a
MB		 1157 switch (level) {
1158 case SND_SOC_BIAS_ON:
db13802e
JN		 1159 break;
1160 case SND_SOC_BIAS_PREPARE:
ce6120cc 1161 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY &&
c23fd751 1162 aic3x->master) {
44d0a879 1163 /* enable pll */
9c173d15
AL		 1164 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1165 PLL_ENABLE, PLL_ENABLE);
44d0a879
VB		 1166 }
1167 break;
0be9898a 1168 case SND_SOC_BIAS_STANDBY:
6c1a7d40
JN		 1169 if (!aic3x->power)
1170 aic3x_set_power(codec, 1);
ce6120cc 1171 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE &&
c23fd751 1172 aic3x->master) {
44d0a879 1173 /* disable pll */
9c173d15
AL		 1174 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1175 PLL_ENABLE, 0);
44d0a879
VB		 1176 }
1177 break;
c23fd751 1178 case SND_SOC_BIAS_OFF:
6c1a7d40
JN		 1179 if (aic3x->power)
1180 aic3x_set_power(codec, 0);
c23fd751 1181 break;
44d0a879 1182 }
ce6120cc 1183 codec->dapm.bias_level = level;
44d0a879
VB		 1184
1185 return 0;
1186}
1187
54e7e616
DM		 1188void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
1189{
1190 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1191 u8 bit = gpio ? 3: 0;
e18eca43
JN		 1192 u8 val = snd_soc_read(codec, reg) & ~(1 << bit);
1193 snd_soc_write(codec, reg, val | (!!state << bit));
54e7e616
DM		 1194}
1195EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1196
1197int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1198{
1199 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
fe99b559 1200 u8 val = 0, bit = gpio ? 2 : 1;
54e7e616
DM		 1201
1202 aic3x_read(codec, reg, &val);
1203 return (val >> bit) & 1;
1204}
1205EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1206
6f2a974b
DM		 1207void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
1208 int headset_debounce, int button_debounce)
1209{
1210 u8 val;
1211
1212 val = ((detect & AIC3X_HEADSET_DETECT_MASK)
1213 << AIC3X_HEADSET_DETECT_SHIFT) |
1214 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK)
1215 << AIC3X_HEADSET_DEBOUNCE_SHIFT) |
1216 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK)
1217 << AIC3X_BUTTON_DEBOUNCE_SHIFT);
1218
1219 if (detect & AIC3X_HEADSET_DETECT_MASK)
1220 val |= AIC3X_HEADSET_DETECT_ENABLED;
1221
e18eca43 1222 snd_soc_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val);
6f2a974b
DM		 1223}
1224EXPORT_SYMBOL_GPL(aic3x_set_headset_detection);
1225
54e7e616
DM		 1226int aic3x_headset_detected(struct snd_soc_codec *codec)
1227{
fe99b559 1228 u8 val = 0;
6f2a974b
DM		 1229 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1230 return (val >> 4) & 1;
54e7e616
DM		 1231}
1232EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1233
6f2a974b
DM		 1234int aic3x_button_pressed(struct snd_soc_codec *codec)
1235{
fe99b559 1236 u8 val = 0;
6f2a974b
DM		 1237 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1238 return (val >> 5) & 1;
1239}
1240EXPORT_SYMBOL_GPL(aic3x_button_pressed);
1241
44d0a879
VB		 1242#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1243#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1244 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1245
85e7652d 1246static const struct snd_soc_dai_ops aic3x_dai_ops = {
6335d055
EM		 1247 .hw_params = aic3x_hw_params,
1248 .digital_mute = aic3x_mute,
1249 .set_sysclk = aic3x_set_dai_sysclk,
1250 .set_fmt = aic3x_set_dai_fmt,
1251};
1252
f0fba2ad
LG		 1253static struct snd_soc_dai_driver aic3x_dai = {
1254 .name = "tlv320aic3x-hifi",
44d0a879
VB		 1255 .playback = {
1256 .stream_name = "Playback",
1257 .channels_min = 1,
1258 .channels_max = 2,
1259 .rates = AIC3X_RATES,
1260 .formats = AIC3X_FORMATS,},
1261 .capture = {
1262 .stream_name = "Capture",
1263 .channels_min = 1,
1264 .channels_max = 2,
1265 .rates = AIC3X_RATES,
1266 .formats = AIC3X_FORMATS,},
6335d055 1267 .ops = &aic3x_dai_ops,
14017615 1268 .symmetric_rates = 1,
44d0a879 1269};
44d0a879 1270
84b315ee 1271static int aic3x_suspend(struct snd_soc_codec *codec)
44d0a879 1272{
0be9898a 1273 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
44d0a879
VB		 1274
1275 return 0;
1276}
1277
f0fba2ad 1278static int aic3x_resume(struct snd_soc_codec *codec)
44d0a879 1279{
29e189c2 1280 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
44d0a879
VB		 1281
1282 return 0;
1283}
1284
1285/*
1286 * initialise the AIC3X driver
1287 * register the mixer and dsp interfaces with the kernel
1288 */
cb3826f5 1289static int aic3x_init(struct snd_soc_codec *codec)
44d0a879 1290{
6184f105 1291 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
cb3826f5 1292
e18eca43
JN		 1293 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1294 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
44d0a879 1295
44d0a879 1296 /* DAC default volume and mute */
e18eca43
JN		 1297 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1298 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
44d0a879
VB		 1299
1300 /* DAC to HP default volume and route to Output mixer */
e18eca43
JN		 1301 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1302 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1303 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1304 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879 1305 /* DAC to Line Out default volume and route to Output mixer */
e18eca43
JN		 1306 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1307 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879 1308 /* DAC to Mono Line Out default volume and route to Output mixer */
e18eca43
JN		 1309 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1310 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879
VB		 1311
1312 /* unmute all outputs */
9c173d15
AL		 1313 snd_soc_update_bits(codec, LLOPM_CTRL, UNMUTE, UNMUTE);
1314 snd_soc_update_bits(codec, RLOPM_CTRL, UNMUTE, UNMUTE);
1315 snd_soc_update_bits(codec, MONOLOPM_CTRL, UNMUTE, UNMUTE);
1316 snd_soc_update_bits(codec, HPLOUT_CTRL, UNMUTE, UNMUTE);
1317 snd_soc_update_bits(codec, HPROUT_CTRL, UNMUTE, UNMUTE);
1318 snd_soc_update_bits(codec, HPLCOM_CTRL, UNMUTE, UNMUTE);
1319 snd_soc_update_bits(codec, HPRCOM_CTRL, UNMUTE, UNMUTE);
44d0a879
VB		 1320
1321 /* ADC default volume and unmute */
e18eca43
JN		 1322 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN);
1323 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN);
44d0a879 1324 /* By default route Line1 to ADC PGA mixer */
e18eca43
JN		 1325 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1326 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0);
44d0a879
VB		 1327
1328 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
e18eca43
JN		 1329 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1330 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1331 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1332 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
44d0a879 1333 /* PGA to Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1334 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1335 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
44d0a879 1336 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1337 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1338 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
44d0a879
VB		 1339
1340 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
e18eca43
JN		 1341 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1342 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1343 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1344 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
44d0a879 1345 /* Line2 Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1346 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1347 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
44d0a879 1348 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1349 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1350 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
44d0a879 1351
6184f105 1352 if (aic3x->model == AIC3X_MODEL_3007) {
6c1a7d40 1353 aic3x_init_3007(codec);
e18eca43 1354 snd_soc_write(codec, CLASSD_CTRL, 0);
6184f105
RC		 1355 }
1356
cb3826f5
BD		 1357 return 0;
1358}
54e7e616 1359
414c73ab
JN		 1360static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
1361{
1362 struct aic3x_priv *a;
1363
1364 list_for_each_entry(a, &reset_list, list) {
1365 if (gpio_is_valid(aic3x->gpio_reset) &&
1366 aic3x->gpio_reset == a->gpio_reset)
1367 return true;
1368 }
1369
1370 return false;
1371}
1372
f0fba2ad 1373static int aic3x_probe(struct snd_soc_codec *codec)
cb3826f5 1374{
f0fba2ad 1375 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
2f24111a 1376 int ret, i;
f0fba2ad 1377
414c73ab 1378 INIT_LIST_HEAD(&aic3x->list);
5a895f8a 1379 aic3x->codec = codec;
cb3826f5 1380
a84a441b
JN		 1381 ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type);
1382 if (ret != 0) {
1383 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1384 return ret;
1385 }
1386
414c73ab
JN		 1387 if (gpio_is_valid(aic3x->gpio_reset) &&
1388 !aic3x_is_shared_reset(aic3x)) {
2f24111a
JN		 1389 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
1390 if (ret != 0)
1391 goto err_gpio;
1392 gpio_direction_output(aic3x->gpio_reset, 0);
1393 }
1394
1395 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1396 aic3x->supplies[i].supply = aic3x_supply_names[i];
1397
1398 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies),
1399 aic3x->supplies);
1400 if (ret != 0) {
1401 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1402 goto err_get;
1403 }
5a895f8a
JN		 1404 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1405 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1406 aic3x->disable_nb[i].aic3x = aic3x;
1407 ret = regulator_register_notifier(aic3x->supplies[i].consumer,
1408 &aic3x->disable_nb[i].nb);
1409 if (ret) {
1410 dev_err(codec->dev,
1411 "Failed to request regulator notifier: %d\n",
1412 ret);
1413 goto err_notif;
1414 }
1415 }
2f24111a 1416
7d1be0a6 1417 codec->cache_only = 1;
37b47656
JN		 1418 aic3x_init(codec);
1419
f0fba2ad
LG		 1420 if (aic3x->setup) {
1421 /* setup GPIO functions */
e18eca43
JN		 1422 snd_soc_write(codec, AIC3X_GPIO1_REG,
1423 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1424 snd_soc_write(codec, AIC3X_GPIO2_REG,
1425 (aic3x->setup->gpio_func[1] & 0xf) << 4);
44d0a879
VB		 1426 }
1427
022658be 1428 snd_soc_add_codec_controls(codec, aic3x_snd_controls,
f0fba2ad 1429 ARRAY_SIZE(aic3x_snd_controls));
6184f105 1430 if (aic3x->model == AIC3X_MODEL_3007)
022658be 1431 snd_soc_add_codec_controls(codec, &aic3x_classd_amp_gain_ctrl, 1);
cb3826f5 1432
f0fba2ad 1433 aic3x_add_widgets(codec);
414c73ab 1434 list_add(&aic3x->list, &reset_list);
cb3826f5
BD		 1435
1436 return 0;
2f24111a 1437
5a895f8a
JN		 1438err_notif:
1439 while (i--)
1440 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1441 &aic3x->disable_nb[i].nb);
2f24111a
JN		 1442 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1443err_get:
414c73ab
JN		 1444 if (gpio_is_valid(aic3x->gpio_reset) &&
1445 !aic3x_is_shared_reset(aic3x))
2f24111a
JN		 1446 gpio_free(aic3x->gpio_reset);
1447err_gpio:
2f24111a 1448 return ret;
44d0a879
VB		 1449}
1450
f0fba2ad 1451static int aic3x_remove(struct snd_soc_codec *codec)
cb3826f5 1452{
2f24111a 1453 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
5a895f8a 1454 int i;
2f24111a 1455
f0fba2ad 1456 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
414c73ab
JN		 1457 list_del(&aic3x->list);
1458 if (gpio_is_valid(aic3x->gpio_reset) &&
1459 !aic3x_is_shared_reset(aic3x)) {
2f24111a
JN		 1460 gpio_set_value(aic3x->gpio_reset, 0);
1461 gpio_free(aic3x->gpio_reset);
1462 }
5a895f8a
JN		 1463 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1464 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1465 &aic3x->disable_nb[i].nb);
2f24111a
JN		 1466 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1467
cb3826f5
BD		 1468 return 0;
1469}
44d0a879 1470
f0fba2ad 1471static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
f0fba2ad 1472 .set_bias_level = aic3x_set_bias_level,
eb3032f8 1473 .idle_bias_off = true,
f0fba2ad
LG		 1474 .reg_cache_size = ARRAY_SIZE(aic3x_reg),
1475 .reg_word_size = sizeof(u8),
1476 .reg_cache_default = aic3x_reg,
1477 .probe = aic3x_probe,
1478 .remove = aic3x_remove,
1479 .suspend = aic3x_suspend,
1480 .resume = aic3x_resume,
1481};
1482
44d0a879
VB		 1483/*
1484 * AIC3X 2 wire address can be up to 4 devices with device addresses
1485 * 0x18, 0x19, 0x1A, 0x1B
1486 */
44d0a879 1487
6184f105 1488static const struct i2c_device_id aic3x_i2c_id[] = {
177fdd89
AL		 1489 { "tlv320aic3x", AIC3X_MODEL_3X },
1490 { "tlv320aic33", AIC3X_MODEL_33 },
1491 { "tlv320aic3007", AIC3X_MODEL_3007 },
6184f105
RC		 1492 { }
1493};
1494MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1495
44d0a879
VB		 1496/*
1497 * If the i2c layer weren't so broken, we could pass this kind of data
1498 * around
1499 */
ba8ed121
JD		 1500static int aic3x_i2c_probe(struct i2c_client *i2c,
1501 const struct i2c_device_id *id)
44d0a879 1502{
5193d62f 1503 struct aic3x_pdata *pdata = i2c->dev.platform_data;
f0fba2ad 1504 struct aic3x_priv *aic3x;
2f24111a 1505 int ret;
44d0a879 1506
e2257db3 1507 aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL);
cb3826f5
BD		 1508 if (aic3x == NULL) {
1509 dev_err(&i2c->dev, "failed to create private data\n");
1510 return -ENOMEM;
1511 }
1512
a84a441b
JN		 1513 aic3x->control_type = SND_SOC_I2C;
1514
cb3826f5 1515 i2c_set_clientdata(i2c, aic3x);
c776357e
JN		 1516 if (pdata) {
1517 aic3x->gpio_reset = pdata->gpio_reset;
1518 aic3x->setup = pdata->setup;
1519 } else {
1520 aic3x->gpio_reset = -1;
1521 }
cb3826f5 1522
177fdd89 1523 aic3x->model = id->driver_data;
6184f105 1524
f0fba2ad
LG		 1525 ret = snd_soc_register_codec(&i2c->dev,
1526 &soc_codec_dev_aic3x, &aic3x_dai, 1);
07779fdd 1527 return ret;
44d0a879
VB		 1528}
1529
ba8ed121 1530static int aic3x_i2c_remove(struct i2c_client *client)
44d0a879 1531{
f0fba2ad 1532 snd_soc_unregister_codec(&client->dev);
f0fba2ad 1533 return 0;
44d0a879
VB		 1534}
1535
44d0a879
VB		 1536/* machine i2c codec control layer */
1537static struct i2c_driver aic3x_i2c_driver = {
1538 .driver = {
f0fba2ad 1539 .name = "tlv320aic3x-codec",
44d0a879
VB		 1540 .owner = THIS_MODULE,
1541 },
cb3826f5 1542 .probe = aic3x_i2c_probe,
ba8ed121
JD		 1543 .remove = aic3x_i2c_remove,
1544 .id_table = aic3x_i2c_id,
44d0a879 1545};
44d0a879 1546
f0fba2ad 1547static int __init aic3x_modinit(void)
44d0a879 1548{
44d0a879 1549 int ret = 0;
f0fba2ad
LG		 1550 ret = i2c_add_driver(&aic3x_i2c_driver);
1551 if (ret != 0) {
1552 printk(KERN_ERR "Failed to register TLV320AIC3x I2C driver: %d\n",
1553 ret);
44d0a879 1554 }
44d0a879
VB		 1555 return ret;
1556}
64089b84
MB		 1557module_init(aic3x_modinit);
1558
1559static void __exit aic3x_exit(void)
1560{
f0fba2ad 1561 i2c_del_driver(&aic3x_i2c_driver);
64089b84
MB		 1562}
1563module_exit(aic3x_exit);
1564
44d0a879
VB		 1565MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1566MODULE_AUTHOR("Vladimir Barinov");
1567MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)