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44d0a879 VB |
1 | /* |
2 | * ALSA SoC TLV320AIC3X codec driver | |
3 | * | |
d6b52039 | 4 | * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> |
44d0a879 VB |
5 | * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> |
6 | * | |
7 | * Based on sound/soc/codecs/wm8753.c by Liam Girdwood | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * Notes: | |
14 | * The AIC3X is a driver for a low power stereo audio | |
15 | * codecs aic31, aic32, aic33. | |
16 | * | |
17 | * It supports full aic33 codec functionality. | |
18 | * The compatibility with aic32, aic31 is as follows: | |
19 | * aic32 | aic31 | |
20 | * --------------------------------------- | |
21 | * MONO_LOUT -> N/A | MONO_LOUT -> N/A | |
22 | * | IN1L -> LINE1L | |
23 | * | IN1R -> LINE1R | |
24 | * | IN2L -> LINE2L | |
25 | * | IN2R -> LINE2R | |
26 | * | MIC3L/R -> N/A | |
27 | * truncated internal functionality in | |
28 | * accordance with documentation | |
29 | * --------------------------------------- | |
30 | * | |
31 | * Hence the machine layer should disable unsupported inputs/outputs by | |
a5302181 | 32 | * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc. |
44d0a879 VB |
33 | */ |
34 | ||
35 | #include <linux/module.h> | |
36 | #include <linux/moduleparam.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/pm.h> | |
40 | #include <linux/i2c.h> | |
41 | #include <linux/platform_device.h> | |
44d0a879 VB |
42 | #include <sound/core.h> |
43 | #include <sound/pcm.h> | |
44 | #include <sound/pcm_params.h> | |
45 | #include <sound/soc.h> | |
46 | #include <sound/soc-dapm.h> | |
47 | #include <sound/initval.h> | |
7565fc38 | 48 | #include <sound/tlv.h> |
44d0a879 VB |
49 | |
50 | #include "tlv320aic3x.h" | |
51 | ||
4f9c16cc | 52 | #define AIC3X_VERSION "0.2" |
44d0a879 VB |
53 | |
54 | /* codec private data */ | |
55 | struct aic3x_priv { | |
56 | unsigned int sysclk; | |
57 | int master; | |
58 | }; | |
59 | ||
60 | /* | |
61 | * AIC3X register cache | |
62 | * We can't read the AIC3X register space when we are | |
63 | * using 2 wire for device control, so we cache them instead. | |
64 | * There is no point in caching the reset register | |
65 | */ | |
66 | static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = { | |
67 | 0x00, 0x00, 0x00, 0x10, /* 0 */ | |
68 | 0x04, 0x00, 0x00, 0x00, /* 4 */ | |
69 | 0x00, 0x00, 0x00, 0x01, /* 8 */ | |
70 | 0x00, 0x00, 0x00, 0x80, /* 12 */ | |
71 | 0x80, 0xff, 0xff, 0x78, /* 16 */ | |
72 | 0x78, 0x78, 0x78, 0x78, /* 20 */ | |
73 | 0x78, 0x00, 0x00, 0xfe, /* 24 */ | |
74 | 0x00, 0x00, 0xfe, 0x00, /* 28 */ | |
75 | 0x18, 0x18, 0x00, 0x00, /* 32 */ | |
76 | 0x00, 0x00, 0x00, 0x00, /* 36 */ | |
77 | 0x00, 0x00, 0x00, 0x80, /* 40 */ | |
78 | 0x80, 0x00, 0x00, 0x00, /* 44 */ | |
79 | 0x00, 0x00, 0x00, 0x04, /* 48 */ | |
80 | 0x00, 0x00, 0x00, 0x00, /* 52 */ | |
81 | 0x00, 0x00, 0x04, 0x00, /* 56 */ | |
82 | 0x00, 0x00, 0x00, 0x00, /* 60 */ | |
83 | 0x00, 0x04, 0x00, 0x00, /* 64 */ | |
84 | 0x00, 0x00, 0x00, 0x00, /* 68 */ | |
85 | 0x04, 0x00, 0x00, 0x00, /* 72 */ | |
86 | 0x00, 0x00, 0x00, 0x00, /* 76 */ | |
87 | 0x00, 0x00, 0x00, 0x00, /* 80 */ | |
88 | 0x00, 0x00, 0x00, 0x00, /* 84 */ | |
89 | 0x00, 0x00, 0x00, 0x00, /* 88 */ | |
90 | 0x00, 0x00, 0x00, 0x00, /* 92 */ | |
91 | 0x00, 0x00, 0x00, 0x00, /* 96 */ | |
92 | 0x00, 0x00, 0x02, /* 100 */ | |
93 | }; | |
94 | ||
95 | /* | |
96 | * read aic3x register cache | |
97 | */ | |
98 | static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec, | |
99 | unsigned int reg) | |
100 | { | |
101 | u8 *cache = codec->reg_cache; | |
102 | if (reg >= AIC3X_CACHEREGNUM) | |
103 | return -1; | |
104 | return cache[reg]; | |
105 | } | |
106 | ||
107 | /* | |
108 | * write aic3x register cache | |
109 | */ | |
110 | static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec, | |
111 | u8 reg, u8 value) | |
112 | { | |
113 | u8 *cache = codec->reg_cache; | |
114 | if (reg >= AIC3X_CACHEREGNUM) | |
115 | return; | |
116 | cache[reg] = value; | |
117 | } | |
118 | ||
119 | /* | |
120 | * write to the aic3x register space | |
121 | */ | |
122 | static int aic3x_write(struct snd_soc_codec *codec, unsigned int reg, | |
123 | unsigned int value) | |
124 | { | |
125 | u8 data[2]; | |
126 | ||
127 | /* data is | |
128 | * D15..D8 aic3x register offset | |
129 | * D7...D0 register data | |
130 | */ | |
131 | data[0] = reg & 0xff; | |
132 | data[1] = value & 0xff; | |
133 | ||
134 | aic3x_write_reg_cache(codec, data[0], data[1]); | |
135 | if (codec->hw_write(codec->control_data, data, 2) == 2) | |
136 | return 0; | |
137 | else | |
138 | return -EIO; | |
139 | } | |
140 | ||
54e7e616 DM |
141 | /* |
142 | * read from the aic3x register space | |
143 | */ | |
144 | static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg, | |
145 | u8 *value) | |
146 | { | |
147 | *value = reg & 0xff; | |
148 | if (codec->hw_read(codec->control_data, value, 1) != 1) | |
149 | return -EIO; | |
150 | ||
151 | aic3x_write_reg_cache(codec, reg, *value); | |
152 | return 0; | |
153 | } | |
154 | ||
44d0a879 VB |
155 | #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \ |
156 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
157 | .info = snd_soc_info_volsw, \ | |
158 | .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \ | |
159 | .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) } | |
160 | ||
161 | /* | |
162 | * All input lines are connected when !0xf and disconnected with 0xf bit field, | |
163 | * so we have to use specific dapm_put call for input mixer | |
164 | */ | |
165 | static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol, | |
166 | struct snd_ctl_elem_value *ucontrol) | |
167 | { | |
168 | struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); | |
4453dba5 EN |
169 | struct soc_mixer_control *mc = |
170 | (struct soc_mixer_control *)kcontrol->private_value; | |
171 | unsigned int reg = mc->reg; | |
172 | unsigned int shift = mc->shift; | |
173 | int max = mc->max; | |
174 | unsigned int mask = (1 << fls(max)) - 1; | |
175 | unsigned int invert = mc->invert; | |
44d0a879 VB |
176 | unsigned short val, val_mask; |
177 | int ret; | |
178 | struct snd_soc_dapm_path *path; | |
179 | int found = 0; | |
180 | ||
181 | val = (ucontrol->value.integer.value[0] & mask); | |
182 | ||
183 | mask = 0xf; | |
184 | if (val) | |
185 | val = mask; | |
186 | ||
187 | if (invert) | |
188 | val = mask - val; | |
189 | val_mask = mask << shift; | |
190 | val = val << shift; | |
191 | ||
192 | mutex_lock(&widget->codec->mutex); | |
193 | ||
194 | if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) { | |
195 | /* find dapm widget path assoc with kcontrol */ | |
196 | list_for_each_entry(path, &widget->codec->dapm_paths, list) { | |
197 | if (path->kcontrol != kcontrol) | |
198 | continue; | |
199 | ||
200 | /* found, now check type */ | |
201 | found = 1; | |
202 | if (val) | |
203 | /* new connection */ | |
204 | path->connect = invert ? 0 : 1; | |
205 | else | |
206 | /* old connection must be powered down */ | |
207 | path->connect = invert ? 1 : 0; | |
208 | break; | |
209 | } | |
210 | ||
211 | if (found) | |
a5302181 | 212 | snd_soc_dapm_sync(widget->codec); |
44d0a879 VB |
213 | } |
214 | ||
215 | ret = snd_soc_update_bits(widget->codec, reg, val_mask, val); | |
216 | ||
217 | mutex_unlock(&widget->codec->mutex); | |
218 | return ret; | |
219 | } | |
220 | ||
221 | static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" }; | |
222 | static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" }; | |
223 | static const char *aic3x_left_hpcom_mux[] = | |
224 | { "differential of HPLOUT", "constant VCM", "single-ended" }; | |
225 | static const char *aic3x_right_hpcom_mux[] = | |
226 | { "differential of HPROUT", "constant VCM", "single-ended", | |
227 | "differential of HPLCOM", "external feedback" }; | |
228 | static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" }; | |
4d20f70a JN |
229 | static const char *aic3x_adc_hpf[] = |
230 | { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" }; | |
44d0a879 VB |
231 | |
232 | #define LDAC_ENUM 0 | |
233 | #define RDAC_ENUM 1 | |
234 | #define LHPCOM_ENUM 2 | |
235 | #define RHPCOM_ENUM 3 | |
236 | #define LINE1L_ENUM 4 | |
237 | #define LINE1R_ENUM 5 | |
238 | #define LINE2L_ENUM 6 | |
239 | #define LINE2R_ENUM 7 | |
4d20f70a | 240 | #define ADC_HPF_ENUM 8 |
44d0a879 VB |
241 | |
242 | static const struct soc_enum aic3x_enum[] = { | |
243 | SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux), | |
244 | SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux), | |
245 | SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux), | |
246 | SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux), | |
247 | SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), | |
248 | SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), | |
249 | SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), | |
250 | SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), | |
4d20f70a | 251 | SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf), |
44d0a879 VB |
252 | }; |
253 | ||
7565fc38 JN |
254 | /* |
255 | * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps | |
256 | */ | |
257 | static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0); | |
258 | /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */ | |
259 | static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0); | |
260 | /* | |
261 | * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB. | |
262 | * Step size is approximately 0.5 dB over most of the scale but increasing | |
263 | * near the very low levels. | |
264 | * Define dB scale so that it is mostly correct for range about -55 to 0 dB | |
265 | * but having increasing dB difference below that (and where it doesn't count | |
266 | * so much). This setting shows -50 dB (actual is -50.3 dB) for register | |
267 | * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117. | |
268 | */ | |
269 | static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1); | |
270 | ||
44d0a879 VB |
271 | static const struct snd_kcontrol_new aic3x_snd_controls[] = { |
272 | /* Output */ | |
7565fc38 JN |
273 | SOC_DOUBLE_R_TLV("PCM Playback Volume", |
274 | LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv), | |
44d0a879 | 275 | |
7565fc38 JN |
276 | SOC_DOUBLE_R_TLV("Line DAC Playback Volume", |
277 | DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL, | |
278 | 0, 118, 1, output_stage_tlv), | |
28a1d869 DM |
279 | SOC_SINGLE("LineL Playback Switch", LLOPM_CTRL, 3, 0x01, 0), |
280 | SOC_SINGLE("LineR Playback Switch", RLOPM_CTRL, 3, 0x01, 0), | |
7565fc38 JN |
281 | SOC_DOUBLE_R_TLV("LineL DAC Playback Volume", |
282 | DACL1_2_LLOPM_VOL, DACR1_2_LLOPM_VOL, | |
283 | 0, 118, 1, output_stage_tlv), | |
284 | SOC_SINGLE_TLV("LineL Left PGA Bypass Playback Volume", | |
285 | PGAL_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), | |
286 | SOC_SINGLE_TLV("LineR Right PGA Bypass Playback Volume", | |
287 | PGAR_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), | |
288 | SOC_DOUBLE_R_TLV("LineL Line2 Bypass Playback Volume", | |
289 | LINE2L_2_LLOPM_VOL, LINE2R_2_LLOPM_VOL, | |
290 | 0, 118, 1, output_stage_tlv), | |
291 | SOC_DOUBLE_R_TLV("LineR Line2 Bypass Playback Volume", | |
292 | LINE2L_2_RLOPM_VOL, LINE2R_2_RLOPM_VOL, | |
293 | 0, 118, 1, output_stage_tlv), | |
294 | ||
295 | SOC_DOUBLE_R_TLV("Mono DAC Playback Volume", | |
296 | DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL, | |
297 | 0, 118, 1, output_stage_tlv), | |
44d0a879 | 298 | SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0), |
7565fc38 JN |
299 | SOC_DOUBLE_R_TLV("Mono PGA Bypass Playback Volume", |
300 | PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL, | |
301 | 0, 118, 1, output_stage_tlv), | |
302 | SOC_DOUBLE_R_TLV("Mono Line2 Bypass Playback Volume", | |
303 | LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL, | |
304 | 0, 118, 1, output_stage_tlv), | |
305 | ||
306 | SOC_DOUBLE_R_TLV("HP DAC Playback Volume", | |
307 | DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL, | |
308 | 0, 118, 1, output_stage_tlv), | |
44d0a879 VB |
309 | SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3, |
310 | 0x01, 0), | |
7565fc38 JN |
311 | SOC_DOUBLE_R_TLV("HP Right PGA Bypass Playback Volume", |
312 | PGAR_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL, | |
313 | 0, 118, 1, output_stage_tlv), | |
314 | SOC_SINGLE_TLV("HPL PGA Bypass Playback Volume", | |
315 | PGAL_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), | |
316 | SOC_SINGLE_TLV("HPR PGA Bypass Playback Volume", | |
317 | PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), | |
318 | SOC_DOUBLE_R_TLV("HP Line2 Bypass Playback Volume", | |
319 | LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL, | |
320 | 0, 118, 1, output_stage_tlv), | |
321 | ||
322 | SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume", | |
323 | DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL, | |
324 | 0, 118, 1, output_stage_tlv), | |
44d0a879 VB |
325 | SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3, |
326 | 0x01, 0), | |
7565fc38 JN |
327 | SOC_SINGLE_TLV("HPLCOM PGA Bypass Playback Volume", |
328 | PGAL_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), | |
329 | SOC_SINGLE_TLV("HPRCOM PGA Bypass Playback Volume", | |
330 | PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), | |
331 | SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Playback Volume", | |
332 | LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL, | |
333 | 0, 118, 1, output_stage_tlv), | |
44d0a879 VB |
334 | |
335 | /* | |
336 | * Note: enable Automatic input Gain Controller with care. It can | |
337 | * adjust PGA to max value when ADC is on and will never go back. | |
338 | */ | |
339 | SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0), | |
340 | ||
341 | /* Input */ | |
7565fc38 JN |
342 | SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL, |
343 | 0, 119, 0, adc_tlv), | |
44d0a879 | 344 | SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1), |
4d20f70a JN |
345 | |
346 | SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]), | |
44d0a879 VB |
347 | }; |
348 | ||
44d0a879 VB |
349 | /* Left DAC Mux */ |
350 | static const struct snd_kcontrol_new aic3x_left_dac_mux_controls = | |
351 | SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]); | |
352 | ||
353 | /* Right DAC Mux */ | |
354 | static const struct snd_kcontrol_new aic3x_right_dac_mux_controls = | |
355 | SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]); | |
356 | ||
357 | /* Left HPCOM Mux */ | |
358 | static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls = | |
359 | SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]); | |
360 | ||
361 | /* Right HPCOM Mux */ | |
362 | static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls = | |
363 | SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]); | |
364 | ||
365 | /* Left DAC_L1 Mixer */ | |
366 | static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = { | |
54f01916 DM |
367 | SOC_DAPM_SINGLE("LineL Switch", DACL1_2_LLOPM_VOL, 7, 1, 0), |
368 | SOC_DAPM_SINGLE("LineR Switch", DACL1_2_RLOPM_VOL, 7, 1, 0), | |
44d0a879 VB |
369 | SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0), |
370 | SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0), | |
371 | SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0), | |
372 | }; | |
373 | ||
374 | /* Right DAC_R1 Mixer */ | |
375 | static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = { | |
54f01916 DM |
376 | SOC_DAPM_SINGLE("LineL Switch", DACR1_2_LLOPM_VOL, 7, 1, 0), |
377 | SOC_DAPM_SINGLE("LineR Switch", DACR1_2_RLOPM_VOL, 7, 1, 0), | |
44d0a879 VB |
378 | SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0), |
379 | SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0), | |
380 | SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0), | |
381 | }; | |
382 | ||
383 | /* Left PGA Mixer */ | |
384 | static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = { | |
385 | SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1), | |
54f01916 | 386 | SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1), |
44d0a879 VB |
387 | SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1), |
388 | SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1), | |
54f01916 | 389 | SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1), |
44d0a879 VB |
390 | }; |
391 | ||
392 | /* Right PGA Mixer */ | |
393 | static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = { | |
394 | SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1), | |
54f01916 | 395 | SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1), |
44d0a879 | 396 | SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1), |
54f01916 | 397 | SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1), |
44d0a879 VB |
398 | SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1), |
399 | }; | |
400 | ||
401 | /* Left Line1 Mux */ | |
402 | static const struct snd_kcontrol_new aic3x_left_line1_mux_controls = | |
403 | SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]); | |
404 | ||
405 | /* Right Line1 Mux */ | |
406 | static const struct snd_kcontrol_new aic3x_right_line1_mux_controls = | |
407 | SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]); | |
408 | ||
409 | /* Left Line2 Mux */ | |
410 | static const struct snd_kcontrol_new aic3x_left_line2_mux_controls = | |
411 | SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]); | |
412 | ||
413 | /* Right Line2 Mux */ | |
414 | static const struct snd_kcontrol_new aic3x_right_line2_mux_controls = | |
415 | SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]); | |
416 | ||
417 | /* Left PGA Bypass Mixer */ | |
418 | static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = { | |
54f01916 DM |
419 | SOC_DAPM_SINGLE("LineL Switch", PGAL_2_LLOPM_VOL, 7, 1, 0), |
420 | SOC_DAPM_SINGLE("LineR Switch", PGAL_2_RLOPM_VOL, 7, 1, 0), | |
44d0a879 | 421 | SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0), |
54f01916 DM |
422 | SOC_DAPM_SINGLE("HPL Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0), |
423 | SOC_DAPM_SINGLE("HPR Switch", PGAL_2_HPROUT_VOL, 7, 1, 0), | |
424 | SOC_DAPM_SINGLE("HPLCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0), | |
425 | SOC_DAPM_SINGLE("HPRCOM Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0), | |
44d0a879 VB |
426 | }; |
427 | ||
428 | /* Right PGA Bypass Mixer */ | |
429 | static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = { | |
54f01916 DM |
430 | SOC_DAPM_SINGLE("LineL Switch", PGAR_2_LLOPM_VOL, 7, 1, 0), |
431 | SOC_DAPM_SINGLE("LineR Switch", PGAR_2_RLOPM_VOL, 7, 1, 0), | |
44d0a879 | 432 | SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0), |
54f01916 DM |
433 | SOC_DAPM_SINGLE("HPL Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0), |
434 | SOC_DAPM_SINGLE("HPR Switch", PGAR_2_HPROUT_VOL, 7, 1, 0), | |
435 | SOC_DAPM_SINGLE("HPLCOM Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0), | |
436 | SOC_DAPM_SINGLE("HPRCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0), | |
44d0a879 VB |
437 | }; |
438 | ||
439 | /* Left Line2 Bypass Mixer */ | |
440 | static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = { | |
54f01916 DM |
441 | SOC_DAPM_SINGLE("LineL Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0), |
442 | SOC_DAPM_SINGLE("LineR Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0), | |
44d0a879 VB |
443 | SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0), |
444 | SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0), | |
54f01916 | 445 | SOC_DAPM_SINGLE("HPLCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0), |
44d0a879 VB |
446 | }; |
447 | ||
448 | /* Right Line2 Bypass Mixer */ | |
449 | static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = { | |
54f01916 DM |
450 | SOC_DAPM_SINGLE("LineL Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0), |
451 | SOC_DAPM_SINGLE("LineR Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0), | |
44d0a879 VB |
452 | SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0), |
453 | SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0), | |
54f01916 | 454 | SOC_DAPM_SINGLE("HPRCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0), |
44d0a879 VB |
455 | }; |
456 | ||
457 | static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { | |
458 | /* Left DAC to Left Outputs */ | |
459 | SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0), | |
460 | SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0, | |
461 | &aic3x_left_dac_mux_controls), | |
462 | SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0, | |
463 | &aic3x_left_dac_mixer_controls[0], | |
464 | ARRAY_SIZE(aic3x_left_dac_mixer_controls)), | |
465 | SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0, | |
466 | &aic3x_left_hpcom_mux_controls), | |
467 | SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0), | |
468 | SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0), | |
469 | SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0), | |
470 | ||
471 | /* Right DAC to Right Outputs */ | |
472 | SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0), | |
473 | SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0, | |
474 | &aic3x_right_dac_mux_controls), | |
475 | SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0, | |
476 | &aic3x_right_dac_mixer_controls[0], | |
477 | ARRAY_SIZE(aic3x_right_dac_mixer_controls)), | |
478 | SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0, | |
479 | &aic3x_right_hpcom_mux_controls), | |
480 | SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0), | |
481 | SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0), | |
482 | SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0), | |
483 | ||
484 | /* Mono Output */ | |
485 | SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0), | |
486 | ||
54f01916 | 487 | /* Inputs to Left ADC */ |
44d0a879 VB |
488 | SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0), |
489 | SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0, | |
490 | &aic3x_left_pga_mixer_controls[0], | |
491 | ARRAY_SIZE(aic3x_left_pga_mixer_controls)), | |
492 | SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0, | |
493 | &aic3x_left_line1_mux_controls), | |
54f01916 DM |
494 | SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0, |
495 | &aic3x_left_line1_mux_controls), | |
44d0a879 VB |
496 | SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0, |
497 | &aic3x_left_line2_mux_controls), | |
498 | ||
54f01916 | 499 | /* Inputs to Right ADC */ |
44d0a879 VB |
500 | SND_SOC_DAPM_ADC("Right ADC", "Right Capture", |
501 | LINE1R_2_RADC_CTRL, 2, 0), | |
502 | SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0, | |
503 | &aic3x_right_pga_mixer_controls[0], | |
504 | ARRAY_SIZE(aic3x_right_pga_mixer_controls)), | |
54f01916 DM |
505 | SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0, |
506 | &aic3x_right_line1_mux_controls), | |
44d0a879 VB |
507 | SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0, |
508 | &aic3x_right_line1_mux_controls), | |
509 | SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0, | |
510 | &aic3x_right_line2_mux_controls), | |
511 | ||
ee15ffdb JN |
512 | /* |
513 | * Not a real mic bias widget but similar function. This is for dynamic | |
514 | * control of GPIO1 digital mic modulator clock output function when | |
515 | * using digital mic. | |
516 | */ | |
517 | SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk", | |
518 | AIC3X_GPIO1_REG, 4, 0xf, | |
519 | AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK, | |
520 | AIC3X_GPIO1_FUNC_DISABLED), | |
521 | ||
522 | /* | |
523 | * Also similar function like mic bias. Selects digital mic with | |
524 | * configurable oversampling rate instead of ADC converter. | |
525 | */ | |
526 | SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128", | |
527 | AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0), | |
528 | SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64", | |
529 | AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0), | |
530 | SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32", | |
531 | AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0), | |
532 | ||
44d0a879 | 533 | /* Mic Bias */ |
0bd72a3d JN |
534 | SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V", |
535 | MICBIAS_CTRL, 6, 3, 1, 0), | |
536 | SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V", | |
537 | MICBIAS_CTRL, 6, 3, 2, 0), | |
538 | SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD", | |
539 | MICBIAS_CTRL, 6, 3, 3, 0), | |
44d0a879 VB |
540 | |
541 | /* Left PGA to Left Output bypass */ | |
542 | SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0, | |
543 | &aic3x_left_pga_bp_mixer_controls[0], | |
544 | ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls)), | |
545 | ||
546 | /* Right PGA to Right Output bypass */ | |
547 | SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0, | |
548 | &aic3x_right_pga_bp_mixer_controls[0], | |
549 | ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls)), | |
550 | ||
551 | /* Left Line2 to Left Output bypass */ | |
552 | SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0, | |
553 | &aic3x_left_line2_bp_mixer_controls[0], | |
554 | ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)), | |
555 | ||
556 | /* Right Line2 to Right Output bypass */ | |
557 | SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0, | |
558 | &aic3x_right_line2_bp_mixer_controls[0], | |
559 | ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)), | |
560 | ||
561 | SND_SOC_DAPM_OUTPUT("LLOUT"), | |
562 | SND_SOC_DAPM_OUTPUT("RLOUT"), | |
563 | SND_SOC_DAPM_OUTPUT("MONO_LOUT"), | |
564 | SND_SOC_DAPM_OUTPUT("HPLOUT"), | |
565 | SND_SOC_DAPM_OUTPUT("HPROUT"), | |
566 | SND_SOC_DAPM_OUTPUT("HPLCOM"), | |
567 | SND_SOC_DAPM_OUTPUT("HPRCOM"), | |
568 | ||
569 | SND_SOC_DAPM_INPUT("MIC3L"), | |
570 | SND_SOC_DAPM_INPUT("MIC3R"), | |
571 | SND_SOC_DAPM_INPUT("LINE1L"), | |
572 | SND_SOC_DAPM_INPUT("LINE1R"), | |
573 | SND_SOC_DAPM_INPUT("LINE2L"), | |
574 | SND_SOC_DAPM_INPUT("LINE2R"), | |
575 | }; | |
576 | ||
d0cc0d3a | 577 | static const struct snd_soc_dapm_route intercon[] = { |
44d0a879 VB |
578 | /* Left Output */ |
579 | {"Left DAC Mux", "DAC_L1", "Left DAC"}, | |
580 | {"Left DAC Mux", "DAC_L2", "Left DAC"}, | |
581 | {"Left DAC Mux", "DAC_L3", "Left DAC"}, | |
582 | ||
54f01916 DM |
583 | {"Left DAC_L1 Mixer", "LineL Switch", "Left DAC Mux"}, |
584 | {"Left DAC_L1 Mixer", "LineR Switch", "Left DAC Mux"}, | |
44d0a879 VB |
585 | {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"}, |
586 | {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"}, | |
587 | {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"}, | |
588 | {"Left Line Out", NULL, "Left DAC Mux"}, | |
589 | {"Left HP Out", NULL, "Left DAC Mux"}, | |
590 | ||
591 | {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"}, | |
592 | {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"}, | |
593 | {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"}, | |
594 | ||
595 | {"Left Line Out", NULL, "Left DAC_L1 Mixer"}, | |
596 | {"Mono Out", NULL, "Left DAC_L1 Mixer"}, | |
597 | {"Left HP Out", NULL, "Left DAC_L1 Mixer"}, | |
598 | {"Left HP Com", NULL, "Left HPCOM Mux"}, | |
599 | ||
600 | {"LLOUT", NULL, "Left Line Out"}, | |
601 | {"LLOUT", NULL, "Left Line Out"}, | |
602 | {"HPLOUT", NULL, "Left HP Out"}, | |
603 | {"HPLCOM", NULL, "Left HP Com"}, | |
604 | ||
605 | /* Right Output */ | |
606 | {"Right DAC Mux", "DAC_R1", "Right DAC"}, | |
607 | {"Right DAC Mux", "DAC_R2", "Right DAC"}, | |
608 | {"Right DAC Mux", "DAC_R3", "Right DAC"}, | |
609 | ||
54f01916 DM |
610 | {"Right DAC_R1 Mixer", "LineL Switch", "Right DAC Mux"}, |
611 | {"Right DAC_R1 Mixer", "LineR Switch", "Right DAC Mux"}, | |
44d0a879 VB |
612 | {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"}, |
613 | {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"}, | |
614 | {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"}, | |
615 | {"Right Line Out", NULL, "Right DAC Mux"}, | |
616 | {"Right HP Out", NULL, "Right DAC Mux"}, | |
617 | ||
618 | {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"}, | |
619 | {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"}, | |
620 | {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"}, | |
621 | {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"}, | |
622 | {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"}, | |
623 | ||
624 | {"Right Line Out", NULL, "Right DAC_R1 Mixer"}, | |
625 | {"Mono Out", NULL, "Right DAC_R1 Mixer"}, | |
626 | {"Right HP Out", NULL, "Right DAC_R1 Mixer"}, | |
627 | {"Right HP Com", NULL, "Right HPCOM Mux"}, | |
628 | ||
629 | {"RLOUT", NULL, "Right Line Out"}, | |
630 | {"RLOUT", NULL, "Right Line Out"}, | |
631 | {"HPROUT", NULL, "Right HP Out"}, | |
632 | {"HPRCOM", NULL, "Right HP Com"}, | |
633 | ||
634 | /* Mono Output */ | |
5b006137 JN |
635 | {"MONO_LOUT", NULL, "Mono Out"}, |
636 | {"MONO_LOUT", NULL, "Mono Out"}, | |
44d0a879 VB |
637 | |
638 | /* Left Input */ | |
639 | {"Left Line1L Mux", "single-ended", "LINE1L"}, | |
640 | {"Left Line1L Mux", "differential", "LINE1L"}, | |
641 | ||
642 | {"Left Line2L Mux", "single-ended", "LINE2L"}, | |
643 | {"Left Line2L Mux", "differential", "LINE2L"}, | |
644 | ||
645 | {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"}, | |
54f01916 | 646 | {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"}, |
44d0a879 VB |
647 | {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"}, |
648 | {"Left PGA Mixer", "Mic3L Switch", "MIC3L"}, | |
54f01916 | 649 | {"Left PGA Mixer", "Mic3R Switch", "MIC3R"}, |
44d0a879 VB |
650 | |
651 | {"Left ADC", NULL, "Left PGA Mixer"}, | |
ee15ffdb | 652 | {"Left ADC", NULL, "GPIO1 dmic modclk"}, |
44d0a879 VB |
653 | |
654 | /* Right Input */ | |
655 | {"Right Line1R Mux", "single-ended", "LINE1R"}, | |
656 | {"Right Line1R Mux", "differential", "LINE1R"}, | |
657 | ||
658 | {"Right Line2R Mux", "single-ended", "LINE2R"}, | |
659 | {"Right Line2R Mux", "differential", "LINE2R"}, | |
660 | ||
54f01916 | 661 | {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"}, |
44d0a879 VB |
662 | {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"}, |
663 | {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"}, | |
54f01916 | 664 | {"Right PGA Mixer", "Mic3L Switch", "MIC3L"}, |
44d0a879 VB |
665 | {"Right PGA Mixer", "Mic3R Switch", "MIC3R"}, |
666 | ||
667 | {"Right ADC", NULL, "Right PGA Mixer"}, | |
ee15ffdb | 668 | {"Right ADC", NULL, "GPIO1 dmic modclk"}, |
44d0a879 VB |
669 | |
670 | /* Left PGA Bypass */ | |
54f01916 DM |
671 | {"Left PGA Bypass Mixer", "LineL Switch", "Left PGA Mixer"}, |
672 | {"Left PGA Bypass Mixer", "LineR Switch", "Left PGA Mixer"}, | |
44d0a879 | 673 | {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"}, |
54f01916 DM |
674 | {"Left PGA Bypass Mixer", "HPL Switch", "Left PGA Mixer"}, |
675 | {"Left PGA Bypass Mixer", "HPR Switch", "Left PGA Mixer"}, | |
676 | {"Left PGA Bypass Mixer", "HPLCOM Switch", "Left PGA Mixer"}, | |
677 | {"Left PGA Bypass Mixer", "HPRCOM Switch", "Left PGA Mixer"}, | |
44d0a879 VB |
678 | |
679 | {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"}, | |
680 | {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"}, | |
681 | {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"}, | |
682 | ||
683 | {"Left Line Out", NULL, "Left PGA Bypass Mixer"}, | |
684 | {"Mono Out", NULL, "Left PGA Bypass Mixer"}, | |
685 | {"Left HP Out", NULL, "Left PGA Bypass Mixer"}, | |
686 | ||
687 | /* Right PGA Bypass */ | |
54f01916 DM |
688 | {"Right PGA Bypass Mixer", "LineL Switch", "Right PGA Mixer"}, |
689 | {"Right PGA Bypass Mixer", "LineR Switch", "Right PGA Mixer"}, | |
44d0a879 | 690 | {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"}, |
54f01916 DM |
691 | {"Right PGA Bypass Mixer", "HPL Switch", "Right PGA Mixer"}, |
692 | {"Right PGA Bypass Mixer", "HPR Switch", "Right PGA Mixer"}, | |
693 | {"Right PGA Bypass Mixer", "HPLCOM Switch", "Right PGA Mixer"}, | |
694 | {"Right PGA Bypass Mixer", "HPRCOM Switch", "Right PGA Mixer"}, | |
44d0a879 VB |
695 | |
696 | {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"}, | |
697 | {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"}, | |
698 | {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"}, | |
699 | {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"}, | |
700 | {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"}, | |
701 | ||
702 | {"Right Line Out", NULL, "Right PGA Bypass Mixer"}, | |
703 | {"Mono Out", NULL, "Right PGA Bypass Mixer"}, | |
704 | {"Right HP Out", NULL, "Right PGA Bypass Mixer"}, | |
705 | ||
706 | /* Left Line2 Bypass */ | |
54f01916 DM |
707 | {"Left Line2 Bypass Mixer", "LineL Switch", "Left Line2L Mux"}, |
708 | {"Left Line2 Bypass Mixer", "LineR Switch", "Left Line2L Mux"}, | |
44d0a879 VB |
709 | {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"}, |
710 | {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"}, | |
54f01916 | 711 | {"Left Line2 Bypass Mixer", "HPLCOM Switch", "Left Line2L Mux"}, |
44d0a879 VB |
712 | |
713 | {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"}, | |
714 | {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"}, | |
715 | {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"}, | |
716 | ||
717 | {"Left Line Out", NULL, "Left Line2 Bypass Mixer"}, | |
718 | {"Mono Out", NULL, "Left Line2 Bypass Mixer"}, | |
719 | {"Left HP Out", NULL, "Left Line2 Bypass Mixer"}, | |
720 | ||
721 | /* Right Line2 Bypass */ | |
54f01916 DM |
722 | {"Right Line2 Bypass Mixer", "LineL Switch", "Right Line2R Mux"}, |
723 | {"Right Line2 Bypass Mixer", "LineR Switch", "Right Line2R Mux"}, | |
44d0a879 VB |
724 | {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"}, |
725 | {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"}, | |
54f01916 | 726 | {"Right Line2 Bypass Mixer", "HPRCOM Switch", "Right Line2R Mux"}, |
44d0a879 VB |
727 | |
728 | {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"}, | |
729 | {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"}, | |
730 | {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"}, | |
731 | {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"}, | |
732 | {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"}, | |
733 | ||
734 | {"Right Line Out", NULL, "Right Line2 Bypass Mixer"}, | |
735 | {"Mono Out", NULL, "Right Line2 Bypass Mixer"}, | |
736 | {"Right HP Out", NULL, "Right Line2 Bypass Mixer"}, | |
ee15ffdb JN |
737 | |
738 | /* | |
739 | * Logical path between digital mic enable and GPIO1 modulator clock | |
740 | * output function | |
741 | */ | |
742 | {"GPIO1 dmic modclk", NULL, "DMic Rate 128"}, | |
743 | {"GPIO1 dmic modclk", NULL, "DMic Rate 64"}, | |
744 | {"GPIO1 dmic modclk", NULL, "DMic Rate 32"}, | |
44d0a879 VB |
745 | }; |
746 | ||
747 | static int aic3x_add_widgets(struct snd_soc_codec *codec) | |
748 | { | |
d0cc0d3a MB |
749 | snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets, |
750 | ARRAY_SIZE(aic3x_dapm_widgets)); | |
44d0a879 VB |
751 | |
752 | /* set up audio path interconnects */ | |
d0cc0d3a | 753 | snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); |
44d0a879 VB |
754 | |
755 | snd_soc_dapm_new_widgets(codec); | |
756 | return 0; | |
757 | } | |
758 | ||
44d0a879 | 759 | static int aic3x_hw_params(struct snd_pcm_substream *substream, |
dee89c4d MB |
760 | struct snd_pcm_hw_params *params, |
761 | struct snd_soc_dai *dai) | |
44d0a879 VB |
762 | { |
763 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
764 | struct snd_soc_device *socdev = rtd->socdev; | |
6627a653 | 765 | struct snd_soc_codec *codec = socdev->card->codec; |
44d0a879 | 766 | struct aic3x_priv *aic3x = codec->private_data; |
4f9c16cc DM |
767 | int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0; |
768 | u8 data, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1; | |
769 | u16 pll_d = 1; | |
44d0a879 | 770 | |
4f9c16cc DM |
771 | /* select data word length */ |
772 | data = | |
773 | aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4)); | |
774 | switch (params_format(params)) { | |
775 | case SNDRV_PCM_FORMAT_S16_LE: | |
44d0a879 | 776 | break; |
4f9c16cc DM |
777 | case SNDRV_PCM_FORMAT_S20_3LE: |
778 | data |= (0x01 << 4); | |
44d0a879 | 779 | break; |
4f9c16cc DM |
780 | case SNDRV_PCM_FORMAT_S24_LE: |
781 | data |= (0x02 << 4); | |
44d0a879 | 782 | break; |
4f9c16cc DM |
783 | case SNDRV_PCM_FORMAT_S32_LE: |
784 | data |= (0x03 << 4); | |
44d0a879 VB |
785 | break; |
786 | } | |
4f9c16cc DM |
787 | aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data); |
788 | ||
789 | /* Fsref can be 44100 or 48000 */ | |
790 | fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000; | |
791 | ||
792 | /* Try to find a value for Q which allows us to bypass the PLL and | |
793 | * generate CODEC_CLK directly. */ | |
794 | for (pll_q = 2; pll_q < 18; pll_q++) | |
795 | if (aic3x->sysclk / (128 * pll_q) == fsref) { | |
796 | bypass_pll = 1; | |
797 | break; | |
798 | } | |
799 | ||
800 | if (bypass_pll) { | |
801 | pll_q &= 0xf; | |
802 | aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT); | |
803 | aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV); | |
804 | } else | |
805 | aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV); | |
806 | ||
807 | /* Route Left DAC to left channel input and | |
808 | * right DAC to right channel input */ | |
809 | data = (LDAC2LCH | RDAC2RCH); | |
810 | data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000; | |
811 | if (params_rate(params) >= 64000) | |
812 | data |= DUAL_RATE_MODE; | |
44d0a879 VB |
813 | aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data); |
814 | ||
815 | /* codec sample rate select */ | |
4f9c16cc DM |
816 | data = (fsref * 20) / params_rate(params); |
817 | if (params_rate(params) < 64000) | |
818 | data /= 2; | |
819 | data /= 5; | |
820 | data -= 2; | |
44d0a879 VB |
821 | data |= (data << 4); |
822 | aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data); | |
823 | ||
4f9c16cc DM |
824 | if (bypass_pll) |
825 | return 0; | |
826 | ||
827 | /* Use PLL | |
828 | * find an apropriate setup for j, d, r and p by iterating over | |
829 | * p and r - j and d are calculated for each fraction. | |
830 | * Up to 128 values are probed, the closest one wins the game. | |
831 | * The sysclk is divided by 1000 to prevent integer overflows. | |
44d0a879 | 832 | */ |
4f9c16cc DM |
833 | codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000); |
834 | ||
835 | for (r = 1; r <= 16; r++) | |
836 | for (p = 1; p <= 8; p++) { | |
837 | int clk, tmp = (codec_clk * pll_r * 10) / pll_p; | |
838 | u8 j = tmp / 10000; | |
839 | u16 d = tmp % 10000; | |
840 | ||
841 | if (j > 63) | |
842 | continue; | |
843 | ||
844 | if (d != 0 && aic3x->sysclk < 10000000) | |
845 | continue; | |
846 | ||
847 | /* This is actually 1000 * ((j + (d/10000)) * r) / p | |
848 | * The term had to be converted to get rid of the | |
849 | * division by 10000 */ | |
850 | clk = ((10000 * j * r) + (d * r)) / (10 * p); | |
851 | ||
852 | /* check whether this values get closer than the best | |
853 | * ones we had before */ | |
854 | if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) { | |
855 | pll_j = j; pll_d = d; pll_r = r; pll_p = p; | |
856 | last_clk = clk; | |
857 | } | |
858 | ||
859 | /* Early exit for exact matches */ | |
860 | if (clk == codec_clk) | |
861 | break; | |
862 | } | |
863 | ||
864 | if (last_clk == 0) { | |
865 | printk(KERN_ERR "%s(): unable to setup PLL\n", __func__); | |
866 | return -EINVAL; | |
867 | } | |
44d0a879 VB |
868 | |
869 | data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); | |
870 | aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT)); | |
871 | aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT); | |
872 | aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT); | |
873 | aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT); | |
874 | aic3x_write(codec, AIC3X_PLL_PROGD_REG, | |
875 | (pll_d & 0x3F) << PLLD_LSB_SHIFT); | |
876 | ||
44d0a879 VB |
877 | return 0; |
878 | } | |
879 | ||
e550e17f | 880 | static int aic3x_mute(struct snd_soc_dai *dai, int mute) |
44d0a879 VB |
881 | { |
882 | struct snd_soc_codec *codec = dai->codec; | |
883 | u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON; | |
884 | u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON; | |
885 | ||
886 | if (mute) { | |
887 | aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON); | |
888 | aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON); | |
889 | } else { | |
890 | aic3x_write(codec, LDAC_VOL, ldac_reg); | |
891 | aic3x_write(codec, RDAC_VOL, rdac_reg); | |
892 | } | |
893 | ||
894 | return 0; | |
895 | } | |
896 | ||
e550e17f | 897 | static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai, |
44d0a879 VB |
898 | int clk_id, unsigned int freq, int dir) |
899 | { | |
900 | struct snd_soc_codec *codec = codec_dai->codec; | |
901 | struct aic3x_priv *aic3x = codec->private_data; | |
902 | ||
4f9c16cc DM |
903 | aic3x->sysclk = freq; |
904 | return 0; | |
44d0a879 VB |
905 | } |
906 | ||
e550e17f | 907 | static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai, |
44d0a879 VB |
908 | unsigned int fmt) |
909 | { | |
910 | struct snd_soc_codec *codec = codec_dai->codec; | |
911 | struct aic3x_priv *aic3x = codec->private_data; | |
81971a14 | 912 | u8 iface_areg, iface_breg; |
a24f4f68 | 913 | int delay = 0; |
81971a14 JN |
914 | |
915 | iface_areg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f; | |
916 | iface_breg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f; | |
44d0a879 VB |
917 | |
918 | /* set master/slave audio interface */ | |
919 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
920 | case SND_SOC_DAIFMT_CBM_CFM: | |
921 | aic3x->master = 1; | |
922 | iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER; | |
923 | break; | |
924 | case SND_SOC_DAIFMT_CBS_CFS: | |
925 | aic3x->master = 0; | |
926 | break; | |
927 | default: | |
928 | return -EINVAL; | |
929 | } | |
930 | ||
4b7d2831 JN |
931 | /* |
932 | * match both interface format and signal polarities since they | |
933 | * are fixed | |
934 | */ | |
935 | switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK | | |
936 | SND_SOC_DAIFMT_INV_MASK)) { | |
937 | case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF): | |
44d0a879 | 938 | break; |
a24f4f68 TK |
939 | case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF): |
940 | delay = 1; | |
4b7d2831 | 941 | case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF): |
44d0a879 VB |
942 | iface_breg |= (0x01 << 6); |
943 | break; | |
4b7d2831 | 944 | case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF): |
44d0a879 VB |
945 | iface_breg |= (0x02 << 6); |
946 | break; | |
4b7d2831 | 947 | case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF): |
44d0a879 VB |
948 | iface_breg |= (0x03 << 6); |
949 | break; | |
950 | default: | |
951 | return -EINVAL; | |
952 | } | |
953 | ||
954 | /* set iface */ | |
955 | aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg); | |
956 | aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg); | |
a24f4f68 | 957 | aic3x_write(codec, AIC3X_ASD_INTF_CTRLC, delay); |
44d0a879 VB |
958 | |
959 | return 0; | |
960 | } | |
961 | ||
0be9898a MB |
962 | static int aic3x_set_bias_level(struct snd_soc_codec *codec, |
963 | enum snd_soc_bias_level level) | |
44d0a879 VB |
964 | { |
965 | struct aic3x_priv *aic3x = codec->private_data; | |
966 | u8 reg; | |
967 | ||
0be9898a MB |
968 | switch (level) { |
969 | case SND_SOC_BIAS_ON: | |
44d0a879 VB |
970 | /* all power is driven by DAPM system */ |
971 | if (aic3x->master) { | |
972 | /* enable pll */ | |
973 | reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); | |
974 | aic3x_write(codec, AIC3X_PLL_PROGA_REG, | |
975 | reg | PLL_ENABLE); | |
976 | } | |
977 | break; | |
0be9898a | 978 | case SND_SOC_BIAS_PREPARE: |
44d0a879 | 979 | break; |
0be9898a | 980 | case SND_SOC_BIAS_STANDBY: |
44d0a879 VB |
981 | /* |
982 | * all power is driven by DAPM system, | |
983 | * so output power is safe if bypass was set | |
984 | */ | |
985 | if (aic3x->master) { | |
986 | /* disable pll */ | |
987 | reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); | |
988 | aic3x_write(codec, AIC3X_PLL_PROGA_REG, | |
989 | reg & ~PLL_ENABLE); | |
990 | } | |
991 | break; | |
0be9898a | 992 | case SND_SOC_BIAS_OFF: |
44d0a879 VB |
993 | /* force all power off */ |
994 | reg = aic3x_read_reg_cache(codec, LINE1L_2_LADC_CTRL); | |
995 | aic3x_write(codec, LINE1L_2_LADC_CTRL, reg & ~LADC_PWR_ON); | |
996 | reg = aic3x_read_reg_cache(codec, LINE1R_2_RADC_CTRL); | |
997 | aic3x_write(codec, LINE1R_2_RADC_CTRL, reg & ~RADC_PWR_ON); | |
998 | ||
999 | reg = aic3x_read_reg_cache(codec, DAC_PWR); | |
1000 | aic3x_write(codec, DAC_PWR, reg & ~(LDAC_PWR_ON | RDAC_PWR_ON)); | |
1001 | ||
1002 | reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL); | |
1003 | aic3x_write(codec, HPLOUT_CTRL, reg & ~HPLOUT_PWR_ON); | |
1004 | reg = aic3x_read_reg_cache(codec, HPROUT_CTRL); | |
1005 | aic3x_write(codec, HPROUT_CTRL, reg & ~HPROUT_PWR_ON); | |
1006 | ||
1007 | reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL); | |
1008 | aic3x_write(codec, HPLCOM_CTRL, reg & ~HPLCOM_PWR_ON); | |
1009 | reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL); | |
1010 | aic3x_write(codec, HPRCOM_CTRL, reg & ~HPRCOM_PWR_ON); | |
1011 | ||
1012 | reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL); | |
1013 | aic3x_write(codec, MONOLOPM_CTRL, reg & ~MONOLOPM_PWR_ON); | |
1014 | ||
1015 | reg = aic3x_read_reg_cache(codec, LLOPM_CTRL); | |
1016 | aic3x_write(codec, LLOPM_CTRL, reg & ~LLOPM_PWR_ON); | |
1017 | reg = aic3x_read_reg_cache(codec, RLOPM_CTRL); | |
1018 | aic3x_write(codec, RLOPM_CTRL, reg & ~RLOPM_PWR_ON); | |
1019 | ||
1020 | if (aic3x->master) { | |
1021 | /* disable pll */ | |
1022 | reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); | |
1023 | aic3x_write(codec, AIC3X_PLL_PROGA_REG, | |
1024 | reg & ~PLL_ENABLE); | |
1025 | } | |
1026 | break; | |
1027 | } | |
0be9898a | 1028 | codec->bias_level = level; |
44d0a879 VB |
1029 | |
1030 | return 0; | |
1031 | } | |
1032 | ||
54e7e616 DM |
1033 | void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state) |
1034 | { | |
1035 | u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG; | |
1036 | u8 bit = gpio ? 3: 0; | |
1037 | u8 val = aic3x_read_reg_cache(codec, reg) & ~(1 << bit); | |
1038 | aic3x_write(codec, reg, val | (!!state << bit)); | |
1039 | } | |
1040 | EXPORT_SYMBOL_GPL(aic3x_set_gpio); | |
1041 | ||
1042 | int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio) | |
1043 | { | |
1044 | u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG; | |
1045 | u8 val, bit = gpio ? 2: 1; | |
1046 | ||
1047 | aic3x_read(codec, reg, &val); | |
1048 | return (val >> bit) & 1; | |
1049 | } | |
1050 | EXPORT_SYMBOL_GPL(aic3x_get_gpio); | |
1051 | ||
6f2a974b DM |
1052 | void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect, |
1053 | int headset_debounce, int button_debounce) | |
1054 | { | |
1055 | u8 val; | |
1056 | ||
1057 | val = ((detect & AIC3X_HEADSET_DETECT_MASK) | |
1058 | << AIC3X_HEADSET_DETECT_SHIFT) | | |
1059 | ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK) | |
1060 | << AIC3X_HEADSET_DEBOUNCE_SHIFT) | | |
1061 | ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK) | |
1062 | << AIC3X_BUTTON_DEBOUNCE_SHIFT); | |
1063 | ||
1064 | if (detect & AIC3X_HEADSET_DETECT_MASK) | |
1065 | val |= AIC3X_HEADSET_DETECT_ENABLED; | |
1066 | ||
1067 | aic3x_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val); | |
1068 | } | |
1069 | EXPORT_SYMBOL_GPL(aic3x_set_headset_detection); | |
1070 | ||
54e7e616 DM |
1071 | int aic3x_headset_detected(struct snd_soc_codec *codec) |
1072 | { | |
1073 | u8 val; | |
6f2a974b DM |
1074 | aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val); |
1075 | return (val >> 4) & 1; | |
54e7e616 DM |
1076 | } |
1077 | EXPORT_SYMBOL_GPL(aic3x_headset_detected); | |
1078 | ||
6f2a974b DM |
1079 | int aic3x_button_pressed(struct snd_soc_codec *codec) |
1080 | { | |
1081 | u8 val; | |
1082 | aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val); | |
1083 | return (val >> 5) & 1; | |
1084 | } | |
1085 | EXPORT_SYMBOL_GPL(aic3x_button_pressed); | |
1086 | ||
44d0a879 VB |
1087 | #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000 |
1088 | #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
1089 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) | |
1090 | ||
e550e17f | 1091 | struct snd_soc_dai aic3x_dai = { |
e78cc18d | 1092 | .name = "tlv320aic3x", |
44d0a879 VB |
1093 | .playback = { |
1094 | .stream_name = "Playback", | |
1095 | .channels_min = 1, | |
1096 | .channels_max = 2, | |
1097 | .rates = AIC3X_RATES, | |
1098 | .formats = AIC3X_FORMATS,}, | |
1099 | .capture = { | |
1100 | .stream_name = "Capture", | |
1101 | .channels_min = 1, | |
1102 | .channels_max = 2, | |
1103 | .rates = AIC3X_RATES, | |
1104 | .formats = AIC3X_FORMATS,}, | |
1105 | .ops = { | |
1106 | .hw_params = aic3x_hw_params, | |
44d0a879 VB |
1107 | .digital_mute = aic3x_mute, |
1108 | .set_sysclk = aic3x_set_dai_sysclk, | |
1109 | .set_fmt = aic3x_set_dai_fmt, | |
1110 | } | |
1111 | }; | |
1112 | EXPORT_SYMBOL_GPL(aic3x_dai); | |
1113 | ||
1114 | static int aic3x_suspend(struct platform_device *pdev, pm_message_t state) | |
1115 | { | |
1116 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
6627a653 | 1117 | struct snd_soc_codec *codec = socdev->card->codec; |
44d0a879 | 1118 | |
0be9898a | 1119 | aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF); |
44d0a879 VB |
1120 | |
1121 | return 0; | |
1122 | } | |
1123 | ||
1124 | static int aic3x_resume(struct platform_device *pdev) | |
1125 | { | |
1126 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
6627a653 | 1127 | struct snd_soc_codec *codec = socdev->card->codec; |
44d0a879 VB |
1128 | int i; |
1129 | u8 data[2]; | |
1130 | u8 *cache = codec->reg_cache; | |
1131 | ||
1132 | /* Sync reg_cache with the hardware */ | |
1133 | for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) { | |
1134 | data[0] = i; | |
1135 | data[1] = cache[i]; | |
1136 | codec->hw_write(codec->control_data, data, 2); | |
1137 | } | |
1138 | ||
0be9898a | 1139 | aic3x_set_bias_level(codec, codec->suspend_bias_level); |
44d0a879 VB |
1140 | |
1141 | return 0; | |
1142 | } | |
1143 | ||
1144 | /* | |
1145 | * initialise the AIC3X driver | |
1146 | * register the mixer and dsp interfaces with the kernel | |
1147 | */ | |
1148 | static int aic3x_init(struct snd_soc_device *socdev) | |
1149 | { | |
6627a653 | 1150 | struct snd_soc_codec *codec = socdev->card->codec; |
54e7e616 | 1151 | struct aic3x_setup_data *setup = socdev->codec_data; |
44d0a879 VB |
1152 | int reg, ret = 0; |
1153 | ||
e78cc18d | 1154 | codec->name = "tlv320aic3x"; |
44d0a879 VB |
1155 | codec->owner = THIS_MODULE; |
1156 | codec->read = aic3x_read_reg_cache; | |
1157 | codec->write = aic3x_write; | |
0be9898a | 1158 | codec->set_bias_level = aic3x_set_bias_level; |
44d0a879 VB |
1159 | codec->dai = &aic3x_dai; |
1160 | codec->num_dai = 1; | |
ae2ff191 | 1161 | codec->reg_cache_size = ARRAY_SIZE(aic3x_reg); |
44d0a879 VB |
1162 | codec->reg_cache = kmemdup(aic3x_reg, sizeof(aic3x_reg), GFP_KERNEL); |
1163 | if (codec->reg_cache == NULL) | |
1164 | return -ENOMEM; | |
1165 | ||
1166 | aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT); | |
1167 | aic3x_write(codec, AIC3X_RESET, SOFT_RESET); | |
1168 | ||
1169 | /* register pcms */ | |
1170 | ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); | |
1171 | if (ret < 0) { | |
1172 | printk(KERN_ERR "aic3x: failed to create pcms\n"); | |
1173 | goto pcm_err; | |
1174 | } | |
1175 | ||
1176 | /* DAC default volume and mute */ | |
1177 | aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON); | |
1178 | aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON); | |
1179 | ||
1180 | /* DAC to HP default volume and route to Output mixer */ | |
1181 | aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON); | |
1182 | aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON); | |
1183 | aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON); | |
1184 | aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON); | |
1185 | /* DAC to Line Out default volume and route to Output mixer */ | |
1186 | aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON); | |
1187 | aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON); | |
1188 | /* DAC to Mono Line Out default volume and route to Output mixer */ | |
1189 | aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); | |
1190 | aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); | |
1191 | ||
1192 | /* unmute all outputs */ | |
1193 | reg = aic3x_read_reg_cache(codec, LLOPM_CTRL); | |
1194 | aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE); | |
1195 | reg = aic3x_read_reg_cache(codec, RLOPM_CTRL); | |
1196 | aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE); | |
1197 | reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL); | |
1198 | aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE); | |
1199 | reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL); | |
1200 | aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE); | |
1201 | reg = aic3x_read_reg_cache(codec, HPROUT_CTRL); | |
1202 | aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE); | |
1203 | reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL); | |
1204 | aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE); | |
1205 | reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL); | |
1206 | aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE); | |
1207 | ||
1208 | /* ADC default volume and unmute */ | |
1209 | aic3x_write(codec, LADC_VOL, DEFAULT_GAIN); | |
1210 | aic3x_write(codec, RADC_VOL, DEFAULT_GAIN); | |
1211 | /* By default route Line1 to ADC PGA mixer */ | |
1212 | aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0); | |
1213 | aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0); | |
1214 | ||
1215 | /* PGA to HP Bypass default volume, disconnect from Output Mixer */ | |
1216 | aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL); | |
1217 | aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL); | |
1218 | aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL); | |
1219 | aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL); | |
1220 | /* PGA to Line Out default volume, disconnect from Output Mixer */ | |
1221 | aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL); | |
1222 | aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL); | |
1223 | /* PGA to Mono Line Out default volume, disconnect from Output Mixer */ | |
1224 | aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL); | |
1225 | aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL); | |
1226 | ||
1227 | /* Line2 to HP Bypass default volume, disconnect from Output Mixer */ | |
1228 | aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL); | |
1229 | aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL); | |
1230 | aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL); | |
1231 | aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL); | |
1232 | /* Line2 Line Out default volume, disconnect from Output Mixer */ | |
1233 | aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL); | |
1234 | aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL); | |
1235 | /* Line2 to Mono Out default volume, disconnect from Output Mixer */ | |
1236 | aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL); | |
1237 | aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL); | |
1238 | ||
1239 | /* off, with power on */ | |
0be9898a | 1240 | aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
44d0a879 | 1241 | |
54e7e616 DM |
1242 | /* setup GPIO functions */ |
1243 | aic3x_write(codec, AIC3X_GPIO1_REG, (setup->gpio_func[0] & 0xf) << 4); | |
1244 | aic3x_write(codec, AIC3X_GPIO2_REG, (setup->gpio_func[1] & 0xf) << 4); | |
1245 | ||
3e8e1952 IM |
1246 | snd_soc_add_controls(codec, aic3x_snd_controls, |
1247 | ARRAY_SIZE(aic3x_snd_controls)); | |
44d0a879 | 1248 | aic3x_add_widgets(codec); |
968a6025 | 1249 | ret = snd_soc_init_card(socdev); |
44d0a879 VB |
1250 | if (ret < 0) { |
1251 | printk(KERN_ERR "aic3x: failed to register card\n"); | |
1252 | goto card_err; | |
1253 | } | |
1254 | ||
1255 | return ret; | |
1256 | ||
1257 | card_err: | |
1258 | snd_soc_free_pcms(socdev); | |
1259 | snd_soc_dapm_free(socdev); | |
1260 | pcm_err: | |
1261 | kfree(codec->reg_cache); | |
1262 | return ret; | |
1263 | } | |
1264 | ||
1265 | static struct snd_soc_device *aic3x_socdev; | |
1266 | ||
1267 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
1268 | /* | |
1269 | * AIC3X 2 wire address can be up to 4 devices with device addresses | |
1270 | * 0x18, 0x19, 0x1A, 0x1B | |
1271 | */ | |
44d0a879 VB |
1272 | |
1273 | /* | |
1274 | * If the i2c layer weren't so broken, we could pass this kind of data | |
1275 | * around | |
1276 | */ | |
ba8ed121 JD |
1277 | static int aic3x_i2c_probe(struct i2c_client *i2c, |
1278 | const struct i2c_device_id *id) | |
44d0a879 VB |
1279 | { |
1280 | struct snd_soc_device *socdev = aic3x_socdev; | |
6627a653 | 1281 | struct snd_soc_codec *codec = socdev->card->codec; |
44d0a879 VB |
1282 | int ret; |
1283 | ||
44d0a879 VB |
1284 | i2c_set_clientdata(i2c, codec); |
1285 | codec->control_data = i2c; | |
1286 | ||
44d0a879 | 1287 | ret = aic3x_init(socdev); |
ba8ed121 | 1288 | if (ret < 0) |
44d0a879 | 1289 | printk(KERN_ERR "aic3x: failed to initialise AIC3X\n"); |
44d0a879 VB |
1290 | return ret; |
1291 | } | |
1292 | ||
ba8ed121 | 1293 | static int aic3x_i2c_remove(struct i2c_client *client) |
44d0a879 VB |
1294 | { |
1295 | struct snd_soc_codec *codec = i2c_get_clientdata(client); | |
44d0a879 | 1296 | kfree(codec->reg_cache); |
44d0a879 VB |
1297 | return 0; |
1298 | } | |
1299 | ||
ba8ed121 JD |
1300 | static const struct i2c_device_id aic3x_i2c_id[] = { |
1301 | { "tlv320aic3x", 0 }, | |
1302 | { } | |
1303 | }; | |
1304 | MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id); | |
44d0a879 VB |
1305 | |
1306 | /* machine i2c codec control layer */ | |
1307 | static struct i2c_driver aic3x_i2c_driver = { | |
1308 | .driver = { | |
1309 | .name = "aic3x I2C Codec", | |
1310 | .owner = THIS_MODULE, | |
1311 | }, | |
ba8ed121 JD |
1312 | .probe = aic3x_i2c_probe, |
1313 | .remove = aic3x_i2c_remove, | |
1314 | .id_table = aic3x_i2c_id, | |
44d0a879 | 1315 | }; |
54e7e616 DM |
1316 | |
1317 | static int aic3x_i2c_read(struct i2c_client *client, u8 *value, int len) | |
1318 | { | |
1319 | value[0] = i2c_smbus_read_byte_data(client, value[0]); | |
1320 | return (len == 1); | |
1321 | } | |
ba8ed121 JD |
1322 | |
1323 | static int aic3x_add_i2c_device(struct platform_device *pdev, | |
1324 | const struct aic3x_setup_data *setup) | |
1325 | { | |
1326 | struct i2c_board_info info; | |
1327 | struct i2c_adapter *adapter; | |
1328 | struct i2c_client *client; | |
1329 | int ret; | |
1330 | ||
1331 | ret = i2c_add_driver(&aic3x_i2c_driver); | |
1332 | if (ret != 0) { | |
1333 | dev_err(&pdev->dev, "can't add i2c driver\n"); | |
1334 | return ret; | |
1335 | } | |
1336 | ||
1337 | memset(&info, 0, sizeof(struct i2c_board_info)); | |
1338 | info.addr = setup->i2c_address; | |
1339 | strlcpy(info.type, "tlv320aic3x", I2C_NAME_SIZE); | |
1340 | ||
1341 | adapter = i2c_get_adapter(setup->i2c_bus); | |
1342 | if (!adapter) { | |
1343 | dev_err(&pdev->dev, "can't get i2c adapter %d\n", | |
1344 | setup->i2c_bus); | |
1345 | goto err_driver; | |
1346 | } | |
1347 | ||
1348 | client = i2c_new_device(adapter, &info); | |
1349 | i2c_put_adapter(adapter); | |
1350 | if (!client) { | |
1351 | dev_err(&pdev->dev, "can't add i2c device at 0x%x\n", | |
1352 | (unsigned int)info.addr); | |
1353 | goto err_driver; | |
1354 | } | |
1355 | ||
1356 | return 0; | |
1357 | ||
1358 | err_driver: | |
1359 | i2c_del_driver(&aic3x_i2c_driver); | |
1360 | return -ENODEV; | |
1361 | } | |
44d0a879 VB |
1362 | #endif |
1363 | ||
1364 | static int aic3x_probe(struct platform_device *pdev) | |
1365 | { | |
1366 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
1367 | struct aic3x_setup_data *setup; | |
1368 | struct snd_soc_codec *codec; | |
1369 | struct aic3x_priv *aic3x; | |
1370 | int ret = 0; | |
1371 | ||
1372 | printk(KERN_INFO "AIC3X Audio Codec %s\n", AIC3X_VERSION); | |
1373 | ||
1374 | setup = socdev->codec_data; | |
1375 | codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); | |
1376 | if (codec == NULL) | |
1377 | return -ENOMEM; | |
1378 | ||
1379 | aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL); | |
1380 | if (aic3x == NULL) { | |
1381 | kfree(codec); | |
1382 | return -ENOMEM; | |
1383 | } | |
1384 | ||
1385 | codec->private_data = aic3x; | |
6627a653 | 1386 | socdev->card->codec = codec; |
44d0a879 VB |
1387 | mutex_init(&codec->mutex); |
1388 | INIT_LIST_HEAD(&codec->dapm_widgets); | |
1389 | INIT_LIST_HEAD(&codec->dapm_paths); | |
1390 | ||
1391 | aic3x_socdev = socdev; | |
1392 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
1393 | if (setup->i2c_address) { | |
44d0a879 | 1394 | codec->hw_write = (hw_write_t) i2c_master_send; |
54e7e616 | 1395 | codec->hw_read = (hw_read_t) aic3x_i2c_read; |
ba8ed121 | 1396 | ret = aic3x_add_i2c_device(pdev, setup); |
44d0a879 VB |
1397 | } |
1398 | #else | |
1399 | /* Add other interfaces here */ | |
1400 | #endif | |
3051e41a JD |
1401 | |
1402 | if (ret != 0) { | |
1403 | kfree(codec->private_data); | |
1404 | kfree(codec); | |
1405 | } | |
44d0a879 VB |
1406 | return ret; |
1407 | } | |
1408 | ||
1409 | static int aic3x_remove(struct platform_device *pdev) | |
1410 | { | |
1411 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
6627a653 | 1412 | struct snd_soc_codec *codec = socdev->card->codec; |
44d0a879 VB |
1413 | |
1414 | /* power down chip */ | |
1415 | if (codec->control_data) | |
0be9898a | 1416 | aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF); |
44d0a879 VB |
1417 | |
1418 | snd_soc_free_pcms(socdev); | |
1419 | snd_soc_dapm_free(socdev); | |
1420 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
ba8ed121 | 1421 | i2c_unregister_device(codec->control_data); |
44d0a879 VB |
1422 | i2c_del_driver(&aic3x_i2c_driver); |
1423 | #endif | |
1424 | kfree(codec->private_data); | |
1425 | kfree(codec); | |
1426 | ||
1427 | return 0; | |
1428 | } | |
1429 | ||
1430 | struct snd_soc_codec_device soc_codec_dev_aic3x = { | |
1431 | .probe = aic3x_probe, | |
1432 | .remove = aic3x_remove, | |
1433 | .suspend = aic3x_suspend, | |
1434 | .resume = aic3x_resume, | |
1435 | }; | |
1436 | EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x); | |
1437 | ||
c9b3a40f | 1438 | static int __init aic3x_modinit(void) |
64089b84 MB |
1439 | { |
1440 | return snd_soc_register_dai(&aic3x_dai); | |
1441 | } | |
1442 | module_init(aic3x_modinit); | |
1443 | ||
1444 | static void __exit aic3x_exit(void) | |
1445 | { | |
1446 | snd_soc_unregister_dai(&aic3x_dai); | |
1447 | } | |
1448 | module_exit(aic3x_exit); | |
1449 | ||
44d0a879 VB |
1450 | MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver"); |
1451 | MODULE_AUTHOR("Vladimir Barinov"); | |
1452 | MODULE_LICENSE("GPL"); |