[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / jz4740.c

/*
 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include <linux/delay.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>

#define JZ4740_REG_CODEC_1 0x0
#define JZ4740_REG_CODEC_2 0x1

#define JZ4740_CODEC_1_LINE_ENABLE BIT(29)
#define JZ4740_CODEC_1_MIC_ENABLE BIT(28)
#define JZ4740_CODEC_1_SW1_ENABLE BIT(27)
#define JZ4740_CODEC_1_ADC_ENABLE BIT(26)
#define JZ4740_CODEC_1_SW2_ENABLE BIT(25)
#define JZ4740_CODEC_1_DAC_ENABLE BIT(24)
#define JZ4740_CODEC_1_VREF_DISABLE BIT(20)
#define JZ4740_CODEC_1_VREF_AMP_DISABLE BIT(19)
#define JZ4740_CODEC_1_VREF_PULLDOWN BIT(18)
#define JZ4740_CODEC_1_VREF_LOW_CURRENT BIT(17)
#define JZ4740_CODEC_1_VREF_HIGH_CURRENT BIT(16)
#define JZ4740_CODEC_1_HEADPHONE_DISABLE BIT(14)
#define JZ4740_CODEC_1_HEADPHONE_AMP_CHANGE_ANY BIT(13)
#define JZ4740_CODEC_1_HEADPHONE_CHARGE BIT(12)
#define JZ4740_CODEC_1_HEADPHONE_PULLDOWN (BIT(11) | BIT(10))
#define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M BIT(9)
#define JZ4740_CODEC_1_HEADPHONE_POWERDOWN BIT(8)
#define JZ4740_CODEC_1_SUSPEND BIT(1)
#define JZ4740_CODEC_1_RESET BIT(0)

#define JZ4740_CODEC_1_LINE_ENABLE_OFFSET 29
#define JZ4740_CODEC_1_MIC_ENABLE_OFFSET 28
#define JZ4740_CODEC_1_SW1_ENABLE_OFFSET 27
#define JZ4740_CODEC_1_ADC_ENABLE_OFFSET 26
#define JZ4740_CODEC_1_SW2_ENABLE_OFFSET 25
#define JZ4740_CODEC_1_DAC_ENABLE_OFFSET 24
#define JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET 14
#define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET 8

#define JZ4740_CODEC_2_INPUT_VOLUME_MASK		0x1f0000
#define JZ4740_CODEC_2_SAMPLE_RATE_MASK			0x000f00
#define JZ4740_CODEC_2_MIC_BOOST_GAIN_MASK		0x000030
#define JZ4740_CODEC_2_HEADPHONE_VOLUME_MASK	0x000003

#define JZ4740_CODEC_2_INPUT_VOLUME_OFFSET		16
#define JZ4740_CODEC_2_SAMPLE_RATE_OFFSET		 8
#define JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET	 4
#define JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET	 0

static const uint32_t jz4740_codec_regs[] = {
	0x021b2302, 0x00170803,
};

struct jz4740_codec {
	void __iomem *base;
	struct resource *mem;
};

static unsigned int jz4740_codec_read(struct snd_soc_codec *codec,
	unsigned int reg)
{
	struct jz4740_codec *jz4740_codec = snd_soc_codec_get_drvdata(codec);
	return readl(jz4740_codec->base + (reg << 2));
}

static int jz4740_codec_write(struct snd_soc_codec *codec, unsigned int reg,
	unsigned int val)
{
	struct jz4740_codec *jz4740_codec = snd_soc_codec_get_drvdata(codec);
	u32 *cache = codec->reg_cache;

	cache[reg] = val;
	writel(val, jz4740_codec->base + (reg << 2));

	return 0;
}

static const struct snd_kcontrol_new jz4740_codec_controls[] = {
	SOC_SINGLE("Master Playback Volume", JZ4740_REG_CODEC_2,
			JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET, 3, 0),
	SOC_SINGLE("Master Capture Volume", JZ4740_REG_CODEC_2,
			JZ4740_CODEC_2_INPUT_VOLUME_OFFSET, 31, 0),
	SOC_SINGLE("Master Playback Switch", JZ4740_REG_CODEC_1,
			JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET, 1, 1),
	SOC_SINGLE("Mic Capture Volume", JZ4740_REG_CODEC_2,
			JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET, 3, 0),
};

static const struct snd_kcontrol_new jz4740_codec_output_controls[] = {
	SOC_DAPM_SINGLE("Bypass Switch", JZ4740_REG_CODEC_1,
			JZ4740_CODEC_1_SW1_ENABLE_OFFSET, 1, 0),
	SOC_DAPM_SINGLE("DAC Switch", JZ4740_REG_CODEC_1,
			JZ4740_CODEC_1_SW2_ENABLE_OFFSET, 1, 0),
};

static const struct snd_kcontrol_new jz4740_codec_input_controls[] = {
	SOC_DAPM_SINGLE("Line Capture Switch", JZ4740_REG_CODEC_1,
			JZ4740_CODEC_1_LINE_ENABLE_OFFSET, 1, 0),
	SOC_DAPM_SINGLE("Mic Capture Switch", JZ4740_REG_CODEC_1,
			JZ4740_CODEC_1_MIC_ENABLE_OFFSET, 1, 0),
};

static const struct snd_soc_dapm_widget jz4740_codec_dapm_widgets[] = {
	SND_SOC_DAPM_ADC("ADC", "Capture", JZ4740_REG_CODEC_1,
			JZ4740_CODEC_1_ADC_ENABLE_OFFSET, 0),
	SND_SOC_DAPM_DAC("DAC", "Playback", JZ4740_REG_CODEC_1,
			JZ4740_CODEC_1_DAC_ENABLE_OFFSET, 0),

	SND_SOC_DAPM_MIXER("Output Mixer", JZ4740_REG_CODEC_1,
			JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET, 1,
			jz4740_codec_output_controls,
			ARRAY_SIZE(jz4740_codec_output_controls)),

	SND_SOC_DAPM_MIXER_NAMED_CTL("Input Mixer", SND_SOC_NOPM, 0, 0,
			jz4740_codec_input_controls,
			ARRAY_SIZE(jz4740_codec_input_controls)),
	SND_SOC_DAPM_MIXER("Line Input", SND_SOC_NOPM, 0, 0, NULL, 0),

	SND_SOC_DAPM_OUTPUT("LOUT"),
	SND_SOC_DAPM_OUTPUT("ROUT"),

	SND_SOC_DAPM_INPUT("MIC"),
	SND_SOC_DAPM_INPUT("LIN"),
	SND_SOC_DAPM_INPUT("RIN"),
};

static const struct snd_soc_dapm_route jz4740_codec_dapm_routes[] = {
	{"Line Input", NULL, "LIN"},
	{"Line Input", NULL, "RIN"},

	{"Input Mixer", "Line Capture Switch", "Line Input"},
	{"Input Mixer", "Mic Capture Switch", "MIC"},

	{"ADC", NULL, "Input Mixer"},

	{"Output Mixer", "Bypass Switch", "Input Mixer"},
	{"Output Mixer", "DAC Switch", "DAC"},

	{"LOUT", NULL, "Output Mixer"},
	{"ROUT", NULL, "Output Mixer"},
};

static int jz4740_codec_hw_params(struct snd_pcm_substream *substream,
	struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
	uint32_t val;
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_codec *codec =rtd->codec;

	switch (params_rate(params)) {
	case 8000:
		val = 0;
		break;
	case 11025:
		val = 1;
		break;
	case 12000:
		val = 2;
		break;
	case 16000:
		val = 3;
		break;
	case 22050:
		val = 4;
		break;
	case 24000:
		val = 5;
		break;
	case 32000:
		val = 6;
		break;
	case 44100:
		val = 7;
		break;
	case 48000:
		val = 8;
		break;
	default:
		return -EINVAL;
	}

	val <<= JZ4740_CODEC_2_SAMPLE_RATE_OFFSET;

	snd_soc_update_bits(codec, JZ4740_REG_CODEC_2,
				JZ4740_CODEC_2_SAMPLE_RATE_MASK, val);

	return 0;
}

static struct snd_soc_dai_ops jz4740_codec_dai_ops = {
	.hw_params = jz4740_codec_hw_params,
};

static struct snd_soc_dai_driver jz4740_codec_dai = {
	.name = "jz4740-hifi",
	.playback = {
		.stream_name = "Playback",
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_48000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
	},
	.capture = {
		.stream_name = "Capture",
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_48000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
	},
	.ops = &jz4740_codec_dai_ops,
	.symmetric_rates = 1,
};

static void jz4740_codec_wakeup(struct snd_soc_codec *codec)
{
	int i;
	uint32_t *cache = codec->reg_cache;

	snd_soc_update_bits(codec, JZ4740_REG_CODEC_1,
		JZ4740_CODEC_1_RESET, JZ4740_CODEC_1_RESET);
	udelay(2);

	snd_soc_update_bits(codec, JZ4740_REG_CODEC_1,
		JZ4740_CODEC_1_SUSPEND | JZ4740_CODEC_1_RESET, 0);

	for (i = 0; i < ARRAY_SIZE(jz4740_codec_regs); ++i)
		jz4740_codec_write(codec, i, cache[i]);
}

static int jz4740_codec_set_bias_level(struct snd_soc_codec *codec,
	enum snd_soc_bias_level level)
{
	unsigned int mask;
	unsigned int value;

	switch (level) {
	case SND_SOC_BIAS_ON:
		break;
	case SND_SOC_BIAS_PREPARE:
		mask = JZ4740_CODEC_1_VREF_DISABLE |
				JZ4740_CODEC_1_VREF_AMP_DISABLE |
				JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
		value = 0;

		snd_soc_update_bits(codec, JZ4740_REG_CODEC_1, mask, value);
		break;
	case SND_SOC_BIAS_STANDBY:
		/* The only way to clear the suspend flag is to reset the codec */
		if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
			jz4740_codec_wakeup(codec);

		mask = JZ4740_CODEC_1_VREF_DISABLE |
			JZ4740_CODEC_1_VREF_AMP_DISABLE |
			JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
		value = JZ4740_CODEC_1_VREF_DISABLE |
			JZ4740_CODEC_1_VREF_AMP_DISABLE |
			JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;

		snd_soc_update_bits(codec, JZ4740_REG_CODEC_1, mask, value);
		break;
	case SND_SOC_BIAS_OFF:
		mask = JZ4740_CODEC_1_SUSPEND;
		value = JZ4740_CODEC_1_SUSPEND;

		snd_soc_update_bits(codec, JZ4740_REG_CODEC_1, mask, value);
		break;
	default:
		break;
	}

	codec->dapm.bias_level = level;

	return 0;
}

static int jz4740_codec_dev_probe(struct snd_soc_codec *codec)
{
	struct snd_soc_dapm_context *dapm = &codec->dapm;

	snd_soc_update_bits(codec, JZ4740_REG_CODEC_1,
			JZ4740_CODEC_1_SW2_ENABLE, JZ4740_CODEC_1_SW2_ENABLE);

	snd_soc_add_controls(codec, jz4740_codec_controls,
		ARRAY_SIZE(jz4740_codec_controls));

	snd_soc_dapm_new_controls(dapm, jz4740_codec_dapm_widgets,
		ARRAY_SIZE(jz4740_codec_dapm_widgets));

	snd_soc_dapm_add_routes(dapm, jz4740_codec_dapm_routes,
		ARRAY_SIZE(jz4740_codec_dapm_routes));

	jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);

	return 0;
}

static int jz4740_codec_dev_remove(struct snd_soc_codec *codec)
{
	jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_OFF);

	return 0;
}

#ifdef CONFIG_PM_SLEEP

static int jz4740_codec_suspend(struct snd_soc_codec *codec, pm_message_t state)
{
	return jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_OFF);
}

static int jz4740_codec_resume(struct snd_soc_codec *codec)
{
	return jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
}

#else
#define jz4740_codec_suspend NULL
#define jz4740_codec_resume NULL
#endif

static struct snd_soc_codec_driver soc_codec_dev_jz4740_codec = {
	.probe = jz4740_codec_dev_probe,
	.remove = jz4740_codec_dev_remove,
	.suspend = jz4740_codec_suspend,
	.resume = jz4740_codec_resume,
	.read = jz4740_codec_read,
	.write = jz4740_codec_write,
	.set_bias_level = jz4740_codec_set_bias_level,
	.reg_cache_default	= jz4740_codec_regs,
	.reg_word_size = sizeof(u32),
	.reg_cache_size	= 2,
};

static int __devinit jz4740_codec_probe(struct platform_device *pdev)
{
	int ret;
	struct jz4740_codec *jz4740_codec;
	struct resource *mem;

	jz4740_codec = kzalloc(sizeof(*jz4740_codec), GFP_KERNEL);
	if (!jz4740_codec)
		return -ENOMEM;

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem) {
		dev_err(&pdev->dev, "Failed to get mmio memory resource\n");
		ret = -ENOENT;
		goto err_free_codec;
	}

	mem = request_mem_region(mem->start, resource_size(mem), pdev->name);
	if (!mem) {
		dev_err(&pdev->dev, "Failed to request mmio memory region\n");
		ret = -EBUSY;
		goto err_free_codec;
	}

	jz4740_codec->base = ioremap(mem->start, resource_size(mem));
	if (!jz4740_codec->base) {
		dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
		ret = -EBUSY;
		goto err_release_mem_region;
	}
	jz4740_codec->mem = mem;

	platform_set_drvdata(pdev, jz4740_codec);

	ret = snd_soc_register_codec(&pdev->dev,
			&soc_codec_dev_jz4740_codec, &jz4740_codec_dai, 1);
	if (ret) {
		dev_err(&pdev->dev, "Failed to register codec\n");
		goto err_iounmap;
	}

	return 0;

err_iounmap:
	iounmap(jz4740_codec->base);
err_release_mem_region:
	release_mem_region(mem->start, resource_size(mem));
err_free_codec:
	kfree(jz4740_codec);

	return ret;
}

static int __devexit jz4740_codec_remove(struct platform_device *pdev)
{
	struct jz4740_codec *jz4740_codec = platform_get_drvdata(pdev);
	struct resource *mem = jz4740_codec->mem;

	snd_soc_unregister_codec(&pdev->dev);

	iounmap(jz4740_codec->base);
	release_mem_region(mem->start, resource_size(mem));

	platform_set_drvdata(pdev, NULL);
	kfree(jz4740_codec);

	return 0;
}

static struct platform_driver jz4740_codec_driver = {
	.probe = jz4740_codec_probe,
	.remove = __devexit_p(jz4740_codec_remove),
	.driver = {
		.name = "jz4740-codec",
		.owner = THIS_MODULE,
	},
};

static int __init jz4740_codec_init(void)
{
	return platform_driver_register(&jz4740_codec_driver);
}
module_init(jz4740_codec_init);

static void __exit jz4740_codec_exit(void)
{
	platform_driver_unregister(&jz4740_codec_driver);
}
module_exit(jz4740_codec_exit);

MODULE_DESCRIPTION("JZ4740 SoC internal codec driver");
MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:jz4740-codec");
Commit	Line	Data
3b097d64 LPC	1	/*
	2	* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* You should have received a copy of the GNU General Public License along
	9	* with this program; if not, write to the Free Software Foundation, Inc.,
	10	* 675 Mass Ave, Cambridge, MA 02139, USA.
	11	*
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/module.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/slab.h>
	18
	19	#include <linux/delay.h>
	20
	21	#include <sound/core.h>
	22	#include <sound/pcm.h>
	23	#include <sound/pcm_params.h>
	24	#include <sound/initval.h>
3b097d64 LPC	25	#include <sound/soc.h>
	26
	27	#define JZ4740_REG_CODEC_1 0x0
	28	#define JZ4740_REG_CODEC_2 0x1
	29
	30	#define JZ4740_CODEC_1_LINE_ENABLE BIT(29)
	31	#define JZ4740_CODEC_1_MIC_ENABLE BIT(28)
	32	#define JZ4740_CODEC_1_SW1_ENABLE BIT(27)
	33	#define JZ4740_CODEC_1_ADC_ENABLE BIT(26)
	34	#define JZ4740_CODEC_1_SW2_ENABLE BIT(25)
	35	#define JZ4740_CODEC_1_DAC_ENABLE BIT(24)
	36	#define JZ4740_CODEC_1_VREF_DISABLE BIT(20)
	37	#define JZ4740_CODEC_1_VREF_AMP_DISABLE BIT(19)
	38	#define JZ4740_CODEC_1_VREF_PULLDOWN BIT(18)
	39	#define JZ4740_CODEC_1_VREF_LOW_CURRENT BIT(17)
	40	#define JZ4740_CODEC_1_VREF_HIGH_CURRENT BIT(16)
	41	#define JZ4740_CODEC_1_HEADPHONE_DISABLE BIT(14)
	42	#define JZ4740_CODEC_1_HEADPHONE_AMP_CHANGE_ANY BIT(13)
	43	#define JZ4740_CODEC_1_HEADPHONE_CHARGE BIT(12)
	44	#define JZ4740_CODEC_1_HEADPHONE_PULLDOWN (BIT(11) \| BIT(10))
	45	#define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M BIT(9)
	46	#define JZ4740_CODEC_1_HEADPHONE_POWERDOWN BIT(8)
	47	#define JZ4740_CODEC_1_SUSPEND BIT(1)
	48	#define JZ4740_CODEC_1_RESET BIT(0)
	49
	50	#define JZ4740_CODEC_1_LINE_ENABLE_OFFSET 29
	51	#define JZ4740_CODEC_1_MIC_ENABLE_OFFSET 28
	52	#define JZ4740_CODEC_1_SW1_ENABLE_OFFSET 27
	53	#define JZ4740_CODEC_1_ADC_ENABLE_OFFSET 26
	54	#define JZ4740_CODEC_1_SW2_ENABLE_OFFSET 25
	55	#define JZ4740_CODEC_1_DAC_ENABLE_OFFSET 24
	56	#define JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET 14
	57	#define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET 8
	58
	59	#define JZ4740_CODEC_2_INPUT_VOLUME_MASK 0x1f0000
	60	#define JZ4740_CODEC_2_SAMPLE_RATE_MASK 0x000f00
	61	#define JZ4740_CODEC_2_MIC_BOOST_GAIN_MASK 0x000030
	62	#define JZ4740_CODEC_2_HEADPHONE_VOLUME_MASK 0x000003
	63
	64	#define JZ4740_CODEC_2_INPUT_VOLUME_OFFSET 16
	65	#define JZ4740_CODEC_2_SAMPLE_RATE_OFFSET 8
	66	#define JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET 4
	67	#define JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET 0
	68
	69	static const uint32_t jz4740_codec_regs[] = {
	70	0x021b2302, 0x00170803,
	71	};
	72
	73	struct jz4740_codec {
	74	void __iomem *base;
	75	struct resource *mem;
3b097d64 LPC	76	};
3b097d64 LPC	77
3b097d64 LPC	78	static unsigned int jz4740_codec_read(struct snd_soc_codec *codec,
	79	unsigned int reg)
	80	{
f0fba2ad	81	struct jz4740_codec *jz4740_codec = snd_soc_codec_get_drvdata(codec);
3b097d64 LPC	82	return readl(jz4740_codec->base + (reg << 2));
	83	}
	84
	85	static int jz4740_codec_write(struct snd_soc_codec *codec, unsigned int reg,
	86	unsigned int val)
	87	{
f0fba2ad LG	88	struct jz4740_codec *jz4740_codec = snd_soc_codec_get_drvdata(codec);
f0fba2ad LG	89	u32 *cache = codec->reg_cache;
3b097d64	90
f0fba2ad	91	cache[reg] = val;
3b097d64 LPC	92	writel(val, jz4740_codec->base + (reg << 2));
	93
	94	return 0;
	95	}
	96
	97	static const struct snd_kcontrol_new jz4740_codec_controls[] = {
	98	SOC_SINGLE("Master Playback Volume", JZ4740_REG_CODEC_2,
	99	JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET, 3, 0),
	100	SOC_SINGLE("Master Capture Volume", JZ4740_REG_CODEC_2,
	101	JZ4740_CODEC_2_INPUT_VOLUME_OFFSET, 31, 0),
	102	SOC_SINGLE("Master Playback Switch", JZ4740_REG_CODEC_1,
	103	JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET, 1, 1),
	104	SOC_SINGLE("Mic Capture Volume", JZ4740_REG_CODEC_2,
	105	JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET, 3, 0),
	106	};
	107
	108	static const struct snd_kcontrol_new jz4740_codec_output_controls[] = {
	109	SOC_DAPM_SINGLE("Bypass Switch", JZ4740_REG_CODEC_1,
	110	JZ4740_CODEC_1_SW1_ENABLE_OFFSET, 1, 0),
	111	SOC_DAPM_SINGLE("DAC Switch", JZ4740_REG_CODEC_1,
	112	JZ4740_CODEC_1_SW2_ENABLE_OFFSET, 1, 0),
	113	};
	114
	115	static const struct snd_kcontrol_new jz4740_codec_input_controls[] = {
	116	SOC_DAPM_SINGLE("Line Capture Switch", JZ4740_REG_CODEC_1,
	117	JZ4740_CODEC_1_LINE_ENABLE_OFFSET, 1, 0),
	118	SOC_DAPM_SINGLE("Mic Capture Switch", JZ4740_REG_CODEC_1,
	119	JZ4740_CODEC_1_MIC_ENABLE_OFFSET, 1, 0),
	120	};
	121
	122	static const struct snd_soc_dapm_widget jz4740_codec_dapm_widgets[] = {
	123	SND_SOC_DAPM_ADC("ADC", "Capture", JZ4740_REG_CODEC_1,
	124	JZ4740_CODEC_1_ADC_ENABLE_OFFSET, 0),
	125	SND_SOC_DAPM_DAC("DAC", "Playback", JZ4740_REG_CODEC_1,
	126	JZ4740_CODEC_1_DAC_ENABLE_OFFSET, 0),
	127
	128	SND_SOC_DAPM_MIXER("Output Mixer", JZ4740_REG_CODEC_1,
	129	JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET, 1,
	130	jz4740_codec_output_controls,
	131	ARRAY_SIZE(jz4740_codec_output_controls)),
	132
	133	SND_SOC_DAPM_MIXER_NAMED_CTL("Input Mixer", SND_SOC_NOPM, 0, 0,
	134	jz4740_codec_input_controls,
	135	ARRAY_SIZE(jz4740_codec_input_controls)),
	136	SND_SOC_DAPM_MIXER("Line Input", SND_SOC_NOPM, 0, 0, NULL, 0),
	137
	138	SND_SOC_DAPM_OUTPUT("LOUT"),
	139	SND_SOC_DAPM_OUTPUT("ROUT"),
	140
	141	SND_SOC_DAPM_INPUT("MIC"),
	142	SND_SOC_DAPM_INPUT("LIN"),
	143	SND_SOC_DAPM_INPUT("RIN"),
	144	};
	145
	146	static const struct snd_soc_dapm_route jz4740_codec_dapm_routes[] = {
	147	{"Line Input", NULL, "LIN"},
	148	{"Line Input", NULL, "RIN"},
	149
	150	{"Input Mixer", "Line Capture Switch", "Line Input"},
	151	{"Input Mixer", "Mic Capture Switch", "MIC"},
	152
	153	{"ADC", NULL, "Input Mixer"},
	154
	155	{"Output Mixer", "Bypass Switch", "Input Mixer"},
156	{"Output Mixer", "DAC Switch", "DAC"},
157
158	{"LOUT", NULL, "Output Mixer"},
159	{"ROUT", NULL, "Output Mixer"},
160	};
161
162	static int jz4740_codec_hw_params(struct snd_pcm_substream *substream,
163	struct snd_pcm_hw_params params, struct snd_soc_dai dai)
164	{
165	uint32_t val;
166	struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad	167	struct snd_soc_codec *codec =rtd->codec;
3b097d64 LPC	168
	169	switch (params_rate(params)) {
	170	case 8000:
	171	val = 0;
	172	break;
	173	case 11025:
	174	val = 1;
	175	break;
	176	case 12000:
	177	val = 2;
	178	break;
	179	case 16000:
	180	val = 3;
	181	break;
	182	case 22050:
	183	val = 4;
	184	break;
	185	case 24000:
	186	val = 5;
	187	break;
	188	case 32000:
	189	val = 6;
	190	break;
	191	case 44100:
	192	val = 7;
	193	break;
	194	case 48000:
	195	val = 8;
	196	break;
	197	default:
	198	return -EINVAL;
	199	}
	200
	201	val <<= JZ4740_CODEC_2_SAMPLE_RATE_OFFSET;
	202
	203	snd_soc_update_bits(codec, JZ4740_REG_CODEC_2,
	204	JZ4740_CODEC_2_SAMPLE_RATE_MASK, val);
	205
	206	return 0;
	207	}
	208
	209	static struct snd_soc_dai_ops jz4740_codec_dai_ops = {
	210	.hw_params = jz4740_codec_hw_params,
	211	};
	212
f0fba2ad LG	213	static struct snd_soc_dai_driver jz4740_codec_dai = {
f0fba2ad LG	214	.name = "jz4740-hifi",
3b097d64 LPC	215	.playback = {
	216	.stream_name = "Playback",
	217	.channels_min = 2,
	218	.channels_max = 2,
	219	.rates = SNDRV_PCM_RATE_8000_48000,
	220	.formats = SNDRV_PCM_FMTBIT_S16_LE \| SNDRV_PCM_FMTBIT_S8,
	221	},
	222	.capture = {
	223	.stream_name = "Capture",
	224	.channels_min = 2,
	225	.channels_max = 2,
	226	.rates = SNDRV_PCM_RATE_8000_48000,
	227	.formats = SNDRV_PCM_FMTBIT_S16_LE \| SNDRV_PCM_FMTBIT_S8,
	228	},
	229	.ops = &jz4740_codec_dai_ops,
	230	.symmetric_rates = 1,
	231	};
3b097d64 LPC	232
	233	static void jz4740_codec_wakeup(struct snd_soc_codec *codec)
	234	{
	235	int i;
	236	uint32_t *cache = codec->reg_cache;
	237
	238	snd_soc_update_bits(codec, JZ4740_REG_CODEC_1,
	239	JZ4740_CODEC_1_RESET, JZ4740_CODEC_1_RESET);
	240	udelay(2);
	241
	242	snd_soc_update_bits(codec, JZ4740_REG_CODEC_1,
	243	JZ4740_CODEC_1_SUSPEND \| JZ4740_CODEC_1_RESET, 0);
	244
	245	for (i = 0; i < ARRAY_SIZE(jz4740_codec_regs); ++i)
	246	jz4740_codec_write(codec, i, cache[i]);
	247	}
	248
	249	static int jz4740_codec_set_bias_level(struct snd_soc_codec *codec,
	250	enum snd_soc_bias_level level)
	251	{
	252	unsigned int mask;
	253	unsigned int value;
	254
	255	switch (level) {
	256	case SND_SOC_BIAS_ON:
	257	break;
	258	case SND_SOC_BIAS_PREPARE:
	259	mask = JZ4740_CODEC_1_VREF_DISABLE \|
	260	JZ4740_CODEC_1_VREF_AMP_DISABLE \|
	261	JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
	262	value = 0;
	263
	264	snd_soc_update_bits(codec, JZ4740_REG_CODEC_1, mask, value);
	265	break;
	266	case SND_SOC_BIAS_STANDBY:
	267	/* The only way to clear the suspend flag is to reset the codec */
ce6120cc	268	if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
3b097d64 LPC	269	jz4740_codec_wakeup(codec);
	270
	271	mask = JZ4740_CODEC_1_VREF_DISABLE \|
	272	JZ4740_CODEC_1_VREF_AMP_DISABLE \|
	273	JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
	274	value = JZ4740_CODEC_1_VREF_DISABLE \|
	275	JZ4740_CODEC_1_VREF_AMP_DISABLE \|
	276	JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
	277
	278	snd_soc_update_bits(codec, JZ4740_REG_CODEC_1, mask, value);
	279	break;
	280	case SND_SOC_BIAS_OFF:
	281	mask = JZ4740_CODEC_1_SUSPEND;
	282	value = JZ4740_CODEC_1_SUSPEND;
	283
	284	snd_soc_update_bits(codec, JZ4740_REG_CODEC_1, mask, value);
	285	break;
	286	default:
	287	break;
	288	}
	289
ce6120cc	290	codec->dapm.bias_level = level;
3b097d64 LPC	291
	292	return 0;
	293	}
	294
f0fba2ad	295	static int jz4740_codec_dev_probe(struct snd_soc_codec *codec)
3b097d64	296	{
ce6120cc LG	297	struct snd_soc_dapm_context *dapm = &codec->dapm;
ce6120cc LG	298
f0fba2ad LG	299	snd_soc_update_bits(codec, JZ4740_REG_CODEC_1,
f0fba2ad LG	300	JZ4740_CODEC_1_SW2_ENABLE, JZ4740_CODEC_1_SW2_ENABLE);
3b097d64 LPC	301
	302	snd_soc_add_controls(codec, jz4740_codec_controls,
	303	ARRAY_SIZE(jz4740_codec_controls));
	304
ce6120cc	305	snd_soc_dapm_new_controls(dapm, jz4740_codec_dapm_widgets,
3b097d64 LPC	306	ARRAY_SIZE(jz4740_codec_dapm_widgets));
3b097d64 LPC	307
ce6120cc	308	snd_soc_dapm_add_routes(dapm, jz4740_codec_dapm_routes,
3b097d64 LPC	309	ARRAY_SIZE(jz4740_codec_dapm_routes));
3b097d64 LPC	310
f0fba2ad LG	311	jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
f0fba2ad LG	312
3b097d64 LPC	313	return 0;
	314	}
	315
f0fba2ad	316	static int jz4740_codec_dev_remove(struct snd_soc_codec *codec)
3b097d64	317	{
f0fba2ad	318	jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_OFF);
3b097d64 LPC	319
	320	return 0;
	321	}
	322
	323	#ifdef CONFIG_PM_SLEEP
	324
f0fba2ad	325	static int jz4740_codec_suspend(struct snd_soc_codec *codec, pm_message_t state)
3b097d64	326	{
3b097d64 LPC	327	return jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_OFF);
	328	}
	329
f0fba2ad	330	static int jz4740_codec_resume(struct snd_soc_codec *codec)
3b097d64	331	{
3b097d64 LPC	332	return jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
	333	}
	334
	335	#else
	336	#define jz4740_codec_suspend NULL
	337	#define jz4740_codec_resume NULL
	338	#endif
	339
f0fba2ad	340	static struct snd_soc_codec_driver soc_codec_dev_jz4740_codec = {
3b097d64 LPC	341	.probe = jz4740_codec_dev_probe,
	342	.remove = jz4740_codec_dev_remove,
	343	.suspend = jz4740_codec_suspend,
	344	.resume = jz4740_codec_resume,
f0fba2ad LG	345	.read = jz4740_codec_read,
	346	.write = jz4740_codec_write,
	347	.set_bias_level = jz4740_codec_set_bias_level,
	348	.reg_cache_default = jz4740_codec_regs,
	349	.reg_word_size = sizeof(u32),
	350	.reg_cache_size = 2,
3b097d64	351	};
3b097d64 LPC	352
	353	static int __devinit jz4740_codec_probe(struct platform_device *pdev)
	354	{
	355	int ret;
	356	struct jz4740_codec *jz4740_codec;
3b097d64 LPC	357	struct resource *mem;
	358
	359	jz4740_codec = kzalloc(sizeof(*jz4740_codec), GFP_KERNEL);
	360	if (!jz4740_codec)
	361	return -ENOMEM;
	362
	363	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	364	if (!mem) {
	365	dev_err(&pdev->dev, "Failed to get mmio memory resource\n");
	366	ret = -ENOENT;
	367	goto err_free_codec;
	368	}
	369
	370	mem = request_mem_region(mem->start, resource_size(mem), pdev->name);
	371	if (!mem) {
	372	dev_err(&pdev->dev, "Failed to request mmio memory region\n");
	373	ret = -EBUSY;
	374	goto err_free_codec;
	375	}
	376
	377	jz4740_codec->base = ioremap(mem->start, resource_size(mem));
	378	if (!jz4740_codec->base) {
	379	dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
	380	ret = -EBUSY;
	381	goto err_release_mem_region;
	382	}
	383	jz4740_codec->mem = mem;
	384
3b097d64 LPC	385	platform_set_drvdata(pdev, jz4740_codec);
3b097d64 LPC	386
f0fba2ad LG	387	ret = snd_soc_register_codec(&pdev->dev,
f0fba2ad LG	388	&soc_codec_dev_jz4740_codec, &jz4740_codec_dai, 1);
3b097d64 LPC	389	if (ret) {
	390	dev_err(&pdev->dev, "Failed to register codec\n");
	391	goto err_iounmap;
	392	}
	393
3b097d64 LPC	394	return 0;
3b097d64 LPC	395
3b097d64 LPC	396	err_iounmap:
	397	iounmap(jz4740_codec->base);
	398	err_release_mem_region:
	399	release_mem_region(mem->start, resource_size(mem));
	400	err_free_codec:
	401	kfree(jz4740_codec);
	402
	403	return ret;
	404	}
	405
	406	static int __devexit jz4740_codec_remove(struct platform_device *pdev)
	407	{
	408	struct jz4740_codec *jz4740_codec = platform_get_drvdata(pdev);
	409	struct resource *mem = jz4740_codec->mem;
	410
f0fba2ad	411	snd_soc_unregister_codec(&pdev->dev);
3b097d64 LPC	412
	413	iounmap(jz4740_codec->base);
	414	release_mem_region(mem->start, resource_size(mem));
	415
	416	platform_set_drvdata(pdev, NULL);
	417	kfree(jz4740_codec);
	418
	419	return 0;
	420	}
	421
	422	static struct platform_driver jz4740_codec_driver = {
	423	.probe = jz4740_codec_probe,
	424	.remove = __devexit_p(jz4740_codec_remove),
	425	.driver = {
	426	.name = "jz4740-codec",
	427	.owner = THIS_MODULE,
	428	},
	429	};
	430
	431	static int __init jz4740_codec_init(void)
	432	{
	433	return platform_driver_register(&jz4740_codec_driver);
	434	}
	435	module_init(jz4740_codec_init);
	436
	437	static void __exit jz4740_codec_exit(void)
	438	{
	439	platform_driver_unregister(&jz4740_codec_driver);
	440	}
	441	module_exit(jz4740_codec_exit);
	442
	443	MODULE_DESCRIPTION("JZ4740 SoC internal codec driver");
	444	MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
	445	MODULE_LICENSE("GPL v2");
	446	MODULE_ALIAS("platform:jz4740-codec");