[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / ak4642.c

/*
 * ak4642.c  --  AK4642/AK4643 ALSA Soc Audio driver
 *
 * Copyright (C) 2009 Renesas Solutions Corp.
 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
 *
 * Based on wm8731.c by Richard Purdie
 * Based on ak4535.c by Richard Purdie
 * Based on wm8753.c by Liam Girdwood
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/* ** CAUTION **
 *
 * This is very simple driver.
 * It can use headphone output / stereo input only
 *
 * AK4642 is tested.
 * AK4643 is tested.
 */

#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>

#define AK4642_VERSION "0.0.1"

#define PW_MGMT1	0x00
#define PW_MGMT2	0x01
#define SG_SL1		0x02
#define SG_SL2		0x03
#define MD_CTL1		0x04
#define MD_CTL2		0x05
#define TIMER		0x06
#define ALC_CTL1	0x07
#define ALC_CTL2	0x08
#define L_IVC		0x09
#define L_DVC		0x0a
#define ALC_CTL3	0x0b
#define R_IVC		0x0c
#define R_DVC		0x0d
#define MD_CTL3		0x0e
#define MD_CTL4		0x0f
#define PW_MGMT3	0x10
#define DF_S		0x11
#define FIL3_0		0x12
#define FIL3_1		0x13
#define FIL3_2		0x14
#define FIL3_3		0x15
#define EQ_0		0x16
#define EQ_1		0x17
#define EQ_2		0x18
#define EQ_3		0x19
#define EQ_4		0x1a
#define EQ_5		0x1b
#define FIL1_0		0x1c
#define FIL1_1		0x1d
#define FIL1_2		0x1e
#define FIL1_3		0x1f
#define PW_MGMT4	0x20
#define MD_CTL5		0x21
#define LO_MS		0x22
#define HP_MS		0x23
#define SPK_MS		0x24

#define AK4642_CACHEREGNUM 	0x25

/* PW_MGMT1*/
#define PMVCM		(1 << 6) /* VCOM Power Management */
#define PMMIN		(1 << 5) /* MIN Input Power Management */
#define PMDAC		(1 << 2) /* DAC Power Management */
#define PMADL		(1 << 0) /* MIC Amp Lch and ADC Lch Power Management */

/* PW_MGMT2 */
#define HPMTN		(1 << 6)
#define PMHPL		(1 << 5)
#define PMHPR		(1 << 4)
#define MS		(1 << 3) /* master/slave select */
#define MCKO		(1 << 1)
#define PMPLL		(1 << 0)

#define PMHP_MASK	(PMHPL | PMHPR)
#define PMHP		PMHP_MASK

/* PW_MGMT3 */
#define PMADR		(1 << 0) /* MIC L / ADC R Power Management */

/* SG_SL1 */
#define MINS		(1 << 6) /* Switch from MIN to Speaker */
#define DACL		(1 << 4) /* Switch from DAC to Stereo or Receiver */
#define PMMP		(1 << 2) /* MPWR pin Power Management */
#define MGAIN0		(1 << 0) /* MIC amp gain*/

/* TIMER */
#define ZTM(param)	((param & 0x3) << 4) /* ALC Zoro Crossing TimeOut */
#define WTM(param)	(((param & 0x4) << 4) | ((param & 0x3) << 2))

/* ALC_CTL1 */
#define ALC		(1 << 5) /* ALC Enable */
#define LMTH0		(1 << 0) /* ALC Limiter / Recovery Level */

/* MD_CTL1 */
#define PLL3		(1 << 7)
#define PLL2		(1 << 6)
#define PLL1		(1 << 5)
#define PLL0		(1 << 4)
#define PLL_MASK	(PLL3 | PLL2 | PLL1 | PLL0)

#define BCKO_MASK	(1 << 3)
#define BCKO_64		BCKO_MASK

#define DIF_MASK	(3 << 0)
#define DSP		(0 << 0)
#define RIGHT_J		(1 << 0)
#define LEFT_J		(2 << 0)
#define I2S		(3 << 0)

/* MD_CTL2 */
#define FS0		(1 << 0)
#define FS1		(1 << 1)
#define FS2		(1 << 2)
#define FS3		(1 << 5)
#define FS_MASK		(FS0 | FS1 | FS2 | FS3)

/* MD_CTL3 */
#define BST1		(1 << 3)

/* MD_CTL4 */
#define DACH		(1 << 0)

/*
 * Playback Volume (table 39)
 *
 * max : 0x00 : +12.0 dB
 *       ( 0.5 dB step )
 * min : 0xFE : -115.0 dB
 * mute: 0xFF
 */
static const DECLARE_TLV_DB_SCALE(out_tlv, -11500, 50, 1);

static const struct snd_kcontrol_new ak4642_snd_controls[] = {

	SOC_DOUBLE_R_TLV("Digital Playback Volume", L_DVC, R_DVC,
			 0, 0xFF, 1, out_tlv),

	SOC_SINGLE("Headphone Switch", PW_MGMT2, 6, 1, 0),
};

static const struct snd_kcontrol_new ak4642_hpout_mixer_controls[] = {
	SOC_DAPM_SINGLE("DACH", MD_CTL4, 0, 1, 0),
};

static const struct snd_kcontrol_new ak4642_lout_mixer_controls[] = {
	SOC_DAPM_SINGLE("DACL", SG_SL1, 4, 1, 0),
};

static const struct snd_soc_dapm_widget ak4642_dapm_widgets[] = {

	/* Outputs */
	SND_SOC_DAPM_OUTPUT("HPOUTL"),
	SND_SOC_DAPM_OUTPUT("HPOUTR"),
	SND_SOC_DAPM_OUTPUT("LINEOUT"),

	SND_SOC_DAPM_MIXER("HPOUTL Mixer", PW_MGMT2, 5, 0,
			   &ak4642_hpout_mixer_controls[0],
			   ARRAY_SIZE(ak4642_hpout_mixer_controls)),

	SND_SOC_DAPM_MIXER("HPOUTR Mixer", PW_MGMT2, 4, 0,
			   &ak4642_hpout_mixer_controls[0],
			   ARRAY_SIZE(ak4642_hpout_mixer_controls)),

	SND_SOC_DAPM_MIXER("LINEOUT Mixer", PW_MGMT1, 3, 0,
			   &ak4642_lout_mixer_controls[0],
			   ARRAY_SIZE(ak4642_lout_mixer_controls)),

	/* DAC */
	SND_SOC_DAPM_DAC("DAC", "HiFi Playback", PW_MGMT1, 2, 0),
};

static const struct snd_soc_dapm_route ak4642_intercon[] = {

	/* Outputs */
	{"HPOUTL", NULL, "HPOUTL Mixer"},
	{"HPOUTR", NULL, "HPOUTR Mixer"},
	{"LINEOUT", NULL, "LINEOUT Mixer"},

	{"HPOUTL Mixer", "DACH", "DAC"},
	{"HPOUTR Mixer", "DACH", "DAC"},
	{"LINEOUT Mixer", "DACL", "DAC"},
};

/* codec private data */
struct ak4642_priv {
	unsigned int sysclk;
	enum snd_soc_control_type control_type;
};

/*
 * ak4642 register cache
 */
static const u8 ak4642_reg[AK4642_CACHEREGNUM] = {
	0x00, 0x00, 0x01, 0x00,
	0x02, 0x00, 0x00, 0x00,
	0xe1, 0xe1, 0x18, 0x00,
	0xe1, 0x18, 0x11, 0x08,
	0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00,
	0x00,
};

static int ak4642_dai_startup(struct snd_pcm_substream *substream,
			      struct snd_soc_dai *dai)
{
	int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
	struct snd_soc_codec *codec = dai->codec;

	if (is_play) {
		/*
		 * start headphone output
		 *
		 * PLL, Master Mode
		 * Audio I/F Format :MSB justified (ADC & DAC)
		 * Bass Boost Level : Middle
		 *
		 * This operation came from example code of
		 * "ASAHI KASEI AK4642" (japanese) manual p97.
		 */
		snd_soc_write(codec, L_IVC, 0x91); /* volume */
		snd_soc_write(codec, R_IVC, 0x91); /* volume */
	} else {
		/*
		 * start stereo input
		 *
		 * PLL Master Mode
		 * Audio I/F Format:MSB justified (ADC & DAC)
		 * Pre MIC AMP:+20dB
		 * MIC Power On
		 * ALC setting:Refer to Table 35
		 * ALC bit=“1”
		 *
		 * This operation came from example code of
		 * "ASAHI KASEI AK4642" (japanese) manual p94.
		 */
		snd_soc_write(codec, SG_SL1, PMMP | MGAIN0);
		snd_soc_write(codec, TIMER, ZTM(0x3) | WTM(0x3));
		snd_soc_write(codec, ALC_CTL1, ALC | LMTH0);
		snd_soc_update_bits(codec, PW_MGMT1, PMADL, PMADL);
		snd_soc_update_bits(codec, PW_MGMT3, PMADR, PMADR);
	}

	return 0;
}

static void ak4642_dai_shutdown(struct snd_pcm_substream *substream,
			       struct snd_soc_dai *dai)
{
	int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
	struct snd_soc_codec *codec = dai->codec;

	if (is_play) {
	} else {
		/* stop stereo input */
		snd_soc_update_bits(codec, PW_MGMT1, PMADL, 0);
		snd_soc_update_bits(codec, PW_MGMT3, PMADR, 0);
		snd_soc_update_bits(codec, ALC_CTL1, ALC, 0);
	}
}

static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai,
	int clk_id, unsigned int freq, int dir)
{
	struct snd_soc_codec *codec = codec_dai->codec;
	u8 pll;

	switch (freq) {
	case 11289600:
		pll = PLL2;
		break;
	case 12288000:
		pll = PLL2 | PLL0;
		break;
	case 12000000:
		pll = PLL2 | PLL1;
		break;
	case 24000000:
		pll = PLL2 | PLL1 | PLL0;
		break;
	case 13500000:
		pll = PLL3 | PLL2;
		break;
	case 27000000:
		pll = PLL3 | PLL2 | PLL0;
		break;
	default:
		return -EINVAL;
	}
	snd_soc_update_bits(codec, MD_CTL1, PLL_MASK, pll);

	return 0;
}

static int ak4642_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
	struct snd_soc_codec *codec = dai->codec;
	u8 data;
	u8 bcko;

	data = MCKO | PMPLL; /* use MCKO */
	bcko = 0;

	/* set master/slave audio interface */
	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBM_CFM:
		data |= MS;
		bcko = BCKO_64;
		break;
	case SND_SOC_DAIFMT_CBS_CFS:
		break;
	default:
		return -EINVAL;
	}
	snd_soc_update_bits(codec, PW_MGMT2, MS | MCKO | PMPLL, data);
	snd_soc_update_bits(codec, MD_CTL1, BCKO_MASK, bcko);

	/* format type */
	data = 0;
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_LEFT_J:
		data = LEFT_J;
		break;
	case SND_SOC_DAIFMT_I2S:
		data = I2S;
		break;
	/* FIXME
	 * Please add RIGHT_J / DSP support here
	 */
	default:
		return -EINVAL;
		break;
	}
	snd_soc_update_bits(codec, MD_CTL1, DIF_MASK, data);

	return 0;
}

static int ak4642_dai_hw_params(struct snd_pcm_substream *substream,
				struct snd_pcm_hw_params *params,
				struct snd_soc_dai *dai)
{
	struct snd_soc_codec *codec = dai->codec;
	u8 rate;

	switch (params_rate(params)) {
	case 7350:
		rate = FS2;
		break;
	case 8000:
		rate = 0;
		break;
	case 11025:
		rate = FS2 | FS0;
		break;
	case 12000:
		rate = FS0;
		break;
	case 14700:
		rate = FS2 | FS1;
		break;
	case 16000:
		rate = FS1;
		break;
	case 22050:
		rate = FS2 | FS1 | FS0;
		break;
	case 24000:
		rate = FS1 | FS0;
		break;
	case 29400:
		rate = FS3 | FS2 | FS1;
		break;
	case 32000:
		rate = FS3 | FS1;
		break;
	case 44100:
		rate = FS3 | FS2 | FS1 | FS0;
		break;
	case 48000:
		rate = FS3 | FS1 | FS0;
		break;
	default:
		return -EINVAL;
		break;
	}
	snd_soc_update_bits(codec, MD_CTL2, FS_MASK, rate);

	return 0;
}

static int ak4642_set_bias_level(struct snd_soc_codec *codec,
				 enum snd_soc_bias_level level)
{
	switch (level) {
	case SND_SOC_BIAS_OFF:
		snd_soc_write(codec, PW_MGMT1, 0x00);
		break;
	default:
		snd_soc_update_bits(codec, PW_MGMT1, PMVCM, PMVCM);
		break;
	}
	codec->dapm.bias_level = level;

	return 0;
}

static struct snd_soc_dai_ops ak4642_dai_ops = {
	.startup	= ak4642_dai_startup,
	.shutdown	= ak4642_dai_shutdown,
	.set_sysclk	= ak4642_dai_set_sysclk,
	.set_fmt	= ak4642_dai_set_fmt,
	.hw_params	= ak4642_dai_hw_params,
};

static struct snd_soc_dai_driver ak4642_dai = {
	.name = "ak4642-hifi",
	.playback = {
		.stream_name = "Playback",
		.channels_min = 1,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_48000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE },
	.capture = {
		.stream_name = "Capture",
		.channels_min = 1,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_48000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE },
	.ops = &ak4642_dai_ops,
	.symmetric_rates = 1,
};

static int ak4642_resume(struct snd_soc_codec *codec)
{
	snd_soc_cache_sync(codec);
	return 0;
}


static int ak4642_probe(struct snd_soc_codec *codec)
{
	struct ak4642_priv *ak4642 = snd_soc_codec_get_drvdata(codec);
	int ret;

	dev_info(codec->dev, "AK4642 Audio Codec %s", AK4642_VERSION);

	ret = snd_soc_codec_set_cache_io(codec, 8, 8, ak4642->control_type);
	if (ret < 0) {
		dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
		return ret;
	}

	snd_soc_add_controls(codec, ak4642_snd_controls,
			     ARRAY_SIZE(ak4642_snd_controls));

	ak4642_set_bias_level(codec, SND_SOC_BIAS_STANDBY);

	return 0;
}

static int ak4642_remove(struct snd_soc_codec *codec)
{
	ak4642_set_bias_level(codec, SND_SOC_BIAS_OFF);
	return 0;
}

static struct snd_soc_codec_driver soc_codec_dev_ak4642 = {
	.probe			= ak4642_probe,
	.remove			= ak4642_remove,
	.resume			= ak4642_resume,
	.set_bias_level		= ak4642_set_bias_level,
	.reg_cache_size		= ARRAY_SIZE(ak4642_reg),
	.reg_word_size		= sizeof(u8),
	.reg_cache_default	= ak4642_reg,
	.dapm_widgets		= ak4642_dapm_widgets,
	.num_dapm_widgets	= ARRAY_SIZE(ak4642_dapm_widgets),
	.dapm_routes		= ak4642_intercon,
	.num_dapm_routes	= ARRAY_SIZE(ak4642_intercon),
};

#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
static __devinit int ak4642_i2c_probe(struct i2c_client *i2c,
				      const struct i2c_device_id *id)
{
	struct ak4642_priv *ak4642;
	int ret;

	ak4642 = kzalloc(sizeof(struct ak4642_priv), GFP_KERNEL);
	if (!ak4642)
		return -ENOMEM;

	i2c_set_clientdata(i2c, ak4642);
	ak4642->control_type = SND_SOC_I2C;

	ret =  snd_soc_register_codec(&i2c->dev,
			&soc_codec_dev_ak4642, &ak4642_dai, 1);
	if (ret < 0)
		kfree(ak4642);
	return ret;
}

static __devexit int ak4642_i2c_remove(struct i2c_client *client)
{
	snd_soc_unregister_codec(&client->dev);
	kfree(i2c_get_clientdata(client));
	return 0;
}

static const struct i2c_device_id ak4642_i2c_id[] = {
	{ "ak4642", 0 },
	{ "ak4643", 0 },
	{ }
};
MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id);

static struct i2c_driver ak4642_i2c_driver = {
	.driver = {
		.name = "ak4642-codec",
		.owner = THIS_MODULE,
	},
	.probe		= ak4642_i2c_probe,
	.remove		= __devexit_p(ak4642_i2c_remove),
	.id_table	= ak4642_i2c_id,
};
#endif

static int __init ak4642_modinit(void)
{
	int ret = 0;
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
	ret = i2c_add_driver(&ak4642_i2c_driver);
#endif
	return ret;

}
module_init(ak4642_modinit);

static void __exit ak4642_exit(void)
{
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
	i2c_del_driver(&ak4642_i2c_driver);
#endif

}
module_exit(ak4642_exit);

MODULE_DESCRIPTION("Soc AK4642 driver");
MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
a3a83d9a KM	1	/*
	2	* ak4642.c -- AK4642/AK4643 ALSA Soc Audio driver
	3	*
	4	* Copyright (C) 2009 Renesas Solutions Corp.
	5	* Kuninori Morimoto <morimoto.kuninori@renesas.com>
	6	*
	7	* Based on wm8731.c by Richard Purdie
	8	* Based on ak4535.c by Richard Purdie
	9	* Based on wm8753.c by Liam Girdwood
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	/* CAUTION
	17	*
	18	* This is very simple driver.
	19	* It can use headphone output / stereo input only
	20	*
20211391	21	* AK4642 is tested.
a3a83d9a KM	22	* AK4643 is tested.
	23	*/
	24
a3a83d9a	25	#include <linux/delay.h>
a3a83d9a KM	26	#include <linux/i2c.h>
a3a83d9a KM	27	#include <linux/platform_device.h>
5a0e3ad6	28	#include <linux/slab.h>
da155d5b	29	#include <linux/module.h>
ce6120cc	30	#include <sound/soc.h>
a3a83d9a	31	#include <sound/initval.h>
a300de3c	32	#include <sound/tlv.h>
a3a83d9a	33
a3a83d9a KM	34	#define AK4642_VERSION "0.0.1"
	35
	36	#define PW_MGMT1 0x00
	37	#define PW_MGMT2 0x01
	38	#define SG_SL1 0x02
	39	#define SG_SL2 0x03
	40	#define MD_CTL1 0x04
	41	#define MD_CTL2 0x05
	42	#define TIMER 0x06
	43	#define ALC_CTL1 0x07
	44	#define ALC_CTL2 0x08
	45	#define L_IVC 0x09
	46	#define L_DVC 0x0a
	47	#define ALC_CTL3 0x0b
	48	#define R_IVC 0x0c
	49	#define R_DVC 0x0d
	50	#define MD_CTL3 0x0e
	51	#define MD_CTL4 0x0f
	52	#define PW_MGMT3 0x10
	53	#define DF_S 0x11
	54	#define FIL3_0 0x12
	55	#define FIL3_1 0x13
	56	#define FIL3_2 0x14
	57	#define FIL3_3 0x15
	58	#define EQ_0 0x16
	59	#define EQ_1 0x17
	60	#define EQ_2 0x18
	61	#define EQ_3 0x19
	62	#define EQ_4 0x1a
	63	#define EQ_5 0x1b
	64	#define FIL1_0 0x1c
	65	#define FIL1_1 0x1d
	66	#define FIL1_2 0x1e
	67	#define FIL1_3 0x1f
	68	#define PW_MGMT4 0x20
	69	#define MD_CTL5 0x21
	70	#define LO_MS 0x22
	71	#define HP_MS 0x23
	72	#define SPK_MS 0x24
	73
	74	#define AK4642_CACHEREGNUM 0x25
	75
a3471239 KM	76	/* PW_MGMT1*/
	77	#define PMVCM (1 << 6) /* VCOM Power Management */
	78	#define PMMIN (1 << 5) /* MIN Input Power Management */
	79	#define PMDAC (1 << 2) /* DAC Power Management */
	80	#define PMADL (1 << 0) /* MIC Amp Lch and ADC Lch Power Management */
	81
0643ce8f KM	82	/* PW_MGMT2 */
	83	#define HPMTN (1 << 6)
	84	#define PMHPL (1 << 5)
	85	#define PMHPR (1 << 4)
	86	#define MS (1 << 3) /* master/slave select */
	87	#define MCKO (1 << 1)
	88	#define PMPLL (1 << 0)
	89
	90	#define PMHP_MASK (PMHPL \| PMHPR)
	91	#define PMHP PMHP_MASK
	92
a3471239 KM	93	/* PW_MGMT3 */
	94	#define PMADR (1 << 0) /* MIC L / ADC R Power Management */
	95
	96	/* SG_SL1 */
	97	#define MINS (1 << 6) /* Switch from MIN to Speaker */
	98	#define DACL (1 << 4) /* Switch from DAC to Stereo or Receiver */
	99	#define PMMP (1 << 2) /* MPWR pin Power Management */
	100	#define MGAIN0 (1 << 0) /* MIC amp gain*/
	101
	102	/* TIMER */
	103	#define ZTM(param) ((param & 0x3) << 4) /* ALC Zoro Crossing TimeOut */
	104	#define WTM(param) (((param & 0x4) << 4) \| ((param & 0x3) << 2))
	105
	106	/* ALC_CTL1 */
	107	#define ALC (1 << 5) /* ALC Enable */
	108	#define LMTH0 (1 << 0) /* ALC Limiter / Recovery Level */
	109
4b6316b4 KM	110	/* MD_CTL1 */
	111	#define PLL3 (1 << 7)
	112	#define PLL2 (1 << 6)
	113	#define PLL1 (1 << 5)
	114	#define PLL0 (1 << 4)
	115	#define PLL_MASK (PLL3 \| PLL2 \| PLL1 \| PLL0)
	116
0643ce8f KM	117	#define BCKO_MASK (1 << 3)
	118	#define BCKO_64 BCKO_MASK
	119
cb9c130a KM	120	#define DIF_MASK (3 << 0)
	121	#define DSP (0 << 0)
	122	#define RIGHT_J (1 << 0)
	123	#define LEFT_J (2 << 0)
	124	#define I2S (3 << 0)
	125
1ad747ca KM	126	/* MD_CTL2 */
	127	#define FS0 (1 << 0)
	128	#define FS1 (1 << 1)
	129	#define FS2 (1 << 2)
	130	#define FS3 (1 << 5)
	131	#define FS_MASK (FS0 \| FS1 \| FS2 \| FS3)
	132
a3471239 KM	133	/* MD_CTL3 */
	134	#define BST1 (1 << 3)
	135
	136	/* MD_CTL4 */
	137	#define DACH (1 << 0)
a3a83d9a	138
a300de3c KM	139	/*
	140	* Playback Volume (table 39)
	141	*
	142	* max : 0x00 : +12.0 dB
	143	* ( 0.5 dB step )
	144	* min : 0xFE : -115.0 dB
	145	* mute: 0xFF
	146	*/
	147	static const DECLARE_TLV_DB_SCALE(out_tlv, -11500, 50, 1);
	148
	149	static const struct snd_kcontrol_new ak4642_snd_controls[] = {
	150
	151	SOC_DOUBLE_R_TLV("Digital Playback Volume", L_DVC, R_DVC,
	152	0, 0xFF, 1, out_tlv),
3c703526 KM	153
3c703526 KM	154	SOC_SINGLE("Headphone Switch", PW_MGMT2, 6, 1, 0),
a300de3c KM	155	};
a300de3c KM	156
24747dae KM	157	static const struct snd_kcontrol_new ak4642_hpout_mixer_controls[] = {
	158	SOC_DAPM_SINGLE("DACH", MD_CTL4, 0, 1, 0),
	159	};
	160
e8c83dbf KM	161	static const struct snd_kcontrol_new ak4642_lout_mixer_controls[] = {
	162	SOC_DAPM_SINGLE("DACL", SG_SL1, 4, 1, 0),
	163	};
	164
24747dae KM	165	static const struct snd_soc_dapm_widget ak4642_dapm_widgets[] = {
	166
	167	/* Outputs */
	168	SND_SOC_DAPM_OUTPUT("HPOUTL"),
	169	SND_SOC_DAPM_OUTPUT("HPOUTR"),
e8c83dbf	170	SND_SOC_DAPM_OUTPUT("LINEOUT"),
24747dae KM	171
	172	SND_SOC_DAPM_MIXER("HPOUTL Mixer", PW_MGMT2, 5, 0,
	173	&ak4642_hpout_mixer_controls[0],
	174	ARRAY_SIZE(ak4642_hpout_mixer_controls)),
	175
	176	SND_SOC_DAPM_MIXER("HPOUTR Mixer", PW_MGMT2, 4, 0,
	177	&ak4642_hpout_mixer_controls[0],
	178	ARRAY_SIZE(ak4642_hpout_mixer_controls)),
	179
e8c83dbf KM	180	SND_SOC_DAPM_MIXER("LINEOUT Mixer", PW_MGMT1, 3, 0,
	181	&ak4642_lout_mixer_controls[0],
	182	ARRAY_SIZE(ak4642_lout_mixer_controls)),
	183
24747dae KM	184	/* DAC */
	185	SND_SOC_DAPM_DAC("DAC", "HiFi Playback", PW_MGMT1, 2, 0),
	186	};
	187
	188	static const struct snd_soc_dapm_route ak4642_intercon[] = {
	189
	190	/* Outputs */
	191	{"HPOUTL", NULL, "HPOUTL Mixer"},
	192	{"HPOUTR", NULL, "HPOUTR Mixer"},
e8c83dbf	193	{"LINEOUT", NULL, "LINEOUT Mixer"},
24747dae KM	194
	195	{"HPOUTL Mixer", "DACH", "DAC"},
	196	{"HPOUTR Mixer", "DACH", "DAC"},
e8c83dbf	197	{"LINEOUT Mixer", "DACL", "DAC"},
24747dae	198	};
a300de3c	199
a3a83d9a KM	200	/* codec private data */
a3a83d9a KM	201	struct ak4642_priv {
f0fba2ad LG	202	unsigned int sysclk;
f0fba2ad LG	203	enum snd_soc_control_type control_type;
a3a83d9a KM	204	};
a3a83d9a KM	205
a3a83d9a KM	206	/*
	207	* ak4642 register cache
	208	*/
19b115e5 KM	209	static const u8 ak4642_reg[AK4642_CACHEREGNUM] = {
	210	0x00, 0x00, 0x01, 0x00,
	211	0x02, 0x00, 0x00, 0x00,
	212	0xe1, 0xe1, 0x18, 0x00,
	213	0xe1, 0x18, 0x11, 0x08,
	214	0x00, 0x00, 0x00, 0x00,
	215	0x00, 0x00, 0x00, 0x00,
	216	0x00, 0x00, 0x00, 0x00,
	217	0x00, 0x00, 0x00, 0x00,
	218	0x00, 0x00, 0x00, 0x00,
	219	0x00,
a3a83d9a KM	220	};
a3a83d9a KM	221
a3a83d9a KM	222	static int ak4642_dai_startup(struct snd_pcm_substream *substream,
	223	struct snd_soc_dai *dai)
	224	{
	225	int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
	226	struct snd_soc_codec *codec = dai->codec;
	227
	228	if (is_play) {
	229	/*
	230	* start headphone output
	231	*
	232	* PLL, Master Mode
	233	* Audio I/F Format :MSB justified (ADC & DAC)
a3a83d9a KM	234	* Bass Boost Level : Middle
	235	*
	236	* This operation came from example code of
	237	* "ASAHI KASEI AK4642" (japanese) manual p97.
a3a83d9a	238	*/
b91470bb AL	239	snd_soc_write(codec, L_IVC, 0x91); /* volume */
b91470bb AL	240	snd_soc_write(codec, R_IVC, 0x91); /* volume */
a3a83d9a KM	241	} else {
	242	/*
	243	* start stereo input
	244	*
	245	* PLL Master Mode
	246	* Audio I/F Format:MSB justified (ADC & DAC)
a3a83d9a KM	247	* Pre MIC AMP:+20dB
	248	* MIC Power On
	249	* ALC setting:Refer to Table 35
	250	* ALC bit=“1”
	251	*
	252	* This operation came from example code of
	253	* "ASAHI KASEI AK4642" (japanese) manual p94.
	254	*/
b91470bb AL	255	snd_soc_write(codec, SG_SL1, PMMP \| MGAIN0);
	256	snd_soc_write(codec, TIMER, ZTM(0x3) \| WTM(0x3));
	257	snd_soc_write(codec, ALC_CTL1, ALC \| LMTH0);
ed2dd7da	258	snd_soc_update_bits(codec, PW_MGMT1, PMADL, PMADL);
a3471239	259	snd_soc_update_bits(codec, PW_MGMT3, PMADR, PMADR);
a3a83d9a KM	260	}
	261
	262	return 0;
	263	}
	264
	265	static void ak4642_dai_shutdown(struct snd_pcm_substream *substream,
	266	struct snd_soc_dai *dai)
	267	{
	268	int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
	269	struct snd_soc_codec *codec = dai->codec;
	270
	271	if (is_play) {
a3a83d9a KM	272	} else {
a3a83d9a KM	273	/* stop stereo input */
a3471239 KM	274	snd_soc_update_bits(codec, PW_MGMT1, PMADL, 0);
	275	snd_soc_update_bits(codec, PW_MGMT3, PMADR, 0);
	276	snd_soc_update_bits(codec, ALC_CTL1, ALC, 0);
a3a83d9a KM	277	}
	278	}
	279
	280	static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai,
	281	int clk_id, unsigned int freq, int dir)
	282	{
	283	struct snd_soc_codec *codec = codec_dai->codec;
4b6316b4 KM	284	u8 pll;
	285
	286	switch (freq) {
	287	case 11289600:
	288	pll = PLL2;
	289	break;
	290	case 12288000:
	291	pll = PLL2 \| PLL0;
	292	break;
	293	case 12000000:
	294	pll = PLL2 \| PLL1;
	295	break;
	296	case 24000000:
	297	pll = PLL2 \| PLL1 \| PLL0;
	298	break;
	299	case 13500000:
	300	pll = PLL3 \| PLL2;
	301	break;
	302	case 27000000:
	303	pll = PLL3 \| PLL2 \| PLL0;
	304	break;
	305	default:
	306	return -EINVAL;
	307	}
	308	snd_soc_update_bits(codec, MD_CTL1, PLL_MASK, pll);
a3a83d9a	309
a3a83d9a KM	310	return 0;
	311	}
	312
0643ce8f KM	313	static int ak4642_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
	314	{
	315	struct snd_soc_codec *codec = dai->codec;
	316	u8 data;
	317	u8 bcko;
	318
	319	data = MCKO \| PMPLL; /* use MCKO */
	320	bcko = 0;
	321
	322	/* set master/slave audio interface */
	323	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	324	case SND_SOC_DAIFMT_CBM_CFM:
	325	data \|= MS;
	326	bcko = BCKO_64;
	327	break;
	328	case SND_SOC_DAIFMT_CBS_CFS:
	329	break;
	330	default:
	331	return -EINVAL;
	332	}
bd7fdbca	333	snd_soc_update_bits(codec, PW_MGMT2, MS \| MCKO \| PMPLL, data);
0643ce8f KM	334	snd_soc_update_bits(codec, MD_CTL1, BCKO_MASK, bcko);
0643ce8f KM	335
cb9c130a KM	336	/* format type */
	337	data = 0;
	338	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	339	case SND_SOC_DAIFMT_LEFT_J:
	340	data = LEFT_J;
	341	break;
	342	case SND_SOC_DAIFMT_I2S:
	343	data = I2S;
	344	break;
	345	/* FIXME
	346	* Please add RIGHT_J / DSP support here
	347	*/
	348	default:
	349	return -EINVAL;
	350	break;
	351	}
	352	snd_soc_update_bits(codec, MD_CTL1, DIF_MASK, data);
	353
0643ce8f KM	354	return 0;
	355	}
	356
1ad747ca KM	357	static int ak4642_dai_hw_params(struct snd_pcm_substream *substream,
	358	struct snd_pcm_hw_params *params,
	359	struct snd_soc_dai *dai)
	360	{
	361	struct snd_soc_codec *codec = dai->codec;
	362	u8 rate;
	363
	364	switch (params_rate(params)) {
	365	case 7350:
	366	rate = FS2;
	367	break;
	368	case 8000:
	369	rate = 0;
	370	break;
	371	case 11025:
	372	rate = FS2 \| FS0;
	373	break;
	374	case 12000:
	375	rate = FS0;
	376	break;
	377	case 14700:
	378	rate = FS2 \| FS1;
	379	break;
	380	case 16000:
	381	rate = FS1;
	382	break;
	383	case 22050:
	384	rate = FS2 \| FS1 \| FS0;
	385	break;
	386	case 24000:
	387	rate = FS1 \| FS0;
	388	break;
	389	case 29400:
	390	rate = FS3 \| FS2 \| FS1;
	391	break;
	392	case 32000:
	393	rate = FS3 \| FS1;
	394	break;
	395	case 44100:
	396	rate = FS3 \| FS2 \| FS1 \| FS0;
	397	break;
	398	case 48000:
	399	rate = FS3 \| FS1 \| FS0;
	400	break;
	401	default:
	402	return -EINVAL;
	403	break;
	404	}
	405	snd_soc_update_bits(codec, MD_CTL2, FS_MASK, rate);
a3a83d9a	406
a3a83d9a KM	407	return 0;
	408	}
	409
ed2dd7da KM	410	static int ak4642_set_bias_level(struct snd_soc_codec *codec,
	411	enum snd_soc_bias_level level)
	412	{
	413	switch (level) {
	414	case SND_SOC_BIAS_OFF:
	415	snd_soc_write(codec, PW_MGMT1, 0x00);
	416	break;
	417	default:
	418	snd_soc_update_bits(codec, PW_MGMT1, PMVCM, PMVCM);
	419	break;
	420	}
	421	codec->dapm.bias_level = level;
	422
	423	return 0;
	424	}
	425
a3a83d9a KM	426	static struct snd_soc_dai_ops ak4642_dai_ops = {
	427	.startup = ak4642_dai_startup,
	428	.shutdown = ak4642_dai_shutdown,
	429	.set_sysclk = ak4642_dai_set_sysclk,
0643ce8f	430	.set_fmt = ak4642_dai_set_fmt,
1ad747ca	431	.hw_params = ak4642_dai_hw_params,
a3a83d9a KM	432	};
a3a83d9a KM	433
f0fba2ad LG	434	static struct snd_soc_dai_driver ak4642_dai = {
f0fba2ad LG	435	.name = "ak4642-hifi",
a3a83d9a KM	436	.playback = {
	437	.stream_name = "Playback",
	438	.channels_min = 1,
	439	.channels_max = 2,
	440	.rates = SNDRV_PCM_RATE_8000_48000,
	441	.formats = SNDRV_PCM_FMTBIT_S16_LE },
	442	.capture = {
	443	.stream_name = "Capture",
	444	.channels_min = 1,
	445	.channels_max = 2,
	446	.rates = SNDRV_PCM_RATE_8000_48000,
	447	.formats = SNDRV_PCM_FMTBIT_S16_LE },
	448	.ops = &ak4642_dai_ops,
1ad747ca	449	.symmetric_rates = 1,
a3a83d9a	450	};
a3a83d9a	451
f0fba2ad	452	static int ak4642_resume(struct snd_soc_codec *codec)
a3a83d9a	453	{
b91470bb	454	snd_soc_cache_sync(codec);
a3a83d9a KM	455	return 0;
	456	}
	457
f0fba2ad LG	458
f0fba2ad LG	459	static int ak4642_probe(struct snd_soc_codec *codec)
a3a83d9a	460	{
f0fba2ad	461	struct ak4642_priv *ak4642 = snd_soc_codec_get_drvdata(codec);
b91470bb	462	int ret;
a3a83d9a	463
f0fba2ad	464	dev_info(codec->dev, "AK4642 Audio Codec %s", AK4642_VERSION);
a3a83d9a	465
b91470bb AL	466	ret = snd_soc_codec_set_cache_io(codec, 8, 8, ak4642->control_type);
	467	if (ret < 0) {
	468	dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
	469	return ret;
	470	}
a3a83d9a	471
73bb379f KM	472	snd_soc_add_controls(codec, ak4642_snd_controls,
73bb379f KM	473	ARRAY_SIZE(ak4642_snd_controls));
a3a83d9a	474
ed2dd7da KM	475	ak4642_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
	476
	477	return 0;
	478	}
	479
	480	static int ak4642_remove(struct snd_soc_codec *codec)
	481	{
	482	ak4642_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad	483	return 0;
a3a83d9a KM	484	}
a3a83d9a KM	485
f0fba2ad	486	static struct snd_soc_codec_driver soc_codec_dev_ak4642 = {
0ce75aa4	487	.probe = ak4642_probe,
ed2dd7da	488	.remove = ak4642_remove,
0ce75aa4	489	.resume = ak4642_resume,
ed2dd7da	490	.set_bias_level = ak4642_set_bias_level,
0ce75aa4 KM	491	.reg_cache_size = ARRAY_SIZE(ak4642_reg),
0ce75aa4 KM	492	.reg_word_size = sizeof(u8),
f0fba2ad	493	.reg_cache_default = ak4642_reg,
24747dae KM	494	.dapm_widgets = ak4642_dapm_widgets,
	495	.num_dapm_widgets = ARRAY_SIZE(ak4642_dapm_widgets),
	496	.dapm_routes = ak4642_intercon,
	497	.num_dapm_routes = ARRAY_SIZE(ak4642_intercon),
f0fba2ad LG	498	};
f0fba2ad LG	499
a3a83d9a	500	#if defined(CONFIG_I2C) \|\| defined(CONFIG_I2C_MODULE)
f0fba2ad LG	501	static __devinit int ak4642_i2c_probe(struct i2c_client *i2c,
f0fba2ad LG	502	const struct i2c_device_id *id)
a3a83d9a KM	503	{
a3a83d9a KM	504	struct ak4642_priv *ak4642;
a3a83d9a KM	505	int ret;
	506
	507	ak4642 = kzalloc(sizeof(struct ak4642_priv), GFP_KERNEL);
0ce75aa4	508	if (!ak4642)
a3a83d9a KM	509	return -ENOMEM;
a3a83d9a KM	510
a3a83d9a	511	i2c_set_clientdata(i2c, ak4642);
f0fba2ad	512	ak4642->control_type = SND_SOC_I2C;
a3a83d9a	513
f0fba2ad LG	514	ret = snd_soc_register_codec(&i2c->dev,
	515	&soc_codec_dev_ak4642, &ak4642_dai, 1);
	516	if (ret < 0)
7bcaad91	517	kfree(ak4642);
a3a83d9a KM	518	return ret;
	519	}
	520
f0fba2ad	521	static __devexit int ak4642_i2c_remove(struct i2c_client *client)
a3a83d9a	522	{
f0fba2ad LG	523	snd_soc_unregister_codec(&client->dev);
f0fba2ad LG	524	kfree(i2c_get_clientdata(client));
a3a83d9a KM	525	return 0;
	526	}
	527
	528	static const struct i2c_device_id ak4642_i2c_id[] = {
	529	{ "ak4642", 0 },
	530	{ "ak4643", 0 },
	531	{ }
	532	};
	533	MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id);
	534
	535	static struct i2c_driver ak4642_i2c_driver = {
	536	.driver = {
f0fba2ad	537	.name = "ak4642-codec",
a3a83d9a KM	538	.owner = THIS_MODULE,
a3a83d9a KM	539	},
0ce75aa4 KM	540	.probe = ak4642_i2c_probe,
	541	.remove = __devexit_p(ak4642_i2c_remove),
	542	.id_table = ak4642_i2c_id,
a3a83d9a	543	};
a3a83d9a KM	544	#endif
a3a83d9a KM	545
a3a83d9a KM	546	static int __init ak4642_modinit(void)
a3a83d9a KM	547	{
1cf86f6f	548	int ret = 0;
a3a83d9a KM	549	#if defined(CONFIG_I2C) \|\| defined(CONFIG_I2C_MODULE)
	550	ret = i2c_add_driver(&ak4642_i2c_driver);
	551	#endif
	552	return ret;
	553
	554	}
	555	module_init(ak4642_modinit);
	556
	557	static void __exit ak4642_exit(void)
	558	{
	559	#if defined(CONFIG_I2C) \|\| defined(CONFIG_I2C_MODULE)
	560	i2c_del_driver(&ak4642_i2c_driver);
	561	#endif
	562
	563	}
	564	module_exit(ak4642_exit);
	565
	566	MODULE_DESCRIPTION("Soc AK4642 driver");
	567	MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
	568	MODULE_LICENSE("GPL");