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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
079d88cc
WF		 9 *
10 * Authors:
11 * Wu Fengguang <wfg@linux.intel.com>
12 *
13 * Maintained by:
14 * Wu Fengguang <wfg@linux.intel.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the Free
18 * Software Foundation; either version 2 of the License, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
23 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 * for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software Foundation,
28 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
84eb01be
TI		 31#include <linux/init.h>
32#include <linux/delay.h>
33#include <linux/slab.h>
65a77217 34#include <linux/module.h>
84eb01be 35#include <sound/core.h>
07acecc1 36#include <sound/jack.h>
433968da 37#include <sound/asoundef.h>
d45e6889 38#include <sound/tlv.h>
84eb01be
TI		 39#include "hda_codec.h"
40#include "hda_local.h"
1835a0f9 41#include "hda_jack.h"
84eb01be 42
0ebaa24c
TI		 43static bool static_hdmi_pcm;
44module_param(static_hdmi_pcm, bool, 0644);
45MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
46
384a48d7
SW		 47struct hdmi_spec_per_cvt {
48 hda_nid_t cvt_nid;
49 int assigned;
50 unsigned int channels_min;
51 unsigned int channels_max;
52 u32 rates;
53 u64 formats;
54 unsigned int maxbps;
55};
079d88cc 56
4eea3091
TI		 57/* max. connections to a widget */
58#define HDA_MAX_CONNECTIONS 32
59
384a48d7
SW		 60struct hdmi_spec_per_pin {
61 hda_nid_t pin_nid;
62 int num_mux_nids;
63 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
744626da
WF		 64
65 struct hda_codec *codec;
384a48d7 66 struct hdmi_eld sink_eld;
744626da 67 struct delayed_work work;
92c69e79 68 struct snd_kcontrol *eld_ctl;
c6e8453e 69 int repoll_count;
dc780f7f
TI		 70 bool setup; /* the stream has been set up by prepare callback */
71 int channels; /* current number of channels */
1a6003b5 72 bool non_pcm;
d45e6889
TI		 73 bool chmap_set; /* channel-map override by ALSA API? */
74 unsigned char chmap[8]; /* ALSA API channel-map */
bce0d2a8 75 char pcm_name[8]; /* filled in build_pcm callbacks */
384a48d7 76};
079d88cc 77
384a48d7
SW		 78struct hdmi_spec {
79 int num_cvts;
bce0d2a8
TI		 80 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
81 hda_nid_t cvt_nids[4]; /* only for haswell fix */
079d88cc 82
384a48d7 83 int num_pins;
bce0d2a8
TI		 84 struct snd_array pins; /* struct hdmi_spec_per_pin */
85 struct snd_array pcm_rec; /* struct hda_pcm */
d45e6889 86 unsigned int channels_max; /* max over all cvts */
079d88cc 87
4bd038f9 88 struct hdmi_eld temp_eld;
2b1461bb
SW		 89
90 bool dyn_pin_out;
91
079d88cc 92 /*
384a48d7 93 * Non-generic ATI/NVIDIA specific
079d88cc
WF		 94 */
95 struct hda_multi_out multiout;
d0b1252d 96 struct hda_pcm_stream pcm_playback;
079d88cc
WF		 97};
98
99
100struct hdmi_audio_infoframe {
101 u8 type; /* 0x84 */
102 u8 ver; /* 0x01 */
103 u8 len; /* 0x0a */
104
53d7d69d
WF		 105 u8 checksum;
106
079d88cc
WF		 107 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
108 u8 SS01_SF24;
109 u8 CXT04;
110 u8 CA;
111 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 112};
113
114struct dp_audio_infoframe {
115 u8 type; /* 0x84 */
116 u8 len; /* 0x1b */
117 u8 ver; /* 0x11 << 2 */
118
119 u8 CC02_CT47; /* match with HDMI infoframe from this on */
120 u8 SS01_SF24;
121 u8 CXT04;
122 u8 CA;
123 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 124};
125
2b203dbb
TI		 126union audio_infoframe {
127 struct hdmi_audio_infoframe hdmi;
128 struct dp_audio_infoframe dp;
129 u8 bytes[0];
130};
131
079d88cc
WF		 132/*
133 * CEA speaker placement:
134 *
135 * FLH FCH FRH
136 * FLW FL FLC FC FRC FR FRW
137 *
138 * LFE
139 * TC
140 *
141 * RL RLC RC RRC RR
142 *
143 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
144 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
145 */
146enum cea_speaker_placement {
147 FL = (1 << 0), /* Front Left */
148 FC = (1 << 1), /* Front Center */
149 FR = (1 << 2), /* Front Right */
150 FLC = (1 << 3), /* Front Left Center */
151 FRC = (1 << 4), /* Front Right Center */
152 RL = (1 << 5), /* Rear Left */
153 RC = (1 << 6), /* Rear Center */
154 RR = (1 << 7), /* Rear Right */
155 RLC = (1 << 8), /* Rear Left Center */
156 RRC = (1 << 9), /* Rear Right Center */
157 LFE = (1 << 10), /* Low Frequency Effect */
158 FLW = (1 << 11), /* Front Left Wide */
159 FRW = (1 << 12), /* Front Right Wide */
160 FLH = (1 << 13), /* Front Left High */
161 FCH = (1 << 14), /* Front Center High */
162 FRH = (1 << 15), /* Front Right High */
163 TC = (1 << 16), /* Top Center */
164};
165
166/*
167 * ELD SA bits in the CEA Speaker Allocation data block
168 */
169static int eld_speaker_allocation_bits[] = {
170 [0] = FL | FR,
171 [1] = LFE,
172 [2] = FC,
173 [3] = RL | RR,
174 [4] = RC,
175 [5] = FLC | FRC,
176 [6] = RLC | RRC,
177 /* the following are not defined in ELD yet */
178 [7] = FLW | FRW,
179 [8] = FLH | FRH,
180 [9] = TC,
181 [10] = FCH,
182};
183
184struct cea_channel_speaker_allocation {
185 int ca_index;
186 int speakers[8];
187
188 /* derived values, just for convenience */
189 int channels;
190 int spk_mask;
191};
192
193/*
194 * ALSA sequence is:
195 *
196 * surround40 surround41 surround50 surround51 surround71
197 * ch0 front left = = = =
198 * ch1 front right = = = =
199 * ch2 rear left = = = =
200 * ch3 rear right = = = =
201 * ch4 LFE center center center
202 * ch5 LFE LFE
203 * ch6 side left
204 * ch7 side right
205 *
206 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
207 */
208static int hdmi_channel_mapping[0x32][8] = {
209 /* stereo */
210 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
211 /* 2.1 */
212 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
213 /* Dolby Surround */
214 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
215 /* surround40 */
216 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
217 /* 4ch */
218 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
219 /* surround41 */
9396d317 220 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 221 /* surround50 */
222 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
223 /* surround51 */
224 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
225 /* 7.1 */
226 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
227};
228
229/*
230 * This is an ordered list!
231 *
232 * The preceding ones have better chances to be selected by
53d7d69d 233 * hdmi_channel_allocation().
079d88cc
WF		 234 */
235static struct cea_channel_speaker_allocation channel_allocations[] = {
236/* channel: 7 6 5 4 3 2 1 0 */
237{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
238 /* 2.1 */
239{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
240 /* Dolby Surround */
241{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
242 /* surround40 */
243{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
244 /* surround41 */
245{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
246 /* surround50 */
247{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
248 /* surround51 */
249{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
250 /* 6.1 */
251{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
252 /* surround71 */
253{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
254
255{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
256{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
257{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
258{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
259{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
260{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
261{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
262{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
263{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
264{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
265{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
266{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
267{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
268{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
269{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
270{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
271{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
272{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
273{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
274{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
275{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
276{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
277{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
278{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
279{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
280{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
281{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
282{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
283{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
284{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
285{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
286{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
287{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
288{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
289{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
290{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
291{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
292{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
293{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
294{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
295{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
296};
297
298
299/*
300 * HDMI routines
301 */
302
bce0d2a8
TI		 303#define get_pin(spec, idx) \
304 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
305#define get_cvt(spec, idx) \
306 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
307#define get_pcm_rec(spec, idx) \
308 ((struct hda_pcm *)snd_array_elem(&spec->pcm_rec, idx))
309
384a48d7 310static int pin_nid_to_pin_index(struct hdmi_spec *spec, hda_nid_t pin_nid)
079d88cc 311{
384a48d7 312 int pin_idx;
079d88cc 313
384a48d7 314 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 315 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
384a48d7 316 return pin_idx;
079d88cc 317
384a48d7
SW		 318 snd_printk(KERN_WARNING "HDMI: pin nid %d not registered\n", pin_nid);
319 return -EINVAL;
320}
321
322static int hinfo_to_pin_index(struct hdmi_spec *spec,
323 struct hda_pcm_stream *hinfo)
324{
325 int pin_idx;
326
327 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 328 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
384a48d7
SW		 329 return pin_idx;
330
331 snd_printk(KERN_WARNING "HDMI: hinfo %p not registered\n", hinfo);
332 return -EINVAL;
333}
334
335static int cvt_nid_to_cvt_index(struct hdmi_spec *spec, hda_nid_t cvt_nid)
336{
337 int cvt_idx;
338
339 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
bce0d2a8 340 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
384a48d7
SW		 341 return cvt_idx;
342
343 snd_printk(KERN_WARNING "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 344 return -EINVAL;
345}
346
14bc52b8
PLB		 347static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
348 struct snd_ctl_elem_info *uinfo)
349{
350 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9
DH		 351 struct hdmi_spec *spec = codec->spec;
352 struct hdmi_eld *eld;
14bc52b8
PLB		 353 int pin_idx;
354
14bc52b8
PLB		 355 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
356
357 pin_idx = kcontrol->private_value;
bce0d2a8 358 eld = &get_pin(spec, pin_idx)->sink_eld;
68e03de9 359
4bd038f9 360 mutex_lock(&eld->lock);
68e03de9 361 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
4bd038f9 362 mutex_unlock(&eld->lock);
14bc52b8
PLB		 363
364 return 0;
365}
366
367static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
368 struct snd_ctl_elem_value *ucontrol)
369{
370 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9
DH		 371 struct hdmi_spec *spec = codec->spec;
372 struct hdmi_eld *eld;
14bc52b8
PLB		 373 int pin_idx;
374
14bc52b8 375 pin_idx = kcontrol->private_value;
bce0d2a8 376 eld = &get_pin(spec, pin_idx)->sink_eld;
68e03de9 377
4bd038f9 378 mutex_lock(&eld->lock);
68e03de9 379 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
4bd038f9 380 mutex_unlock(&eld->lock);
68e03de9
DH		 381 snd_BUG();
382 return -EINVAL;
383 }
384
385 memset(ucontrol->value.bytes.data, 0,
386 ARRAY_SIZE(ucontrol->value.bytes.data));
387 if (eld->eld_valid)
388 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
389 eld->eld_size);
4bd038f9 390 mutex_unlock(&eld->lock);
14bc52b8
PLB		 391
392 return 0;
393}
394
395static struct snd_kcontrol_new eld_bytes_ctl = {
396 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
397 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
398 .name = "ELD",
399 .info = hdmi_eld_ctl_info,
400 .get = hdmi_eld_ctl_get,
401};
402
403static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
404 int device)
405{
406 struct snd_kcontrol *kctl;
407 struct hdmi_spec *spec = codec->spec;
408 int err;
409
410 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
411 if (!kctl)
412 return -ENOMEM;
413 kctl->private_value = pin_idx;
414 kctl->id.device = device;
415
bce0d2a8 416 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
14bc52b8
PLB		 417 if (err < 0)
418 return err;
419
bce0d2a8 420 get_pin(spec, pin_idx)->eld_ctl = kctl;
14bc52b8
PLB		 421 return 0;
422}
423
079d88cc
WF		 424#ifdef BE_PARANOID
425static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
426 int *packet_index, int *byte_index)
427{
428 int val;
429
430 val = snd_hda_codec_read(codec, pin_nid, 0,
431 AC_VERB_GET_HDMI_DIP_INDEX, 0);
432
433 *packet_index = val >> 5;
434 *byte_index = val & 0x1f;
435}
436#endif
437
438static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
439 int packet_index, int byte_index)
440{
441 int val;
442
443 val = (packet_index << 5) | (byte_index & 0x1f);
444
445 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
446}
447
448static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
449 unsigned char val)
450{
451 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
452}
453
384a48d7 454static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc 455{
2b1461bb
SW		 456 struct hdmi_spec *spec = codec->spec;
457 int pin_out;
458
079d88cc
WF		 459 /* Unmute */
460 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
461 snd_hda_codec_write(codec, pin_nid, 0,
462 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
2b1461bb
SW		 463
464 if (spec->dyn_pin_out)
465 /* Disable pin out until stream is active */
466 pin_out = 0;
467 else
468 /* Enable pin out: some machines with GM965 gets broken output
469 * when the pin is disabled or changed while using with HDMI
470 */
471 pin_out = PIN_OUT;
472
079d88cc 473 snd_hda_codec_write(codec, pin_nid, 0,
2b1461bb 474 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
079d88cc
WF		 475}
476
384a48d7 477static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 478{
384a48d7 479 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 480 AC_VERB_GET_CVT_CHAN_COUNT, 0);
481}
482
483static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 484 hda_nid_t cvt_nid, int chs)
079d88cc 485{
384a48d7
SW		 486 if (chs != hdmi_get_channel_count(codec, cvt_nid))
487 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 488 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
489}
490
491
492/*
493 * Channel mapping routines
494 */
495
496/*
497 * Compute derived values in channel_allocations[].
498 */
499static void init_channel_allocations(void)
500{
501 int i, j;
502 struct cea_channel_speaker_allocation *p;
503
504 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
505 p = channel_allocations + i;
506 p->channels = 0;
507 p->spk_mask = 0;
508 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
509 if (p->speakers[j]) {
510 p->channels++;
511 p->spk_mask |= p->speakers[j];
512 }
513 }
514}
515
72357c78
WX		 516static int get_channel_allocation_order(int ca)
517{
518 int i;
519
520 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
521 if (channel_allocations[i].ca_index == ca)
522 break;
523 }
524 return i;
525}
526
079d88cc
WF		 527/*
528 * The transformation takes two steps:
529 *
530 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
531 * spk_mask => (channel_allocations[]) => ai->CA
532 *
533 * TODO: it could select the wrong CA from multiple candidates.
534*/
384a48d7 535static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
079d88cc 536{
079d88cc 537 int i;
53d7d69d 538 int ca = 0;
079d88cc 539 int spk_mask = 0;
079d88cc
WF		 540 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
541
542 /*
543 * CA defaults to 0 for basic stereo audio
544 */
545 if (channels <= 2)
546 return 0;
547
079d88cc
WF		 548 /*
549 * expand ELD's speaker allocation mask
550 *
551 * ELD tells the speaker mask in a compact(paired) form,
552 * expand ELD's notions to match the ones used by Audio InfoFrame.
553 */
554 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
1613d6b4 555 if (eld->info.spk_alloc & (1 << i))
079d88cc
WF		 556 spk_mask |= eld_speaker_allocation_bits[i];
557 }
558
559 /* search for the first working match in the CA table */
560 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
561 if (channels == channel_allocations[i].channels &&
562 (spk_mask & channel_allocations[i].spk_mask) ==
563 channel_allocations[i].spk_mask) {
53d7d69d 564 ca = channel_allocations[i].ca_index;
079d88cc
WF		 565 break;
566 }
567 }
568
686edbc0
AH		 569 if (!ca) {
570 /* if there was no match, select the regular ALSA channel
571 * allocation with the matching number of channels */
572 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
573 if (channels == channel_allocations[i].channels) {
574 ca = channel_allocations[i].ca_index;
575 break;
576 }
577 }
578 }
579
1613d6b4 580 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
2abbf439 581 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 582 ca, channels, buf);
079d88cc 583
53d7d69d 584 return ca;
079d88cc
WF		 585}
586
587static void hdmi_debug_channel_mapping(struct hda_codec *codec,
588 hda_nid_t pin_nid)
589{
590#ifdef CONFIG_SND_DEBUG_VERBOSE
591 int i;
592 int slot;
593
594 for (i = 0; i < 8; i++) {
595 slot = snd_hda_codec_read(codec, pin_nid, 0,
596 AC_VERB_GET_HDMI_CHAN_SLOT, i);
597 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
598 slot >> 4, slot & 0xf);
599 }
600#endif
601}
602
603
d45e6889 604static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
079d88cc 605 hda_nid_t pin_nid,
433968da 606 bool non_pcm,
53d7d69d 607 int ca)
079d88cc
WF		 608{
609 int i;
079d88cc 610 int err;
72357c78 611 int order;
433968da 612 int non_pcm_mapping[8];
079d88cc 613
72357c78 614 order = get_channel_allocation_order(ca);
433968da 615
079d88cc 616 if (hdmi_channel_mapping[ca][1] == 0) {
72357c78 617 for (i = 0; i < channel_allocations[order].channels; i++)
079d88cc
WF		 618 hdmi_channel_mapping[ca][i] = i | (i << 4);
619 for (; i < 8; i++)
620 hdmi_channel_mapping[ca][i] = 0xf | (i << 4);
621 }
622
433968da
WX		 623 if (non_pcm) {
624 for (i = 0; i < channel_allocations[order].channels; i++)
625 non_pcm_mapping[i] = i | (i << 4);
626 for (; i < 8; i++)
627 non_pcm_mapping[i] = 0xf | (i << 4);
628 }
629
079d88cc
WF		 630 for (i = 0; i < 8; i++) {
631 err = snd_hda_codec_write(codec, pin_nid, 0,
632 AC_VERB_SET_HDMI_CHAN_SLOT,
433968da 633 non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i]);
079d88cc 634 if (err) {
2abbf439
WF		 635 snd_printdd(KERN_NOTICE
636 "HDMI: channel mapping failed\n");
079d88cc
WF		 637 break;
638 }
639 }
640
641 hdmi_debug_channel_mapping(codec, pin_nid);
642}
643
d45e6889
TI		 644struct channel_map_table {
645 unsigned char map; /* ALSA API channel map position */
646 unsigned char cea_slot; /* CEA slot value */
647 int spk_mask; /* speaker position bit mask */
648};
649
650static struct channel_map_table map_tables[] = {
651 { SNDRV_CHMAP_FL, 0x00, FL },
652 { SNDRV_CHMAP_FR, 0x01, FR },
653 { SNDRV_CHMAP_RL, 0x04, RL },
654 { SNDRV_CHMAP_RR, 0x05, RR },
655 { SNDRV_CHMAP_LFE, 0x02, LFE },
656 { SNDRV_CHMAP_FC, 0x03, FC },
657 { SNDRV_CHMAP_RLC, 0x06, RLC },
658 { SNDRV_CHMAP_RRC, 0x07, RRC },
659 {} /* terminator */
660};
661
662/* from ALSA API channel position to speaker bit mask */
663static int to_spk_mask(unsigned char c)
664{
665 struct channel_map_table *t = map_tables;
666 for (; t->map; t++) {
667 if (t->map == c)
668 return t->spk_mask;
669 }
670 return 0;
671}
672
673/* from ALSA API channel position to CEA slot */
674static int to_cea_slot(unsigned char c)
675{
676 struct channel_map_table *t = map_tables;
677 for (; t->map; t++) {
678 if (t->map == c)
679 return t->cea_slot;
680 }
681 return 0x0f;
682}
683
684/* from CEA slot to ALSA API channel position */
685static int from_cea_slot(unsigned char c)
686{
687 struct channel_map_table *t = map_tables;
688 for (; t->map; t++) {
689 if (t->cea_slot == c)
690 return t->map;
691 }
692 return 0;
693}
694
695/* from speaker bit mask to ALSA API channel position */
696static int spk_to_chmap(int spk)
697{
698 struct channel_map_table *t = map_tables;
699 for (; t->map; t++) {
700 if (t->spk_mask == spk)
701 return t->map;
702 }
703 return 0;
704}
705
706/* get the CA index corresponding to the given ALSA API channel map */
707static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
708{
709 int i, spks = 0, spk_mask = 0;
710
711 for (i = 0; i < chs; i++) {
712 int mask = to_spk_mask(map[i]);
713 if (mask) {
714 spk_mask |= mask;
715 spks++;
716 }
717 }
718
719 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
720 if ((chs == channel_allocations[i].channels ||
721 spks == channel_allocations[i].channels) &&
722 (spk_mask & channel_allocations[i].spk_mask) ==
723 channel_allocations[i].spk_mask)
724 return channel_allocations[i].ca_index;
725 }
726 return -1;
727}
728
729/* set up the channel slots for the given ALSA API channel map */
730static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
731 hda_nid_t pin_nid,
732 int chs, unsigned char *map)
733{
734 int i;
735 for (i = 0; i < 8; i++) {
736 int val, err;
737 if (i < chs)
738 val = to_cea_slot(map[i]);
739 else
740 val = 0xf;
741 val |= (i << 4);
742 err = snd_hda_codec_write(codec, pin_nid, 0,
743 AC_VERB_SET_HDMI_CHAN_SLOT, val);
744 if (err)
745 return -EINVAL;
746 }
747 return 0;
748}
749
750/* store ALSA API channel map from the current default map */
751static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
752{
753 int i;
1c645a14 754 int ordered_ca = get_channel_allocation_order(ca);
d45e6889 755 for (i = 0; i < 8; i++) {
1c645a14
AH		 756 if (i < channel_allocations[ordered_ca].channels)
757 map[i] = from_cea_slot(hdmi_channel_mapping[ca][i] & 0x0f);
d45e6889
TI		 758 else
759 map[i] = 0;
760 }
761}
762
763static void hdmi_setup_channel_mapping(struct hda_codec *codec,
764 hda_nid_t pin_nid, bool non_pcm, int ca,
20608731
AH		 765 int channels, unsigned char *map,
766 bool chmap_set)
d45e6889 767{
20608731 768 if (!non_pcm && chmap_set) {
d45e6889
TI		 769 hdmi_manual_setup_channel_mapping(codec, pin_nid,
770 channels, map);
771 } else {
772 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
773 hdmi_setup_fake_chmap(map, ca);
774 }
775}
079d88cc
WF		 776
777/*
778 * Audio InfoFrame routines
779 */
780
781/*
782 * Enable Audio InfoFrame Transmission
783 */
784static void hdmi_start_infoframe_trans(struct hda_codec *codec,
785 hda_nid_t pin_nid)
786{
787 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
788 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
789 AC_DIPXMIT_BEST);
790}
791
792/*
793 * Disable Audio InfoFrame Transmission
794 */
795static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
796 hda_nid_t pin_nid)
797{
798 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
799 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
800 AC_DIPXMIT_DISABLE);
801}
802
803static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
804{
805#ifdef CONFIG_SND_DEBUG_VERBOSE
806 int i;
807 int size;
808
809 size = snd_hdmi_get_eld_size(codec, pin_nid);
810 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
811
812 for (i = 0; i < 8; i++) {
813 size = snd_hda_codec_read(codec, pin_nid, 0,
814 AC_VERB_GET_HDMI_DIP_SIZE, i);
815 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
816 }
817#endif
818}
819
820static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
821{
822#ifdef BE_PARANOID
823 int i, j;
824 int size;
825 int pi, bi;
826 for (i = 0; i < 8; i++) {
827 size = snd_hda_codec_read(codec, pin_nid, 0,
828 AC_VERB_GET_HDMI_DIP_SIZE, i);
829 if (size == 0)
830 continue;
831
832 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
833 for (j = 1; j < 1000; j++) {
834 hdmi_write_dip_byte(codec, pin_nid, 0x0);
835 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
836 if (pi != i)
837 snd_printd(KERN_INFO "dip index %d: %d != %d\n",
838 bi, pi, i);
839 if (bi == 0) /* byte index wrapped around */
840 break;
841 }
842 snd_printd(KERN_INFO
843 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
844 i, size, j);
845 }
846#endif
847}
848
53d7d69d 849static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 850{
53d7d69d 851 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 852 u8 sum = 0;
853 int i;
854
53d7d69d 855 hdmi_ai->checksum = 0;
079d88cc 856
53d7d69d 857 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 858 sum += bytes[i];
859
53d7d69d 860 hdmi_ai->checksum = -sum;
079d88cc
WF		 861}
862
863static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
864 hda_nid_t pin_nid,
53d7d69d 865 u8 *dip, int size)
079d88cc 866{
079d88cc
WF		 867 int i;
868
869 hdmi_debug_dip_size(codec, pin_nid);
870 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
871
079d88cc 872 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 873 for (i = 0; i < size; i++)
874 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 875}
876
877static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 878 u8 *dip, int size)
079d88cc 879{
079d88cc
WF		 880 u8 val;
881 int i;
882
883 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
884 != AC_DIPXMIT_BEST)
885 return false;
886
887 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 888 for (i = 0; i < size; i++) {
079d88cc
WF		 889 val = snd_hda_codec_read(codec, pin_nid, 0,
890 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 891 if (val != dip[i])
079d88cc
WF		 892 return false;
893 }
894
895 return true;
896}
897
dc780f7f
TI		 898static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
899 struct hdmi_spec_per_pin *per_pin,
900 bool non_pcm)
079d88cc 901{
384a48d7 902 hda_nid_t pin_nid = per_pin->pin_nid;
dc780f7f 903 int channels = per_pin->channels;
384a48d7 904 struct hdmi_eld *eld;
53d7d69d 905 int ca;
2b203dbb 906 union audio_infoframe ai;
079d88cc 907
dc780f7f
TI		 908 if (!channels)
909 return;
910
bce0d2a8 911 eld = &per_pin->sink_eld;
384a48d7
SW		 912 if (!eld->monitor_present)
913 return;
079d88cc 914
d45e6889
TI		 915 if (!non_pcm && per_pin->chmap_set)
916 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
917 else
918 ca = hdmi_channel_allocation(eld, channels);
919 if (ca < 0)
920 ca = 0;
384a48d7
SW		 921
922 memset(&ai, 0, sizeof(ai));
1613d6b4 923 if (eld->info.conn_type == 0) { /* HDMI */
384a48d7
SW		 924 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
925
926 hdmi_ai->type = 0x84;
927 hdmi_ai->ver = 0x01;
928 hdmi_ai->len = 0x0a;
929 hdmi_ai->CC02_CT47 = channels - 1;
930 hdmi_ai->CA = ca;
931 hdmi_checksum_audio_infoframe(hdmi_ai);
1613d6b4 932 } else if (eld->info.conn_type == 1) { /* DisplayPort */
384a48d7
SW		 933 struct dp_audio_infoframe *dp_ai = &ai.dp;
934
935 dp_ai->type = 0x84;
936 dp_ai->len = 0x1b;
937 dp_ai->ver = 0x11 << 2;
938 dp_ai->CC02_CT47 = channels - 1;
939 dp_ai->CA = ca;
940 } else {
941 snd_printd("HDMI: unknown connection type at pin %d\n",
942 pin_nid);
943 return;
944 }
53d7d69d 945
43d3dd15
AH		 946 /*
947 * always configure channel mapping, it may have been changed by the
948 * user in the meantime
949 */
950 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
951 channels, per_pin->chmap,
952 per_pin->chmap_set);
953
384a48d7
SW		 954 /*
955 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
956 * sizeof(*dp_ai) to avoid partial match/update problems when
957 * the user switches between HDMI/DP monitors.
958 */
959 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
960 sizeof(ai))) {
961 snd_printdd("hdmi_setup_audio_infoframe: "
962 "pin=%d channels=%d\n",
963 pin_nid,
964 channels);
384a48d7
SW		 965 hdmi_stop_infoframe_trans(codec, pin_nid);
966 hdmi_fill_audio_infoframe(codec, pin_nid,
967 ai.bytes, sizeof(ai));
968 hdmi_start_infoframe_trans(codec, pin_nid);
079d88cc 969 }
433968da 970
1a6003b5 971 per_pin->non_pcm = non_pcm;
079d88cc
WF		 972}
973
974
975/*
976 * Unsolicited events
977 */
978
c6e8453e 979static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 980
079d88cc
WF		 981static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
982{
983 struct hdmi_spec *spec = codec->spec;
3a93897e
TI		 984 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
985 int pin_nid;
384a48d7 986 int pin_idx;
3a93897e
TI		 987 struct hda_jack_tbl *jack;
988
989 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
990 if (!jack)
991 return;
992 pin_nid = jack->nid;
993 jack->jack_dirty = 1;
079d88cc 994
fae3d88a 995 _snd_printd(SND_PR_VERBOSE,
384a48d7 996 "HDMI hot plug event: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
fae3d88a
FW		 997 codec->addr, pin_nid,
998 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 999
384a48d7
SW		 1000 pin_idx = pin_nid_to_pin_index(spec, pin_nid);
1001 if (pin_idx < 0)
079d88cc
WF		 1002 return;
1003
bce0d2a8 1004 hdmi_present_sense(get_pin(spec, pin_idx), 1);
01a61e12 1005 snd_hda_jack_report_sync(codec);
079d88cc
WF		 1006}
1007
1008static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1009{
1010 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1011 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1012 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1013 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1014
1015 printk(KERN_INFO
e9ea8e8f 1016 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 1017 codec->addr,
079d88cc
WF		 1018 tag,
1019 subtag,
1020 cp_state,
1021 cp_ready);
1022
1023 /* TODO */
1024 if (cp_state)
1025 ;
1026 if (cp_ready)
1027 ;
1028}
1029
1030
1031static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1032{
079d88cc
WF		 1033 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1034 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1035
3a93897e 1036 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
079d88cc
WF		 1037 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
1038 return;
1039 }
1040
1041 if (subtag == 0)
1042 hdmi_intrinsic_event(codec, res);
1043 else
1044 hdmi_non_intrinsic_event(codec, res);
1045}
1046
83f26ad2
DH		 1047static void haswell_verify_pin_D0(struct hda_codec *codec, hda_nid_t nid)
1048{
1049 int pwr, lamp, ramp;
1050
1051 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1052 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1053 if (pwr != AC_PWRST_D0) {
1054 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1055 AC_PWRST_D0);
1056 msleep(40);
1057 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1058 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1059 snd_printd("Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
1060 }
1061
1062 lamp = snd_hda_codec_read(codec, nid, 0,
1063 AC_VERB_GET_AMP_GAIN_MUTE,
1064 AC_AMP_GET_LEFT | AC_AMP_GET_OUTPUT);
1065 ramp = snd_hda_codec_read(codec, nid, 0,
1066 AC_VERB_GET_AMP_GAIN_MUTE,
1067 AC_AMP_GET_RIGHT | AC_AMP_GET_OUTPUT);
1068 if (lamp != ramp) {
1069 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_AMP_GAIN_MUTE,
1070 AC_AMP_SET_RIGHT | AC_AMP_SET_OUTPUT | lamp);
1071
1072 lamp = snd_hda_codec_read(codec, nid, 0,
1073 AC_VERB_GET_AMP_GAIN_MUTE,
1074 AC_AMP_GET_LEFT | AC_AMP_GET_OUTPUT);
1075 ramp = snd_hda_codec_read(codec, nid, 0,
1076 AC_VERB_GET_AMP_GAIN_MUTE,
1077 AC_AMP_GET_RIGHT | AC_AMP_GET_OUTPUT);
1078 snd_printd("Haswell HDMI audio: Mute after set on pin 0x%x: [0x%x 0x%x]\n", nid, lamp, ramp);
1079 }
1080}
1081
079d88cc
WF		 1082/*
1083 * Callbacks
1084 */
1085
92f10b3f
TI		 1086/* HBR should be Non-PCM, 8 channels */
1087#define is_hbr_format(format) \
1088 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1089
384a48d7
SW		 1090static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1091 hda_nid_t pin_nid, u32 stream_tag, int format)
079d88cc 1092{
ea87d1c4
AH		 1093 int pinctl;
1094 int new_pinctl = 0;
ea87d1c4 1095
83f26ad2
DH		 1096 if (codec->vendor_id == 0x80862807)
1097 haswell_verify_pin_D0(codec, pin_nid);
1098
384a48d7
SW		 1099 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1100 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 1101 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1102
1103 new_pinctl = pinctl & ~AC_PINCTL_EPT;
92f10b3f 1104 if (is_hbr_format(format))
ea87d1c4
AH		 1105 new_pinctl |= AC_PINCTL_EPT_HBR;
1106 else
1107 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1108
1109 snd_printdd("hdmi_setup_stream: "
1110 "NID=0x%x, %spinctl=0x%x\n",
384a48d7 1111 pin_nid,
ea87d1c4
AH		 1112 pinctl == new_pinctl ? "" : "new-",
1113 new_pinctl);
1114
1115 if (pinctl != new_pinctl)
384a48d7 1116 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 1117 AC_VERB_SET_PIN_WIDGET_CONTROL,
1118 new_pinctl);
ea87d1c4 1119
384a48d7 1120 }
92f10b3f 1121 if (is_hbr_format(format) && !new_pinctl) {
ea87d1c4
AH		 1122 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
1123 return -EINVAL;
1124 }
079d88cc 1125
384a48d7 1126 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 1127 return 0;
079d88cc
WF		 1128}
1129
bbbe3390
TI		 1130/*
1131 * HDA PCM callbacks
1132 */
1133static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1134 struct hda_codec *codec,
1135 struct snd_pcm_substream *substream)
1136{
1137 struct hdmi_spec *spec = codec->spec;
639cef0e 1138 struct snd_pcm_runtime *runtime = substream->runtime;
384a48d7
SW		 1139 int pin_idx, cvt_idx, mux_idx = 0;
1140 struct hdmi_spec_per_pin *per_pin;
1141 struct hdmi_eld *eld;
1142 struct hdmi_spec_per_cvt *per_cvt = NULL;
bbbe3390 1143
384a48d7
SW		 1144 /* Validate hinfo */
1145 pin_idx = hinfo_to_pin_index(spec, hinfo);
1146 if (snd_BUG_ON(pin_idx < 0))
bbbe3390 1147 return -EINVAL;
bce0d2a8 1148 per_pin = get_pin(spec, pin_idx);
384a48d7
SW		 1149 eld = &per_pin->sink_eld;
1150
1151 /* Dynamically assign converter to stream */
1152 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
bce0d2a8 1153 per_cvt = get_cvt(spec, cvt_idx);
bbbe3390 1154
384a48d7
SW		 1155 /* Must not already be assigned */
1156 if (per_cvt->assigned)
1157 continue;
1158 /* Must be in pin's mux's list of converters */
1159 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1160 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1161 break;
1162 /* Not in mux list */
1163 if (mux_idx == per_pin->num_mux_nids)
1164 continue;
1165 break;
1166 }
1167 /* No free converters */
1168 if (cvt_idx == spec->num_cvts)
1169 return -ENODEV;
1170
1171 /* Claim converter */
1172 per_cvt->assigned = 1;
1173 hinfo->nid = per_cvt->cvt_nid;
1174
27035caa 1175 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
384a48d7
SW		 1176 AC_VERB_SET_CONNECT_SEL,
1177 mux_idx);
384a48d7 1178 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
bbbe3390 1179
2def8172 1180 /* Initially set the converter's capabilities */
384a48d7
SW		 1181 hinfo->channels_min = per_cvt->channels_min;
1182 hinfo->channels_max = per_cvt->channels_max;
1183 hinfo->rates = per_cvt->rates;
1184 hinfo->formats = per_cvt->formats;
1185 hinfo->maxbps = per_cvt->maxbps;
2def8172 1186
384a48d7 1187 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1188 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1189 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1190 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1191 !hinfo->rates || !hinfo->formats) {
1192 per_cvt->assigned = 0;
1193 hinfo->nid = 0;
1194 snd_hda_spdif_ctls_unassign(codec, pin_idx);
bbbe3390 1195 return -ENODEV;
2ad779b7 1196 }
bbbe3390 1197 }
2def8172
SW		 1198
1199 /* Store the updated parameters */
639cef0e
TI		 1200 runtime->hw.channels_min = hinfo->channels_min;
1201 runtime->hw.channels_max = hinfo->channels_max;
1202 runtime->hw.formats = hinfo->formats;
1203 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1204
1205 snd_pcm_hw_constraint_step(substream->runtime, 0,
1206 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 1207 return 0;
1208}
1209
079d88cc
WF		 1210/*
1211 * HDA/HDMI auto parsing
1212 */
384a48d7 1213static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1214{
1215 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1216 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1217 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1218
1219 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1220 snd_printk(KERN_WARNING
1221 "HDMI: pin %d wcaps %#x "
1222 "does not support connection list\n",
1223 pin_nid, get_wcaps(codec, pin_nid));
1224 return -EINVAL;
1225 }
1226
384a48d7
SW		 1227 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1228 per_pin->mux_nids,
1229 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1230
1231 return 0;
1232}
1233
c6e8453e 1234static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
079d88cc 1235{
744626da 1236 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1237 struct hdmi_spec *spec = codec->spec;
1238 struct hdmi_eld *eld = &spec->temp_eld;
1239 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
744626da 1240 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1241 /*
1242 * Always execute a GetPinSense verb here, even when called from
1243 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1244 * response's PD bit is not the real PD value, but indicates that
1245 * the real PD value changed. An older version of the HD-audio
1246 * specification worked this way. Hence, we just ignore the data in
1247 * the unsolicited response to avoid custom WARs.
1248 */
079d88cc 1249 int present = snd_hda_pin_sense(codec, pin_nid);
4bd038f9
DH		 1250 bool update_eld = false;
1251 bool eld_changed = false;
079d88cc 1252
4bd038f9
DH		 1253 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1254 if (pin_eld->monitor_present)
1255 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1256 else
1257 eld->eld_valid = false;
079d88cc 1258
fae3d88a 1259 _snd_printd(SND_PR_VERBOSE,
384a48d7 1260 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
10250911 1261 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
5d44f927 1262
4bd038f9 1263 if (eld->eld_valid) {
1613d6b4
DH		 1264 if (snd_hdmi_get_eld(codec, pin_nid, eld->eld_buffer,
1265 &eld->eld_size) < 0)
4bd038f9 1266 eld->eld_valid = false;
1613d6b4
DH		 1267 else {
1268 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1269 if (snd_hdmi_parse_eld(&eld->info, eld->eld_buffer,
1270 eld->eld_size) < 0)
4bd038f9 1271 eld->eld_valid = false;
1613d6b4
DH		 1272 }
1273
4bd038f9 1274 if (eld->eld_valid) {
1613d6b4 1275 snd_hdmi_show_eld(&eld->info);
4bd038f9 1276 update_eld = true;
1613d6b4 1277 }
c6e8453e 1278 else if (repoll) {
744626da
WF		 1279 queue_delayed_work(codec->bus->workq,
1280 &per_pin->work,
1281 msecs_to_jiffies(300));
4bd038f9 1282 return;
744626da
WF		 1283 }
1284 }
4bd038f9
DH		 1285
1286 mutex_lock(&pin_eld->lock);
92c69e79 1287 if (pin_eld->eld_valid && !eld->eld_valid) {
4bd038f9 1288 update_eld = true;
92c69e79
DH		 1289 eld_changed = true;
1290 }
4bd038f9 1291 if (update_eld) {
dc780f7f 1292 bool old_eld_valid = pin_eld->eld_valid;
4bd038f9 1293 pin_eld->eld_valid = eld->eld_valid;
92c69e79
DH		 1294 eld_changed = pin_eld->eld_size != eld->eld_size ||
1295 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
4bd038f9
DH		 1296 eld->eld_size) != 0;
1297 if (eld_changed)
1298 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1299 eld->eld_size);
1300 pin_eld->eld_size = eld->eld_size;
1301 pin_eld->info = eld->info;
dc780f7f
TI		 1302
1303 /* Haswell-specific workaround: re-setup when the transcoder is
1304 * changed during the stream playback
1305 */
1306 if (codec->vendor_id == 0x80862807 &&
1307 eld->eld_valid && !old_eld_valid && per_pin->setup) {
1308 snd_hda_codec_write(codec, pin_nid, 0,
1309 AC_VERB_SET_AMP_GAIN_MUTE,
1310 AMP_OUT_UNMUTE);
1311 hdmi_setup_audio_infoframe(codec, per_pin,
1312 per_pin->non_pcm);
1313 }
4bd038f9
DH		 1314 }
1315 mutex_unlock(&pin_eld->lock);
92c69e79
DH		 1316
1317 if (eld_changed)
1318 snd_ctl_notify(codec->bus->card,
1319 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1320 &per_pin->eld_ctl->id);
079d88cc
WF		 1321}
1322
744626da
WF		 1323static void hdmi_repoll_eld(struct work_struct *work)
1324{
1325 struct hdmi_spec_per_pin *per_pin =
1326 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1327
c6e8453e
WF		 1328 if (per_pin->repoll_count++ > 6)
1329 per_pin->repoll_count = 0;
1330
1331 hdmi_present_sense(per_pin, per_pin->repoll_count);
744626da
WF		 1332}
1333
c88d4e84
TI		 1334static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1335 hda_nid_t nid);
1336
079d88cc
WF		 1337static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1338{
1339 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1340 unsigned int caps, config;
1341 int pin_idx;
1342 struct hdmi_spec_per_pin *per_pin;
07acecc1 1343 int err;
079d88cc 1344
efc2f8de 1345 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1346 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1347 return 0;
1348
efc2f8de 1349 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1350 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1351 return 0;
1352
c88d4e84
TI		 1353 if (codec->vendor_id == 0x80862807)
1354 intel_haswell_fixup_connect_list(codec, pin_nid);
1355
384a48d7 1356 pin_idx = spec->num_pins;
bce0d2a8
TI		 1357 per_pin = snd_array_new(&spec->pins);
1358 if (!per_pin)
1359 return -ENOMEM;
384a48d7
SW		 1360
1361 per_pin->pin_nid = pin_nid;
1a6003b5 1362 per_pin->non_pcm = false;
079d88cc 1363
384a48d7
SW		 1364 err = hdmi_read_pin_conn(codec, pin_idx);
1365 if (err < 0)
1366 return err;
079d88cc 1367
079d88cc
WF		 1368 spec->num_pins++;
1369
384a48d7 1370 return 0;
079d88cc
WF		 1371}
1372
384a48d7 1373static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1374{
1375 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1376 struct hdmi_spec_per_cvt *per_cvt;
1377 unsigned int chans;
1378 int err;
079d88cc 1379
384a48d7
SW		 1380 chans = get_wcaps(codec, cvt_nid);
1381 chans = get_wcaps_channels(chans);
1382
bce0d2a8
TI		 1383 per_cvt = snd_array_new(&spec->cvts);
1384 if (!per_cvt)
1385 return -ENOMEM;
384a48d7
SW		 1386
1387 per_cvt->cvt_nid = cvt_nid;
1388 per_cvt->channels_min = 2;
d45e6889 1389 if (chans <= 16) {
384a48d7 1390 per_cvt->channels_max = chans;
d45e6889
TI		 1391 if (chans > spec->channels_max)
1392 spec->channels_max = chans;
1393 }
384a48d7
SW		 1394
1395 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1396 &per_cvt->rates,
1397 &per_cvt->formats,
1398 &per_cvt->maxbps);
1399 if (err < 0)
1400 return err;
1401
bce0d2a8
TI		 1402 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1403 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1404 spec->num_cvts++;
079d88cc
WF		 1405
1406 return 0;
1407}
1408
1409static int hdmi_parse_codec(struct hda_codec *codec)
1410{
1411 hda_nid_t nid;
1412 int i, nodes;
1413
1414 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1415 if (!nid || nodes < 0) {
1416 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
1417 return -EINVAL;
1418 }
1419
1420 for (i = 0; i < nodes; i++, nid++) {
1421 unsigned int caps;
1422 unsigned int type;
1423
efc2f8de 1424 caps = get_wcaps(codec, nid);
079d88cc
WF		 1425 type = get_wcaps_type(caps);
1426
1427 if (!(caps & AC_WCAP_DIGITAL))
1428 continue;
1429
1430 switch (type) {
1431 case AC_WID_AUD_OUT:
384a48d7 1432 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1433 break;
1434 case AC_WID_PIN:
3eaead57 1435 hdmi_add_pin(codec, nid);
079d88cc
WF		 1436 break;
1437 }
1438 }
1439
c9adeefd
DH		 1440#ifdef CONFIG_PM
1441 /* We're seeing some problems with unsolicited hot plug events on
1442 * PantherPoint after S3, if this is not enabled */
1443 if (codec->vendor_id == 0x80862806)
1444 codec->bus->power_keep_link_on = 1;
079d88cc
WF		 1445 /*
1446 * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
1447 * can be lost and presence sense verb will become inaccurate if the
1448 * HDA link is powered off at hot plug or hw initialization time.
1449 */
c9adeefd 1450 else if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
079d88cc
WF		 1451 AC_PWRST_EPSS))
1452 codec->bus->power_keep_link_on = 1;
1453#endif
1454
1455 return 0;
1456}
1457
84eb01be
TI		 1458/*
1459 */
1a6003b5
TI		 1460static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1461{
1462 struct hda_spdif_out *spdif;
1463 bool non_pcm;
1464
1465 mutex_lock(&codec->spdif_mutex);
1466 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1467 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1468 mutex_unlock(&codec->spdif_mutex);
1469 return non_pcm;
1470}
1471
1472
84eb01be
TI		 1473/*
1474 * HDMI callbacks
1475 */
1476
1477static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1478 struct hda_codec *codec,
1479 unsigned int stream_tag,
1480 unsigned int format,
1481 struct snd_pcm_substream *substream)
1482{
384a48d7
SW		 1483 hda_nid_t cvt_nid = hinfo->nid;
1484 struct hdmi_spec *spec = codec->spec;
1485 int pin_idx = hinfo_to_pin_index(spec, hinfo);
dc780f7f
TI		 1486 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1487 hda_nid_t pin_nid = per_pin->pin_nid;
1a6003b5 1488 bool non_pcm;
2b1461bb 1489 int pinctl;
1a6003b5
TI		 1490
1491 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
dc780f7f
TI		 1492 per_pin->channels = substream->runtime->channels;
1493 per_pin->setup = true;
384a48d7
SW		 1494
1495 hdmi_set_channel_count(codec, cvt_nid, substream->runtime->channels);
84eb01be 1496
dc780f7f 1497 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
84eb01be 1498
2b1461bb
SW		 1499 if (spec->dyn_pin_out) {
1500 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1501 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1502 snd_hda_codec_write(codec, pin_nid, 0,
1503 AC_VERB_SET_PIN_WIDGET_CONTROL,
1504 pinctl | PIN_OUT);
1505 }
1506
384a48d7 1507 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
84eb01be
TI		 1508}
1509
8dfaa573
TI		 1510static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1511 struct hda_codec *codec,
1512 struct snd_pcm_substream *substream)
1513{
1514 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1515 return 0;
1516}
1517
f2ad24fa
TI		 1518static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1519 struct hda_codec *codec,
1520 struct snd_pcm_substream *substream)
384a48d7
SW		 1521{
1522 struct hdmi_spec *spec = codec->spec;
1523 int cvt_idx, pin_idx;
1524 struct hdmi_spec_per_cvt *per_cvt;
1525 struct hdmi_spec_per_pin *per_pin;
2b1461bb 1526 int pinctl;
384a48d7 1527
384a48d7
SW		 1528 if (hinfo->nid) {
1529 cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid);
1530 if (snd_BUG_ON(cvt_idx < 0))
1531 return -EINVAL;
bce0d2a8 1532 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1533
1534 snd_BUG_ON(!per_cvt->assigned);
1535 per_cvt->assigned = 0;
1536 hinfo->nid = 0;
1537
1538 pin_idx = hinfo_to_pin_index(spec, hinfo);
1539 if (snd_BUG_ON(pin_idx < 0))
1540 return -EINVAL;
bce0d2a8 1541 per_pin = get_pin(spec, pin_idx);
384a48d7 1542
2b1461bb
SW		 1543 if (spec->dyn_pin_out) {
1544 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1545 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1546 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1547 AC_VERB_SET_PIN_WIDGET_CONTROL,
1548 pinctl & ~PIN_OUT);
1549 }
1550
384a48d7 1551 snd_hda_spdif_ctls_unassign(codec, pin_idx);
d45e6889
TI		 1552 per_pin->chmap_set = false;
1553 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
dc780f7f
TI		 1554
1555 per_pin->setup = false;
1556 per_pin->channels = 0;
384a48d7 1557 }
d45e6889 1558
384a48d7
SW		 1559 return 0;
1560}
1561
1562static const struct hda_pcm_ops generic_ops = {
1563 .open = hdmi_pcm_open,
f2ad24fa 1564 .close = hdmi_pcm_close,
384a48d7 1565 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 1566 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 1567};
1568
d45e6889
TI		 1569/*
1570 * ALSA API channel-map control callbacks
1571 */
1572static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1573 struct snd_ctl_elem_info *uinfo)
1574{
1575 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1576 struct hda_codec *codec = info->private_data;
1577 struct hdmi_spec *spec = codec->spec;
1578 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1579 uinfo->count = spec->channels_max;
1580 uinfo->value.integer.min = 0;
1581 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1582 return 0;
1583}
1584
1585static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1586 unsigned int size, unsigned int __user *tlv)
1587{
1588 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1589 struct hda_codec *codec = info->private_data;
1590 struct hdmi_spec *spec = codec->spec;
1591 const unsigned int valid_mask =
1592 FL | FR | RL | RR | LFE | FC | RLC | RRC;
1593 unsigned int __user *dst;
1594 int chs, count = 0;
1595
1596 if (size < 8)
1597 return -ENOMEM;
1598 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1599 return -EFAULT;
1600 size -= 8;
1601 dst = tlv + 2;
498dab3a 1602 for (chs = 2; chs <= spec->channels_max; chs++) {
d45e6889
TI		 1603 int i, c;
1604 struct cea_channel_speaker_allocation *cap;
1605 cap = channel_allocations;
1606 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1607 int chs_bytes = chs * 4;
1608 if (cap->channels != chs)
1609 continue;
1610 if (cap->spk_mask & ~valid_mask)
1611 continue;
1612 if (size < 8)
1613 return -ENOMEM;
1614 if (put_user(SNDRV_CTL_TLVT_CHMAP_VAR, dst) ||
1615 put_user(chs_bytes, dst + 1))
1616 return -EFAULT;
1617 dst += 2;
1618 size -= 8;
1619 count += 8;
1620 if (size < chs_bytes)
1621 return -ENOMEM;
1622 size -= chs_bytes;
1623 count += chs_bytes;
1624 for (c = 7; c >= 0; c--) {
1625 int spk = cap->speakers[c];
1626 if (!spk)
1627 continue;
1628 if (put_user(spk_to_chmap(spk), dst))
1629 return -EFAULT;
1630 dst++;
1631 }
1632 }
1633 }
1634 if (put_user(count, tlv + 1))
1635 return -EFAULT;
1636 return 0;
1637}
1638
1639static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
1640 struct snd_ctl_elem_value *ucontrol)
1641{
1642 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1643 struct hda_codec *codec = info->private_data;
1644 struct hdmi_spec *spec = codec->spec;
1645 int pin_idx = kcontrol->private_value;
bce0d2a8 1646 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1647 int i;
1648
1649 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
1650 ucontrol->value.integer.value[i] = per_pin->chmap[i];
1651 return 0;
1652}
1653
1654static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
1655 struct snd_ctl_elem_value *ucontrol)
1656{
1657 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1658 struct hda_codec *codec = info->private_data;
1659 struct hdmi_spec *spec = codec->spec;
1660 int pin_idx = kcontrol->private_value;
bce0d2a8 1661 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1662 unsigned int ctl_idx;
1663 struct snd_pcm_substream *substream;
1664 unsigned char chmap[8];
1665 int i, ca, prepared = 0;
1666
1667 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
1668 substream = snd_pcm_chmap_substream(info, ctl_idx);
1669 if (!substream || !substream->runtime)
6f54c361 1670 return 0; /* just for avoiding error from alsactl restore */
d45e6889
TI		 1671 switch (substream->runtime->status->state) {
1672 case SNDRV_PCM_STATE_OPEN:
1673 case SNDRV_PCM_STATE_SETUP:
1674 break;
1675 case SNDRV_PCM_STATE_PREPARED:
1676 prepared = 1;
1677 break;
1678 default:
1679 return -EBUSY;
1680 }
1681 memset(chmap, 0, sizeof(chmap));
1682 for (i = 0; i < ARRAY_SIZE(chmap); i++)
1683 chmap[i] = ucontrol->value.integer.value[i];
1684 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
1685 return 0;
1686 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
1687 if (ca < 0)
1688 return -EINVAL;
1689 per_pin->chmap_set = true;
1690 memcpy(per_pin->chmap, chmap, sizeof(chmap));
1691 if (prepared)
dc780f7f 1692 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
d45e6889
TI		 1693
1694 return 0;
1695}
1696
84eb01be
TI		 1697static int generic_hdmi_build_pcms(struct hda_codec *codec)
1698{
1699 struct hdmi_spec *spec = codec->spec;
384a48d7 1700 int pin_idx;
84eb01be 1701
384a48d7
SW		 1702 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1703 struct hda_pcm *info;
84eb01be 1704 struct hda_pcm_stream *pstr;
bce0d2a8
TI		 1705 struct hdmi_spec_per_pin *per_pin;
1706
1707 per_pin = get_pin(spec, pin_idx);
1708 sprintf(per_pin->pcm_name, "HDMI %d", pin_idx);
1709 info = snd_array_new(&spec->pcm_rec);
1710 if (!info)
1711 return -ENOMEM;
1712 info->name = per_pin->pcm_name;
84eb01be 1713 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 1714 info->own_chmap = true;
384a48d7 1715
84eb01be 1716 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 1717 pstr->substreams = 1;
1718 pstr->ops = generic_ops;
1719 /* other pstr fields are set in open */
84eb01be
TI		 1720 }
1721
384a48d7 1722 codec->num_pcms = spec->num_pins;
bce0d2a8 1723 codec->pcm_info = spec->pcm_rec.list;
384a48d7 1724
84eb01be
TI		 1725 return 0;
1726}
1727
0b6c49b5
DH		 1728static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
1729{
31ef2257 1730 char hdmi_str[32] = "HDMI/DP";
0b6c49b5 1731 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 1732 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1733 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
0b6c49b5 1734
31ef2257
TI		 1735 if (pcmdev > 0)
1736 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
30efd8de
DH		 1737 if (!is_jack_detectable(codec, per_pin->pin_nid))
1738 strncat(hdmi_str, " Phantom",
1739 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
0b6c49b5 1740
31ef2257 1741 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
0b6c49b5
DH		 1742}
1743
84eb01be
TI		 1744static int generic_hdmi_build_controls(struct hda_codec *codec)
1745{
1746 struct hdmi_spec *spec = codec->spec;
1747 int err;
384a48d7 1748 int pin_idx;
84eb01be 1749
384a48d7 1750 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1751 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
0b6c49b5
DH		 1752
1753 err = generic_hdmi_build_jack(codec, pin_idx);
1754 if (err < 0)
1755 return err;
1756
dcda5806
TI		 1757 err = snd_hda_create_dig_out_ctls(codec,
1758 per_pin->pin_nid,
1759 per_pin->mux_nids[0],
1760 HDA_PCM_TYPE_HDMI);
84eb01be
TI		 1761 if (err < 0)
1762 return err;
384a48d7 1763 snd_hda_spdif_ctls_unassign(codec, pin_idx);
14bc52b8
PLB		 1764
1765 /* add control for ELD Bytes */
bce0d2a8
TI		 1766 err = hdmi_create_eld_ctl(codec, pin_idx,
1767 get_pcm_rec(spec, pin_idx)->device);
14bc52b8
PLB		 1768
1769 if (err < 0)
1770 return err;
31ef2257 1771
82b1d73f 1772 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 1773 }
1774
d45e6889
TI		 1775 /* add channel maps */
1776 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1777 struct snd_pcm_chmap *chmap;
1778 struct snd_kcontrol *kctl;
1779 int i;
da958137
TI		 1780
1781 if (!codec->pcm_info[pin_idx].pcm)
1782 break;
d45e6889
TI		 1783 err = snd_pcm_add_chmap_ctls(codec->pcm_info[pin_idx].pcm,
1784 SNDRV_PCM_STREAM_PLAYBACK,
1785 NULL, 0, pin_idx, &chmap);
1786 if (err < 0)
1787 return err;
1788 /* override handlers */
1789 chmap->private_data = codec;
1790 kctl = chmap->kctl;
1791 for (i = 0; i < kctl->count; i++)
1792 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
1793 kctl->info = hdmi_chmap_ctl_info;
1794 kctl->get = hdmi_chmap_ctl_get;
1795 kctl->put = hdmi_chmap_ctl_put;
1796 kctl->tlv.c = hdmi_chmap_ctl_tlv;
1797 }
1798
84eb01be
TI		 1799 return 0;
1800}
1801
8b8d654b 1802static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 1803{
1804 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1805 int pin_idx;
1806
1807 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1808 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1809 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1810
744626da 1811 per_pin->codec = codec;
4bd038f9 1812 mutex_init(&eld->lock);
744626da 1813 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
384a48d7 1814 snd_hda_eld_proc_new(codec, eld, pin_idx);
84eb01be 1815 }
8b8d654b
TI		 1816 return 0;
1817}
1818
1819static int generic_hdmi_init(struct hda_codec *codec)
1820{
1821 struct hdmi_spec *spec = codec->spec;
1822 int pin_idx;
1823
1824 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1825 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
8b8d654b
TI		 1826 hda_nid_t pin_nid = per_pin->pin_nid;
1827
1828 hdmi_init_pin(codec, pin_nid);
1829 snd_hda_jack_detect_enable(codec, pin_nid, pin_nid);
1830 }
84eb01be
TI		 1831 return 0;
1832}
1833
bce0d2a8
TI		 1834static void hdmi_array_init(struct hdmi_spec *spec, int nums)
1835{
1836 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
1837 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
1838 snd_array_init(&spec->pcm_rec, sizeof(struct hda_pcm), nums);
1839}
1840
1841static void hdmi_array_free(struct hdmi_spec *spec)
1842{
1843 snd_array_free(&spec->pins);
1844 snd_array_free(&spec->cvts);
1845 snd_array_free(&spec->pcm_rec);
1846}
1847
84eb01be
TI		 1848static void generic_hdmi_free(struct hda_codec *codec)
1849{
1850 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1851 int pin_idx;
1852
1853 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1854 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1855 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1856
744626da 1857 cancel_delayed_work(&per_pin->work);
384a48d7
SW		 1858 snd_hda_eld_proc_free(codec, eld);
1859 }
84eb01be 1860
744626da 1861 flush_workqueue(codec->bus->workq);
bce0d2a8 1862 hdmi_array_free(spec);
84eb01be
TI		 1863 kfree(spec);
1864}
1865
fb79e1e0 1866static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 1867 .init = generic_hdmi_init,
1868 .free = generic_hdmi_free,
1869 .build_pcms = generic_hdmi_build_pcms,
1870 .build_controls = generic_hdmi_build_controls,
1871 .unsol_event = hdmi_unsol_event,
1872};
1873
6ffe168f 1874
c88d4e84
TI		 1875static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1876 hda_nid_t nid)
1877{
1878 struct hdmi_spec *spec = codec->spec;
1879 hda_nid_t conns[4];
1880 int nconns;
6ffe168f 1881
c88d4e84
TI		 1882 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
1883 if (nconns == spec->num_cvts &&
1884 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 1885 return;
1886
c88d4e84
TI		 1887 /* override pins connection list */
1888 snd_printdd("hdmi: haswell: override pin connection 0x%x\n", nid);
bce0d2a8 1889 nconns = max(spec->num_cvts, 4);
c88d4e84 1890 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 1891}
1892
1611a9c9
ML		 1893#define INTEL_VENDOR_NID 0x08
1894#define INTEL_GET_VENDOR_VERB 0xf81
1895#define INTEL_SET_VENDOR_VERB 0x781
1896#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
1897#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
1898
1899static void intel_haswell_enable_all_pins(struct hda_codec *codec,
17df3f55 1900 bool update_tree)
1611a9c9
ML		 1901{
1902 unsigned int vendor_param;
1903
1611a9c9
ML		 1904 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
1905 INTEL_GET_VENDOR_VERB, 0);
1906 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
1907 return;
1908
1909 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
1910 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
1911 INTEL_SET_VENDOR_VERB, vendor_param);
1912 if (vendor_param == -1)
1913 return;
1914
17df3f55
TI		 1915 if (update_tree)
1916 snd_hda_codec_update_widgets(codec);
1611a9c9
ML		 1917}
1918
c88d4e84
TI		 1919static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
1920{
1921 unsigned int vendor_param;
1922
1923 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
1924 INTEL_GET_VENDOR_VERB, 0);
1925 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
1926 return;
1927
1928 /* enable DP1.2 mode */
1929 vendor_param |= INTEL_EN_DP12;
1930 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
1931 INTEL_SET_VENDOR_VERB, vendor_param);
1932}
1933
17df3f55
TI		 1934/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
1935 * Otherwise you may get severe h/w communication errors.
1936 */
1937static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
1938 unsigned int power_state)
1939{
1940 if (power_state == AC_PWRST_D0) {
1941 intel_haswell_enable_all_pins(codec, false);
1942 intel_haswell_fixup_enable_dp12(codec);
1943 }
c88d4e84 1944
17df3f55
TI		 1945 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
1946 snd_hda_codec_set_power_to_all(codec, fg, power_state);
1947}
6ffe168f 1948
84eb01be
TI		 1949static int patch_generic_hdmi(struct hda_codec *codec)
1950{
1951 struct hdmi_spec *spec;
84eb01be
TI		 1952
1953 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1954 if (spec == NULL)
1955 return -ENOMEM;
1956
1957 codec->spec = spec;
bce0d2a8 1958 hdmi_array_init(spec, 4);
6ffe168f 1959
17df3f55
TI		 1960 if (codec->vendor_id == 0x80862807) {
1961 intel_haswell_enable_all_pins(codec, true);
c88d4e84 1962 intel_haswell_fixup_enable_dp12(codec);
17df3f55 1963 }
6ffe168f 1964
84eb01be
TI		 1965 if (hdmi_parse_codec(codec) < 0) {
1966 codec->spec = NULL;
1967 kfree(spec);
1968 return -EINVAL;
1969 }
1970 codec->patch_ops = generic_hdmi_patch_ops;
17df3f55
TI		 1971 if (codec->vendor_id == 0x80862807)
1972 codec->patch_ops.set_power_state = haswell_set_power_state;
1973
8b8d654b 1974 generic_hdmi_init_per_pins(codec);
84eb01be 1975
84eb01be
TI		 1976 init_channel_allocations();
1977
1978 return 0;
1979}
1980
3aaf8980
SW		 1981/*
1982 * Shared non-generic implementations
1983 */
1984
1985static int simple_playback_build_pcms(struct hda_codec *codec)
1986{
1987 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1988 struct hda_pcm *info;
8ceb332d
TI		 1989 unsigned int chans;
1990 struct hda_pcm_stream *pstr;
bce0d2a8 1991 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 1992
bce0d2a8
TI		 1993 per_cvt = get_cvt(spec, 0);
1994 chans = get_wcaps(codec, per_cvt->cvt_nid);
8ceb332d 1995 chans = get_wcaps_channels(chans);
3aaf8980 1996
bce0d2a8
TI		 1997 info = snd_array_new(&spec->pcm_rec);
1998 if (!info)
1999 return -ENOMEM;
2000 info->name = get_pin(spec, 0)->pcm_name;
2001 sprintf(info->name, "HDMI 0");
8ceb332d
TI		 2002 info->pcm_type = HDA_PCM_TYPE_HDMI;
2003 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2004 *pstr = spec->pcm_playback;
bce0d2a8 2005 pstr->nid = per_cvt->cvt_nid;
8ceb332d
TI		 2006 if (pstr->channels_max <= 2 && chans && chans <= 16)
2007 pstr->channels_max = chans;
3aaf8980 2008
bce0d2a8
TI		 2009 codec->num_pcms = 1;
2010 codec->pcm_info = info;
2011
3aaf8980
SW		 2012 return 0;
2013}
2014
4b6ace9e
TI		 2015/* unsolicited event for jack sensing */
2016static void simple_hdmi_unsol_event(struct hda_codec *codec,
2017 unsigned int res)
2018{
9dd8cf12 2019 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 2020 snd_hda_jack_report_sync(codec);
2021}
2022
2023/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2024 * as long as spec->pins[] is set correctly
2025 */
2026#define simple_hdmi_build_jack generic_hdmi_build_jack
2027
3aaf8980
SW		 2028static int simple_playback_build_controls(struct hda_codec *codec)
2029{
2030 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2031 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2032 int err;
3aaf8980 2033
bce0d2a8 2034 per_cvt = get_cvt(spec, 0);
6492e3de
AH		 2035 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2036 per_cvt->cvt_nid,
2037 HDA_PCM_TYPE_HDMI);
8ceb332d
TI		 2038 if (err < 0)
2039 return err;
2040 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 2041}
2042
4f0110ce
TI		 2043static int simple_playback_init(struct hda_codec *codec)
2044{
2045 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2046 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2047 hda_nid_t pin = per_pin->pin_nid;
8ceb332d
TI		 2048
2049 snd_hda_codec_write(codec, pin, 0,
2050 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2051 /* some codecs require to unmute the pin */
2052 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2053 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2054 AMP_OUT_UNMUTE);
2055 snd_hda_jack_detect_enable(codec, pin, pin);
4f0110ce
TI		 2056 return 0;
2057}
2058
3aaf8980
SW		 2059static void simple_playback_free(struct hda_codec *codec)
2060{
2061 struct hdmi_spec *spec = codec->spec;
2062
bce0d2a8 2063 hdmi_array_free(spec);
3aaf8980
SW		 2064 kfree(spec);
2065}
2066
84eb01be
TI		 2067/*
2068 * Nvidia specific implementations
2069 */
2070
2071#define Nv_VERB_SET_Channel_Allocation 0xF79
2072#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2073#define Nv_VERB_SET_Audio_Protection_On 0xF98
2074#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2075
2076#define nvhdmi_master_con_nid_7x 0x04
2077#define nvhdmi_master_pin_nid_7x 0x05
2078
fb79e1e0 2079static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 2080 /*front, rear, clfe, rear_surr */
2081 0x6, 0x8, 0xa, 0xc,
2082};
2083
ceaa86ba
TI		 2084static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2085 /* set audio protect on */
2086 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2087 /* enable digital output on pin widget */
2088 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2089 {} /* terminator */
2090};
2091
2092static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 2093 /* set audio protect on */
2094 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2095 /* enable digital output on pin widget */
2096 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2097 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2098 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2099 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2100 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2101 {} /* terminator */
2102};
2103
2104#ifdef LIMITED_RATE_FMT_SUPPORT
2105/* support only the safe format and rate */
2106#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2107#define SUPPORTED_MAXBPS 16
2108#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2109#else
2110/* support all rates and formats */
2111#define SUPPORTED_RATES \
2112 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2113 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2114 SNDRV_PCM_RATE_192000)
2115#define SUPPORTED_MAXBPS 24
2116#define SUPPORTED_FORMATS \
2117 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2118#endif
2119
ceaa86ba
TI		 2120static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2121{
2122 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2123 return 0;
2124}
2125
2126static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 2127{
ceaa86ba 2128 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 2129 return 0;
2130}
2131
393004b2
ND		 2132static unsigned int channels_2_6_8[] = {
2133 2, 6, 8
2134};
2135
2136static unsigned int channels_2_8[] = {
2137 2, 8
2138};
2139
2140static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2141 .count = ARRAY_SIZE(channels_2_6_8),
2142 .list = channels_2_6_8,
2143 .mask = 0,
2144};
2145
2146static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2147 .count = ARRAY_SIZE(channels_2_8),
2148 .list = channels_2_8,
2149 .mask = 0,
2150};
2151
84eb01be
TI		 2152static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2153 struct hda_codec *codec,
2154 struct snd_pcm_substream *substream)
2155{
2156 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 2157 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2158
2159 switch (codec->preset->id) {
2160 case 0x10de0002:
2161 case 0x10de0003:
2162 case 0x10de0005:
2163 case 0x10de0006:
2164 hw_constraints_channels = &hw_constraints_2_8_channels;
2165 break;
2166 case 0x10de0007:
2167 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2168 break;
2169 default:
2170 break;
2171 }
2172
2173 if (hw_constraints_channels != NULL) {
2174 snd_pcm_hw_constraint_list(substream->runtime, 0,
2175 SNDRV_PCM_HW_PARAM_CHANNELS,
2176 hw_constraints_channels);
ad09fc9d
TI		 2177 } else {
2178 snd_pcm_hw_constraint_step(substream->runtime, 0,
2179 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 2180 }
2181
84eb01be
TI		 2182 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2183}
2184
2185static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2186 struct hda_codec *codec,
2187 struct snd_pcm_substream *substream)
2188{
2189 struct hdmi_spec *spec = codec->spec;
2190 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2191}
2192
2193static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2194 struct hda_codec *codec,
2195 unsigned int stream_tag,
2196 unsigned int format,
2197 struct snd_pcm_substream *substream)
2198{
2199 struct hdmi_spec *spec = codec->spec;
2200 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2201 stream_tag, format, substream);
2202}
2203
d0b1252d
TI		 2204static const struct hda_pcm_stream simple_pcm_playback = {
2205 .substreams = 1,
2206 .channels_min = 2,
2207 .channels_max = 2,
2208 .ops = {
2209 .open = simple_playback_pcm_open,
2210 .close = simple_playback_pcm_close,
2211 .prepare = simple_playback_pcm_prepare
2212 },
2213};
2214
2215static const struct hda_codec_ops simple_hdmi_patch_ops = {
2216 .build_controls = simple_playback_build_controls,
2217 .build_pcms = simple_playback_build_pcms,
2218 .init = simple_playback_init,
2219 .free = simple_playback_free,
250e41ac 2220 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 2221};
2222
2223static int patch_simple_hdmi(struct hda_codec *codec,
2224 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2225{
2226 struct hdmi_spec *spec;
bce0d2a8
TI		 2227 struct hdmi_spec_per_cvt *per_cvt;
2228 struct hdmi_spec_per_pin *per_pin;
d0b1252d
TI		 2229
2230 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2231 if (!spec)
2232 return -ENOMEM;
2233
2234 codec->spec = spec;
bce0d2a8 2235 hdmi_array_init(spec, 1);
d0b1252d
TI		 2236
2237 spec->multiout.num_dacs = 0; /* no analog */
2238 spec->multiout.max_channels = 2;
2239 spec->multiout.dig_out_nid = cvt_nid;
2240 spec->num_cvts = 1;
2241 spec->num_pins = 1;
bce0d2a8
TI		 2242 per_pin = snd_array_new(&spec->pins);
2243 per_cvt = snd_array_new(&spec->cvts);
2244 if (!per_pin || !per_cvt) {
2245 simple_playback_free(codec);
2246 return -ENOMEM;
2247 }
2248 per_cvt->cvt_nid = cvt_nid;
2249 per_pin->pin_nid = pin_nid;
d0b1252d
TI		 2250 spec->pcm_playback = simple_pcm_playback;
2251
2252 codec->patch_ops = simple_hdmi_patch_ops;
2253
2254 return 0;
2255}
2256
1f348522
AP		 2257static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2258 int channels)
2259{
2260 unsigned int chanmask;
2261 int chan = channels ? (channels - 1) : 1;
2262
2263 switch (channels) {
2264 default:
2265 case 0:
2266 case 2:
2267 chanmask = 0x00;
2268 break;
2269 case 4:
2270 chanmask = 0x08;
2271 break;
2272 case 6:
2273 chanmask = 0x0b;
2274 break;
2275 case 8:
2276 chanmask = 0x13;
2277 break;
2278 }
2279
2280 /* Set the audio infoframe channel allocation and checksum fields. The
2281 * channel count is computed implicitly by the hardware. */
2282 snd_hda_codec_write(codec, 0x1, 0,
2283 Nv_VERB_SET_Channel_Allocation, chanmask);
2284
2285 snd_hda_codec_write(codec, 0x1, 0,
2286 Nv_VERB_SET_Info_Frame_Checksum,
2287 (0x71 - chan - chanmask));
2288}
2289
84eb01be
TI		 2290static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2291 struct hda_codec *codec,
2292 struct snd_pcm_substream *substream)
2293{
2294 struct hdmi_spec *spec = codec->spec;
2295 int i;
2296
2297 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2298 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2299 for (i = 0; i < 4; i++) {
2300 /* set the stream id */
2301 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2302 AC_VERB_SET_CHANNEL_STREAMID, 0);
2303 /* set the stream format */
2304 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2305 AC_VERB_SET_STREAM_FORMAT, 0);
2306 }
2307
1f348522
AP		 2308 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2309 * streams are disabled. */
2310 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2311
84eb01be
TI		 2312 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2313}
2314
2315static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2316 struct hda_codec *codec,
2317 unsigned int stream_tag,
2318 unsigned int format,
2319 struct snd_pcm_substream *substream)
2320{
2321 int chs;
112daa7a 2322 unsigned int dataDCC2, channel_id;
84eb01be 2323 int i;
7c935976 2324 struct hdmi_spec *spec = codec->spec;
e3245cdd 2325 struct hda_spdif_out *spdif;
bce0d2a8 2326 struct hdmi_spec_per_cvt *per_cvt;
84eb01be
TI		 2327
2328 mutex_lock(&codec->spdif_mutex);
bce0d2a8
TI		 2329 per_cvt = get_cvt(spec, 0);
2330 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
84eb01be
TI		 2331
2332 chs = substream->runtime->channels;
84eb01be 2333
84eb01be
TI		 2334 dataDCC2 = 0x2;
2335
84eb01be 2336 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 2337 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2338 snd_hda_codec_write(codec,
2339 nvhdmi_master_con_nid_7x,
2340 0,
2341 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2342 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2343
2344 /* set the stream id */
2345 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2346 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2347
2348 /* set the stream format */
2349 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2350 AC_VERB_SET_STREAM_FORMAT, format);
2351
2352 /* turn on again (if needed) */
2353 /* enable and set the channel status audio/data flag */
7c935976 2354 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2355 snd_hda_codec_write(codec,
2356 nvhdmi_master_con_nid_7x,
2357 0,
2358 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2359 spdif->ctls & 0xff);
84eb01be
TI		 2360 snd_hda_codec_write(codec,
2361 nvhdmi_master_con_nid_7x,
2362 0,
2363 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2364 }
2365
2366 for (i = 0; i < 4; i++) {
2367 if (chs == 2)
2368 channel_id = 0;
2369 else
2370 channel_id = i * 2;
2371
2372 /* turn off SPDIF once;
2373 *otherwise the IEC958 bits won't be updated
2374 */
2375 if (codec->spdif_status_reset &&
7c935976 2376 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2377 snd_hda_codec_write(codec,
2378 nvhdmi_con_nids_7x[i],
2379 0,
2380 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2381 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2382 /* set the stream id */
2383 snd_hda_codec_write(codec,
2384 nvhdmi_con_nids_7x[i],
2385 0,
2386 AC_VERB_SET_CHANNEL_STREAMID,
2387 (stream_tag << 4) | channel_id);
2388 /* set the stream format */
2389 snd_hda_codec_write(codec,
2390 nvhdmi_con_nids_7x[i],
2391 0,
2392 AC_VERB_SET_STREAM_FORMAT,
2393 format);
2394 /* turn on again (if needed) */
2395 /* enable and set the channel status audio/data flag */
2396 if (codec->spdif_status_reset &&
7c935976 2397 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2398 snd_hda_codec_write(codec,
2399 nvhdmi_con_nids_7x[i],
2400 0,
2401 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2402 spdif->ctls & 0xff);
84eb01be
TI		 2403 snd_hda_codec_write(codec,
2404 nvhdmi_con_nids_7x[i],
2405 0,
2406 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2407 }
2408 }
2409
1f348522 2410 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 2411
2412 mutex_unlock(&codec->spdif_mutex);
2413 return 0;
2414}
2415
fb79e1e0 2416static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 2417 .substreams = 1,
2418 .channels_min = 2,
2419 .channels_max = 8,
2420 .nid = nvhdmi_master_con_nid_7x,
2421 .rates = SUPPORTED_RATES,
2422 .maxbps = SUPPORTED_MAXBPS,
2423 .formats = SUPPORTED_FORMATS,
2424 .ops = {
2425 .open = simple_playback_pcm_open,
2426 .close = nvhdmi_8ch_7x_pcm_close,
2427 .prepare = nvhdmi_8ch_7x_pcm_prepare
2428 },
2429};
2430
84eb01be
TI		 2431static int patch_nvhdmi_2ch(struct hda_codec *codec)
2432{
2433 struct hdmi_spec *spec;
d0b1252d
TI		 2434 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2435 nvhdmi_master_pin_nid_7x);
2436 if (err < 0)
2437 return err;
84eb01be 2438
ceaa86ba 2439 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 2440 /* override the PCM rates, etc, as the codec doesn't give full list */
2441 spec = codec->spec;
2442 spec->pcm_playback.rates = SUPPORTED_RATES;
2443 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2444 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 2445 return 0;
2446}
2447
53775b0d
TI		 2448static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2449{
2450 struct hdmi_spec *spec = codec->spec;
2451 int err = simple_playback_build_pcms(codec);
bce0d2a8
TI		 2452 if (!err) {
2453 struct hda_pcm *info = get_pcm_rec(spec, 0);
2454 info->own_chmap = true;
2455 }
53775b0d
TI		 2456 return err;
2457}
2458
2459static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2460{
2461 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2462 struct hda_pcm *info;
53775b0d
TI		 2463 struct snd_pcm_chmap *chmap;
2464 int err;
2465
2466 err = simple_playback_build_controls(codec);
2467 if (err < 0)
2468 return err;
2469
2470 /* add channel maps */
bce0d2a8
TI		 2471 info = get_pcm_rec(spec, 0);
2472 err = snd_pcm_add_chmap_ctls(info->pcm,
53775b0d
TI		 2473 SNDRV_PCM_STREAM_PLAYBACK,
2474 snd_pcm_alt_chmaps, 8, 0, &chmap);
2475 if (err < 0)
2476 return err;
2477 switch (codec->preset->id) {
2478 case 0x10de0002:
2479 case 0x10de0003:
2480 case 0x10de0005:
2481 case 0x10de0006:
2482 chmap->channel_mask = (1U << 2) | (1U << 8);
2483 break;
2484 case 0x10de0007:
2485 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2486 }
2487 return 0;
2488}
2489
84eb01be
TI		 2490static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2491{
2492 struct hdmi_spec *spec;
2493 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 2494 if (err < 0)
2495 return err;
2496 spec = codec->spec;
2497 spec->multiout.max_channels = 8;
d0b1252d 2498 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 2499 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 2500 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2501 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 2502
2503 /* Initialize the audio infoframe channel mask and checksum to something
2504 * valid */
2505 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2506
84eb01be
TI		 2507 return 0;
2508}
2509
c6a3cab8
AH		 2510static int patch_nvhdmi(struct hda_codec *codec)
2511{
2512 struct hdmi_spec *spec;
2513 int err;
2514
2515 err = patch_generic_hdmi(codec);
2516 if (err)
2517 return err;
2518
2519 spec = codec->spec;
2b1461bb 2520 spec->dyn_pin_out = true;
c6a3cab8
AH		 2521
2522 return 0;
2523}
2524
84eb01be
TI		 2525/*
2526 * ATI-specific implementations
2527 *
2528 * FIXME: we may omit the whole this and use the generic code once after
2529 * it's confirmed to work.
2530 */
2531
2532#define ATIHDMI_CVT_NID 0x02 /* audio converter */
2533#define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
2534
2535static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2536 struct hda_codec *codec,
2537 unsigned int stream_tag,
2538 unsigned int format,
2539 struct snd_pcm_substream *substream)
2540{
2541 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2542 struct hdmi_spec_per_cvt *per_cvt = get_cvt(spec, 0);
84eb01be
TI		 2543 int chans = substream->runtime->channels;
2544 int i, err;
2545
2546 err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format,
2547 substream);
2548 if (err < 0)
2549 return err;
bce0d2a8 2550 snd_hda_codec_write(codec, per_cvt->cvt_nid, 0,
384a48d7 2551 AC_VERB_SET_CVT_CHAN_COUNT, chans - 1);
84eb01be
TI		 2552 /* FIXME: XXX */
2553 for (i = 0; i < chans; i++) {
bce0d2a8 2554 snd_hda_codec_write(codec, per_cvt->cvt_nid, 0,
84eb01be
TI		 2555 AC_VERB_SET_HDMI_CHAN_SLOT,
2556 (i << 4) | i);
2557 }
2558 return 0;
2559}
2560
84eb01be
TI		 2561static int patch_atihdmi(struct hda_codec *codec)
2562{
2563 struct hdmi_spec *spec;
d0b1252d
TI		 2564 int err = patch_simple_hdmi(codec, ATIHDMI_CVT_NID, ATIHDMI_PIN_NID);
2565 if (err < 0)
2566 return err;
2567 spec = codec->spec;
2568 spec->pcm_playback.ops.prepare = atihdmi_playback_pcm_prepare;
84eb01be
TI		 2569 return 0;
2570}
2571
3de5ff88
AL		 2572/* VIA HDMI Implementation */
2573#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
2574#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
2575
3de5ff88
AL		 2576static int patch_via_hdmi(struct hda_codec *codec)
2577{
250e41ac 2578 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 2579}
84eb01be
TI		 2580
2581/*
2582 * patch entries
2583 */
fb79e1e0 2584static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
84eb01be
TI		 2585{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
2586{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
2587{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
36e9c135 2588{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 2589{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
2590{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
2591{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
2592{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2593{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2594{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2595{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2596{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
c6a3cab8
AH		 2597{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_nvhdmi },
2598{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_nvhdmi },
2599{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_nvhdmi },
2600{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_nvhdmi },
2601{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_nvhdmi },
2602{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_nvhdmi },
2603{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_nvhdmi },
2604{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_nvhdmi },
2605{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_nvhdmi },
2606{ .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_nvhdmi },
2607{ .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_nvhdmi },
c8900a0f 2608/* 17 is known to be absent */
c6a3cab8
AH		 2609{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_nvhdmi },
2610{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_nvhdmi },
2611{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_nvhdmi },
2612{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_nvhdmi },
2613{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_nvhdmi },
2614{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_nvhdmi },
2615{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_nvhdmi },
2616{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_nvhdmi },
2617{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_nvhdmi },
2618{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_nvhdmi },
2619{ .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_nvhdmi },
2620{ .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_nvhdmi },
84eb01be
TI		 2621{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
2622{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
3de5ff88
AL		 2623{ .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
2624{ .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
2625{ .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
2626{ .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 2627{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
2628{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
2629{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
2630{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
2631{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
2632{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
591e610d 2633{ .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
1c76684d 2634{ .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
6edc59e6 2635{ .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 2636{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
2637{} /* terminator */
2638};
2639
2640MODULE_ALIAS("snd-hda-codec-id:1002793c");
2641MODULE_ALIAS("snd-hda-codec-id:10027919");
2642MODULE_ALIAS("snd-hda-codec-id:1002791a");
2643MODULE_ALIAS("snd-hda-codec-id:1002aa01");
2644MODULE_ALIAS("snd-hda-codec-id:10951390");
2645MODULE_ALIAS("snd-hda-codec-id:10951392");
2646MODULE_ALIAS("snd-hda-codec-id:10de0002");
2647MODULE_ALIAS("snd-hda-codec-id:10de0003");
2648MODULE_ALIAS("snd-hda-codec-id:10de0005");
2649MODULE_ALIAS("snd-hda-codec-id:10de0006");
2650MODULE_ALIAS("snd-hda-codec-id:10de0007");
2651MODULE_ALIAS("snd-hda-codec-id:10de000a");
2652MODULE_ALIAS("snd-hda-codec-id:10de000b");
2653MODULE_ALIAS("snd-hda-codec-id:10de000c");
2654MODULE_ALIAS("snd-hda-codec-id:10de000d");
2655MODULE_ALIAS("snd-hda-codec-id:10de0010");
2656MODULE_ALIAS("snd-hda-codec-id:10de0011");
2657MODULE_ALIAS("snd-hda-codec-id:10de0012");
2658MODULE_ALIAS("snd-hda-codec-id:10de0013");
2659MODULE_ALIAS("snd-hda-codec-id:10de0014");
c8900a0f
RS		 2660MODULE_ALIAS("snd-hda-codec-id:10de0015");
2661MODULE_ALIAS("snd-hda-codec-id:10de0016");
84eb01be
TI		 2662MODULE_ALIAS("snd-hda-codec-id:10de0018");
2663MODULE_ALIAS("snd-hda-codec-id:10de0019");
2664MODULE_ALIAS("snd-hda-codec-id:10de001a");
2665MODULE_ALIAS("snd-hda-codec-id:10de001b");
2666MODULE_ALIAS("snd-hda-codec-id:10de001c");
2667MODULE_ALIAS("snd-hda-codec-id:10de0040");
2668MODULE_ALIAS("snd-hda-codec-id:10de0041");
2669MODULE_ALIAS("snd-hda-codec-id:10de0042");
2670MODULE_ALIAS("snd-hda-codec-id:10de0043");
2671MODULE_ALIAS("snd-hda-codec-id:10de0044");
7ae48b56 2672MODULE_ALIAS("snd-hda-codec-id:10de0051");
782e9cac 2673MODULE_ALIAS("snd-hda-codec-id:10de0060");
84eb01be
TI		 2674MODULE_ALIAS("snd-hda-codec-id:10de0067");
2675MODULE_ALIAS("snd-hda-codec-id:10de8001");
3de5ff88
AL		 2676MODULE_ALIAS("snd-hda-codec-id:11069f80");
2677MODULE_ALIAS("snd-hda-codec-id:11069f81");
2678MODULE_ALIAS("snd-hda-codec-id:11069f84");
2679MODULE_ALIAS("snd-hda-codec-id:11069f85");
84eb01be
TI		 2680MODULE_ALIAS("snd-hda-codec-id:17e80047");
2681MODULE_ALIAS("snd-hda-codec-id:80860054");
2682MODULE_ALIAS("snd-hda-codec-id:80862801");
2683MODULE_ALIAS("snd-hda-codec-id:80862802");
2684MODULE_ALIAS("snd-hda-codec-id:80862803");
2685MODULE_ALIAS("snd-hda-codec-id:80862804");
2686MODULE_ALIAS("snd-hda-codec-id:80862805");
591e610d 2687MODULE_ALIAS("snd-hda-codec-id:80862806");
1c76684d 2688MODULE_ALIAS("snd-hda-codec-id:80862807");
6edc59e6 2689MODULE_ALIAS("snd-hda-codec-id:80862880");
84eb01be
TI		 2690MODULE_ALIAS("snd-hda-codec-id:808629fb");
2691
2692MODULE_LICENSE("GPL");
2693MODULE_DESCRIPTION("HDMI HD-audio codec");
2694MODULE_ALIAS("snd-hda-codec-intelhdmi");
2695MODULE_ALIAS("snd-hda-codec-nvhdmi");
2696MODULE_ALIAS("snd-hda-codec-atihdmi");
2697
2698static struct hda_codec_preset_list intel_list = {
2699 .preset = snd_hda_preset_hdmi,
2700 .owner = THIS_MODULE,
2701};
2702
2703static int __init patch_hdmi_init(void)
2704{
2705 return snd_hda_add_codec_preset(&intel_list);
2706}
2707
2708static void __exit patch_hdmi_exit(void)
2709{
2710 snd_hda_delete_codec_preset(&intel_list);
2711}
2712
2713module_init(patch_hdmi_init)
2714module_exit(patch_hdmi_exit)
kernel source for telekom puls (alcatel/mediatek)