Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Dynamic DMA mapping support. | |
3 | * | |
563aaf06 | 4 | * This implementation is a fallback for platforms that do not support |
1da177e4 LT |
5 | * I/O TLBs (aka DMA address translation hardware). |
6 | * Copyright (C) 2000 Asit Mallick <Asit.K.Mallick@intel.com> | |
7 | * Copyright (C) 2000 Goutham Rao <goutham.rao@intel.com> | |
8 | * Copyright (C) 2000, 2003 Hewlett-Packard Co | |
9 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
10 | * | |
11 | * 03/05/07 davidm Switch from PCI-DMA to generic device DMA API. | |
12 | * 00/12/13 davidm Rename to swiotlb.c and add mark_clean() to avoid | |
13 | * unnecessary i-cache flushing. | |
569c8bf5 JL |
14 | * 04/07/.. ak Better overflow handling. Assorted fixes. |
15 | * 05/09/10 linville Add support for syncing ranges, support syncing for | |
16 | * DMA_BIDIRECTIONAL mappings, miscellaneous cleanup. | |
fb05a379 | 17 | * 08/12/11 beckyb Add highmem support |
1da177e4 LT |
18 | */ |
19 | ||
f2a4f762 KC |
20 | #define pr_fmt(fmt) "software IO TLB: " fmt |
21 | ||
1da177e4 | 22 | #include <linux/cache.h> |
17e5ad6c | 23 | #include <linux/dma-mapping.h> |
1da177e4 | 24 | #include <linux/mm.h> |
8bc3bcc9 | 25 | #include <linux/export.h> |
1da177e4 LT |
26 | #include <linux/spinlock.h> |
27 | #include <linux/string.h> | |
0016fdee | 28 | #include <linux/swiotlb.h> |
fb05a379 | 29 | #include <linux/pfn.h> |
1da177e4 LT |
30 | #include <linux/types.h> |
31 | #include <linux/ctype.h> | |
ef9b1893 | 32 | #include <linux/highmem.h> |
5a0e3ad6 | 33 | #include <linux/gfp.h> |
84be456f | 34 | #include <linux/scatterlist.h> |
c7753208 | 35 | #include <linux/mem_encrypt.h> |
1da177e4 LT |
36 | |
37 | #include <asm/io.h> | |
1da177e4 LT |
38 | #include <asm/dma.h> |
39 | ||
40 | #include <linux/init.h> | |
41 | #include <linux/bootmem.h> | |
a8522509 | 42 | #include <linux/iommu-helper.h> |
1da177e4 | 43 | |
ce5be5a1 | 44 | #define CREATE_TRACE_POINTS |
2b2b614d ZK |
45 | #include <trace/events/swiotlb.h> |
46 | ||
1da177e4 LT |
47 | #define OFFSET(val,align) ((unsigned long) \ |
48 | ( (val) & ( (align) - 1))) | |
49 | ||
0b9afede AW |
50 | #define SLABS_PER_PAGE (1 << (PAGE_SHIFT - IO_TLB_SHIFT)) |
51 | ||
52 | /* | |
53 | * Minimum IO TLB size to bother booting with. Systems with mainly | |
54 | * 64bit capable cards will only lightly use the swiotlb. If we can't | |
55 | * allocate a contiguous 1MB, we're probably in trouble anyway. | |
56 | */ | |
57 | #define IO_TLB_MIN_SLABS ((1<<20) >> IO_TLB_SHIFT) | |
58 | ||
ae7871be | 59 | enum swiotlb_force swiotlb_force; |
1da177e4 LT |
60 | |
61 | /* | |
bfc5501f KRW |
62 | * Used to do a quick range check in swiotlb_tbl_unmap_single and |
63 | * swiotlb_tbl_sync_single_*, to see if the memory was in fact allocated by this | |
1da177e4 LT |
64 | * API. |
65 | */ | |
ff7204a7 | 66 | static phys_addr_t io_tlb_start, io_tlb_end; |
1da177e4 LT |
67 | |
68 | /* | |
b595076a | 69 | * The number of IO TLB blocks (in groups of 64) between io_tlb_start and |
1da177e4 LT |
70 | * io_tlb_end. This is command line adjustable via setup_io_tlb_npages. |
71 | */ | |
72 | static unsigned long io_tlb_nslabs; | |
73 | ||
74 | /* | |
75 | * When the IOMMU overflows we return a fallback buffer. This sets the size. | |
76 | */ | |
77 | static unsigned long io_tlb_overflow = 32*1024; | |
78 | ||
ee3f6ba8 | 79 | static phys_addr_t io_tlb_overflow_buffer; |
1da177e4 LT |
80 | |
81 | /* | |
82 | * This is a free list describing the number of free entries available from | |
83 | * each index | |
84 | */ | |
85 | static unsigned int *io_tlb_list; | |
86 | static unsigned int io_tlb_index; | |
87 | ||
7453c549 KRW |
88 | /* |
89 | * Max segment that we can provide which (if pages are contingous) will | |
90 | * not be bounced (unless SWIOTLB_FORCE is set). | |
91 | */ | |
92 | unsigned int max_segment; | |
93 | ||
1da177e4 LT |
94 | /* |
95 | * We need to save away the original address corresponding to a mapped entry | |
96 | * for the sync operations. | |
97 | */ | |
8e0629c1 | 98 | #define INVALID_PHYS_ADDR (~(phys_addr_t)0) |
bc40ac66 | 99 | static phys_addr_t *io_tlb_orig_addr; |
1da177e4 LT |
100 | |
101 | /* | |
102 | * Protect the above data structures in the map and unmap calls | |
103 | */ | |
104 | static DEFINE_SPINLOCK(io_tlb_lock); | |
105 | ||
5740afdb FT |
106 | static int late_alloc; |
107 | ||
1da177e4 LT |
108 | static int __init |
109 | setup_io_tlb_npages(char *str) | |
110 | { | |
111 | if (isdigit(*str)) { | |
e8579e72 | 112 | io_tlb_nslabs = simple_strtoul(str, &str, 0); |
1da177e4 LT |
113 | /* avoid tail segment of size < IO_TLB_SEGSIZE */ |
114 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
115 | } | |
116 | if (*str == ',') | |
117 | ++str; | |
fff5d992 | 118 | if (!strcmp(str, "force")) { |
ae7871be | 119 | swiotlb_force = SWIOTLB_FORCE; |
fff5d992 GU |
120 | } else if (!strcmp(str, "noforce")) { |
121 | swiotlb_force = SWIOTLB_NO_FORCE; | |
122 | io_tlb_nslabs = 1; | |
123 | } | |
b18485e7 | 124 | |
c729de8f | 125 | return 0; |
1da177e4 | 126 | } |
c729de8f | 127 | early_param("swiotlb", setup_io_tlb_npages); |
1da177e4 LT |
128 | /* make io_tlb_overflow tunable too? */ |
129 | ||
f21ffe9f | 130 | unsigned long swiotlb_nr_tbl(void) |
5f98ecdb FT |
131 | { |
132 | return io_tlb_nslabs; | |
133 | } | |
f21ffe9f | 134 | EXPORT_SYMBOL_GPL(swiotlb_nr_tbl); |
c729de8f | 135 | |
7453c549 KRW |
136 | unsigned int swiotlb_max_segment(void) |
137 | { | |
138 | return max_segment; | |
139 | } | |
140 | EXPORT_SYMBOL_GPL(swiotlb_max_segment); | |
141 | ||
142 | void swiotlb_set_max_segment(unsigned int val) | |
143 | { | |
144 | if (swiotlb_force == SWIOTLB_FORCE) | |
145 | max_segment = 1; | |
146 | else | |
147 | max_segment = rounddown(val, PAGE_SIZE); | |
148 | } | |
149 | ||
c729de8f YL |
150 | /* default to 64MB */ |
151 | #define IO_TLB_DEFAULT_SIZE (64UL<<20) | |
152 | unsigned long swiotlb_size_or_default(void) | |
153 | { | |
154 | unsigned long size; | |
155 | ||
156 | size = io_tlb_nslabs << IO_TLB_SHIFT; | |
157 | ||
158 | return size ? size : (IO_TLB_DEFAULT_SIZE); | |
159 | } | |
160 | ||
c7753208 TL |
161 | void __weak swiotlb_set_mem_attributes(void *vaddr, unsigned long size) { } |
162 | ||
163 | /* For swiotlb, clear memory encryption mask from dma addresses */ | |
164 | static dma_addr_t swiotlb_phys_to_dma(struct device *hwdev, | |
165 | phys_addr_t address) | |
166 | { | |
167 | return __sme_clr(phys_to_dma(hwdev, address)); | |
168 | } | |
169 | ||
02ca646e | 170 | /* Note that this doesn't work with highmem page */ |
70a7d3cc JF |
171 | static dma_addr_t swiotlb_virt_to_bus(struct device *hwdev, |
172 | volatile void *address) | |
e08e1f7a | 173 | { |
862d196b | 174 | return phys_to_dma(hwdev, virt_to_phys(address)); |
e08e1f7a IC |
175 | } |
176 | ||
ac2cbab2 YL |
177 | static bool no_iotlb_memory; |
178 | ||
ad32e8cb | 179 | void swiotlb_print_info(void) |
2e5b2b86 | 180 | { |
ad32e8cb | 181 | unsigned long bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
2e5b2b86 | 182 | |
ac2cbab2 | 183 | if (no_iotlb_memory) { |
f2a4f762 | 184 | pr_warn("No low mem\n"); |
ac2cbab2 YL |
185 | return; |
186 | } | |
187 | ||
f2a4f762 | 188 | pr_info("mapped [mem %#010llx-%#010llx] (%luMB)\n", |
ff7204a7 | 189 | (unsigned long long)io_tlb_start, |
c40dba06 | 190 | (unsigned long long)io_tlb_end, |
f2a4f762 | 191 | bytes >> 20); |
2e5b2b86 IC |
192 | } |
193 | ||
c7753208 TL |
194 | /* |
195 | * Early SWIOTLB allocation may be too early to allow an architecture to | |
196 | * perform the desired operations. This function allows the architecture to | |
197 | * call SWIOTLB when the operations are possible. It needs to be called | |
198 | * before the SWIOTLB memory is used. | |
199 | */ | |
200 | void __init swiotlb_update_mem_attributes(void) | |
201 | { | |
202 | void *vaddr; | |
203 | unsigned long bytes; | |
204 | ||
205 | if (no_iotlb_memory || late_alloc) | |
206 | return; | |
207 | ||
208 | vaddr = phys_to_virt(io_tlb_start); | |
209 | bytes = PAGE_ALIGN(io_tlb_nslabs << IO_TLB_SHIFT); | |
210 | swiotlb_set_mem_attributes(vaddr, bytes); | |
211 | memset(vaddr, 0, bytes); | |
212 | ||
213 | vaddr = phys_to_virt(io_tlb_overflow_buffer); | |
214 | bytes = PAGE_ALIGN(io_tlb_overflow); | |
215 | swiotlb_set_mem_attributes(vaddr, bytes); | |
216 | memset(vaddr, 0, bytes); | |
217 | } | |
218 | ||
ac2cbab2 | 219 | int __init swiotlb_init_with_tbl(char *tlb, unsigned long nslabs, int verbose) |
1da177e4 | 220 | { |
ee3f6ba8 | 221 | void *v_overflow_buffer; |
563aaf06 | 222 | unsigned long i, bytes; |
1da177e4 | 223 | |
abbceff7 | 224 | bytes = nslabs << IO_TLB_SHIFT; |
1da177e4 | 225 | |
abbceff7 | 226 | io_tlb_nslabs = nslabs; |
ff7204a7 AD |
227 | io_tlb_start = __pa(tlb); |
228 | io_tlb_end = io_tlb_start + bytes; | |
1da177e4 | 229 | |
ee3f6ba8 AD |
230 | /* |
231 | * Get the overflow emergency buffer | |
232 | */ | |
ad6492b8 | 233 | v_overflow_buffer = memblock_virt_alloc_low_nopanic( |
457ff1de SS |
234 | PAGE_ALIGN(io_tlb_overflow), |
235 | PAGE_SIZE); | |
ee3f6ba8 | 236 | if (!v_overflow_buffer) |
ac2cbab2 | 237 | return -ENOMEM; |
ee3f6ba8 AD |
238 | |
239 | io_tlb_overflow_buffer = __pa(v_overflow_buffer); | |
240 | ||
1da177e4 LT |
241 | /* |
242 | * Allocate and initialize the free list array. This array is used | |
243 | * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE | |
244 | * between io_tlb_start and io_tlb_end. | |
245 | */ | |
457ff1de SS |
246 | io_tlb_list = memblock_virt_alloc( |
247 | PAGE_ALIGN(io_tlb_nslabs * sizeof(int)), | |
248 | PAGE_SIZE); | |
457ff1de SS |
249 | io_tlb_orig_addr = memblock_virt_alloc( |
250 | PAGE_ALIGN(io_tlb_nslabs * sizeof(phys_addr_t)), | |
251 | PAGE_SIZE); | |
8e0629c1 JB |
252 | for (i = 0; i < io_tlb_nslabs; i++) { |
253 | io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE); | |
254 | io_tlb_orig_addr[i] = INVALID_PHYS_ADDR; | |
255 | } | |
256 | io_tlb_index = 0; | |
1da177e4 | 257 | |
ad32e8cb FT |
258 | if (verbose) |
259 | swiotlb_print_info(); | |
ac2cbab2 | 260 | |
7453c549 | 261 | swiotlb_set_max_segment(io_tlb_nslabs << IO_TLB_SHIFT); |
ac2cbab2 | 262 | return 0; |
1da177e4 LT |
263 | } |
264 | ||
abbceff7 FT |
265 | /* |
266 | * Statically reserve bounce buffer space and initialize bounce buffer data | |
267 | * structures for the software IO TLB used to implement the DMA API. | |
268 | */ | |
ac2cbab2 YL |
269 | void __init |
270 | swiotlb_init(int verbose) | |
abbceff7 | 271 | { |
c729de8f | 272 | size_t default_size = IO_TLB_DEFAULT_SIZE; |
ff7204a7 | 273 | unsigned char *vstart; |
abbceff7 FT |
274 | unsigned long bytes; |
275 | ||
276 | if (!io_tlb_nslabs) { | |
277 | io_tlb_nslabs = (default_size >> IO_TLB_SHIFT); | |
278 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
279 | } | |
280 | ||
281 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; | |
282 | ||
ac2cbab2 | 283 | /* Get IO TLB memory from the low pages */ |
ad6492b8 | 284 | vstart = memblock_virt_alloc_low_nopanic(PAGE_ALIGN(bytes), PAGE_SIZE); |
ac2cbab2 YL |
285 | if (vstart && !swiotlb_init_with_tbl(vstart, io_tlb_nslabs, verbose)) |
286 | return; | |
abbceff7 | 287 | |
ac2cbab2 | 288 | if (io_tlb_start) |
457ff1de SS |
289 | memblock_free_early(io_tlb_start, |
290 | PAGE_ALIGN(io_tlb_nslabs << IO_TLB_SHIFT)); | |
f2a4f762 | 291 | pr_warn("Cannot allocate buffer"); |
ac2cbab2 | 292 | no_iotlb_memory = true; |
1da177e4 LT |
293 | } |
294 | ||
0b9afede AW |
295 | /* |
296 | * Systems with larger DMA zones (those that don't support ISA) can | |
297 | * initialize the swiotlb later using the slab allocator if needed. | |
298 | * This should be just like above, but with some error catching. | |
299 | */ | |
300 | int | |
563aaf06 | 301 | swiotlb_late_init_with_default_size(size_t default_size) |
0b9afede | 302 | { |
74838b75 | 303 | unsigned long bytes, req_nslabs = io_tlb_nslabs; |
ff7204a7 | 304 | unsigned char *vstart = NULL; |
0b9afede | 305 | unsigned int order; |
74838b75 | 306 | int rc = 0; |
0b9afede AW |
307 | |
308 | if (!io_tlb_nslabs) { | |
309 | io_tlb_nslabs = (default_size >> IO_TLB_SHIFT); | |
310 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
311 | } | |
312 | ||
313 | /* | |
314 | * Get IO TLB memory from the low pages | |
315 | */ | |
563aaf06 | 316 | order = get_order(io_tlb_nslabs << IO_TLB_SHIFT); |
0b9afede | 317 | io_tlb_nslabs = SLABS_PER_PAGE << order; |
563aaf06 | 318 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
0b9afede AW |
319 | |
320 | while ((SLABS_PER_PAGE << order) > IO_TLB_MIN_SLABS) { | |
ff7204a7 AD |
321 | vstart = (void *)__get_free_pages(GFP_DMA | __GFP_NOWARN, |
322 | order); | |
323 | if (vstart) | |
0b9afede AW |
324 | break; |
325 | order--; | |
326 | } | |
327 | ||
ff7204a7 | 328 | if (!vstart) { |
74838b75 KRW |
329 | io_tlb_nslabs = req_nslabs; |
330 | return -ENOMEM; | |
331 | } | |
563aaf06 | 332 | if (order != get_order(bytes)) { |
f2a4f762 KC |
333 | pr_warn("only able to allocate %ld MB\n", |
334 | (PAGE_SIZE << order) >> 20); | |
0b9afede AW |
335 | io_tlb_nslabs = SLABS_PER_PAGE << order; |
336 | } | |
ff7204a7 | 337 | rc = swiotlb_late_init_with_tbl(vstart, io_tlb_nslabs); |
74838b75 | 338 | if (rc) |
ff7204a7 | 339 | free_pages((unsigned long)vstart, order); |
7453c549 | 340 | |
74838b75 KRW |
341 | return rc; |
342 | } | |
343 | ||
344 | int | |
345 | swiotlb_late_init_with_tbl(char *tlb, unsigned long nslabs) | |
346 | { | |
347 | unsigned long i, bytes; | |
ee3f6ba8 | 348 | unsigned char *v_overflow_buffer; |
74838b75 KRW |
349 | |
350 | bytes = nslabs << IO_TLB_SHIFT; | |
351 | ||
352 | io_tlb_nslabs = nslabs; | |
ff7204a7 AD |
353 | io_tlb_start = virt_to_phys(tlb); |
354 | io_tlb_end = io_tlb_start + bytes; | |
74838b75 | 355 | |
c7753208 | 356 | swiotlb_set_mem_attributes(tlb, bytes); |
ff7204a7 | 357 | memset(tlb, 0, bytes); |
0b9afede | 358 | |
ee3f6ba8 AD |
359 | /* |
360 | * Get the overflow emergency buffer | |
361 | */ | |
362 | v_overflow_buffer = (void *)__get_free_pages(GFP_DMA, | |
363 | get_order(io_tlb_overflow)); | |
364 | if (!v_overflow_buffer) | |
365 | goto cleanup2; | |
366 | ||
c7753208 TL |
367 | swiotlb_set_mem_attributes(v_overflow_buffer, io_tlb_overflow); |
368 | memset(v_overflow_buffer, 0, io_tlb_overflow); | |
ee3f6ba8 AD |
369 | io_tlb_overflow_buffer = virt_to_phys(v_overflow_buffer); |
370 | ||
0b9afede AW |
371 | /* |
372 | * Allocate and initialize the free list array. This array is used | |
373 | * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE | |
374 | * between io_tlb_start and io_tlb_end. | |
375 | */ | |
376 | io_tlb_list = (unsigned int *)__get_free_pages(GFP_KERNEL, | |
377 | get_order(io_tlb_nslabs * sizeof(int))); | |
378 | if (!io_tlb_list) | |
ee3f6ba8 | 379 | goto cleanup3; |
0b9afede | 380 | |
bc40ac66 BB |
381 | io_tlb_orig_addr = (phys_addr_t *) |
382 | __get_free_pages(GFP_KERNEL, | |
383 | get_order(io_tlb_nslabs * | |
384 | sizeof(phys_addr_t))); | |
0b9afede | 385 | if (!io_tlb_orig_addr) |
ee3f6ba8 | 386 | goto cleanup4; |
0b9afede | 387 | |
8e0629c1 JB |
388 | for (i = 0; i < io_tlb_nslabs; i++) { |
389 | io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE); | |
390 | io_tlb_orig_addr[i] = INVALID_PHYS_ADDR; | |
391 | } | |
392 | io_tlb_index = 0; | |
0b9afede | 393 | |
ad32e8cb | 394 | swiotlb_print_info(); |
0b9afede | 395 | |
5740afdb FT |
396 | late_alloc = 1; |
397 | ||
7453c549 KRW |
398 | swiotlb_set_max_segment(io_tlb_nslabs << IO_TLB_SHIFT); |
399 | ||
0b9afede AW |
400 | return 0; |
401 | ||
402 | cleanup4: | |
25667d67 TL |
403 | free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs * |
404 | sizeof(int))); | |
0b9afede | 405 | io_tlb_list = NULL; |
ee3f6ba8 AD |
406 | cleanup3: |
407 | free_pages((unsigned long)v_overflow_buffer, | |
408 | get_order(io_tlb_overflow)); | |
409 | io_tlb_overflow_buffer = 0; | |
0b9afede | 410 | cleanup2: |
c40dba06 | 411 | io_tlb_end = 0; |
ff7204a7 | 412 | io_tlb_start = 0; |
74838b75 | 413 | io_tlb_nslabs = 0; |
7453c549 | 414 | max_segment = 0; |
0b9afede AW |
415 | return -ENOMEM; |
416 | } | |
417 | ||
5740afdb FT |
418 | void __init swiotlb_free(void) |
419 | { | |
ee3f6ba8 | 420 | if (!io_tlb_orig_addr) |
5740afdb FT |
421 | return; |
422 | ||
423 | if (late_alloc) { | |
ee3f6ba8 | 424 | free_pages((unsigned long)phys_to_virt(io_tlb_overflow_buffer), |
5740afdb FT |
425 | get_order(io_tlb_overflow)); |
426 | free_pages((unsigned long)io_tlb_orig_addr, | |
427 | get_order(io_tlb_nslabs * sizeof(phys_addr_t))); | |
428 | free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs * | |
429 | sizeof(int))); | |
ff7204a7 | 430 | free_pages((unsigned long)phys_to_virt(io_tlb_start), |
5740afdb FT |
431 | get_order(io_tlb_nslabs << IO_TLB_SHIFT)); |
432 | } else { | |
457ff1de SS |
433 | memblock_free_late(io_tlb_overflow_buffer, |
434 | PAGE_ALIGN(io_tlb_overflow)); | |
435 | memblock_free_late(__pa(io_tlb_orig_addr), | |
436 | PAGE_ALIGN(io_tlb_nslabs * sizeof(phys_addr_t))); | |
437 | memblock_free_late(__pa(io_tlb_list), | |
438 | PAGE_ALIGN(io_tlb_nslabs * sizeof(int))); | |
439 | memblock_free_late(io_tlb_start, | |
440 | PAGE_ALIGN(io_tlb_nslabs << IO_TLB_SHIFT)); | |
5740afdb | 441 | } |
f21ffe9f | 442 | io_tlb_nslabs = 0; |
7453c549 | 443 | max_segment = 0; |
5740afdb FT |
444 | } |
445 | ||
9c5a3621 | 446 | int is_swiotlb_buffer(phys_addr_t paddr) |
640aebfe | 447 | { |
ff7204a7 | 448 | return paddr >= io_tlb_start && paddr < io_tlb_end; |
640aebfe FT |
449 | } |
450 | ||
fb05a379 BB |
451 | /* |
452 | * Bounce: copy the swiotlb buffer back to the original dma location | |
453 | */ | |
af51a9f1 AD |
454 | static void swiotlb_bounce(phys_addr_t orig_addr, phys_addr_t tlb_addr, |
455 | size_t size, enum dma_data_direction dir) | |
fb05a379 | 456 | { |
af51a9f1 AD |
457 | unsigned long pfn = PFN_DOWN(orig_addr); |
458 | unsigned char *vaddr = phys_to_virt(tlb_addr); | |
fb05a379 BB |
459 | |
460 | if (PageHighMem(pfn_to_page(pfn))) { | |
461 | /* The buffer does not have a mapping. Map it in and copy */ | |
af51a9f1 | 462 | unsigned int offset = orig_addr & ~PAGE_MASK; |
fb05a379 BB |
463 | char *buffer; |
464 | unsigned int sz = 0; | |
465 | unsigned long flags; | |
466 | ||
467 | while (size) { | |
67131ad0 | 468 | sz = min_t(size_t, PAGE_SIZE - offset, size); |
fb05a379 BB |
469 | |
470 | local_irq_save(flags); | |
c3eede8e | 471 | buffer = kmap_atomic(pfn_to_page(pfn)); |
fb05a379 | 472 | if (dir == DMA_TO_DEVICE) |
af51a9f1 | 473 | memcpy(vaddr, buffer + offset, sz); |
ef9b1893 | 474 | else |
af51a9f1 | 475 | memcpy(buffer + offset, vaddr, sz); |
c3eede8e | 476 | kunmap_atomic(buffer); |
ef9b1893 | 477 | local_irq_restore(flags); |
fb05a379 BB |
478 | |
479 | size -= sz; | |
480 | pfn++; | |
af51a9f1 | 481 | vaddr += sz; |
fb05a379 | 482 | offset = 0; |
ef9b1893 | 483 | } |
af51a9f1 AD |
484 | } else if (dir == DMA_TO_DEVICE) { |
485 | memcpy(vaddr, phys_to_virt(orig_addr), size); | |
ef9b1893 | 486 | } else { |
af51a9f1 | 487 | memcpy(phys_to_virt(orig_addr), vaddr, size); |
ef9b1893 | 488 | } |
1b548f66 JF |
489 | } |
490 | ||
e05ed4d1 AD |
491 | phys_addr_t swiotlb_tbl_map_single(struct device *hwdev, |
492 | dma_addr_t tbl_dma_addr, | |
493 | phys_addr_t orig_addr, size_t size, | |
0443fa00 AD |
494 | enum dma_data_direction dir, |
495 | unsigned long attrs) | |
1da177e4 LT |
496 | { |
497 | unsigned long flags; | |
e05ed4d1 | 498 | phys_addr_t tlb_addr; |
1da177e4 LT |
499 | unsigned int nslots, stride, index, wrap; |
500 | int i; | |
681cc5cd FT |
501 | unsigned long mask; |
502 | unsigned long offset_slots; | |
503 | unsigned long max_slots; | |
504 | ||
ac2cbab2 YL |
505 | if (no_iotlb_memory) |
506 | panic("Can not allocate SWIOTLB buffer earlier and can't now provide you with the DMA bounce buffer"); | |
507 | ||
648babb7 TL |
508 | if (sme_active()) |
509 | pr_warn_once("SME is active and system is using DMA bounce buffers\n"); | |
510 | ||
681cc5cd | 511 | mask = dma_get_seg_boundary(hwdev); |
681cc5cd | 512 | |
eb605a57 FT |
513 | tbl_dma_addr &= mask; |
514 | ||
515 | offset_slots = ALIGN(tbl_dma_addr, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
a5ddde4a IC |
516 | |
517 | /* | |
518 | * Carefully handle integer overflow which can occur when mask == ~0UL. | |
519 | */ | |
b15a3891 JB |
520 | max_slots = mask + 1 |
521 | ? ALIGN(mask + 1, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT | |
522 | : 1UL << (BITS_PER_LONG - IO_TLB_SHIFT); | |
1da177e4 LT |
523 | |
524 | /* | |
602d9858 NY |
525 | * For mappings greater than or equal to a page, we limit the stride |
526 | * (and hence alignment) to a page size. | |
1da177e4 LT |
527 | */ |
528 | nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
602d9858 | 529 | if (size >= PAGE_SIZE) |
1da177e4 LT |
530 | stride = (1 << (PAGE_SHIFT - IO_TLB_SHIFT)); |
531 | else | |
532 | stride = 1; | |
533 | ||
34814545 | 534 | BUG_ON(!nslots); |
1da177e4 LT |
535 | |
536 | /* | |
537 | * Find suitable number of IO TLB entries size that will fit this | |
538 | * request and allocate a buffer from that IO TLB pool. | |
539 | */ | |
540 | spin_lock_irqsave(&io_tlb_lock, flags); | |
a7133a15 AM |
541 | index = ALIGN(io_tlb_index, stride); |
542 | if (index >= io_tlb_nslabs) | |
543 | index = 0; | |
544 | wrap = index; | |
545 | ||
546 | do { | |
a8522509 FT |
547 | while (iommu_is_span_boundary(index, nslots, offset_slots, |
548 | max_slots)) { | |
b15a3891 JB |
549 | index += stride; |
550 | if (index >= io_tlb_nslabs) | |
551 | index = 0; | |
a7133a15 AM |
552 | if (index == wrap) |
553 | goto not_found; | |
554 | } | |
555 | ||
556 | /* | |
557 | * If we find a slot that indicates we have 'nslots' number of | |
558 | * contiguous buffers, we allocate the buffers from that slot | |
559 | * and mark the entries as '0' indicating unavailable. | |
560 | */ | |
561 | if (io_tlb_list[index] >= nslots) { | |
562 | int count = 0; | |
563 | ||
564 | for (i = index; i < (int) (index + nslots); i++) | |
565 | io_tlb_list[i] = 0; | |
566 | for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE - 1) && io_tlb_list[i]; i--) | |
567 | io_tlb_list[i] = ++count; | |
e05ed4d1 | 568 | tlb_addr = io_tlb_start + (index << IO_TLB_SHIFT); |
1da177e4 | 569 | |
a7133a15 AM |
570 | /* |
571 | * Update the indices to avoid searching in the next | |
572 | * round. | |
573 | */ | |
574 | io_tlb_index = ((index + nslots) < io_tlb_nslabs | |
575 | ? (index + nslots) : 0); | |
576 | ||
577 | goto found; | |
578 | } | |
579 | index += stride; | |
580 | if (index >= io_tlb_nslabs) | |
581 | index = 0; | |
582 | } while (index != wrap); | |
583 | ||
584 | not_found: | |
585 | spin_unlock_irqrestore(&io_tlb_lock, flags); | |
37efa60e | 586 | if (!(attrs & DMA_ATTR_NO_WARN) && printk_ratelimit()) |
0cb637bf | 587 | dev_warn(hwdev, "swiotlb buffer is full (sz: %zd bytes)\n", size); |
e05ed4d1 | 588 | return SWIOTLB_MAP_ERROR; |
a7133a15 | 589 | found: |
1da177e4 LT |
590 | spin_unlock_irqrestore(&io_tlb_lock, flags); |
591 | ||
592 | /* | |
593 | * Save away the mapping from the original address to the DMA address. | |
594 | * This is needed when we sync the memory. Then we sync the buffer if | |
595 | * needed. | |
596 | */ | |
bc40ac66 | 597 | for (i = 0; i < nslots; i++) |
e05ed4d1 | 598 | io_tlb_orig_addr[index+i] = orig_addr + (i << IO_TLB_SHIFT); |
0443fa00 AD |
599 | if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC) && |
600 | (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
af51a9f1 | 601 | swiotlb_bounce(orig_addr, tlb_addr, size, DMA_TO_DEVICE); |
1da177e4 | 602 | |
e05ed4d1 | 603 | return tlb_addr; |
1da177e4 | 604 | } |
d7ef1533 | 605 | EXPORT_SYMBOL_GPL(swiotlb_tbl_map_single); |
1da177e4 | 606 | |
eb605a57 FT |
607 | /* |
608 | * Allocates bounce buffer and returns its kernel virtual address. | |
609 | */ | |
610 | ||
023600f1 AC |
611 | static phys_addr_t |
612 | map_single(struct device *hwdev, phys_addr_t phys, size_t size, | |
0443fa00 | 613 | enum dma_data_direction dir, unsigned long attrs) |
eb605a57 | 614 | { |
fff5d992 GU |
615 | dma_addr_t start_dma_addr; |
616 | ||
617 | if (swiotlb_force == SWIOTLB_NO_FORCE) { | |
618 | dev_warn_ratelimited(hwdev, "Cannot do DMA to address %pa\n", | |
619 | &phys); | |
620 | return SWIOTLB_MAP_ERROR; | |
621 | } | |
eb605a57 | 622 | |
c7753208 | 623 | start_dma_addr = swiotlb_phys_to_dma(hwdev, io_tlb_start); |
0443fa00 AD |
624 | return swiotlb_tbl_map_single(hwdev, start_dma_addr, phys, size, |
625 | dir, attrs); | |
eb605a57 FT |
626 | } |
627 | ||
1da177e4 LT |
628 | /* |
629 | * dma_addr is the kernel virtual address of the bounce buffer to unmap. | |
630 | */ | |
61ca08c3 | 631 | void swiotlb_tbl_unmap_single(struct device *hwdev, phys_addr_t tlb_addr, |
0443fa00 AD |
632 | size_t size, enum dma_data_direction dir, |
633 | unsigned long attrs) | |
1da177e4 LT |
634 | { |
635 | unsigned long flags; | |
636 | int i, count, nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
61ca08c3 AD |
637 | int index = (tlb_addr - io_tlb_start) >> IO_TLB_SHIFT; |
638 | phys_addr_t orig_addr = io_tlb_orig_addr[index]; | |
1da177e4 LT |
639 | |
640 | /* | |
641 | * First, sync the memory before unmapping the entry | |
642 | */ | |
8e0629c1 | 643 | if (orig_addr != INVALID_PHYS_ADDR && |
0443fa00 | 644 | !(attrs & DMA_ATTR_SKIP_CPU_SYNC) && |
8e0629c1 | 645 | ((dir == DMA_FROM_DEVICE) || (dir == DMA_BIDIRECTIONAL))) |
af51a9f1 | 646 | swiotlb_bounce(orig_addr, tlb_addr, size, DMA_FROM_DEVICE); |
1da177e4 LT |
647 | |
648 | /* | |
649 | * Return the buffer to the free list by setting the corresponding | |
af901ca1 | 650 | * entries to indicate the number of contiguous entries available. |
1da177e4 LT |
651 | * While returning the entries to the free list, we merge the entries |
652 | * with slots below and above the pool being returned. | |
653 | */ | |
654 | spin_lock_irqsave(&io_tlb_lock, flags); | |
655 | { | |
656 | count = ((index + nslots) < ALIGN(index + 1, IO_TLB_SEGSIZE) ? | |
657 | io_tlb_list[index + nslots] : 0); | |
658 | /* | |
659 | * Step 1: return the slots to the free list, merging the | |
660 | * slots with superceeding slots | |
661 | */ | |
8e0629c1 | 662 | for (i = index + nslots - 1; i >= index; i--) { |
1da177e4 | 663 | io_tlb_list[i] = ++count; |
8e0629c1 JB |
664 | io_tlb_orig_addr[i] = INVALID_PHYS_ADDR; |
665 | } | |
1da177e4 LT |
666 | /* |
667 | * Step 2: merge the returned slots with the preceding slots, | |
668 | * if available (non zero) | |
669 | */ | |
670 | for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE -1) && io_tlb_list[i]; i--) | |
671 | io_tlb_list[i] = ++count; | |
672 | } | |
673 | spin_unlock_irqrestore(&io_tlb_lock, flags); | |
674 | } | |
d7ef1533 | 675 | EXPORT_SYMBOL_GPL(swiotlb_tbl_unmap_single); |
1da177e4 | 676 | |
fbfda893 AD |
677 | void swiotlb_tbl_sync_single(struct device *hwdev, phys_addr_t tlb_addr, |
678 | size_t size, enum dma_data_direction dir, | |
679 | enum dma_sync_target target) | |
1da177e4 | 680 | { |
fbfda893 AD |
681 | int index = (tlb_addr - io_tlb_start) >> IO_TLB_SHIFT; |
682 | phys_addr_t orig_addr = io_tlb_orig_addr[index]; | |
bc40ac66 | 683 | |
8e0629c1 JB |
684 | if (orig_addr == INVALID_PHYS_ADDR) |
685 | return; | |
fbfda893 | 686 | orig_addr += (unsigned long)tlb_addr & ((1 << IO_TLB_SHIFT) - 1); |
df336d1c | 687 | |
de69e0f0 JL |
688 | switch (target) { |
689 | case SYNC_FOR_CPU: | |
690 | if (likely(dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
af51a9f1 | 691 | swiotlb_bounce(orig_addr, tlb_addr, |
fbfda893 | 692 | size, DMA_FROM_DEVICE); |
34814545 ES |
693 | else |
694 | BUG_ON(dir != DMA_TO_DEVICE); | |
de69e0f0 JL |
695 | break; |
696 | case SYNC_FOR_DEVICE: | |
697 | if (likely(dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
af51a9f1 | 698 | swiotlb_bounce(orig_addr, tlb_addr, |
fbfda893 | 699 | size, DMA_TO_DEVICE); |
34814545 ES |
700 | else |
701 | BUG_ON(dir != DMA_FROM_DEVICE); | |
de69e0f0 JL |
702 | break; |
703 | default: | |
1da177e4 | 704 | BUG(); |
de69e0f0 | 705 | } |
1da177e4 | 706 | } |
d7ef1533 | 707 | EXPORT_SYMBOL_GPL(swiotlb_tbl_sync_single); |
1da177e4 LT |
708 | |
709 | void * | |
710 | swiotlb_alloc_coherent(struct device *hwdev, size_t size, | |
06a54497 | 711 | dma_addr_t *dma_handle, gfp_t flags) |
1da177e4 | 712 | { |
37efa60e | 713 | bool warn = !(flags & __GFP_NOWARN); |
563aaf06 | 714 | dma_addr_t dev_addr; |
1da177e4 LT |
715 | void *ret; |
716 | int order = get_order(size); | |
284901a9 | 717 | u64 dma_mask = DMA_BIT_MASK(32); |
1e74f300 FT |
718 | |
719 | if (hwdev && hwdev->coherent_dma_mask) | |
720 | dma_mask = hwdev->coherent_dma_mask; | |
1da177e4 | 721 | |
25667d67 | 722 | ret = (void *)__get_free_pages(flags, order); |
e05ed4d1 AD |
723 | if (ret) { |
724 | dev_addr = swiotlb_virt_to_bus(hwdev, ret); | |
725 | if (dev_addr + size - 1 > dma_mask) { | |
726 | /* | |
727 | * The allocated memory isn't reachable by the device. | |
728 | */ | |
729 | free_pages((unsigned long) ret, order); | |
730 | ret = NULL; | |
731 | } | |
1da177e4 LT |
732 | } |
733 | if (!ret) { | |
734 | /* | |
bfc5501f KRW |
735 | * We are either out of memory or the device can't DMA to |
736 | * GFP_DMA memory; fall back on map_single(), which | |
ceb5ac32 | 737 | * will grab memory from the lowest available address range. |
1da177e4 | 738 | */ |
37efa60e CK |
739 | phys_addr_t paddr = map_single(hwdev, 0, size, DMA_FROM_DEVICE, |
740 | warn ? 0 : DMA_ATTR_NO_WARN); | |
e05ed4d1 | 741 | if (paddr == SWIOTLB_MAP_ERROR) |
94cc81f9 | 742 | goto err_warn; |
1da177e4 | 743 | |
e05ed4d1 | 744 | ret = phys_to_virt(paddr); |
c7753208 | 745 | dev_addr = swiotlb_phys_to_dma(hwdev, paddr); |
1da177e4 | 746 | |
61ca08c3 AD |
747 | /* Confirm address can be DMA'd by device */ |
748 | if (dev_addr + size - 1 > dma_mask) { | |
749 | printk("hwdev DMA mask = 0x%016Lx, dev_addr = 0x%016Lx\n", | |
750 | (unsigned long long)dma_mask, | |
751 | (unsigned long long)dev_addr); | |
a2b89b59 | 752 | |
0443fa00 AD |
753 | /* |
754 | * DMA_TO_DEVICE to avoid memcpy in unmap_single. | |
755 | * The DMA_ATTR_SKIP_CPU_SYNC is optional. | |
756 | */ | |
61ca08c3 | 757 | swiotlb_tbl_unmap_single(hwdev, paddr, |
0443fa00 AD |
758 | size, DMA_TO_DEVICE, |
759 | DMA_ATTR_SKIP_CPU_SYNC); | |
94cc81f9 | 760 | goto err_warn; |
61ca08c3 | 761 | } |
1da177e4 | 762 | } |
e05ed4d1 | 763 | |
1da177e4 | 764 | *dma_handle = dev_addr; |
e05ed4d1 AD |
765 | memset(ret, 0, size); |
766 | ||
1da177e4 | 767 | return ret; |
94cc81f9 JR |
768 | |
769 | err_warn: | |
37efa60e | 770 | if (warn && printk_ratelimit()) { |
f2a4f762 | 771 | pr_warn("coherent allocation failed for device %s size=%zu\n", |
37efa60e CK |
772 | dev_name(hwdev), size); |
773 | dump_stack(); | |
774 | } | |
94cc81f9 JR |
775 | |
776 | return NULL; | |
1da177e4 | 777 | } |
874d6a95 | 778 | EXPORT_SYMBOL(swiotlb_alloc_coherent); |
1da177e4 LT |
779 | |
780 | void | |
781 | swiotlb_free_coherent(struct device *hwdev, size_t size, void *vaddr, | |
02ca646e | 782 | dma_addr_t dev_addr) |
1da177e4 | 783 | { |
862d196b | 784 | phys_addr_t paddr = dma_to_phys(hwdev, dev_addr); |
02ca646e | 785 | |
aa24886e | 786 | WARN_ON(irqs_disabled()); |
02ca646e FT |
787 | if (!is_swiotlb_buffer(paddr)) |
788 | free_pages((unsigned long)vaddr, get_order(size)); | |
1da177e4 | 789 | else |
0443fa00 AD |
790 | /* |
791 | * DMA_TO_DEVICE to avoid memcpy in swiotlb_tbl_unmap_single. | |
792 | * DMA_ATTR_SKIP_CPU_SYNC is optional. | |
793 | */ | |
794 | swiotlb_tbl_unmap_single(hwdev, paddr, size, DMA_TO_DEVICE, | |
795 | DMA_ATTR_SKIP_CPU_SYNC); | |
1da177e4 | 796 | } |
874d6a95 | 797 | EXPORT_SYMBOL(swiotlb_free_coherent); |
1da177e4 LT |
798 | |
799 | static void | |
22d48269 KRW |
800 | swiotlb_full(struct device *dev, size_t size, enum dma_data_direction dir, |
801 | int do_panic) | |
1da177e4 | 802 | { |
fff5d992 GU |
803 | if (swiotlb_force == SWIOTLB_NO_FORCE) |
804 | return; | |
805 | ||
1da177e4 LT |
806 | /* |
807 | * Ran out of IOMMU space for this operation. This is very bad. | |
808 | * Unfortunately the drivers cannot handle this operation properly. | |
17e5ad6c | 809 | * unless they check for dma_mapping_error (most don't) |
1da177e4 LT |
810 | * When the mapping is small enough return a static buffer to limit |
811 | * the damage, or panic when the transfer is too big. | |
812 | */ | |
0d2e1898 GU |
813 | dev_err_ratelimited(dev, "DMA: Out of SW-IOMMU space for %zu bytes\n", |
814 | size); | |
1da177e4 | 815 | |
c7084b35 CD |
816 | if (size <= io_tlb_overflow || !do_panic) |
817 | return; | |
818 | ||
819 | if (dir == DMA_BIDIRECTIONAL) | |
820 | panic("DMA: Random memory could be DMA accessed\n"); | |
821 | if (dir == DMA_FROM_DEVICE) | |
822 | panic("DMA: Random memory could be DMA written\n"); | |
823 | if (dir == DMA_TO_DEVICE) | |
824 | panic("DMA: Random memory could be DMA read\n"); | |
1da177e4 LT |
825 | } |
826 | ||
827 | /* | |
828 | * Map a single buffer of the indicated size for DMA in streaming mode. The | |
17e5ad6c | 829 | * physical address to use is returned. |
1da177e4 LT |
830 | * |
831 | * Once the device is given the dma address, the device owns this memory until | |
ceb5ac32 | 832 | * either swiotlb_unmap_page or swiotlb_dma_sync_single is performed. |
1da177e4 | 833 | */ |
f98eee8e FT |
834 | dma_addr_t swiotlb_map_page(struct device *dev, struct page *page, |
835 | unsigned long offset, size_t size, | |
836 | enum dma_data_direction dir, | |
00085f1e | 837 | unsigned long attrs) |
1da177e4 | 838 | { |
e05ed4d1 | 839 | phys_addr_t map, phys = page_to_phys(page) + offset; |
862d196b | 840 | dma_addr_t dev_addr = phys_to_dma(dev, phys); |
1da177e4 | 841 | |
34814545 | 842 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 843 | /* |
ceb5ac32 | 844 | * If the address happens to be in the device's DMA window, |
1da177e4 LT |
845 | * we can safely return the device addr and not worry about bounce |
846 | * buffering it. | |
847 | */ | |
ae7871be | 848 | if (dma_capable(dev, dev_addr, size) && swiotlb_force != SWIOTLB_FORCE) |
1da177e4 LT |
849 | return dev_addr; |
850 | ||
2b2b614d ZK |
851 | trace_swiotlb_bounced(dev, dev_addr, size, swiotlb_force); |
852 | ||
e05ed4d1 | 853 | /* Oh well, have to allocate and map a bounce buffer. */ |
0443fa00 | 854 | map = map_single(dev, phys, size, dir, attrs); |
e05ed4d1 | 855 | if (map == SWIOTLB_MAP_ERROR) { |
f98eee8e | 856 | swiotlb_full(dev, size, dir, 1); |
c7753208 | 857 | return swiotlb_phys_to_dma(dev, io_tlb_overflow_buffer); |
1da177e4 LT |
858 | } |
859 | ||
c7753208 | 860 | dev_addr = swiotlb_phys_to_dma(dev, map); |
1da177e4 | 861 | |
e05ed4d1 | 862 | /* Ensure that the address returned is DMA'ble */ |
0443fa00 AD |
863 | if (dma_capable(dev, dev_addr, size)) |
864 | return dev_addr; | |
865 | ||
d29fa0cb AD |
866 | attrs |= DMA_ATTR_SKIP_CPU_SYNC; |
867 | swiotlb_tbl_unmap_single(dev, map, size, dir, attrs); | |
1da177e4 | 868 | |
c7753208 | 869 | return swiotlb_phys_to_dma(dev, io_tlb_overflow_buffer); |
1da177e4 | 870 | } |
f98eee8e | 871 | EXPORT_SYMBOL_GPL(swiotlb_map_page); |
1da177e4 | 872 | |
1da177e4 LT |
873 | /* |
874 | * Unmap a single streaming mode DMA translation. The dma_addr and size must | |
ceb5ac32 | 875 | * match what was provided for in a previous swiotlb_map_page call. All |
1da177e4 LT |
876 | * other usages are undefined. |
877 | * | |
878 | * After this call, reads by the cpu to the buffer are guaranteed to see | |
879 | * whatever the device wrote there. | |
880 | */ | |
7fcebbd2 | 881 | static void unmap_single(struct device *hwdev, dma_addr_t dev_addr, |
0443fa00 AD |
882 | size_t size, enum dma_data_direction dir, |
883 | unsigned long attrs) | |
1da177e4 | 884 | { |
862d196b | 885 | phys_addr_t paddr = dma_to_phys(hwdev, dev_addr); |
1da177e4 | 886 | |
34814545 | 887 | BUG_ON(dir == DMA_NONE); |
7fcebbd2 | 888 | |
02ca646e | 889 | if (is_swiotlb_buffer(paddr)) { |
0443fa00 | 890 | swiotlb_tbl_unmap_single(hwdev, paddr, size, dir, attrs); |
7fcebbd2 BB |
891 | return; |
892 | } | |
893 | ||
894 | if (dir != DMA_FROM_DEVICE) | |
895 | return; | |
896 | ||
02ca646e FT |
897 | /* |
898 | * phys_to_virt doesn't work with hihgmem page but we could | |
899 | * call dma_mark_clean() with hihgmem page here. However, we | |
900 | * are fine since dma_mark_clean() is null on POWERPC. We can | |
901 | * make dma_mark_clean() take a physical address if necessary. | |
902 | */ | |
903 | dma_mark_clean(phys_to_virt(paddr), size); | |
7fcebbd2 BB |
904 | } |
905 | ||
906 | void swiotlb_unmap_page(struct device *hwdev, dma_addr_t dev_addr, | |
907 | size_t size, enum dma_data_direction dir, | |
00085f1e | 908 | unsigned long attrs) |
7fcebbd2 | 909 | { |
0443fa00 | 910 | unmap_single(hwdev, dev_addr, size, dir, attrs); |
1da177e4 | 911 | } |
f98eee8e | 912 | EXPORT_SYMBOL_GPL(swiotlb_unmap_page); |
874d6a95 | 913 | |
1da177e4 LT |
914 | /* |
915 | * Make physical memory consistent for a single streaming mode DMA translation | |
916 | * after a transfer. | |
917 | * | |
ceb5ac32 | 918 | * If you perform a swiotlb_map_page() but wish to interrogate the buffer |
17e5ad6c TL |
919 | * using the cpu, yet do not wish to teardown the dma mapping, you must |
920 | * call this function before doing so. At the next point you give the dma | |
1da177e4 LT |
921 | * address back to the card, you must first perform a |
922 | * swiotlb_dma_sync_for_device, and then the device again owns the buffer | |
923 | */ | |
be6b0267 | 924 | static void |
8270f3f1 | 925 | swiotlb_sync_single(struct device *hwdev, dma_addr_t dev_addr, |
d7ef1533 KRW |
926 | size_t size, enum dma_data_direction dir, |
927 | enum dma_sync_target target) | |
1da177e4 | 928 | { |
862d196b | 929 | phys_addr_t paddr = dma_to_phys(hwdev, dev_addr); |
1da177e4 | 930 | |
34814545 | 931 | BUG_ON(dir == DMA_NONE); |
380d6878 | 932 | |
02ca646e | 933 | if (is_swiotlb_buffer(paddr)) { |
fbfda893 | 934 | swiotlb_tbl_sync_single(hwdev, paddr, size, dir, target); |
380d6878 BB |
935 | return; |
936 | } | |
937 | ||
938 | if (dir != DMA_FROM_DEVICE) | |
939 | return; | |
940 | ||
02ca646e | 941 | dma_mark_clean(phys_to_virt(paddr), size); |
1da177e4 LT |
942 | } |
943 | ||
8270f3f1 JL |
944 | void |
945 | swiotlb_sync_single_for_cpu(struct device *hwdev, dma_addr_t dev_addr, | |
160c1d8e | 946 | size_t size, enum dma_data_direction dir) |
8270f3f1 | 947 | { |
de69e0f0 | 948 | swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_CPU); |
8270f3f1 | 949 | } |
874d6a95 | 950 | EXPORT_SYMBOL(swiotlb_sync_single_for_cpu); |
8270f3f1 | 951 | |
1da177e4 LT |
952 | void |
953 | swiotlb_sync_single_for_device(struct device *hwdev, dma_addr_t dev_addr, | |
160c1d8e | 954 | size_t size, enum dma_data_direction dir) |
1da177e4 | 955 | { |
de69e0f0 | 956 | swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_DEVICE); |
1da177e4 | 957 | } |
874d6a95 | 958 | EXPORT_SYMBOL(swiotlb_sync_single_for_device); |
1da177e4 LT |
959 | |
960 | /* | |
961 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
ceb5ac32 | 962 | * This is the scatter-gather version of the above swiotlb_map_page |
1da177e4 LT |
963 | * interface. Here the scatter gather list elements are each tagged with the |
964 | * appropriate dma address and length. They are obtained via | |
965 | * sg_dma_{address,length}(SG). | |
966 | * | |
967 | * NOTE: An implementation may be able to use a smaller number of | |
968 | * DMA address/length pairs than there are SG table elements. | |
969 | * (for example via virtual mapping capabilities) | |
970 | * The routine returns the number of addr/length pairs actually | |
971 | * used, at most nents. | |
972 | * | |
ceb5ac32 | 973 | * Device ownership issues as mentioned above for swiotlb_map_page are the |
1da177e4 LT |
974 | * same here. |
975 | */ | |
976 | int | |
309df0c5 | 977 | swiotlb_map_sg_attrs(struct device *hwdev, struct scatterlist *sgl, int nelems, |
00085f1e | 978 | enum dma_data_direction dir, unsigned long attrs) |
1da177e4 | 979 | { |
dbfd49fe | 980 | struct scatterlist *sg; |
1da177e4 LT |
981 | int i; |
982 | ||
34814545 | 983 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 984 | |
dbfd49fe | 985 | for_each_sg(sgl, sg, nelems, i) { |
961d7d0e | 986 | phys_addr_t paddr = sg_phys(sg); |
862d196b | 987 | dma_addr_t dev_addr = phys_to_dma(hwdev, paddr); |
bc40ac66 | 988 | |
ae7871be | 989 | if (swiotlb_force == SWIOTLB_FORCE || |
b9394647 | 990 | !dma_capable(hwdev, dev_addr, sg->length)) { |
e05ed4d1 | 991 | phys_addr_t map = map_single(hwdev, sg_phys(sg), |
0443fa00 | 992 | sg->length, dir, attrs); |
e05ed4d1 | 993 | if (map == SWIOTLB_MAP_ERROR) { |
1da177e4 LT |
994 | /* Don't panic here, we expect map_sg users |
995 | to do proper error handling. */ | |
996 | swiotlb_full(hwdev, sg->length, dir, 0); | |
d29fa0cb | 997 | attrs |= DMA_ATTR_SKIP_CPU_SYNC; |
309df0c5 AK |
998 | swiotlb_unmap_sg_attrs(hwdev, sgl, i, dir, |
999 | attrs); | |
4d86ec7a | 1000 | sg_dma_len(sgl) = 0; |
1da177e4 LT |
1001 | return 0; |
1002 | } | |
c7753208 | 1003 | sg->dma_address = swiotlb_phys_to_dma(hwdev, map); |
1da177e4 LT |
1004 | } else |
1005 | sg->dma_address = dev_addr; | |
4d86ec7a | 1006 | sg_dma_len(sg) = sg->length; |
1da177e4 LT |
1007 | } |
1008 | return nelems; | |
1009 | } | |
309df0c5 AK |
1010 | EXPORT_SYMBOL(swiotlb_map_sg_attrs); |
1011 | ||
1da177e4 LT |
1012 | /* |
1013 | * Unmap a set of streaming mode DMA translations. Again, cpu read rules | |
ceb5ac32 | 1014 | * concerning calls here are the same as for swiotlb_unmap_page() above. |
1da177e4 LT |
1015 | */ |
1016 | void | |
309df0c5 | 1017 | swiotlb_unmap_sg_attrs(struct device *hwdev, struct scatterlist *sgl, |
00085f1e KK |
1018 | int nelems, enum dma_data_direction dir, |
1019 | unsigned long attrs) | |
1da177e4 | 1020 | { |
dbfd49fe | 1021 | struct scatterlist *sg; |
1da177e4 LT |
1022 | int i; |
1023 | ||
34814545 | 1024 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 1025 | |
7fcebbd2 | 1026 | for_each_sg(sgl, sg, nelems, i) |
0443fa00 AD |
1027 | unmap_single(hwdev, sg->dma_address, sg_dma_len(sg), dir, |
1028 | attrs); | |
1da177e4 | 1029 | } |
309df0c5 AK |
1030 | EXPORT_SYMBOL(swiotlb_unmap_sg_attrs); |
1031 | ||
1da177e4 LT |
1032 | /* |
1033 | * Make physical memory consistent for a set of streaming mode DMA translations | |
1034 | * after a transfer. | |
1035 | * | |
1036 | * The same as swiotlb_sync_single_* but for a scatter-gather list, same rules | |
1037 | * and usage. | |
1038 | */ | |
be6b0267 | 1039 | static void |
dbfd49fe | 1040 | swiotlb_sync_sg(struct device *hwdev, struct scatterlist *sgl, |
d7ef1533 KRW |
1041 | int nelems, enum dma_data_direction dir, |
1042 | enum dma_sync_target target) | |
1da177e4 | 1043 | { |
dbfd49fe | 1044 | struct scatterlist *sg; |
1da177e4 LT |
1045 | int i; |
1046 | ||
380d6878 BB |
1047 | for_each_sg(sgl, sg, nelems, i) |
1048 | swiotlb_sync_single(hwdev, sg->dma_address, | |
4d86ec7a | 1049 | sg_dma_len(sg), dir, target); |
1da177e4 LT |
1050 | } |
1051 | ||
8270f3f1 JL |
1052 | void |
1053 | swiotlb_sync_sg_for_cpu(struct device *hwdev, struct scatterlist *sg, | |
160c1d8e | 1054 | int nelems, enum dma_data_direction dir) |
8270f3f1 | 1055 | { |
de69e0f0 | 1056 | swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_CPU); |
8270f3f1 | 1057 | } |
874d6a95 | 1058 | EXPORT_SYMBOL(swiotlb_sync_sg_for_cpu); |
8270f3f1 | 1059 | |
1da177e4 LT |
1060 | void |
1061 | swiotlb_sync_sg_for_device(struct device *hwdev, struct scatterlist *sg, | |
160c1d8e | 1062 | int nelems, enum dma_data_direction dir) |
1da177e4 | 1063 | { |
de69e0f0 | 1064 | swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_DEVICE); |
1da177e4 | 1065 | } |
874d6a95 | 1066 | EXPORT_SYMBOL(swiotlb_sync_sg_for_device); |
1da177e4 LT |
1067 | |
1068 | int | |
8d8bb39b | 1069 | swiotlb_dma_mapping_error(struct device *hwdev, dma_addr_t dma_addr) |
1da177e4 | 1070 | { |
c7753208 | 1071 | return (dma_addr == swiotlb_phys_to_dma(hwdev, io_tlb_overflow_buffer)); |
1da177e4 | 1072 | } |
874d6a95 | 1073 | EXPORT_SYMBOL(swiotlb_dma_mapping_error); |
1da177e4 LT |
1074 | |
1075 | /* | |
17e5ad6c | 1076 | * Return whether the given device DMA address mask can be supported |
1da177e4 | 1077 | * properly. For example, if your device can only drive the low 24-bits |
17e5ad6c | 1078 | * during bus mastering, then you would pass 0x00ffffff as the mask to |
1da177e4 LT |
1079 | * this function. |
1080 | */ | |
1081 | int | |
563aaf06 | 1082 | swiotlb_dma_supported(struct device *hwdev, u64 mask) |
1da177e4 | 1083 | { |
c7753208 | 1084 | return swiotlb_phys_to_dma(hwdev, io_tlb_end - 1) <= mask; |
1da177e4 | 1085 | } |
1da177e4 | 1086 | EXPORT_SYMBOL(swiotlb_dma_supported); |