Commit | Line | Data |
---|---|---|
dd87eb3a TG |
1 | /* |
2 | * linux/kernel/irq/chip.c | |
3 | * | |
4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | |
5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | |
6 | * | |
7 | * This file contains the core interrupt handling code, for irq-chip | |
8 | * based architectures. | |
9 | * | |
10 | * Detailed information is available in Documentation/DocBook/genericirq | |
11 | */ | |
12 | ||
13 | #include <linux/irq.h> | |
7fe3730d | 14 | #include <linux/msi.h> |
dd87eb3a TG |
15 | #include <linux/module.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/kernel_stat.h> | |
18 | ||
19 | #include "internals.h" | |
20 | ||
3a16d713 EB |
21 | /** |
22 | * dynamic_irq_init - initialize a dynamically allocated irq | |
23 | * @irq: irq number to initialize | |
24 | */ | |
25 | void dynamic_irq_init(unsigned int irq) | |
26 | { | |
27 | struct irq_desc *desc; | |
28 | unsigned long flags; | |
29 | ||
85c0f909 | 30 | if (irq >= nr_irqs) { |
261c40c1 | 31 | WARN(1, KERN_ERR "Trying to initialize invalid IRQ%d\n", irq); |
3a16d713 EB |
32 | return; |
33 | } | |
34 | ||
35 | /* Ensure we don't have left over values from a previous use of this irq */ | |
36 | desc = irq_desc + irq; | |
37 | spin_lock_irqsave(&desc->lock, flags); | |
38 | desc->status = IRQ_DISABLED; | |
39 | desc->chip = &no_irq_chip; | |
40 | desc->handle_irq = handle_bad_irq; | |
41 | desc->depth = 1; | |
5b912c10 | 42 | desc->msi_desc = NULL; |
3a16d713 EB |
43 | desc->handler_data = NULL; |
44 | desc->chip_data = NULL; | |
45 | desc->action = NULL; | |
46 | desc->irq_count = 0; | |
47 | desc->irqs_unhandled = 0; | |
48 | #ifdef CONFIG_SMP | |
d366f8cb | 49 | cpus_setall(desc->affinity); |
3a16d713 EB |
50 | #endif |
51 | spin_unlock_irqrestore(&desc->lock, flags); | |
52 | } | |
53 | ||
54 | /** | |
55 | * dynamic_irq_cleanup - cleanup a dynamically allocated irq | |
56 | * @irq: irq number to initialize | |
57 | */ | |
58 | void dynamic_irq_cleanup(unsigned int irq) | |
59 | { | |
60 | struct irq_desc *desc; | |
61 | unsigned long flags; | |
62 | ||
85c0f909 | 63 | if (irq >= nr_irqs) { |
261c40c1 | 64 | WARN(1, KERN_ERR "Trying to cleanup invalid IRQ%d\n", irq); |
3a16d713 EB |
65 | return; |
66 | } | |
67 | ||
68 | desc = irq_desc + irq; | |
69 | spin_lock_irqsave(&desc->lock, flags); | |
1f80025e EB |
70 | if (desc->action) { |
71 | spin_unlock_irqrestore(&desc->lock, flags); | |
261c40c1 | 72 | WARN(1, KERN_ERR "Destroying IRQ%d without calling free_irq\n", |
1f80025e | 73 | irq); |
1f80025e EB |
74 | return; |
75 | } | |
5b912c10 EB |
76 | desc->msi_desc = NULL; |
77 | desc->handler_data = NULL; | |
78 | desc->chip_data = NULL; | |
3a16d713 EB |
79 | desc->handle_irq = handle_bad_irq; |
80 | desc->chip = &no_irq_chip; | |
81 | spin_unlock_irqrestore(&desc->lock, flags); | |
82 | } | |
83 | ||
84 | ||
dd87eb3a TG |
85 | /** |
86 | * set_irq_chip - set the irq chip for an irq | |
87 | * @irq: irq number | |
88 | * @chip: pointer to irq chip description structure | |
89 | */ | |
90 | int set_irq_chip(unsigned int irq, struct irq_chip *chip) | |
91 | { | |
92 | struct irq_desc *desc; | |
93 | unsigned long flags; | |
94 | ||
85c0f909 | 95 | if (irq >= nr_irqs) { |
261c40c1 | 96 | WARN(1, KERN_ERR "Trying to install chip for IRQ%d\n", irq); |
dd87eb3a TG |
97 | return -EINVAL; |
98 | } | |
99 | ||
100 | if (!chip) | |
101 | chip = &no_irq_chip; | |
102 | ||
103 | desc = irq_desc + irq; | |
104 | spin_lock_irqsave(&desc->lock, flags); | |
105 | irq_chip_set_defaults(chip); | |
106 | desc->chip = chip; | |
dd87eb3a TG |
107 | spin_unlock_irqrestore(&desc->lock, flags); |
108 | ||
109 | return 0; | |
110 | } | |
111 | EXPORT_SYMBOL(set_irq_chip); | |
112 | ||
113 | /** | |
0c5d1eb7 | 114 | * set_irq_type - set the irq trigger type for an irq |
dd87eb3a | 115 | * @irq: irq number |
0c5d1eb7 | 116 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
dd87eb3a TG |
117 | */ |
118 | int set_irq_type(unsigned int irq, unsigned int type) | |
119 | { | |
120 | struct irq_desc *desc; | |
121 | unsigned long flags; | |
122 | int ret = -ENXIO; | |
123 | ||
85c0f909 | 124 | if (irq >= nr_irqs) { |
dd87eb3a TG |
125 | printk(KERN_ERR "Trying to set irq type for IRQ%d\n", irq); |
126 | return -ENODEV; | |
127 | } | |
128 | ||
129 | desc = irq_desc + irq; | |
0c5d1eb7 DB |
130 | if (type == IRQ_TYPE_NONE) |
131 | return 0; | |
132 | ||
133 | spin_lock_irqsave(&desc->lock, flags); | |
134 | ret = __irq_set_trigger(desc, irq, flags); | |
135 | spin_unlock_irqrestore(&desc->lock, flags); | |
dd87eb3a TG |
136 | return ret; |
137 | } | |
138 | EXPORT_SYMBOL(set_irq_type); | |
139 | ||
140 | /** | |
141 | * set_irq_data - set irq type data for an irq | |
142 | * @irq: Interrupt number | |
143 | * @data: Pointer to interrupt specific data | |
144 | * | |
145 | * Set the hardware irq controller data for an irq | |
146 | */ | |
147 | int set_irq_data(unsigned int irq, void *data) | |
148 | { | |
149 | struct irq_desc *desc; | |
150 | unsigned long flags; | |
151 | ||
85c0f909 | 152 | if (irq >= nr_irqs) { |
dd87eb3a TG |
153 | printk(KERN_ERR |
154 | "Trying to install controller data for IRQ%d\n", irq); | |
155 | return -EINVAL; | |
156 | } | |
157 | ||
158 | desc = irq_desc + irq; | |
159 | spin_lock_irqsave(&desc->lock, flags); | |
160 | desc->handler_data = data; | |
161 | spin_unlock_irqrestore(&desc->lock, flags); | |
162 | return 0; | |
163 | } | |
164 | EXPORT_SYMBOL(set_irq_data); | |
165 | ||
5b912c10 EB |
166 | /** |
167 | * set_irq_data - set irq type data for an irq | |
168 | * @irq: Interrupt number | |
472900b8 | 169 | * @entry: Pointer to MSI descriptor data |
5b912c10 EB |
170 | * |
171 | * Set the hardware irq controller data for an irq | |
172 | */ | |
173 | int set_irq_msi(unsigned int irq, struct msi_desc *entry) | |
174 | { | |
175 | struct irq_desc *desc; | |
176 | unsigned long flags; | |
177 | ||
85c0f909 | 178 | if (irq >= nr_irqs) { |
5b912c10 EB |
179 | printk(KERN_ERR |
180 | "Trying to install msi data for IRQ%d\n", irq); | |
181 | return -EINVAL; | |
182 | } | |
183 | desc = irq_desc + irq; | |
184 | spin_lock_irqsave(&desc->lock, flags); | |
185 | desc->msi_desc = entry; | |
7fe3730d ME |
186 | if (entry) |
187 | entry->irq = irq; | |
5b912c10 EB |
188 | spin_unlock_irqrestore(&desc->lock, flags); |
189 | return 0; | |
190 | } | |
191 | ||
dd87eb3a TG |
192 | /** |
193 | * set_irq_chip_data - set irq chip data for an irq | |
194 | * @irq: Interrupt number | |
195 | * @data: Pointer to chip specific data | |
196 | * | |
197 | * Set the hardware irq chip data for an irq | |
198 | */ | |
199 | int set_irq_chip_data(unsigned int irq, void *data) | |
200 | { | |
201 | struct irq_desc *desc = irq_desc + irq; | |
202 | unsigned long flags; | |
203 | ||
85c0f909 | 204 | if (irq >= nr_irqs || !desc->chip) { |
dd87eb3a TG |
205 | printk(KERN_ERR "BUG: bad set_irq_chip_data(IRQ#%d)\n", irq); |
206 | return -EINVAL; | |
207 | } | |
208 | ||
209 | spin_lock_irqsave(&desc->lock, flags); | |
210 | desc->chip_data = data; | |
211 | spin_unlock_irqrestore(&desc->lock, flags); | |
212 | ||
213 | return 0; | |
214 | } | |
215 | EXPORT_SYMBOL(set_irq_chip_data); | |
216 | ||
217 | /* | |
218 | * default enable function | |
219 | */ | |
220 | static void default_enable(unsigned int irq) | |
221 | { | |
222 | struct irq_desc *desc = irq_desc + irq; | |
223 | ||
224 | desc->chip->unmask(irq); | |
225 | desc->status &= ~IRQ_MASKED; | |
226 | } | |
227 | ||
228 | /* | |
229 | * default disable function | |
230 | */ | |
231 | static void default_disable(unsigned int irq) | |
232 | { | |
dd87eb3a TG |
233 | } |
234 | ||
235 | /* | |
236 | * default startup function | |
237 | */ | |
238 | static unsigned int default_startup(unsigned int irq) | |
239 | { | |
240 | irq_desc[irq].chip->enable(irq); | |
241 | ||
242 | return 0; | |
243 | } | |
244 | ||
89d694b9 TG |
245 | /* |
246 | * default shutdown function | |
247 | */ | |
248 | static void default_shutdown(unsigned int irq) | |
249 | { | |
250 | struct irq_desc *desc = irq_desc + irq; | |
251 | ||
252 | desc->chip->mask(irq); | |
253 | desc->status |= IRQ_MASKED; | |
254 | } | |
255 | ||
dd87eb3a TG |
256 | /* |
257 | * Fixup enable/disable function pointers | |
258 | */ | |
259 | void irq_chip_set_defaults(struct irq_chip *chip) | |
260 | { | |
261 | if (!chip->enable) | |
262 | chip->enable = default_enable; | |
263 | if (!chip->disable) | |
264 | chip->disable = default_disable; | |
265 | if (!chip->startup) | |
266 | chip->startup = default_startup; | |
89d694b9 TG |
267 | /* |
268 | * We use chip->disable, when the user provided its own. When | |
269 | * we have default_disable set for chip->disable, then we need | |
270 | * to use default_shutdown, otherwise the irq line is not | |
271 | * disabled on free_irq(): | |
272 | */ | |
dd87eb3a | 273 | if (!chip->shutdown) |
89d694b9 TG |
274 | chip->shutdown = chip->disable != default_disable ? |
275 | chip->disable : default_shutdown; | |
dd87eb3a TG |
276 | if (!chip->name) |
277 | chip->name = chip->typename; | |
b86432b4 ZY |
278 | if (!chip->end) |
279 | chip->end = dummy_irq_chip.end; | |
dd87eb3a TG |
280 | } |
281 | ||
282 | static inline void mask_ack_irq(struct irq_desc *desc, int irq) | |
283 | { | |
284 | if (desc->chip->mask_ack) | |
285 | desc->chip->mask_ack(irq); | |
286 | else { | |
287 | desc->chip->mask(irq); | |
288 | desc->chip->ack(irq); | |
289 | } | |
290 | } | |
291 | ||
292 | /** | |
293 | * handle_simple_irq - Simple and software-decoded IRQs. | |
294 | * @irq: the interrupt number | |
295 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
296 | * |
297 | * Simple interrupts are either sent from a demultiplexing interrupt | |
298 | * handler or come from hardware, where no interrupt hardware control | |
299 | * is necessary. | |
300 | * | |
301 | * Note: The caller is expected to handle the ack, clear, mask and | |
302 | * unmask issues if necessary. | |
303 | */ | |
7ad5b3a5 | 304 | void |
7d12e780 | 305 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
306 | { |
307 | struct irqaction *action; | |
308 | irqreturn_t action_ret; | |
309 | const unsigned int cpu = smp_processor_id(); | |
310 | ||
311 | spin_lock(&desc->lock); | |
312 | ||
313 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
314 | goto out_unlock; | |
971e5b35 | 315 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
dd87eb3a TG |
316 | kstat_cpu(cpu).irqs[irq]++; |
317 | ||
318 | action = desc->action; | |
971e5b35 | 319 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
dd87eb3a TG |
320 | goto out_unlock; |
321 | ||
322 | desc->status |= IRQ_INPROGRESS; | |
323 | spin_unlock(&desc->lock); | |
324 | ||
7d12e780 | 325 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 326 | if (!noirqdebug) |
7d12e780 | 327 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
328 | |
329 | spin_lock(&desc->lock); | |
330 | desc->status &= ~IRQ_INPROGRESS; | |
331 | out_unlock: | |
332 | spin_unlock(&desc->lock); | |
333 | } | |
334 | ||
335 | /** | |
336 | * handle_level_irq - Level type irq handler | |
337 | * @irq: the interrupt number | |
338 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
339 | * |
340 | * Level type interrupts are active as long as the hardware line has | |
341 | * the active level. This may require to mask the interrupt and unmask | |
342 | * it after the associated handler has acknowledged the device, so the | |
343 | * interrupt line is back to inactive. | |
344 | */ | |
7ad5b3a5 | 345 | void |
7d12e780 | 346 | handle_level_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
347 | { |
348 | unsigned int cpu = smp_processor_id(); | |
349 | struct irqaction *action; | |
350 | irqreturn_t action_ret; | |
351 | ||
352 | spin_lock(&desc->lock); | |
353 | mask_ack_irq(desc, irq); | |
354 | ||
355 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
86998aa6 | 356 | goto out_unlock; |
dd87eb3a TG |
357 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
358 | kstat_cpu(cpu).irqs[irq]++; | |
359 | ||
360 | /* | |
361 | * If its disabled or no action available | |
362 | * keep it masked and get out of here | |
363 | */ | |
364 | action = desc->action; | |
49663421 | 365 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
86998aa6 | 366 | goto out_unlock; |
dd87eb3a TG |
367 | |
368 | desc->status |= IRQ_INPROGRESS; | |
369 | spin_unlock(&desc->lock); | |
370 | ||
7d12e780 | 371 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 372 | if (!noirqdebug) |
7d12e780 | 373 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
374 | |
375 | spin_lock(&desc->lock); | |
376 | desc->status &= ~IRQ_INPROGRESS; | |
dd87eb3a TG |
377 | if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask) |
378 | desc->chip->unmask(irq); | |
86998aa6 | 379 | out_unlock: |
dd87eb3a TG |
380 | spin_unlock(&desc->lock); |
381 | } | |
382 | ||
383 | /** | |
47c2a3aa | 384 | * handle_fasteoi_irq - irq handler for transparent controllers |
dd87eb3a TG |
385 | * @irq: the interrupt number |
386 | * @desc: the interrupt description structure for this irq | |
dd87eb3a | 387 | * |
47c2a3aa | 388 | * Only a single callback will be issued to the chip: an ->eoi() |
dd87eb3a TG |
389 | * call when the interrupt has been serviced. This enables support |
390 | * for modern forms of interrupt handlers, which handle the flow | |
391 | * details in hardware, transparently. | |
392 | */ | |
7ad5b3a5 | 393 | void |
7d12e780 | 394 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
395 | { |
396 | unsigned int cpu = smp_processor_id(); | |
397 | struct irqaction *action; | |
398 | irqreturn_t action_ret; | |
399 | ||
400 | spin_lock(&desc->lock); | |
401 | ||
402 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
403 | goto out; | |
404 | ||
405 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
406 | kstat_cpu(cpu).irqs[irq]++; | |
407 | ||
408 | /* | |
409 | * If its disabled or no action available | |
76d21601 | 410 | * then mask it and get out of here: |
dd87eb3a TG |
411 | */ |
412 | action = desc->action; | |
98bb244b BH |
413 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) { |
414 | desc->status |= IRQ_PENDING; | |
76d21601 IM |
415 | if (desc->chip->mask) |
416 | desc->chip->mask(irq); | |
dd87eb3a | 417 | goto out; |
98bb244b | 418 | } |
dd87eb3a TG |
419 | |
420 | desc->status |= IRQ_INPROGRESS; | |
98bb244b | 421 | desc->status &= ~IRQ_PENDING; |
dd87eb3a TG |
422 | spin_unlock(&desc->lock); |
423 | ||
7d12e780 | 424 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 425 | if (!noirqdebug) |
7d12e780 | 426 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
427 | |
428 | spin_lock(&desc->lock); | |
429 | desc->status &= ~IRQ_INPROGRESS; | |
430 | out: | |
47c2a3aa | 431 | desc->chip->eoi(irq); |
dd87eb3a TG |
432 | |
433 | spin_unlock(&desc->lock); | |
434 | } | |
435 | ||
436 | /** | |
437 | * handle_edge_irq - edge type IRQ handler | |
438 | * @irq: the interrupt number | |
439 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
440 | * |
441 | * Interrupt occures on the falling and/or rising edge of a hardware | |
442 | * signal. The occurence is latched into the irq controller hardware | |
443 | * and must be acked in order to be reenabled. After the ack another | |
444 | * interrupt can happen on the same source even before the first one | |
445 | * is handled by the assosiacted event handler. If this happens it | |
446 | * might be necessary to disable (mask) the interrupt depending on the | |
447 | * controller hardware. This requires to reenable the interrupt inside | |
448 | * of the loop which handles the interrupts which have arrived while | |
449 | * the handler was running. If all pending interrupts are handled, the | |
450 | * loop is left. | |
451 | */ | |
7ad5b3a5 | 452 | void |
7d12e780 | 453 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
454 | { |
455 | const unsigned int cpu = smp_processor_id(); | |
456 | ||
457 | spin_lock(&desc->lock); | |
458 | ||
459 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
460 | ||
461 | /* | |
462 | * If we're currently running this IRQ, or its disabled, | |
463 | * we shouldn't process the IRQ. Mark it pending, handle | |
464 | * the necessary masking and go out | |
465 | */ | |
466 | if (unlikely((desc->status & (IRQ_INPROGRESS | IRQ_DISABLED)) || | |
467 | !desc->action)) { | |
468 | desc->status |= (IRQ_PENDING | IRQ_MASKED); | |
469 | mask_ack_irq(desc, irq); | |
470 | goto out_unlock; | |
471 | } | |
472 | ||
473 | kstat_cpu(cpu).irqs[irq]++; | |
474 | ||
475 | /* Start handling the irq */ | |
476 | desc->chip->ack(irq); | |
477 | ||
478 | /* Mark the IRQ currently in progress.*/ | |
479 | desc->status |= IRQ_INPROGRESS; | |
480 | ||
481 | do { | |
482 | struct irqaction *action = desc->action; | |
483 | irqreturn_t action_ret; | |
484 | ||
485 | if (unlikely(!action)) { | |
486 | desc->chip->mask(irq); | |
487 | goto out_unlock; | |
488 | } | |
489 | ||
490 | /* | |
491 | * When another irq arrived while we were handling | |
492 | * one, we could have masked the irq. | |
493 | * Renable it, if it was not disabled in meantime. | |
494 | */ | |
495 | if (unlikely((desc->status & | |
496 | (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) == | |
497 | (IRQ_PENDING | IRQ_MASKED))) { | |
498 | desc->chip->unmask(irq); | |
499 | desc->status &= ~IRQ_MASKED; | |
500 | } | |
501 | ||
502 | desc->status &= ~IRQ_PENDING; | |
503 | spin_unlock(&desc->lock); | |
7d12e780 | 504 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 505 | if (!noirqdebug) |
7d12e780 | 506 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
507 | spin_lock(&desc->lock); |
508 | ||
509 | } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING); | |
510 | ||
511 | desc->status &= ~IRQ_INPROGRESS; | |
512 | out_unlock: | |
513 | spin_unlock(&desc->lock); | |
514 | } | |
515 | ||
dd87eb3a TG |
516 | /** |
517 | * handle_percpu_IRQ - Per CPU local irq handler | |
518 | * @irq: the interrupt number | |
519 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
520 | * |
521 | * Per CPU interrupts on SMP machines without locking requirements | |
522 | */ | |
7ad5b3a5 | 523 | void |
7d12e780 | 524 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
525 | { |
526 | irqreturn_t action_ret; | |
527 | ||
528 | kstat_this_cpu.irqs[irq]++; | |
529 | ||
530 | if (desc->chip->ack) | |
531 | desc->chip->ack(irq); | |
532 | ||
7d12e780 | 533 | action_ret = handle_IRQ_event(irq, desc->action); |
dd87eb3a | 534 | if (!noirqdebug) |
7d12e780 | 535 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
536 | |
537 | if (desc->chip->eoi) | |
538 | desc->chip->eoi(irq); | |
539 | } | |
540 | ||
dd87eb3a | 541 | void |
a460e745 IM |
542 | __set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
543 | const char *name) | |
dd87eb3a TG |
544 | { |
545 | struct irq_desc *desc; | |
546 | unsigned long flags; | |
547 | ||
85c0f909 | 548 | if (irq >= nr_irqs) { |
dd87eb3a TG |
549 | printk(KERN_ERR |
550 | "Trying to install type control for IRQ%d\n", irq); | |
551 | return; | |
552 | } | |
553 | ||
554 | desc = irq_desc + irq; | |
555 | ||
556 | if (!handle) | |
557 | handle = handle_bad_irq; | |
9d7ac8be | 558 | else if (desc->chip == &no_irq_chip) { |
f8b5473f | 559 | printk(KERN_WARNING "Trying to install %sinterrupt handler " |
b039db8e | 560 | "for IRQ%d\n", is_chained ? "chained " : "", irq); |
f8b5473f TG |
561 | /* |
562 | * Some ARM implementations install a handler for really dumb | |
563 | * interrupt hardware without setting an irq_chip. This worked | |
564 | * with the ARM no_irq_chip but the check in setup_irq would | |
565 | * prevent us to setup the interrupt at all. Switch it to | |
566 | * dummy_irq_chip for easy transition. | |
567 | */ | |
568 | desc->chip = &dummy_irq_chip; | |
569 | } | |
dd87eb3a TG |
570 | |
571 | spin_lock_irqsave(&desc->lock, flags); | |
572 | ||
573 | /* Uninstall? */ | |
574 | if (handle == handle_bad_irq) { | |
5575ddf7 JB |
575 | if (desc->chip != &no_irq_chip) |
576 | mask_ack_irq(desc, irq); | |
dd87eb3a TG |
577 | desc->status |= IRQ_DISABLED; |
578 | desc->depth = 1; | |
579 | } | |
580 | desc->handle_irq = handle; | |
a460e745 | 581 | desc->name = name; |
dd87eb3a TG |
582 | |
583 | if (handle != handle_bad_irq && is_chained) { | |
584 | desc->status &= ~IRQ_DISABLED; | |
585 | desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE; | |
586 | desc->depth = 0; | |
7e6e178a | 587 | desc->chip->startup(irq); |
dd87eb3a TG |
588 | } |
589 | spin_unlock_irqrestore(&desc->lock, flags); | |
590 | } | |
591 | ||
592 | void | |
593 | set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip, | |
57a58a94 | 594 | irq_flow_handler_t handle) |
dd87eb3a TG |
595 | { |
596 | set_irq_chip(irq, chip); | |
a460e745 | 597 | __set_irq_handler(irq, handle, 0, NULL); |
dd87eb3a TG |
598 | } |
599 | ||
a460e745 IM |
600 | void |
601 | set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, | |
602 | irq_flow_handler_t handle, const char *name) | |
dd87eb3a | 603 | { |
a460e745 IM |
604 | set_irq_chip(irq, chip); |
605 | __set_irq_handler(irq, handle, 0, name); | |
dd87eb3a | 606 | } |
46f4f8f6 RB |
607 | |
608 | void __init set_irq_noprobe(unsigned int irq) | |
609 | { | |
610 | struct irq_desc *desc; | |
611 | unsigned long flags; | |
612 | ||
85c0f909 | 613 | if (irq >= nr_irqs) { |
46f4f8f6 RB |
614 | printk(KERN_ERR "Trying to mark IRQ%d non-probeable\n", irq); |
615 | ||
616 | return; | |
617 | } | |
618 | ||
619 | desc = irq_desc + irq; | |
620 | ||
621 | spin_lock_irqsave(&desc->lock, flags); | |
622 | desc->status |= IRQ_NOPROBE; | |
623 | spin_unlock_irqrestore(&desc->lock, flags); | |
624 | } | |
625 | ||
626 | void __init set_irq_probe(unsigned int irq) | |
627 | { | |
628 | struct irq_desc *desc; | |
629 | unsigned long flags; | |
630 | ||
85c0f909 | 631 | if (irq >= nr_irqs) { |
46f4f8f6 RB |
632 | printk(KERN_ERR "Trying to mark IRQ%d probeable\n", irq); |
633 | ||
634 | return; | |
635 | } | |
636 | ||
637 | desc = irq_desc + irq; | |
638 | ||
639 | spin_lock_irqsave(&desc->lock, flags); | |
640 | desc->status &= ~IRQ_NOPROBE; | |
641 | spin_unlock_irqrestore(&desc->lock, flags); | |
642 | } |