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OMAP: DSS2: HDMI: change regn definition
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / video / omapdss.h
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559d6701 1/*
559d6701
TV		 2 * Copyright (C) 2008 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
a0b38cc4
TV		 18#ifndef __OMAP_OMAPDSS_H
19#define __OMAP_OMAPDSS_H
559d6701
TV		 20
21#include <linux/list.h>
22#include <linux/kobject.h>
23#include <linux/device.h>
559d6701
TV		 24
25#define DISPC_IRQ_FRAMEDONE (1 << 0)
26#define DISPC_IRQ_VSYNC (1 << 1)
27#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
28#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
29#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
30#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
31#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
32#define DISPC_IRQ_GFX_END_WIN (1 << 7)
33#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
34#define DISPC_IRQ_OCP_ERR (1 << 9)
35#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
36#define DISPC_IRQ_VID1_END_WIN (1 << 11)
37#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
38#define DISPC_IRQ_VID2_END_WIN (1 << 13)
39#define DISPC_IRQ_SYNC_LOST (1 << 14)
40#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
41#define DISPC_IRQ_WAKEUP (1 << 16)
2a205f34
SS		 42#define DISPC_IRQ_SYNC_LOST2 (1 << 17)
43#define DISPC_IRQ_VSYNC2 (1 << 18)
44#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
45#define DISPC_IRQ_FRAMEDONE2 (1 << 22)
559d6701
TV		 46
47struct omap_dss_device;
48struct omap_overlay_manager;
49
50enum omap_display_type {
51 OMAP_DISPLAY_TYPE_NONE = 0,
52 OMAP_DISPLAY_TYPE_DPI = 1 << 0,
53 OMAP_DISPLAY_TYPE_DBI = 1 << 1,
54 OMAP_DISPLAY_TYPE_SDI = 1 << 2,
55 OMAP_DISPLAY_TYPE_DSI = 1 << 3,
56 OMAP_DISPLAY_TYPE_VENC = 1 << 4,
b119601d 57 OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
559d6701
TV		 58};
59
60enum omap_plane {
61 OMAP_DSS_GFX = 0,
62 OMAP_DSS_VIDEO1 = 1,
63 OMAP_DSS_VIDEO2 = 2
64};
65
66enum omap_channel {
67 OMAP_DSS_CHANNEL_LCD = 0,
68 OMAP_DSS_CHANNEL_DIGIT = 1,
8613b000 69 OMAP_DSS_CHANNEL_LCD2 = 2,
559d6701
TV		 70};
71
72enum omap_color_mode {
73 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
74 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
75 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
76 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
77 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
78 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
79 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
80 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
81 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
82 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
83 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
84 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
85 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
86 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
f20e4220
AJ		 87 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
88 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
89 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
90 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
91 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
559d6701
TV		 92};
93
94enum omap_lcd_display_type {
95 OMAP_DSS_LCD_DISPLAY_STN,
96 OMAP_DSS_LCD_DISPLAY_TFT,
97};
98
99enum omap_dss_load_mode {
100 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
101 OMAP_DSS_LOAD_CLUT_ONLY = 1,
102 OMAP_DSS_LOAD_FRAME_ONLY = 2,
103 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
104};
105
106enum omap_dss_trans_key_type {
107 OMAP_DSS_COLOR_KEY_GFX_DST = 0,
108 OMAP_DSS_COLOR_KEY_VID_SRC = 1,
109};
110
111enum omap_rfbi_te_mode {
112 OMAP_DSS_RFBI_TE_MODE_1 = 1,
113 OMAP_DSS_RFBI_TE_MODE_2 = 2,
114};
115
116enum omap_panel_config {
117 OMAP_DSS_LCD_IVS = 1<<0,
118 OMAP_DSS_LCD_IHS = 1<<1,
119 OMAP_DSS_LCD_IPC = 1<<2,
120 OMAP_DSS_LCD_IEO = 1<<3,
121 OMAP_DSS_LCD_RF = 1<<4,
122 OMAP_DSS_LCD_ONOFF = 1<<5,
123
124 OMAP_DSS_LCD_TFT = 1<<20,
125};
126
127enum omap_dss_venc_type {
128 OMAP_DSS_VENC_TYPE_COMPOSITE,
129 OMAP_DSS_VENC_TYPE_SVIDEO,
130};
131
a3b3cc2b
AT		 132enum omap_dss_dsi_pixel_format {
133 OMAP_DSS_DSI_FMT_RGB888,
134 OMAP_DSS_DSI_FMT_RGB666,
135 OMAP_DSS_DSI_FMT_RGB666_PACKED,
136 OMAP_DSS_DSI_FMT_RGB565,
137};
138
7e951ee9
AT		 139enum omap_dss_dsi_mode {
140 OMAP_DSS_DSI_CMD_MODE = 0,
141 OMAP_DSS_DSI_VIDEO_MODE,
142};
143
559d6701
TV		 144enum omap_display_caps {
145 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
146 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
147};
148
559d6701
TV		 149enum omap_dss_display_state {
150 OMAP_DSS_DISPLAY_DISABLED = 0,
151 OMAP_DSS_DISPLAY_ACTIVE,
152 OMAP_DSS_DISPLAY_SUSPENDED,
153};
154
155/* XXX perhaps this should be removed */
156enum omap_dss_overlay_managers {
157 OMAP_DSS_OVL_MGR_LCD,
158 OMAP_DSS_OVL_MGR_TV,
8613b000 159 OMAP_DSS_OVL_MGR_LCD2,
559d6701
TV		 160};
161
162enum omap_dss_rotation_type {
163 OMAP_DSS_ROT_DMA = 0,
164 OMAP_DSS_ROT_VRFB = 1,
165};
166
167/* clockwise rotation angle */
168enum omap_dss_rotation_angle {
169 OMAP_DSS_ROT_0 = 0,
170 OMAP_DSS_ROT_90 = 1,
171 OMAP_DSS_ROT_180 = 2,
172 OMAP_DSS_ROT_270 = 3,
173};
174
175enum omap_overlay_caps {
176 OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
f6dc8150
TV		 177 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
178 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
559d6701
TV		 179};
180
181enum omap_overlay_manager_caps {
4a9e78ab 182 OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */
559d6701
TV		 183};
184
89a35e51
AT		 185enum omap_dss_clk_source {
186 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
187 * OMAP4: DSS_FCLK */
188 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
189 * OMAP4: PLL1_CLK1 */
190 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
191 * OMAP4: PLL1_CLK2 */
5a8b572d
AT		 192 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
193 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
89a35e51
AT		 194};
195
559d6701
TV		 196/* RFBI */
197
198struct rfbi_timings {
199 int cs_on_time;
200 int cs_off_time;
201 int we_on_time;
202 int we_off_time;
203 int re_on_time;
204 int re_off_time;
205 int we_cycle_time;
206 int re_cycle_time;
207 int cs_pulse_width;
208 int access_time;
209
210 int clk_div;
211
212 u32 tim[5]; /* set by rfbi_convert_timings() */
213
214 int converted;
215};
216
217void omap_rfbi_write_command(const void *buf, u32 len);
218void omap_rfbi_read_data(void *buf, u32 len);
219void omap_rfbi_write_data(const void *buf, u32 len);
220void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
221 u16 x, u16 y,
222 u16 w, u16 h);
223int omap_rfbi_enable_te(bool enable, unsigned line);
224int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
225 unsigned hs_pulse_time, unsigned vs_pulse_time,
226 int hs_pol_inv, int vs_pol_inv, int extif_div);
773139f1
TV		 227void rfbi_bus_lock(void);
228void rfbi_bus_unlock(void);
559d6701
TV		 229
230/* DSI */
8af6ff01
AT		 231
232struct omap_dss_dsi_videomode_data {
233 /* DSI video mode blanking data */
234 /* Unit: byte clock cycles */
235 u16 hsa;
236 u16 hfp;
237 u16 hbp;
238 /* Unit: line clocks */
239 u16 vsa;
240 u16 vfp;
241 u16 vbp;
242
243 /* DSI blanking modes */
244 int blanking_mode;
245 int hsa_blanking_mode;
246 int hbp_blanking_mode;
247 int hfp_blanking_mode;
248
249 /* Video port sync events */
250 int vp_de_pol;
251 int vp_hsync_pol;
252 int vp_vsync_pol;
253 bool vp_vsync_end;
254 bool vp_hsync_end;
255
256 bool ddr_clk_always_on;
257 int window_sync;
258};
259
1ffefe75
AT		 260void dsi_bus_lock(struct omap_dss_device *dssdev);
261void dsi_bus_unlock(struct omap_dss_device *dssdev);
262int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
263 int len);
6ff8aa31
AT		 264int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
265 int len);
266int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd);
267int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel);
1ffefe75
AT		 268int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
269 u8 param);
6ff8aa31
AT		 270int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
271 u8 param);
272int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
273 u8 param1, u8 param2);
1ffefe75
AT		 274int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
275 u8 *data, int len);
6ff8aa31
AT		 276int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
277 u8 *data, int len);
1ffefe75
AT		 278int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
279 u8 *buf, int buflen);
b3b89c05
AT		 280int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
281 int buflen);
282int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
283 u8 *buf, int buflen);
284int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
285 u8 param1, u8 param2, u8 *buf, int buflen);
1ffefe75
AT		 286int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
287 u16 len);
288int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
289int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
8af6ff01
AT		 290int dsi_video_mode_enable(struct omap_dss_device *dssdev, int channel);
291void dsi_video_mode_disable(struct omap_dss_device *dssdev, int channel);
559d6701
TV		 292
293/* Board specific data */
294struct omap_dss_board_info {
aac927c9 295 int (*get_context_loss_count)(struct device *dev);
559d6701
TV		 296 int num_devices;
297 struct omap_dss_device **devices;
298 struct omap_dss_device *default_device;
5bc416cb
TV		 299 int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask);
300 void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
559d6701
TV		 301};
302
b7ee79ab
SS		 303#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
304/* Init with the board info */
305extern int omap_display_init(struct omap_dss_board_info *board_data);
306#else
307static inline int omap_display_init(struct omap_dss_board_info *board_data)
308{
309 return 0;
310}
311#endif
312
cf07f531
SG		 313struct omap_display_platform_data {
314 struct omap_dss_board_info *board_data;
315 /* TODO: Additional members to be added when PM is considered */
316};
317
559d6701
TV		 318struct omap_video_timings {
319 /* Unit: pixels */
320 u16 x_res;
321 /* Unit: pixels */
322 u16 y_res;
323 /* Unit: KHz */
324 u32 pixel_clock;
325 /* Unit: pixel clocks */
326 u16 hsw; /* Horizontal synchronization pulse width */
327 /* Unit: pixel clocks */
328 u16 hfp; /* Horizontal front porch */
329 /* Unit: pixel clocks */
330 u16 hbp; /* Horizontal back porch */
331 /* Unit: line clocks */
332 u16 vsw; /* Vertical synchronization pulse width */
333 /* Unit: line clocks */
334 u16 vfp; /* Vertical front porch */
335 /* Unit: line clocks */
336 u16 vbp; /* Vertical back porch */
337};
338
339#ifdef CONFIG_OMAP2_DSS_VENC
340/* Hardcoded timings for tv modes. Venc only uses these to
341 * identify the mode, and does not actually use the configs
342 * itself. However, the configs should be something that
343 * a normal monitor can also show */
5a1819e3
TK		 344extern const struct omap_video_timings omap_dss_pal_timings;
345extern const struct omap_video_timings omap_dss_ntsc_timings;
559d6701
TV		 346#endif
347
3c07cae2
TV		 348struct omap_dss_cpr_coefs {
349 s16 rr, rg, rb;
350 s16 gr, gg, gb;
351 s16 br, bg, bb;
352};
353
559d6701
TV		 354struct omap_overlay_info {
355 bool enabled;
356
357 u32 paddr;
358 void __iomem *vaddr;
0d66cbb5 359 u32 p_uv_addr; /* for NV12 format */
559d6701
TV		 360 u16 screen_width;
361 u16 width;
362 u16 height;
363 enum omap_color_mode color_mode;
364 u8 rotation;
365 enum omap_dss_rotation_type rotation_type;
366 bool mirror;
367
368 u16 pos_x;
369 u16 pos_y;
370 u16 out_width; /* if 0, out_width == width */
371 u16 out_height; /* if 0, out_height == height */
372 u8 global_alpha;
fd28a390 373 u8 pre_mult_alpha;
559d6701
TV		 374};
375
376struct omap_overlay {
377 struct kobject kobj;
378 struct list_head list;
379
380 /* static fields */
381 const char *name;
4a9e78ab 382 enum omap_plane id;
559d6701
TV		 383 enum omap_color_mode supported_modes;
384 enum omap_overlay_caps caps;
385
386 /* dynamic fields */
387 struct omap_overlay_manager *manager;
388 struct omap_overlay_info info;
389
8fa8031c 390 bool manager_changed;
559d6701
TV		 391 /* if true, info has been changed, but not applied() yet */
392 bool info_dirty;
393
394 int (*set_manager)(struct omap_overlay *ovl,
395 struct omap_overlay_manager *mgr);
396 int (*unset_manager)(struct omap_overlay *ovl);
397
398 int (*set_overlay_info)(struct omap_overlay *ovl,
399 struct omap_overlay_info *info);
400 void (*get_overlay_info)(struct omap_overlay *ovl,
401 struct omap_overlay_info *info);
402
403 int (*wait_for_go)(struct omap_overlay *ovl);
404};
405
406struct omap_overlay_manager_info {
407 u32 default_color;
408
409 enum omap_dss_trans_key_type trans_key_type;
410 u32 trans_key;
411 bool trans_enabled;
412
413 bool alpha_enabled;
3c07cae2
TV		 414
415 bool cpr_enable;
416 struct omap_dss_cpr_coefs cpr_coefs;
559d6701
TV		 417};
418
419struct omap_overlay_manager {
420 struct kobject kobj;
421 struct list_head list;
422
423 /* static fields */
424 const char *name;
4a9e78ab 425 enum omap_channel id;
559d6701
TV		 426 enum omap_overlay_manager_caps caps;
427 int num_overlays;
428 struct omap_overlay **overlays;
429 enum omap_display_type supported_displays;
430
431 /* dynamic fields */
432 struct omap_dss_device *device;
433 struct omap_overlay_manager_info info;
434
435 bool device_changed;
436 /* if true, info has been changed but not applied() yet */
437 bool info_dirty;
438
439 int (*set_device)(struct omap_overlay_manager *mgr,
440 struct omap_dss_device *dssdev);
441 int (*unset_device)(struct omap_overlay_manager *mgr);
442
443 int (*set_manager_info)(struct omap_overlay_manager *mgr,
444 struct omap_overlay_manager_info *info);
445 void (*get_manager_info)(struct omap_overlay_manager *mgr,
446 struct omap_overlay_manager_info *info);
447
448 int (*apply)(struct omap_overlay_manager *mgr);
449 int (*wait_for_go)(struct omap_overlay_manager *mgr);
3f71cbe7 450 int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
a2faee84
TV		 451
452 int (*enable)(struct omap_overlay_manager *mgr);
453 int (*disable)(struct omap_overlay_manager *mgr);
559d6701
TV		 454};
455
456struct omap_dss_device {
457 struct device dev;
458
459 enum omap_display_type type;
460
18faa1b6
SS		 461 enum omap_channel channel;
462
559d6701
TV		 463 union {
464 struct {
465 u8 data_lines;
466 } dpi;
467
468 struct {
469 u8 channel;
470 u8 data_lines;
471 } rfbi;
472
473 struct {
474 u8 datapairs;
475 } sdi;
476
477 struct {
478 u8 clk_lane;
479 u8 clk_pol;
480 u8 data1_lane;
481 u8 data1_pol;
482 u8 data2_lane;
483 u8 data2_pol;
75d7247c
AT		 484 u8 data3_lane;
485 u8 data3_pol;
486 u8 data4_lane;
487 u8 data4_pol;
559d6701 488
a72b64b9
AT		 489 int module;
490
559d6701
TV		 491 bool ext_te;
492 u8 ext_te_gpio;
493 } dsi;
494
495 struct {
496 enum omap_dss_venc_type type;
497 bool invert_polarity;
498 } venc;
499 } phy;
500
c6940a3d
TV		 501 struct {
502 struct {
e8881662
AT		 503 struct {
504 u16 lck_div;
505 u16 pck_div;
506 enum omap_dss_clk_source lcd_clk_src;
507 } channel;
508
509 enum omap_dss_clk_source dispc_fclk_src;
c6940a3d
TV		 510 } dispc;
511
512 struct {
513 u16 regn;
514 u16 regm;
515 u16 regm_dispc;
516 u16 regm_dsi;
517
518 u16 lp_clk_div;
e8881662 519 enum omap_dss_clk_source dsi_fclk_src;
c6940a3d 520 } dsi;
6cb07b25
AT		 521
522 struct {
b44e4582 523 /* regn is one greater than TRM's REGN value */
6cb07b25
AT		 524 u16 regn;
525 u16 regm2;
526 } hdmi;
c6940a3d
TV		 527 } clocks;
528
559d6701
TV		 529 struct {
530 struct omap_video_timings timings;
531
532 int acbi; /* ac-bias pin transitions per interrupt */
533 /* Unit: line clocks */
534 int acb; /* ac-bias pin frequency */
535
536 enum omap_panel_config config;
7e951ee9 537
a3b3cc2b 538 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
7e951ee9 539 enum omap_dss_dsi_mode dsi_mode;
8af6ff01 540 struct omap_dss_dsi_videomode_data dsi_vm_data;
559d6701
TV		 541 } panel;
542
543 struct {
544 u8 pixel_size;
545 struct rfbi_timings rfbi_timings;
559d6701
TV		 546 } ctrl;
547
548 int reset_gpio;
549
550 int max_backlight_level;
551
552 const char *name;
553
554 /* used to match device to driver */
555 const char *driver_name;
556
557 void *data;
558
559 struct omap_dss_driver *driver;
560
561 /* helper variable for driver suspend/resume */
562 bool activate_after_resume;
563
564 enum omap_display_caps caps;
565
566 struct omap_overlay_manager *manager;
567
568 enum omap_dss_display_state state;
569
559d6701
TV		 570 /* platform specific */
571 int (*platform_enable)(struct omap_dss_device *dssdev);
572 void (*platform_disable)(struct omap_dss_device *dssdev);
573 int (*set_backlight)(struct omap_dss_device *dssdev, int level);
574 int (*get_backlight)(struct omap_dss_device *dssdev);
575};
576
577struct omap_dss_driver {
578 struct device_driver driver;
579
580 int (*probe)(struct omap_dss_device *);
581 void (*remove)(struct omap_dss_device *);
582
583 int (*enable)(struct omap_dss_device *display);
584 void (*disable)(struct omap_dss_device *display);
585 int (*suspend)(struct omap_dss_device *display);
586 int (*resume)(struct omap_dss_device *display);
587 int (*run_test)(struct omap_dss_device *display, int test);
588
18946f62
TV		 589 int (*update)(struct omap_dss_device *dssdev,
590 u16 x, u16 y, u16 w, u16 h);
591 int (*sync)(struct omap_dss_device *dssdev);
592
559d6701 593 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
225b650d 594 int (*get_te)(struct omap_dss_device *dssdev);
559d6701
TV		 595
596 u8 (*get_rotate)(struct omap_dss_device *dssdev);
597 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
598
599 bool (*get_mirror)(struct omap_dss_device *dssdev);
600 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
601
602 int (*memory_read)(struct omap_dss_device *dssdev,
603 void *buf, size_t size,
604 u16 x, u16 y, u16 w, u16 h);
96adcece
TV		 605
606 void (*get_resolution)(struct omap_dss_device *dssdev,
607 u16 *xres, u16 *yres);
7a0987bf
JN		 608 void (*get_dimensions)(struct omap_dss_device *dssdev,
609 u32 *width, u32 *height);
a2699504 610 int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
36511312 611
69b2048f
TV		 612 int (*check_timings)(struct omap_dss_device *dssdev,
613 struct omap_video_timings *timings);
614 void (*set_timings)(struct omap_dss_device *dssdev,
615 struct omap_video_timings *timings);
616 void (*get_timings)(struct omap_dss_device *dssdev,
617 struct omap_video_timings *timings);
618
36511312
TV		 619 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
620 u32 (*get_wss)(struct omap_dss_device *dssdev);
559d6701
TV		 621};
622
623int omap_dss_register_driver(struct omap_dss_driver *);
624void omap_dss_unregister_driver(struct omap_dss_driver *);
625
559d6701
TV		 626void omap_dss_get_device(struct omap_dss_device *dssdev);
627void omap_dss_put_device(struct omap_dss_device *dssdev);
628#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
629struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
630struct omap_dss_device *omap_dss_find_device(void *data,
631 int (*match)(struct omap_dss_device *dssdev, void *data));
632
633int omap_dss_start_device(struct omap_dss_device *dssdev);
634void omap_dss_stop_device(struct omap_dss_device *dssdev);
635
636int omap_dss_get_num_overlay_managers(void);
637struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
638
639int omap_dss_get_num_overlays(void);
640struct omap_overlay *omap_dss_get_overlay(int num);
641
96adcece
TV		 642void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
643 u16 *xres, u16 *yres);
a2699504
TV		 644int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
645
559d6701
TV		 646typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
647int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
648int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
649
650int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
651int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
652 unsigned long timeout);
653
654#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
655#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
656
1ffefe75
AT		 657void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
658 bool enable);
225b650d 659int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
61140c9a 660
18946f62 661int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
26a8c250
TV		 662 u16 *x, u16 *y, u16 *w, u16 *h,
663 bool enlarge_update_area);
18946f62
TV		 664int omap_dsi_update(struct omap_dss_device *dssdev,
665 int channel,
666 u16 x, u16 y, u16 w, u16 h,
667 void (*callback)(int, void *), void *data);
5ee3c144
AT		 668int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
669int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
670void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
18946f62 671
37ac60e4 672int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
2a89dc15 673void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
22d6d676 674 bool disconnect_lanes, bool enter_ulps);
37ac60e4
TV		 675
676int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
677void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
69b2048f
TV		 678void dpi_set_timings(struct omap_dss_device *dssdev,
679 struct omap_video_timings *timings);
680int dpi_check_timings(struct omap_dss_device *dssdev,
681 struct omap_video_timings *timings);
37ac60e4
TV		 682
683int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
684void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
685
686int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
687void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
18946f62
TV		 688int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
689 u16 *x, u16 *y, u16 *w, u16 *h);
690int omap_rfbi_update(struct omap_dss_device *dssdev,
691 u16 x, u16 y, u16 w, u16 h,
692 void (*callback)(void *), void *data);
1d5952a8
TV		 693int omap_rfbi_configure(struct omap_dss_device *dssdev, int pixel_size,
694 int data_lines);
18946f62 695
559d6701 696#endif
kernel source for telekom puls (alcatel/mediatek)