OMAPDSS: DSI: get line buffer size at probe
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / video / omapdss.h
CommitLineData
559d6701 1/*
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2 * Copyright (C) 2008 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
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18#ifndef __OMAP_OMAPDSS_H
19#define __OMAP_OMAPDSS_H
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20
21#include <linux/list.h>
22#include <linux/kobject.h>
23#include <linux/device.h>
348be69d 24#include <linux/interrupt.h>
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25
26#define DISPC_IRQ_FRAMEDONE (1 << 0)
27#define DISPC_IRQ_VSYNC (1 << 1)
28#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
29#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
30#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
31#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
32#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
33#define DISPC_IRQ_GFX_END_WIN (1 << 7)
34#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
35#define DISPC_IRQ_OCP_ERR (1 << 9)
36#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
37#define DISPC_IRQ_VID1_END_WIN (1 << 11)
38#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
39#define DISPC_IRQ_VID2_END_WIN (1 << 13)
40#define DISPC_IRQ_SYNC_LOST (1 << 14)
41#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
42#define DISPC_IRQ_WAKEUP (1 << 16)
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43#define DISPC_IRQ_SYNC_LOST2 (1 << 17)
44#define DISPC_IRQ_VSYNC2 (1 << 18)
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45#define DISPC_IRQ_VID3_END_WIN (1 << 19)
46#define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
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47#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
48#define DISPC_IRQ_FRAMEDONE2 (1 << 22)
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49#define DISPC_IRQ_FRAMEDONEWB (1 << 23)
50#define DISPC_IRQ_FRAMEDONETV (1 << 24)
51#define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
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52#define DISPC_IRQ_SYNC_LOST3 (1 << 27)
53#define DISPC_IRQ_VSYNC3 (1 << 28)
54#define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29)
55#define DISPC_IRQ_FRAMEDONE3 (1 << 30)
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56
57struct omap_dss_device;
58struct omap_overlay_manager;
a97a9634 59struct dss_lcd_mgr_config;
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60struct snd_aes_iec958;
61struct snd_cea_861_aud_if;
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62
63enum omap_display_type {
64 OMAP_DISPLAY_TYPE_NONE = 0,
65 OMAP_DISPLAY_TYPE_DPI = 1 << 0,
66 OMAP_DISPLAY_TYPE_DBI = 1 << 1,
67 OMAP_DISPLAY_TYPE_SDI = 1 << 2,
68 OMAP_DISPLAY_TYPE_DSI = 1 << 3,
69 OMAP_DISPLAY_TYPE_VENC = 1 << 4,
b119601d 70 OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
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71};
72
73enum omap_plane {
74 OMAP_DSS_GFX = 0,
75 OMAP_DSS_VIDEO1 = 1,
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76 OMAP_DSS_VIDEO2 = 2,
77 OMAP_DSS_VIDEO3 = 3,
66a0f9e4 78 OMAP_DSS_WB = 4,
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79};
80
81enum omap_channel {
82 OMAP_DSS_CHANNEL_LCD = 0,
83 OMAP_DSS_CHANNEL_DIGIT = 1,
8613b000 84 OMAP_DSS_CHANNEL_LCD2 = 2,
ff6331e2 85 OMAP_DSS_CHANNEL_LCD3 = 3,
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86};
87
88enum omap_color_mode {
89 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
90 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
91 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
92 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
93 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
94 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
95 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
96 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
97 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
98 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
99 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
100 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
101 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
102 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
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103 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
104 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
105 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
106 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
107 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
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108};
109
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110enum omap_dss_load_mode {
111 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
112 OMAP_DSS_LOAD_CLUT_ONLY = 1,
113 OMAP_DSS_LOAD_FRAME_ONLY = 2,
114 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
115};
116
117enum omap_dss_trans_key_type {
118 OMAP_DSS_COLOR_KEY_GFX_DST = 0,
119 OMAP_DSS_COLOR_KEY_VID_SRC = 1,
120};
121
122enum omap_rfbi_te_mode {
123 OMAP_DSS_RFBI_TE_MODE_1 = 1,
124 OMAP_DSS_RFBI_TE_MODE_2 = 2,
125};
126
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127enum omap_dss_signal_level {
128 OMAPDSS_SIG_ACTIVE_HIGH = 0,
129 OMAPDSS_SIG_ACTIVE_LOW = 1,
130};
131
132enum omap_dss_signal_edge {
133 OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
134 OMAPDSS_DRIVE_SIG_RISING_EDGE,
135 OMAPDSS_DRIVE_SIG_FALLING_EDGE,
136};
137
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138enum omap_dss_venc_type {
139 OMAP_DSS_VENC_TYPE_COMPOSITE,
140 OMAP_DSS_VENC_TYPE_SVIDEO,
141};
142
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143enum omap_dss_dsi_pixel_format {
144 OMAP_DSS_DSI_FMT_RGB888,
145 OMAP_DSS_DSI_FMT_RGB666,
146 OMAP_DSS_DSI_FMT_RGB666_PACKED,
147 OMAP_DSS_DSI_FMT_RGB565,
148};
149
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150enum omap_dss_dsi_mode {
151 OMAP_DSS_DSI_CMD_MODE = 0,
152 OMAP_DSS_DSI_VIDEO_MODE,
153};
154
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155enum omap_display_caps {
156 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
157 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
158};
159
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160enum omap_dss_display_state {
161 OMAP_DSS_DISPLAY_DISABLED = 0,
162 OMAP_DSS_DISPLAY_ACTIVE,
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163};
164
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165enum omap_dss_audio_state {
166 OMAP_DSS_AUDIO_DISABLED = 0,
167 OMAP_DSS_AUDIO_ENABLED,
168 OMAP_DSS_AUDIO_CONFIGURED,
169 OMAP_DSS_AUDIO_PLAYING,
170};
171
559d6701 172enum omap_dss_rotation_type {
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173 OMAP_DSS_ROT_DMA = 1 << 0,
174 OMAP_DSS_ROT_VRFB = 1 << 1,
175 OMAP_DSS_ROT_TILER = 1 << 2,
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176};
177
178/* clockwise rotation angle */
179enum omap_dss_rotation_angle {
180 OMAP_DSS_ROT_0 = 0,
181 OMAP_DSS_ROT_90 = 1,
182 OMAP_DSS_ROT_180 = 2,
183 OMAP_DSS_ROT_270 = 3,
184};
185
186enum omap_overlay_caps {
187 OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
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188 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
189 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
11354dd5 190 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
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191 OMAP_DSS_OVL_CAP_POS = 1 << 4,
192 OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
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193};
194
195enum omap_overlay_manager_caps {
4a9e78ab 196 OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */
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197};
198
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199enum omap_dss_clk_source {
200 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
201 * OMAP4: DSS_FCLK */
202 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
203 * OMAP4: PLL1_CLK1 */
204 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
205 * OMAP4: PLL1_CLK2 */
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206 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
207 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
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208};
209
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210enum omap_hdmi_flags {
211 OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0,
212};
213
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214enum omap_dss_output_id {
215 OMAP_DSS_OUTPUT_DPI = 1 << 0,
216 OMAP_DSS_OUTPUT_DBI = 1 << 1,
217 OMAP_DSS_OUTPUT_SDI = 1 << 2,
218 OMAP_DSS_OUTPUT_DSI1 = 1 << 3,
219 OMAP_DSS_OUTPUT_DSI2 = 1 << 4,
220 OMAP_DSS_OUTPUT_VENC = 1 << 5,
221 OMAP_DSS_OUTPUT_HDMI = 1 << 6,
222};
223
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224/* RFBI */
225
226struct rfbi_timings {
227 int cs_on_time;
228 int cs_off_time;
229 int we_on_time;
230 int we_off_time;
231 int re_on_time;
232 int re_off_time;
233 int we_cycle_time;
234 int re_cycle_time;
235 int cs_pulse_width;
236 int access_time;
237
238 int clk_div;
239
240 u32 tim[5]; /* set by rfbi_convert_timings() */
241
242 int converted;
243};
244
245void omap_rfbi_write_command(const void *buf, u32 len);
246void omap_rfbi_read_data(void *buf, u32 len);
247void omap_rfbi_write_data(const void *buf, u32 len);
248void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
249 u16 x, u16 y,
250 u16 w, u16 h);
251int omap_rfbi_enable_te(bool enable, unsigned line);
252int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
253 unsigned hs_pulse_time, unsigned vs_pulse_time,
254 int hs_pol_inv, int vs_pol_inv, int extif_div);
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255void rfbi_bus_lock(void);
256void rfbi_bus_unlock(void);
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257
258/* DSI */
8af6ff01 259
6b849375 260struct omap_dss_dsi_videomode_timings {
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261 /* DSI video mode blanking data */
262 /* Unit: byte clock cycles */
263 u16 hsa;
264 u16 hfp;
265 u16 hbp;
266 /* Unit: line clocks */
267 u16 vsa;
268 u16 vfp;
269 u16 vbp;
270
271 /* DSI blanking modes */
272 int blanking_mode;
273 int hsa_blanking_mode;
274 int hbp_blanking_mode;
275 int hfp_blanking_mode;
276
277 /* Video port sync events */
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278 bool vp_vsync_end;
279 bool vp_hsync_end;
280
281 bool ddr_clk_always_on;
282 int window_sync;
283};
284
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285struct omap_dss_dsi_config {
286 enum omap_dss_dsi_mode mode;
287 enum omap_dss_dsi_pixel_format pixel_format;
288 const struct omap_video_timings *timings;
289 const struct omap_dss_dsi_videomode_timings *vm_timings;
290
291 unsigned long hs_clk;
292 unsigned long lp_clk;
293};
294
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295void dsi_bus_lock(struct omap_dss_device *dssdev);
296void dsi_bus_unlock(struct omap_dss_device *dssdev);
297int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
298 int len);
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299int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
300 int len);
301int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd);
302int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel);
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303int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
304 u8 param);
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305int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
306 u8 param);
307int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
308 u8 param1, u8 param2);
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309int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
310 u8 *data, int len);
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311int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
312 u8 *data, int len);
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313int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
314 u8 *buf, int buflen);
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315int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
316 int buflen);
317int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
318 u8 *buf, int buflen);
319int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
320 u8 param1, u8 param2, u8 *buf, int buflen);
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321int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
322 u16 len);
323int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
324int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
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325int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel);
326void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel);
559d6701 327
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328enum omapdss_version {
329 OMAPDSS_VER_UNKNOWN = 0,
330 OMAPDSS_VER_OMAP24xx,
331 OMAPDSS_VER_OMAP34xx_ES1, /* OMAP3430 ES1.0, 2.0 */
332 OMAPDSS_VER_OMAP34xx_ES3, /* OMAP3430 ES3.0+ */
333 OMAPDSS_VER_OMAP3630,
334 OMAPDSS_VER_AM35xx,
335 OMAPDSS_VER_OMAP4430_ES1, /* OMAP4430 ES1.0 */
336 OMAPDSS_VER_OMAP4430_ES2, /* OMAP4430 ES2.0, 2.1, 2.2 */
337 OMAPDSS_VER_OMAP4, /* All other OMAP4s */
338 OMAPDSS_VER_OMAP5,
339};
340
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341/* Board specific data */
342struct omap_dss_board_info {
aac927c9 343 int (*get_context_loss_count)(struct device *dev);
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344 int num_devices;
345 struct omap_dss_device **devices;
346 struct omap_dss_device *default_device;
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347 int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask);
348 void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
62c1dcfc 349 int (*set_min_bus_tput)(struct device *dev, unsigned long r);
acd18af9 350 enum omapdss_version version;
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351};
352
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353/* Init with the board info */
354extern int omap_display_init(struct omap_dss_board_info *board_data);
ee9dfd82 355/* HDMI mux init*/
9a901683 356extern int omap_hdmi_init(enum omap_hdmi_flags flags);
b7ee79ab 357
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358struct omap_video_timings {
359 /* Unit: pixels */
360 u16 x_res;
361 /* Unit: pixels */
362 u16 y_res;
363 /* Unit: KHz */
364 u32 pixel_clock;
365 /* Unit: pixel clocks */
366 u16 hsw; /* Horizontal synchronization pulse width */
367 /* Unit: pixel clocks */
368 u16 hfp; /* Horizontal front porch */
369 /* Unit: pixel clocks */
370 u16 hbp; /* Horizontal back porch */
371 /* Unit: line clocks */
372 u16 vsw; /* Vertical synchronization pulse width */
373 /* Unit: line clocks */
374 u16 vfp; /* Vertical front porch */
375 /* Unit: line clocks */
376 u16 vbp; /* Vertical back porch */
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377
378 /* Vsync logic level */
379 enum omap_dss_signal_level vsync_level;
380 /* Hsync logic level */
381 enum omap_dss_signal_level hsync_level;
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382 /* Interlaced or Progressive timings */
383 bool interlace;
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384 /* Pixel clock edge to drive LCD data */
385 enum omap_dss_signal_edge data_pclk_edge;
386 /* Data enable logic level */
387 enum omap_dss_signal_level de_level;
388 /* Pixel clock edges to drive HSYNC and VSYNC signals */
389 enum omap_dss_signal_edge sync_pclk_edge;
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390};
391
392#ifdef CONFIG_OMAP2_DSS_VENC
393/* Hardcoded timings for tv modes. Venc only uses these to
394 * identify the mode, and does not actually use the configs
395 * itself. However, the configs should be something that
396 * a normal monitor can also show */
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397extern const struct omap_video_timings omap_dss_pal_timings;
398extern const struct omap_video_timings omap_dss_ntsc_timings;
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399#endif
400
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401struct omap_dss_cpr_coefs {
402 s16 rr, rg, rb;
403 s16 gr, gg, gb;
404 s16 br, bg, bb;
405};
406
559d6701 407struct omap_overlay_info {
559d6701 408 u32 paddr;
0d66cbb5 409 u32 p_uv_addr; /* for NV12 format */
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410 u16 screen_width;
411 u16 width;
412 u16 height;
413 enum omap_color_mode color_mode;
414 u8 rotation;
415 enum omap_dss_rotation_type rotation_type;
416 bool mirror;
417
418 u16 pos_x;
419 u16 pos_y;
420 u16 out_width; /* if 0, out_width == width */
421 u16 out_height; /* if 0, out_height == height */
422 u8 global_alpha;
fd28a390 423 u8 pre_mult_alpha;
54128701 424 u8 zorder;
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425};
426
427struct omap_overlay {
428 struct kobject kobj;
429 struct list_head list;
430
431 /* static fields */
432 const char *name;
4a9e78ab 433 enum omap_plane id;
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434 enum omap_color_mode supported_modes;
435 enum omap_overlay_caps caps;
436
437 /* dynamic fields */
438 struct omap_overlay_manager *manager;
559d6701 439
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440 /*
441 * The following functions do not block:
442 *
443 * is_enabled
444 * set_overlay_info
445 * get_overlay_info
446 *
447 * The rest of the functions may block and cannot be called from
448 * interrupt context
449 */
450
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451 int (*enable)(struct omap_overlay *ovl);
452 int (*disable)(struct omap_overlay *ovl);
453 bool (*is_enabled)(struct omap_overlay *ovl);
454
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455 int (*set_manager)(struct omap_overlay *ovl,
456 struct omap_overlay_manager *mgr);
457 int (*unset_manager)(struct omap_overlay *ovl);
458
459 int (*set_overlay_info)(struct omap_overlay *ovl,
460 struct omap_overlay_info *info);
461 void (*get_overlay_info)(struct omap_overlay *ovl,
462 struct omap_overlay_info *info);
463
464 int (*wait_for_go)(struct omap_overlay *ovl);
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465
466 struct omap_dss_device *(*get_device)(struct omap_overlay *ovl);
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467};
468
469struct omap_overlay_manager_info {
470 u32 default_color;
471
472 enum omap_dss_trans_key_type trans_key_type;
473 u32 trans_key;
474 bool trans_enabled;
475
11354dd5 476 bool partial_alpha_enabled;
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477
478 bool cpr_enable;
479 struct omap_dss_cpr_coefs cpr_coefs;
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480};
481
482struct omap_overlay_manager {
483 struct kobject kobj;
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484
485 /* static fields */
486 const char *name;
4a9e78ab 487 enum omap_channel id;
559d6701 488 enum omap_overlay_manager_caps caps;
07e327c9 489 struct list_head overlays;
559d6701 490 enum omap_display_type supported_displays;
97f01b3a 491 enum omap_dss_output_id supported_outputs;
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492
493 /* dynamic fields */
97f01b3a 494 struct omap_dss_output *output;
559d6701 495
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496 /*
497 * The following functions do not block:
498 *
499 * set_manager_info
500 * get_manager_info
501 * apply
502 *
503 * The rest of the functions may block and cannot be called from
504 * interrupt context
505 */
506
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507 int (*set_output)(struct omap_overlay_manager *mgr,
508 struct omap_dss_output *output);
509 int (*unset_output)(struct omap_overlay_manager *mgr);
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510
511 int (*set_manager_info)(struct omap_overlay_manager *mgr,
512 struct omap_overlay_manager_info *info);
513 void (*get_manager_info)(struct omap_overlay_manager *mgr,
514 struct omap_overlay_manager_info *info);
515
516 int (*apply)(struct omap_overlay_manager *mgr);
517 int (*wait_for_go)(struct omap_overlay_manager *mgr);
3f71cbe7 518 int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
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519
520 struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr);
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521};
522
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523/* 22 pins means 1 clk lane and 10 data lanes */
524#define OMAP_DSS_MAX_DSI_PINS 22
525
526struct omap_dsi_pin_config {
527 int num_pins;
528 /*
529 * pin numbers in the following order:
530 * clk+, clk-
531 * data1+, data1-
532 * data2+, data2-
533 * ...
534 */
535 int pins[OMAP_DSS_MAX_DSI_PINS];
536};
537
749feffa
AT
538struct omap_dss_writeback_info {
539 u32 paddr;
540 u32 p_uv_addr;
541 u16 buf_width;
542 u16 width;
543 u16 height;
544 enum omap_color_mode color_mode;
545 u8 rotation;
546 enum omap_dss_rotation_type rotation_type;
547 bool mirror;
548 u8 pre_mult_alpha;
549};
550
484dc404
AT
551struct omap_dss_output {
552 struct list_head list;
553
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554 const char *name;
555
484dc404
AT
556 /* display type supported by the output */
557 enum omap_display_type type;
558
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559 /* DISPC channel for this output */
560 enum omap_channel dispc_channel;
561
484dc404
AT
562 /* output instance */
563 enum omap_dss_output_id id;
564
565 /* output's platform device pointer */
566 struct platform_device *pdev;
567
568 /* dynamic fields */
569 struct omap_overlay_manager *manager;
570
571 struct omap_dss_device *device;
572};
573
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574struct omap_dss_device {
575 struct device dev;
576
577 enum omap_display_type type;
578
2eea5ae6 579 /* obsolete, to be removed */
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580 enum omap_channel channel;
581
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582 union {
583 struct {
584 u8 data_lines;
585 } dpi;
586
587 struct {
588 u8 channel;
589 u8 data_lines;
590 } rfbi;
591
592 struct {
593 u8 datapairs;
594 } sdi;
595
596 struct {
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AT
597 int module;
598
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599 bool ext_te;
600 u8 ext_te_gpio;
601 } dsi;
602
603 struct {
604 enum omap_dss_venc_type type;
605 bool invert_polarity;
606 } venc;
607 } phy;
608
609 struct {
610 struct omap_video_timings timings;
611
a3b3cc2b 612 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
7e951ee9 613 enum omap_dss_dsi_mode dsi_mode;
6b849375 614 struct omap_dss_dsi_videomode_timings dsi_vm_timings;
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615 } panel;
616
617 struct {
618 u8 pixel_size;
619 struct rfbi_timings rfbi_timings;
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620 } ctrl;
621
622 int reset_gpio;
623
624 int max_backlight_level;
625
626 const char *name;
627
628 /* used to match device to driver */
629 const char *driver_name;
630
631 void *data;
632
633 struct omap_dss_driver *driver;
634
635 /* helper variable for driver suspend/resume */
636 bool activate_after_resume;
637
638 enum omap_display_caps caps;
639
6d71b923 640 struct omap_dss_output *output;
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641
642 enum omap_dss_display_state state;
643
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644 enum omap_dss_audio_state audio_state;
645
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646 /* platform specific */
647 int (*platform_enable)(struct omap_dss_device *dssdev);
648 void (*platform_disable)(struct omap_dss_device *dssdev);
649 int (*set_backlight)(struct omap_dss_device *dssdev, int level);
650 int (*get_backlight)(struct omap_dss_device *dssdev);
651};
652
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653struct omap_dss_hdmi_data
654{
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655 int ct_cp_hpd_gpio;
656 int ls_oe_gpio;
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657 int hpd_gpio;
658};
659
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660struct omap_dss_audio {
661 struct snd_aes_iec958 *iec;
662 struct snd_cea_861_aud_if *cea;
663};
664
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665struct omap_dss_driver {
666 struct device_driver driver;
667
668 int (*probe)(struct omap_dss_device *);
669 void (*remove)(struct omap_dss_device *);
670
671 int (*enable)(struct omap_dss_device *display);
672 void (*disable)(struct omap_dss_device *display);
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673 int (*run_test)(struct omap_dss_device *display, int test);
674
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675 int (*update)(struct omap_dss_device *dssdev,
676 u16 x, u16 y, u16 w, u16 h);
677 int (*sync)(struct omap_dss_device *dssdev);
678
559d6701 679 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
225b650d 680 int (*get_te)(struct omap_dss_device *dssdev);
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681
682 u8 (*get_rotate)(struct omap_dss_device *dssdev);
683 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
684
685 bool (*get_mirror)(struct omap_dss_device *dssdev);
686 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
687
688 int (*memory_read)(struct omap_dss_device *dssdev,
689 void *buf, size_t size,
690 u16 x, u16 y, u16 w, u16 h);
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691
692 void (*get_resolution)(struct omap_dss_device *dssdev,
693 u16 *xres, u16 *yres);
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694 void (*get_dimensions)(struct omap_dss_device *dssdev,
695 u32 *width, u32 *height);
a2699504 696 int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
36511312 697
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698 int (*check_timings)(struct omap_dss_device *dssdev,
699 struct omap_video_timings *timings);
700 void (*set_timings)(struct omap_dss_device *dssdev,
701 struct omap_video_timings *timings);
702 void (*get_timings)(struct omap_dss_device *dssdev,
703 struct omap_video_timings *timings);
704
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705 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
706 u32 (*get_wss)(struct omap_dss_device *dssdev);
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707
708 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
df4769c9 709 bool (*detect)(struct omap_dss_device *dssdev);
9c0b8420
RN
710
711 /*
712 * For display drivers that support audio. This encompasses
713 * HDMI and DisplayPort at the moment.
714 */
715 /*
716 * Note: These functions might sleep. Do not call while
717 * holding a spinlock/readlock.
718 */
719 int (*audio_enable)(struct omap_dss_device *dssdev);
720 void (*audio_disable)(struct omap_dss_device *dssdev);
721 bool (*audio_supported)(struct omap_dss_device *dssdev);
722 int (*audio_config)(struct omap_dss_device *dssdev,
723 struct omap_dss_audio *audio);
724 /* Note: These functions may not sleep */
725 int (*audio_start)(struct omap_dss_device *dssdev);
726 void (*audio_stop)(struct omap_dss_device *dssdev);
727
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728};
729
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730enum omapdss_version omapdss_get_version(void);
731
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732int omap_dss_register_driver(struct omap_dss_driver *);
733void omap_dss_unregister_driver(struct omap_dss_driver *);
734
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735void omap_dss_get_device(struct omap_dss_device *dssdev);
736void omap_dss_put_device(struct omap_dss_device *dssdev);
737#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
738struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
739struct omap_dss_device *omap_dss_find_device(void *data,
740 int (*match)(struct omap_dss_device *dssdev, void *data));
2bbcce5e 741const char *omapdss_get_default_display_name(void);
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742
743int omap_dss_start_device(struct omap_dss_device *dssdev);
744void omap_dss_stop_device(struct omap_dss_device *dssdev);
745
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746int dss_feat_get_num_mgrs(void);
747int dss_feat_get_num_ovls(void);
748enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel);
749enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel);
750enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
751
752
753
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754int omap_dss_get_num_overlay_managers(void);
755struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
756
757int omap_dss_get_num_overlays(void);
758struct omap_overlay *omap_dss_get_overlay(int num);
759
484dc404 760struct omap_dss_output *omap_dss_get_output(enum omap_dss_output_id id);
6d71b923
AT
761int omapdss_output_set_device(struct omap_dss_output *out,
762 struct omap_dss_device *dssdev);
763int omapdss_output_unset_device(struct omap_dss_output *out);
484dc404 764
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765void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
766 u16 *xres, u16 *yres);
a2699504 767int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
4b6430fc
GI
768void omapdss_default_get_timings(struct omap_dss_device *dssdev,
769 struct omap_video_timings *timings);
a2699504 770
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771typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
772int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
773int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
774
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775u32 dispc_read_irqstatus(void);
776void dispc_clear_irqstatus(u32 mask);
777u32 dispc_read_irqenable(void);
778void dispc_write_irqenable(u32 mask);
779
780int dispc_request_irq(irq_handler_t handler, void *dev_id);
781void dispc_free_irq(void *dev_id);
782
783int dispc_runtime_get(void);
784void dispc_runtime_put(void);
785
786void dispc_mgr_enable(enum omap_channel channel, bool enable);
787bool dispc_mgr_is_enabled(enum omap_channel channel);
788u32 dispc_mgr_get_vsync_irq(enum omap_channel channel);
789u32 dispc_mgr_get_framedone_irq(enum omap_channel channel);
790u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel);
791bool dispc_mgr_go_busy(enum omap_channel channel);
792void dispc_mgr_go(enum omap_channel channel);
793void dispc_mgr_set_lcd_config(enum omap_channel channel,
794 const struct dss_lcd_mgr_config *config);
795void dispc_mgr_set_timings(enum omap_channel channel,
796 const struct omap_video_timings *timings);
797void dispc_mgr_setup(enum omap_channel channel,
798 const struct omap_overlay_manager_info *info);
799
800int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
801 const struct omap_overlay_info *oi,
802 const struct omap_video_timings *timings,
803 int *x_predecim, int *y_predecim);
804
805int dispc_ovl_enable(enum omap_plane plane, bool enable);
806bool dispc_ovl_enabled(enum omap_plane plane);
807void dispc_ovl_set_channel_out(enum omap_plane plane,
808 enum omap_channel channel);
809int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
810 bool replication, const struct omap_video_timings *mgr_timings,
811 bool mem_to_mem);
812
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TV
813#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
814#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
815
1ffefe75
AT
816void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
817 bool enable);
225b650d 818int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
777f05cc
TV
819int omapdss_dsi_set_config(struct omap_dss_device *dssdev,
820 const struct omap_dss_dsi_config *config);
61140c9a 821
5476e74a 822int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
18946f62 823 void (*callback)(int, void *), void *data);
5ee3c144
AT
824int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
825int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
826void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
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TV
827int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev,
828 const struct omap_dsi_pin_config *pin_cfg);
18946f62 829
37ac60e4 830int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
2a89dc15 831void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
22d6d676 832 bool disconnect_lanes, bool enter_ulps);
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TV
833
834int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
835void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
c499144c
AT
836void omapdss_dpi_set_timings(struct omap_dss_device *dssdev,
837 struct omap_video_timings *timings);
69b2048f
TV
838int dpi_check_timings(struct omap_dss_device *dssdev,
839 struct omap_video_timings *timings);
c6b393d4 840void omapdss_dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines);
37ac60e4
TV
841
842int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
843void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
c7833f7b
AT
844void omapdss_sdi_set_timings(struct omap_dss_device *dssdev,
845 struct omap_video_timings *timings);
889b4fd7 846void omapdss_sdi_set_datapairs(struct omap_dss_device *dssdev, int datapairs);
37ac60e4
TV
847
848int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
849void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
43eab861
AT
850int omap_rfbi_update(struct omap_dss_device *dssdev, void (*callback)(void *),
851 void *data);
475989b7 852int omap_rfbi_configure(struct omap_dss_device *dssdev);
6ff9dd5a 853void omapdss_rfbi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h);
b02875be
AT
854void omapdss_rfbi_set_pixel_size(struct omap_dss_device *dssdev,
855 int pixel_size);
475989b7
AT
856void omapdss_rfbi_set_data_lines(struct omap_dss_device *dssdev,
857 int data_lines);
6e883324
AT
858void omapdss_rfbi_set_interface_timings(struct omap_dss_device *dssdev,
859 struct rfbi_timings *timings);
18946f62 860
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TV
861int omapdss_compat_init(void);
862void omapdss_compat_uninit(void);
863
a97a9634
TV
864struct dss_mgr_ops {
865 void (*start_update)(struct omap_overlay_manager *mgr);
866 int (*enable)(struct omap_overlay_manager *mgr);
867 void (*disable)(struct omap_overlay_manager *mgr);
868 void (*set_timings)(struct omap_overlay_manager *mgr,
869 const struct omap_video_timings *timings);
870 void (*set_lcd_config)(struct omap_overlay_manager *mgr,
871 const struct dss_lcd_mgr_config *config);
872 int (*register_framedone_handler)(struct omap_overlay_manager *mgr,
873 void (*handler)(void *), void *data);
874 void (*unregister_framedone_handler)(struct omap_overlay_manager *mgr,
875 void (*handler)(void *), void *data);
876};
877
878int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops);
879void dss_uninstall_mgr_ops(void);
880
881void dss_mgr_set_timings(struct omap_overlay_manager *mgr,
882 const struct omap_video_timings *timings);
883void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr,
884 const struct dss_lcd_mgr_config *config);
885int dss_mgr_enable(struct omap_overlay_manager *mgr);
886void dss_mgr_disable(struct omap_overlay_manager *mgr);
887void dss_mgr_start_update(struct omap_overlay_manager *mgr);
888int dss_mgr_register_framedone_handler(struct omap_overlay_manager *mgr,
889 void (*handler)(void *), void *data);
890void dss_mgr_unregister_framedone_handler(struct omap_overlay_manager *mgr,
891 void (*handler)(void *), void *data);
559d6701 892#endif