projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
OMAPDSS/OMAP_VOUT: Fix incorrect OMAP3-alpha compatibility setting
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / video / omapdss.h
CommitLineData
559d6701 1/*
559d6701
TV		 2 * Copyright (C) 2008 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
a0b38cc4
TV		 18#ifndef __OMAP_OMAPDSS_H
19#define __OMAP_OMAPDSS_H
559d6701
TV		 20
21#include <linux/list.h>
22#include <linux/kobject.h>
23#include <linux/device.h>
559d6701
TV		 24
25#define DISPC_IRQ_FRAMEDONE (1 << 0)
26#define DISPC_IRQ_VSYNC (1 << 1)
27#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
28#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
29#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
30#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
31#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
32#define DISPC_IRQ_GFX_END_WIN (1 << 7)
33#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
34#define DISPC_IRQ_OCP_ERR (1 << 9)
35#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
36#define DISPC_IRQ_VID1_END_WIN (1 << 11)
37#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
38#define DISPC_IRQ_VID2_END_WIN (1 << 13)
39#define DISPC_IRQ_SYNC_LOST (1 << 14)
40#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
41#define DISPC_IRQ_WAKEUP (1 << 16)
2a205f34
SS		 42#define DISPC_IRQ_SYNC_LOST2 (1 << 17)
43#define DISPC_IRQ_VSYNC2 (1 << 18)
44#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
45#define DISPC_IRQ_FRAMEDONE2 (1 << 22)
7f6f3c4b
TV		 46#define DISPC_IRQ_FRAMEDONEWB (1 << 23)
47#define DISPC_IRQ_FRAMEDONETV (1 << 24)
48#define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
559d6701
TV		 49
50struct omap_dss_device;
51struct omap_overlay_manager;
52
53enum omap_display_type {
54 OMAP_DISPLAY_TYPE_NONE = 0,
55 OMAP_DISPLAY_TYPE_DPI = 1 << 0,
56 OMAP_DISPLAY_TYPE_DBI = 1 << 1,
57 OMAP_DISPLAY_TYPE_SDI = 1 << 2,
58 OMAP_DISPLAY_TYPE_DSI = 1 << 3,
59 OMAP_DISPLAY_TYPE_VENC = 1 << 4,
b119601d 60 OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
559d6701
TV		 61};
62
63enum omap_plane {
64 OMAP_DSS_GFX = 0,
65 OMAP_DSS_VIDEO1 = 1,
66 OMAP_DSS_VIDEO2 = 2
67};
68
69enum omap_channel {
70 OMAP_DSS_CHANNEL_LCD = 0,
71 OMAP_DSS_CHANNEL_DIGIT = 1,
8613b000 72 OMAP_DSS_CHANNEL_LCD2 = 2,
559d6701
TV		 73};
74
75enum omap_color_mode {
76 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
77 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
78 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
79 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
80 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
81 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
82 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
83 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
84 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
85 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
86 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
87 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
88 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
89 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
f20e4220
AJ		 90 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
91 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
92 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
93 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
94 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
559d6701
TV		 95};
96
97enum omap_lcd_display_type {
98 OMAP_DSS_LCD_DISPLAY_STN,
99 OMAP_DSS_LCD_DISPLAY_TFT,
100};
101
102enum omap_dss_load_mode {
103 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
104 OMAP_DSS_LOAD_CLUT_ONLY = 1,
105 OMAP_DSS_LOAD_FRAME_ONLY = 2,
106 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
107};
108
109enum omap_dss_trans_key_type {
110 OMAP_DSS_COLOR_KEY_GFX_DST = 0,
111 OMAP_DSS_COLOR_KEY_VID_SRC = 1,
112};
113
114enum omap_rfbi_te_mode {
115 OMAP_DSS_RFBI_TE_MODE_1 = 1,
116 OMAP_DSS_RFBI_TE_MODE_2 = 2,
117};
118
119enum omap_panel_config {
120 OMAP_DSS_LCD_IVS = 1<<0,
121 OMAP_DSS_LCD_IHS = 1<<1,
122 OMAP_DSS_LCD_IPC = 1<<2,
123 OMAP_DSS_LCD_IEO = 1<<3,
124 OMAP_DSS_LCD_RF = 1<<4,
125 OMAP_DSS_LCD_ONOFF = 1<<5,
126
127 OMAP_DSS_LCD_TFT = 1<<20,
128};
129
130enum omap_dss_venc_type {
131 OMAP_DSS_VENC_TYPE_COMPOSITE,
132 OMAP_DSS_VENC_TYPE_SVIDEO,
133};
134
a3b3cc2b
AT		 135enum omap_dss_dsi_pixel_format {
136 OMAP_DSS_DSI_FMT_RGB888,
137 OMAP_DSS_DSI_FMT_RGB666,
138 OMAP_DSS_DSI_FMT_RGB666_PACKED,
139 OMAP_DSS_DSI_FMT_RGB565,
140};
141
7e951ee9
AT		 142enum omap_dss_dsi_mode {
143 OMAP_DSS_DSI_CMD_MODE = 0,
144 OMAP_DSS_DSI_VIDEO_MODE,
145};
146
559d6701
TV		 147enum omap_display_caps {
148 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
149 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
150};
151
559d6701
TV		 152enum omap_dss_display_state {
153 OMAP_DSS_DISPLAY_DISABLED = 0,
154 OMAP_DSS_DISPLAY_ACTIVE,
155 OMAP_DSS_DISPLAY_SUSPENDED,
156};
157
158/* XXX perhaps this should be removed */
159enum omap_dss_overlay_managers {
160 OMAP_DSS_OVL_MGR_LCD,
161 OMAP_DSS_OVL_MGR_TV,
8613b000 162 OMAP_DSS_OVL_MGR_LCD2,
559d6701
TV		 163};
164
165enum omap_dss_rotation_type {
166 OMAP_DSS_ROT_DMA = 0,
167 OMAP_DSS_ROT_VRFB = 1,
168};
169
170/* clockwise rotation angle */
171enum omap_dss_rotation_angle {
172 OMAP_DSS_ROT_0 = 0,
173 OMAP_DSS_ROT_90 = 1,
174 OMAP_DSS_ROT_180 = 2,
175 OMAP_DSS_ROT_270 = 3,
176};
177
178enum omap_overlay_caps {
179 OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
f6dc8150
TV		 180 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
181 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
11354dd5 182 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
559d6701
TV		 183};
184
185enum omap_overlay_manager_caps {
4a9e78ab 186 OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */
559d6701
TV		 187};
188
89a35e51
AT		 189enum omap_dss_clk_source {
190 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
191 * OMAP4: DSS_FCLK */
192 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
193 * OMAP4: PLL1_CLK1 */
194 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
195 * OMAP4: PLL1_CLK2 */
5a8b572d
AT		 196 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
197 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
89a35e51
AT		 198};
199
559d6701
TV		 200/* RFBI */
201
202struct rfbi_timings {
203 int cs_on_time;
204 int cs_off_time;
205 int we_on_time;
206 int we_off_time;
207 int re_on_time;
208 int re_off_time;
209 int we_cycle_time;
210 int re_cycle_time;
211 int cs_pulse_width;
212 int access_time;
213
214 int clk_div;
215
216 u32 tim[5]; /* set by rfbi_convert_timings() */
217
218 int converted;
219};
220
221void omap_rfbi_write_command(const void *buf, u32 len);
222void omap_rfbi_read_data(void *buf, u32 len);
223void omap_rfbi_write_data(const void *buf, u32 len);
224void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
225 u16 x, u16 y,
226 u16 w, u16 h);
227int omap_rfbi_enable_te(bool enable, unsigned line);
228int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
229 unsigned hs_pulse_time, unsigned vs_pulse_time,
230 int hs_pol_inv, int vs_pol_inv, int extif_div);
773139f1
TV		 231void rfbi_bus_lock(void);
232void rfbi_bus_unlock(void);
559d6701
TV		 233
234/* DSI */
8af6ff01
AT		 235
236struct omap_dss_dsi_videomode_data {
237 /* DSI video mode blanking data */
238 /* Unit: byte clock cycles */
239 u16 hsa;
240 u16 hfp;
241 u16 hbp;
242 /* Unit: line clocks */
243 u16 vsa;
244 u16 vfp;
245 u16 vbp;
246
247 /* DSI blanking modes */
248 int blanking_mode;
249 int hsa_blanking_mode;
250 int hbp_blanking_mode;
251 int hfp_blanking_mode;
252
253 /* Video port sync events */
254 int vp_de_pol;
255 int vp_hsync_pol;
256 int vp_vsync_pol;
257 bool vp_vsync_end;
258 bool vp_hsync_end;
259
260 bool ddr_clk_always_on;
261 int window_sync;
262};
263
1ffefe75
AT		 264void dsi_bus_lock(struct omap_dss_device *dssdev);
265void dsi_bus_unlock(struct omap_dss_device *dssdev);
266int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
267 int len);
6ff8aa31
AT		 268int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
269 int len);
270int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd);
271int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel);
1ffefe75
AT		 272int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
273 u8 param);
6ff8aa31
AT		 274int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
275 u8 param);
276int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
277 u8 param1, u8 param2);
1ffefe75
AT		 278int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
279 u8 *data, int len);
6ff8aa31
AT		 280int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
281 u8 *data, int len);
1ffefe75
AT		 282int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
283 u8 *buf, int buflen);
b3b89c05
AT		 284int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
285 int buflen);
286int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
287 u8 *buf, int buflen);
288int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
289 u8 param1, u8 param2, u8 *buf, int buflen);
1ffefe75
AT		 290int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
291 u16 len);
292int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
293int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
8af6ff01
AT		 294int dsi_video_mode_enable(struct omap_dss_device *dssdev, int channel);
295void dsi_video_mode_disable(struct omap_dss_device *dssdev, int channel);
559d6701
TV		 296
297/* Board specific data */
298struct omap_dss_board_info {
aac927c9 299 int (*get_context_loss_count)(struct device *dev);
559d6701
TV		 300 int num_devices;
301 struct omap_dss_device **devices;
302 struct omap_dss_device *default_device;
5bc416cb
TV		 303 int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask);
304 void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
559d6701
TV		 305};
306
b7ee79ab
SS		 307#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
308/* Init with the board info */
309extern int omap_display_init(struct omap_dss_board_info *board_data);
310#else
311static inline int omap_display_init(struct omap_dss_board_info *board_data)
312{
313 return 0;
314}
315#endif
316
cf07f531
SG		 317struct omap_display_platform_data {
318 struct omap_dss_board_info *board_data;
319 /* TODO: Additional members to be added when PM is considered */
320};
321
559d6701
TV		 322struct omap_video_timings {
323 /* Unit: pixels */
324 u16 x_res;
325 /* Unit: pixels */
326 u16 y_res;
327 /* Unit: KHz */
328 u32 pixel_clock;
329 /* Unit: pixel clocks */
330 u16 hsw; /* Horizontal synchronization pulse width */
331 /* Unit: pixel clocks */
332 u16 hfp; /* Horizontal front porch */
333 /* Unit: pixel clocks */
334 u16 hbp; /* Horizontal back porch */
335 /* Unit: line clocks */
336 u16 vsw; /* Vertical synchronization pulse width */
337 /* Unit: line clocks */
338 u16 vfp; /* Vertical front porch */
339 /* Unit: line clocks */
340 u16 vbp; /* Vertical back porch */
341};
342
343#ifdef CONFIG_OMAP2_DSS_VENC
344/* Hardcoded timings for tv modes. Venc only uses these to
345 * identify the mode, and does not actually use the configs
346 * itself. However, the configs should be something that
347 * a normal monitor can also show */
5a1819e3
TK		 348extern const struct omap_video_timings omap_dss_pal_timings;
349extern const struct omap_video_timings omap_dss_ntsc_timings;
559d6701
TV		 350#endif
351
3c07cae2
TV		 352struct omap_dss_cpr_coefs {
353 s16 rr, rg, rb;
354 s16 gr, gg, gb;
355 s16 br, bg, bb;
356};
357
559d6701
TV		 358struct omap_overlay_info {
359 bool enabled;
360
361 u32 paddr;
0d66cbb5 362 u32 p_uv_addr; /* for NV12 format */
559d6701
TV		 363 u16 screen_width;
364 u16 width;
365 u16 height;
366 enum omap_color_mode color_mode;
367 u8 rotation;
368 enum omap_dss_rotation_type rotation_type;
369 bool mirror;
370
371 u16 pos_x;
372 u16 pos_y;
373 u16 out_width; /* if 0, out_width == width */
374 u16 out_height; /* if 0, out_height == height */
375 u8 global_alpha;
fd28a390 376 u8 pre_mult_alpha;
559d6701
TV		 377};
378
379struct omap_overlay {
380 struct kobject kobj;
381 struct list_head list;
382
383 /* static fields */
384 const char *name;
4a9e78ab 385 enum omap_plane id;
559d6701
TV		 386 enum omap_color_mode supported_modes;
387 enum omap_overlay_caps caps;
388
389 /* dynamic fields */
390 struct omap_overlay_manager *manager;
391 struct omap_overlay_info info;
392
8fa8031c 393 bool manager_changed;
559d6701
TV		 394 /* if true, info has been changed, but not applied() yet */
395 bool info_dirty;
396
397 int (*set_manager)(struct omap_overlay *ovl,
398 struct omap_overlay_manager *mgr);
399 int (*unset_manager)(struct omap_overlay *ovl);
400
401 int (*set_overlay_info)(struct omap_overlay *ovl,
402 struct omap_overlay_info *info);
403 void (*get_overlay_info)(struct omap_overlay *ovl,
404 struct omap_overlay_info *info);
405
406 int (*wait_for_go)(struct omap_overlay *ovl);
407};
408
409struct omap_overlay_manager_info {
410 u32 default_color;
411
412 enum omap_dss_trans_key_type trans_key_type;
413 u32 trans_key;
414 bool trans_enabled;
415
11354dd5 416 bool partial_alpha_enabled;
3c07cae2
TV		 417
418 bool cpr_enable;
419 struct omap_dss_cpr_coefs cpr_coefs;
559d6701
TV		 420};
421
422struct omap_overlay_manager {
423 struct kobject kobj;
424 struct list_head list;
425
426 /* static fields */
427 const char *name;
4a9e78ab 428 enum omap_channel id;
559d6701
TV		 429 enum omap_overlay_manager_caps caps;
430 int num_overlays;
431 struct omap_overlay **overlays;
432 enum omap_display_type supported_displays;
433
434 /* dynamic fields */
435 struct omap_dss_device *device;
436 struct omap_overlay_manager_info info;
437
438 bool device_changed;
439 /* if true, info has been changed but not applied() yet */
440 bool info_dirty;
441
442 int (*set_device)(struct omap_overlay_manager *mgr,
443 struct omap_dss_device *dssdev);
444 int (*unset_device)(struct omap_overlay_manager *mgr);
445
446 int (*set_manager_info)(struct omap_overlay_manager *mgr,
447 struct omap_overlay_manager_info *info);
448 void (*get_manager_info)(struct omap_overlay_manager *mgr,
449 struct omap_overlay_manager_info *info);
450
451 int (*apply)(struct omap_overlay_manager *mgr);
452 int (*wait_for_go)(struct omap_overlay_manager *mgr);
3f71cbe7 453 int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
a2faee84
TV		 454
455 int (*enable)(struct omap_overlay_manager *mgr);
456 int (*disable)(struct omap_overlay_manager *mgr);
559d6701
TV		 457};
458
459struct omap_dss_device {
460 struct device dev;
461
462 enum omap_display_type type;
463
18faa1b6
SS		 464 enum omap_channel channel;
465
559d6701
TV		 466 union {
467 struct {
468 u8 data_lines;
469 } dpi;
470
471 struct {
472 u8 channel;
473 u8 data_lines;
474 } rfbi;
475
476 struct {
477 u8 datapairs;
478 } sdi;
479
480 struct {
481 u8 clk_lane;
482 u8 clk_pol;
483 u8 data1_lane;
484 u8 data1_pol;
485 u8 data2_lane;
486 u8 data2_pol;
75d7247c
AT		 487 u8 data3_lane;
488 u8 data3_pol;
489 u8 data4_lane;
490 u8 data4_pol;
559d6701 491
a72b64b9
AT		 492 int module;
493
559d6701
TV		 494 bool ext_te;
495 u8 ext_te_gpio;
496 } dsi;
497
498 struct {
499 enum omap_dss_venc_type type;
500 bool invert_polarity;
501 } venc;
502 } phy;
503
c6940a3d
TV		 504 struct {
505 struct {
e8881662
AT		 506 struct {
507 u16 lck_div;
508 u16 pck_div;
509 enum omap_dss_clk_source lcd_clk_src;
510 } channel;
511
512 enum omap_dss_clk_source dispc_fclk_src;
c6940a3d
TV		 513 } dispc;
514
515 struct {
c90a78ec 516 /* regn is one greater than TRM's REGN value */
c6940a3d
TV		 517 u16 regn;
518 u16 regm;
519 u16 regm_dispc;
520 u16 regm_dsi;
521
522 u16 lp_clk_div;
e8881662 523 enum omap_dss_clk_source dsi_fclk_src;
c6940a3d 524 } dsi;
6cb07b25
AT		 525
526 struct {
b44e4582 527 /* regn is one greater than TRM's REGN value */
6cb07b25
AT		 528 u16 regn;
529 u16 regm2;
530 } hdmi;
c6940a3d
TV		 531 } clocks;
532
559d6701
TV		 533 struct {
534 struct omap_video_timings timings;
535
536 int acbi; /* ac-bias pin transitions per interrupt */
537 /* Unit: line clocks */
538 int acb; /* ac-bias pin frequency */
539
540 enum omap_panel_config config;
7e951ee9 541
a3b3cc2b 542 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
7e951ee9 543 enum omap_dss_dsi_mode dsi_mode;
8af6ff01 544 struct omap_dss_dsi_videomode_data dsi_vm_data;
559d6701
TV		 545 } panel;
546
547 struct {
548 u8 pixel_size;
549 struct rfbi_timings rfbi_timings;
559d6701
TV		 550 } ctrl;
551
552 int reset_gpio;
553
554 int max_backlight_level;
555
556 const char *name;
557
558 /* used to match device to driver */
559 const char *driver_name;
560
561 void *data;
562
563 struct omap_dss_driver *driver;
564
565 /* helper variable for driver suspend/resume */
566 bool activate_after_resume;
567
568 enum omap_display_caps caps;
569
570 struct omap_overlay_manager *manager;
571
572 enum omap_dss_display_state state;
573
559d6701
TV		 574 /* platform specific */
575 int (*platform_enable)(struct omap_dss_device *dssdev);
576 void (*platform_disable)(struct omap_dss_device *dssdev);
577 int (*set_backlight)(struct omap_dss_device *dssdev, int level);
578 int (*get_backlight)(struct omap_dss_device *dssdev);
579};
580
581struct omap_dss_driver {
582 struct device_driver driver;
583
584 int (*probe)(struct omap_dss_device *);
585 void (*remove)(struct omap_dss_device *);
586
587 int (*enable)(struct omap_dss_device *display);
588 void (*disable)(struct omap_dss_device *display);
589 int (*suspend)(struct omap_dss_device *display);
590 int (*resume)(struct omap_dss_device *display);
591 int (*run_test)(struct omap_dss_device *display, int test);
592
18946f62
TV		 593 int (*update)(struct omap_dss_device *dssdev,
594 u16 x, u16 y, u16 w, u16 h);
595 int (*sync)(struct omap_dss_device *dssdev);
596
559d6701 597 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
225b650d 598 int (*get_te)(struct omap_dss_device *dssdev);
559d6701
TV		 599
600 u8 (*get_rotate)(struct omap_dss_device *dssdev);
601 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
602
603 bool (*get_mirror)(struct omap_dss_device *dssdev);
604 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
605
606 int (*memory_read)(struct omap_dss_device *dssdev,
607 void *buf, size_t size,
608 u16 x, u16 y, u16 w, u16 h);
96adcece
TV		 609
610 void (*get_resolution)(struct omap_dss_device *dssdev,
611 u16 *xres, u16 *yres);
7a0987bf
JN		 612 void (*get_dimensions)(struct omap_dss_device *dssdev,
613 u32 *width, u32 *height);
a2699504 614 int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
36511312 615
69b2048f
TV		 616 int (*check_timings)(struct omap_dss_device *dssdev,
617 struct omap_video_timings *timings);
618 void (*set_timings)(struct omap_dss_device *dssdev,
619 struct omap_video_timings *timings);
620 void (*get_timings)(struct omap_dss_device *dssdev,
621 struct omap_video_timings *timings);
622
36511312
TV		 623 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
624 u32 (*get_wss)(struct omap_dss_device *dssdev);
3d5e0ef7
TV		 625
626 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
df4769c9 627 bool (*detect)(struct omap_dss_device *dssdev);
559d6701
TV		 628};
629
630int omap_dss_register_driver(struct omap_dss_driver *);
631void omap_dss_unregister_driver(struct omap_dss_driver *);
632
559d6701
TV		 633void omap_dss_get_device(struct omap_dss_device *dssdev);
634void omap_dss_put_device(struct omap_dss_device *dssdev);
635#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
636struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
637struct omap_dss_device *omap_dss_find_device(void *data,
638 int (*match)(struct omap_dss_device *dssdev, void *data));
639
640int omap_dss_start_device(struct omap_dss_device *dssdev);
641void omap_dss_stop_device(struct omap_dss_device *dssdev);
642
643int omap_dss_get_num_overlay_managers(void);
644struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
645
646int omap_dss_get_num_overlays(void);
647struct omap_overlay *omap_dss_get_overlay(int num);
648
96adcece
TV		 649void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
650 u16 *xres, u16 *yres);
a2699504
TV		 651int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
652
559d6701
TV		 653typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
654int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
655int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
656
657int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
658int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
659 unsigned long timeout);
660
661#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
662#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
663
1ffefe75
AT		 664void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
665 bool enable);
225b650d 666int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
61140c9a 667
18946f62 668int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
26a8c250
TV		 669 u16 *x, u16 *y, u16 *w, u16 *h,
670 bool enlarge_update_area);
18946f62
TV		 671int omap_dsi_update(struct omap_dss_device *dssdev,
672 int channel,
673 u16 x, u16 y, u16 w, u16 h,
674 void (*callback)(int, void *), void *data);
5ee3c144
AT		 675int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
676int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
677void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
18946f62 678
37ac60e4 679int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
2a89dc15 680void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
22d6d676 681 bool disconnect_lanes, bool enter_ulps);
37ac60e4
TV		 682
683int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
684void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
69b2048f
TV		 685void dpi_set_timings(struct omap_dss_device *dssdev,
686 struct omap_video_timings *timings);
687int dpi_check_timings(struct omap_dss_device *dssdev,
688 struct omap_video_timings *timings);
37ac60e4
TV		 689
690int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
691void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
692
693int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
694void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
18946f62
TV		 695int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
696 u16 *x, u16 *y, u16 *w, u16 *h);
697int omap_rfbi_update(struct omap_dss_device *dssdev,
698 u16 x, u16 y, u16 w, u16 h,
699 void (*callback)(void *), void *data);
1d5952a8
TV		 700int omap_rfbi_configure(struct omap_dss_device *dssdev, int pixel_size,
701 int data_lines);
18946f62 702
559d6701 703#endif
kernel source for telekom puls (alcatel/mediatek)