Merge branch 'drm-vmwgfx-fixes' of git://people.freedesktop.org/~syeh/repos_linux...
[GitHub/moto-9609/android_kernel_motorola_exynos9610.git] / include / media / drv-intf / exynos-fimc.h
CommitLineData
5f3cc447 1/*
56bc911a 2 * Samsung S5P/Exynos4 SoC series camera interface driver header
5f3cc447 3 *
56bc911a
SN
4 * Copyright (C) 2010 - 2013 Samsung Electronics Co., Ltd.
5 * Sylwester Nawrocki <s.nawrocki@samsung.com>
5f3cc447
SN
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
df7e09a3
SN
12#ifndef S5P_FIMC_H_
13#define S5P_FIMC_H_
5f3cc447 14
b9ee31e6 15#include <media/media-entity.h>
bc7584b0 16#include <media/v4l2-dev.h>
80f958f4 17#include <media/v4l2-mediabus.h>
b9ee31e6 18
02399e35
SN
19/*
20 * Enumeration of data inputs to the camera subsystem.
21 */
22enum fimc_input {
23 FIMC_INPUT_PARALLEL_0 = 1,
24 FIMC_INPUT_PARALLEL_1,
25 FIMC_INPUT_MIPI_CSI2_0 = 3,
26 FIMC_INPUT_MIPI_CSI2_1,
27 FIMC_INPUT_WRITEBACK_A = 5,
28 FIMC_INPUT_WRITEBACK_B,
29 FIMC_INPUT_WRITEBACK_ISP = 5,
30};
31
56bc911a
SN
32/*
33 * Enumeration of the FIMC data bus types.
34 */
35enum fimc_bus_type {
36 /* Camera parallel bus */
37 FIMC_BUS_TYPE_ITU_601 = 1,
38 /* Camera parallel bus with embedded synchronization */
39 FIMC_BUS_TYPE_ITU_656,
40 /* Camera MIPI-CSI2 serial bus */
41 FIMC_BUS_TYPE_MIPI_CSI2,
42 /* FIFO link from LCD controller (WriteBack A) */
43 FIMC_BUS_TYPE_LCD_WRITEBACK_A,
44 /* FIFO link from LCD controller (WriteBack B) */
45 FIMC_BUS_TYPE_LCD_WRITEBACK_B,
46 /* FIFO link from FIMC-IS */
47 FIMC_BUS_TYPE_ISP_WRITEBACK = FIMC_BUS_TYPE_LCD_WRITEBACK_B,
5f3cc447
SN
48};
49
2b13f7d4
SN
50#define fimc_input_is_parallel(x) ((x) == 1 || (x) == 2)
51#define fimc_input_is_mipi_csi(x) ((x) == 3 || (x) == 4)
52
488f29d0
SN
53/*
54 * The subdevices' group IDs.
55 */
56#define GRP_ID_SENSOR (1 << 8)
57#define GRP_ID_FIMC_IS_SENSOR (1 << 9)
58#define GRP_ID_WRITEBACK (1 << 10)
59#define GRP_ID_CSIS (1 << 11)
60#define GRP_ID_FIMC (1 << 12)
61#define GRP_ID_FLITE (1 << 13)
62#define GRP_ID_FIMC_IS (1 << 14)
63
5f3cc447 64/**
56bc911a
SN
65 * struct fimc_source_info - video source description required for the host
66 * interface configuration
5f3cc447 67 *
56bc911a
SN
68 * @fimc_bus_type: FIMC camera input type
69 * @sensor_bus_type: image sensor bus type, MIPI, ITU-R BT.601 etc.
70 * @flags: the parallel sensor bus flags defining signals polarity (V4L2_MBUS_*)
5f3cc447 71 * @mux_id: FIMC camera interface multiplexer index (separate for MIPI and ITU)
5f3cc447 72 */
56bc911a 73struct fimc_source_info {
56bc911a
SN
74 enum fimc_bus_type fimc_bus_type;
75 enum fimc_bus_type sensor_bus_type;
76 u16 flags;
5f3cc447 77 u16 mux_id;
5f3cc447 78};
e1d72f4d
SN
79
80/*
81 * v4l2_device notification id. This is only for internal use in the kernel.
82 * Sensor subdevs should issue S5P_FIMC_TX_END_NOTIFY notification in single
83 * frame capture mode when there is only one VSYNC pulse issued by the sensor
84 * at begining of the frame transmission.
85 */
86#define S5P_FIMC_TX_END_NOTIFY _IO('e', 0)
87
80f958f4
SN
88#define FIMC_MAX_PLANES 3
89
90/**
91 * struct fimc_fmt - color format data structure
92 * @mbus_code: media bus pixel code, -1 if not applicable
93 * @name: format description
94 * @fourcc: fourcc code for this format, 0 if not applicable
95 * @color: the driver's private color format id
96 * @memplanes: number of physically non-contiguous data planes
97 * @colplanes: number of physically contiguous data planes
1c26190a 98 * @colorspace: v4l2 colorspace (V4L2_COLORSPACE_*)
80f958f4
SN
99 * @depth: per plane driver's private 'number of bits per pixel'
100 * @mdataplanes: bitmask indicating meta data plane(s), (1 << plane_no)
101 * @flags: flags indicating which operation mode format applies to
102 */
103struct fimc_fmt {
27ffaeb0 104 u32 mbus_code;
80f958f4
SN
105 char *name;
106 u32 fourcc;
107 u32 color;
108 u16 memplanes;
109 u16 colplanes;
1c26190a 110 u8 colorspace;
80f958f4
SN
111 u8 depth[FIMC_MAX_PLANES];
112 u16 mdataplanes;
113 u16 flags;
114#define FMT_FLAGS_CAM (1 << 0)
115#define FMT_FLAGS_M2M_IN (1 << 1)
116#define FMT_FLAGS_M2M_OUT (1 << 2)
117#define FMT_FLAGS_M2M (1 << 1 | 1 << 2)
118#define FMT_HAS_ALPHA (1 << 3)
119#define FMT_FLAGS_COMPRESSED (1 << 4)
120#define FMT_FLAGS_WRITEBACK (1 << 5)
e90ad659
SN
121#define FMT_FLAGS_RAW_BAYER (1 << 6)
122#define FMT_FLAGS_YUV (1 << 7)
80f958f4
SN
123};
124
403dfbec 125struct exynos_media_pipeline;
0f735f52 126
403dfbec
SN
127/*
128 * Media pipeline operations to be called from within a video node, i.e. the
129 * last entity within the pipeline. Implemented by related media device driver.
130 */
131struct exynos_media_pipeline_ops {
132 int (*prepare)(struct exynos_media_pipeline *p,
133 struct media_entity *me);
134 int (*unprepare)(struct exynos_media_pipeline *p);
135 int (*open)(struct exynos_media_pipeline *p, struct media_entity *me,
136 bool resume);
137 int (*close)(struct exynos_media_pipeline *p);
138 int (*set_stream)(struct exynos_media_pipeline *p, bool state);
0f735f52
SN
139};
140
bc7584b0
SN
141struct exynos_video_entity {
142 struct video_device vdev;
403dfbec 143 struct exynos_media_pipeline *pipe;
bc7584b0
SN
144};
145
403dfbec
SN
146struct exynos_media_pipeline {
147 struct media_pipeline mp;
148 const struct exynos_media_pipeline_ops *ops;
b9ee31e6
SN
149};
150
403dfbec
SN
151static inline struct exynos_video_entity *vdev_to_exynos_video_entity(
152 struct video_device *vdev)
153{
154 return container_of(vdev, struct exynos_video_entity, vdev);
155}
156
157#define fimc_pipeline_call(ent, op, args...) \
158 (!(ent) ? -ENOENT : (((ent)->pipe->ops && (ent)->pipe->ops->op) ? \
159 (ent)->pipe->ops->op(((ent)->pipe), ##args) : -ENOIOCTLCMD)) \
b9ee31e6 160
df7e09a3 161#endif /* S5P_FIMC_H_ */