[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / sh_clk.h

#ifndef __SH_CLOCK_H
#define __SH_CLOCK_H

#include <linux/list.h>
#include <linux/seq_file.h>
#include <linux/cpufreq.h>
#include <linux/types.h>
#include <linux/kref.h>
#include <linux/clk.h>
#include <linux/err.h>

struct clk;

struct clk_mapping {
	phys_addr_t		phys;
	void __iomem		*base;
	unsigned long		len;
	struct kref		ref;
};


struct sh_clk_ops {
#ifdef CONFIG_SH_CLK_CPG_LEGACY
	void (*init)(struct clk *clk);
#endif
	int (*enable)(struct clk *clk);
	void (*disable)(struct clk *clk);
	unsigned long (*recalc)(struct clk *clk);
	int (*set_rate)(struct clk *clk, unsigned long rate);
	int (*set_parent)(struct clk *clk, struct clk *parent);
	long (*round_rate)(struct clk *clk, unsigned long rate);
};

struct clk {
	struct list_head	node;
	struct clk		*parent;
	struct clk		**parent_table;	/* list of parents to */
	unsigned short		parent_num;	/* choose between */
	unsigned char		src_shift;	/* source clock field in the */
	unsigned char		src_width;	/* configuration register */
	struct sh_clk_ops	*ops;

	struct list_head	children;
	struct list_head	sibling;	/* node for children */

	int			usecount;

	unsigned long		rate;
	unsigned long		flags;

	void __iomem		*enable_reg;
	unsigned int		enable_bit;
	void __iomem		*mapped_reg;

	unsigned long		arch_flags;
	void			*priv;
	struct clk_mapping	*mapping;
	struct cpufreq_frequency_table *freq_table;
	unsigned int		nr_freqs;
};

#define CLK_ENABLE_ON_INIT	BIT(0)

#define CLK_ENABLE_REG_32BIT	BIT(1)	/* default access size */
#define CLK_ENABLE_REG_16BIT	BIT(2)
#define CLK_ENABLE_REG_8BIT	BIT(3)

#define CLK_ENABLE_REG_MASK	(CLK_ENABLE_REG_32BIT | \
				 CLK_ENABLE_REG_16BIT | \
				 CLK_ENABLE_REG_8BIT)

/* drivers/sh/clk.c */
unsigned long followparent_recalc(struct clk *);
void recalculate_root_clocks(void);
void propagate_rate(struct clk *);
int clk_reparent(struct clk *child, struct clk *parent);
int clk_register(struct clk *);
void clk_unregister(struct clk *);
void clk_enable_init_clocks(void);

struct clk_div_mult_table {
	unsigned int *divisors;
	unsigned int nr_divisors;
	unsigned int *multipliers;
	unsigned int nr_multipliers;
};

struct cpufreq_frequency_table;
void clk_rate_table_build(struct clk *clk,
			  struct cpufreq_frequency_table *freq_table,
			  int nr_freqs,
			  struct clk_div_mult_table *src_table,
			  unsigned long *bitmap);

long clk_rate_table_round(struct clk *clk,
			  struct cpufreq_frequency_table *freq_table,
			  unsigned long rate);

int clk_rate_table_find(struct clk *clk,
			struct cpufreq_frequency_table *freq_table,
			unsigned long rate);

long clk_rate_div_range_round(struct clk *clk, unsigned int div_min,
			      unsigned int div_max, unsigned long rate);

long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min,
			       unsigned int mult_max, unsigned long rate);

long clk_round_parent(struct clk *clk, unsigned long target,
		      unsigned long *best_freq, unsigned long *parent_freq,
		      unsigned int div_min, unsigned int div_max);

#define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _flags)		\
{									\
	.parent		= _parent,					\
	.enable_reg	= (void __iomem *)_enable_reg,			\
	.enable_bit	= _enable_bit,					\
	.flags		= _flags,					\
}

#define SH_CLK_MSTP32(_p, _r, _b, _f)					\
	SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_32BIT)

#define SH_CLK_MSTP16(_p, _r, _b, _f)					\
	SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_16BIT)

#define SH_CLK_MSTP8(_p, _r, _b, _f)					\
	SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_8BIT)

int sh_clk_mstp_register(struct clk *clks, int nr);

/*
 * MSTP registration never really cared about access size, despite the
 * original enable/disable pairs assuming a 32-bit access. Clocks are
 * responsible for defining their access sizes either directly or via the
 * clock definition wrappers.
 */
static inline int __deprecated sh_clk_mstp32_register(struct clk *clks, int nr)
{
	return sh_clk_mstp_register(clks, nr);
}

#define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags)	\
{								\
	.parent = _parent,					\
	.enable_reg = (void __iomem *)_reg,			\
	.enable_bit = _shift,					\
	.arch_flags = _div_bitmap,				\
	.flags = _flags,					\
}

struct clk_div4_table {
	struct clk_div_mult_table *div_mult_table;
	void (*kick)(struct clk *clk);
};

int sh_clk_div4_register(struct clk *clks, int nr,
			 struct clk_div4_table *table);
int sh_clk_div4_enable_register(struct clk *clks, int nr,
			 struct clk_div4_table *table);
int sh_clk_div4_reparent_register(struct clk *clks, int nr,
			 struct clk_div4_table *table);

#define SH_CLK_DIV6_EXT(_reg, _flags, _parents,			\
			_num_parents, _src_shift, _src_width)	\
{								\
	.enable_reg = (void __iomem *)_reg,			\
	.flags = _flags,					\
	.parent_table = _parents,				\
	.parent_num = _num_parents,				\
	.src_shift = _src_shift,				\
	.src_width = _src_width,				\
}

#define SH_CLK_DIV6(_parent, _reg, _flags)			\
{								\
	.parent		= _parent,				\
	.enable_reg	= (void __iomem *)_reg,			\
	.flags		= _flags,				\
}

int sh_clk_div6_register(struct clk *clks, int nr);
int sh_clk_div6_reparent_register(struct clk *clks, int nr);

#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }

#endif /* __SH_CLOCK_H */
Commit	Line	Data
d28bdf05 MD	1	#ifndef __SH_CLOCK_H
	2	#define __SH_CLOCK_H
	3
	4	#include <linux/list.h>
	5	#include <linux/seq_file.h>
	6	#include <linux/cpufreq.h>
28085bc5 PM	7	#include <linux/types.h>
28085bc5 PM	8	#include <linux/kref.h>
d28bdf05 MD	9	#include <linux/clk.h>
	10	#include <linux/err.h>
	11
	12	struct clk;
	13
28085bc5 PM	14	struct clk_mapping {
	15	phys_addr_t phys;
	16	void __iomem *base;
	17	unsigned long len;
	18	struct kref ref;
	19	};
	20
e3482829	21
84c36ffd	22	struct sh_clk_ops {
549015c3	23	#ifdef CONFIG_SH_CLK_CPG_LEGACY
d28bdf05	24	void (init)(struct clk clk);
549015c3	25	#endif
d28bdf05 MD	26	int (enable)(struct clk clk);
	27	void (disable)(struct clk clk);
	28	unsigned long (recalc)(struct clk clk);
35a96c73	29	int (set_rate)(struct clk clk, unsigned long rate);
d28bdf05 MD	30	int (set_parent)(struct clk clk, struct clk *parent);
	31	long (round_rate)(struct clk clk, unsigned long rate);
	32	};
	33
	34	struct clk {
	35	struct list_head node;
d28bdf05	36	struct clk *parent;
b5272b50 GL	37	struct clk *parent_table; / list of parents to */
	38	unsigned short parent_num; /* choose between */
	39	unsigned char src_shift; /* source clock field in the */
	40	unsigned char src_width; /* configuration register */
84c36ffd	41	struct sh_clk_ops *ops;
d28bdf05 MD	42
	43	struct list_head children;
	44	struct list_head sibling; /* node for children */
	45
	46	int usecount;
	47
	48	unsigned long rate;
	49	unsigned long flags;
	50
	51	void __iomem *enable_reg;
	52	unsigned int enable_bit;
eda2030a	53	void __iomem *mapped_reg;
d28bdf05 MD	54
	55	unsigned long arch_flags;
	56	void *priv;
28085bc5	57	struct clk_mapping *mapping;
d28bdf05	58	struct cpufreq_frequency_table *freq_table;
f586903d	59	unsigned int nr_freqs;
d28bdf05 MD	60	};
d28bdf05 MD	61
4d6ddb08 PM	62	#define CLK_ENABLE_ON_INIT BIT(0)
	63
	64	#define CLK_ENABLE_REG_32BIT BIT(1) /* default access size */
	65	#define CLK_ENABLE_REG_16BIT BIT(2)
	66	#define CLK_ENABLE_REG_8BIT BIT(3)
	67
	68	#define CLK_ENABLE_REG_MASK (CLK_ENABLE_REG_32BIT \| \
	69	CLK_ENABLE_REG_16BIT \| \
	70	CLK_ENABLE_REG_8BIT)
d28bdf05	71
a71ba096	72	/* drivers/sh/clk.c */
d28bdf05 MD	73	unsigned long followparent_recalc(struct clk *);
	74	void recalculate_root_clocks(void);
	75	void propagate_rate(struct clk *);
	76	int clk_reparent(struct clk child, struct clk parent);
	77	int clk_register(struct clk *);
	78	void clk_unregister(struct clk *);
8b5ee113	79	void clk_enable_init_clocks(void);
d28bdf05	80
d28bdf05 MD	81	struct clk_div_mult_table {
	82	unsigned int *divisors;
	83	unsigned int nr_divisors;
	84	unsigned int *multipliers;
	85	unsigned int nr_multipliers;
	86	};
	87
	88	struct cpufreq_frequency_table;
	89	void clk_rate_table_build(struct clk *clk,
	90	struct cpufreq_frequency_table *freq_table,
	91	int nr_freqs,
	92	struct clk_div_mult_table *src_table,
	93	unsigned long *bitmap);
	94
	95	long clk_rate_table_round(struct clk *clk,
	96	struct cpufreq_frequency_table *freq_table,
	97	unsigned long rate);
	98
	99	int clk_rate_table_find(struct clk *clk,
	100	struct cpufreq_frequency_table *freq_table,
	101	unsigned long rate);
	102
8e122db6 PM	103	long clk_rate_div_range_round(struct clk *clk, unsigned int div_min,
	104	unsigned int div_max, unsigned long rate);
	105
dd2c0ca1 KM	106	long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min,
	107	unsigned int mult_max, unsigned long rate);
	108
6af26c6c GL	109	long clk_round_parent(struct clk *clk, unsigned long target,
	110	unsigned long best_freq, unsigned long parent_freq,
	111	unsigned int div_min, unsigned int div_max);
	112
4d6ddb08	113	#define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _flags) \
d28bdf05 MD	114	{ \
	115	.parent = _parent, \
	116	.enable_reg = (void __iomem *)_enable_reg, \
	117	.enable_bit = _enable_bit, \
	118	.flags = _flags, \
	119	}
	120
4d6ddb08 PM	121	#define SH_CLK_MSTP32(_p, _r, _b, _f) \
	122	SH_CLK_MSTP(_p, _r, _b, _f \| CLK_ENABLE_REG_32BIT)
	123
	124	#define SH_CLK_MSTP16(_p, _r, _b, _f) \
	125	SH_CLK_MSTP(_p, _r, _b, _f \| CLK_ENABLE_REG_16BIT)
	126
	127	#define SH_CLK_MSTP8(_p, _r, _b, _f) \
	128	SH_CLK_MSTP(_p, _r, _b, _f \| CLK_ENABLE_REG_8BIT)
	129
	130	int sh_clk_mstp_register(struct clk *clks, int nr);
	131
	132	/*
	133	* MSTP registration never really cared about access size, despite the
	134	* original enable/disable pairs assuming a 32-bit access. Clocks are
	135	* responsible for defining their access sizes either directly or via the
	136	* clock definition wrappers.
	137	*/
	138	static inline int __deprecated sh_clk_mstp32_register(struct clk *clks, int nr)
	139	{
	140	return sh_clk_mstp_register(clks, nr);
	141	}
d28bdf05 MD	142
	143	#define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \
	144	{ \
	145	.parent = _parent, \
	146	.enable_reg = (void __iomem *)_reg, \
	147	.enable_bit = _shift, \
	148	.arch_flags = _div_bitmap, \
	149	.flags = _flags, \
	150	}
	151
	152	struct clk_div4_table {
	153	struct clk_div_mult_table *div_mult_table;
	154	void (kick)(struct clk clk);
	155	};
	156
	157	int sh_clk_div4_register(struct clk *clks, int nr,
	158	struct clk_div4_table *table);
	159	int sh_clk_div4_enable_register(struct clk *clks, int nr,
	160	struct clk_div4_table *table);
	161	int sh_clk_div4_reparent_register(struct clk *clks, int nr,
	162	struct clk_div4_table *table);
	163
56242a1f	164	#define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \
b3dd51a8 GL	165	_num_parents, _src_shift, _src_width) \
b3dd51a8 GL	166	{ \
b3dd51a8 GL	167	.enable_reg = (void __iomem *)_reg, \
	168	.flags = _flags, \
	169	.parent_table = _parents, \
	170	.parent_num = _num_parents, \
	171	.src_shift = _src_shift, \
	172	.src_width = _src_width, \
d28bdf05 MD	173	}
d28bdf05 MD	174
b3dd51a8	175	#define SH_CLK_DIV6(_parent, _reg, _flags) \
56242a1f KM	176	{ \
	177	.parent = _parent, \
	178	.enable_reg = (void __iomem *)_reg, \
	179	.flags = _flags, \
	180	}
b3dd51a8	181
d28bdf05	182	int sh_clk_div6_register(struct clk *clks, int nr);
b3dd51a8	183	int sh_clk_div6_reparent_register(struct clk *clks, int nr);
d28bdf05	184
1522043b KM	185	#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
	186	#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
	187	#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
	188
d28bdf05	189	#endif /* __SH_CLOCK_H */