[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / serial_sci.h

#ifndef __LINUX_SERIAL_SCI_H
#define __LINUX_SERIAL_SCI_H

#include <linux/serial_core.h>
#include <linux/sh_dma.h>

/*
 * Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts)
 */

#define SCIx_NOT_SUPPORTED	(-1)

enum {
	SCBRR_ALGO_1,		/* ((clk + 16 * bps) / (16 * bps) - 1) */
	SCBRR_ALGO_2,		/* ((clk + 16 * bps) / (32 * bps) - 1) */
	SCBRR_ALGO_3,		/* (((clk * 2) + 16 * bps) / (16 * bps) - 1) */
	SCBRR_ALGO_4,		/* (((clk * 2) + 16 * bps) / (32 * bps) - 1) */
	SCBRR_ALGO_5,		/* (((clk * 1000 / 32) / bps) - 1) */
};

#define SCSCR_TIE	(1 << 7)
#define SCSCR_RIE	(1 << 6)
#define SCSCR_TE	(1 << 5)
#define SCSCR_RE	(1 << 4)
#define SCSCR_REIE	(1 << 3)	/* not supported by all parts */
#define SCSCR_TOIE	(1 << 2)	/* not supported by all parts */
#define SCSCR_CKE1	(1 << 1)
#define SCSCR_CKE0	(1 << 0)

/* SCxSR SCI */
#define SCI_TDRE  0x80
#define SCI_RDRF  0x40
#define SCI_ORER  0x20
#define SCI_FER   0x10
#define SCI_PER   0x08
#define SCI_TEND  0x04

#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)

/* SCxSR SCIF */
#define SCIF_ER    0x0080
#define SCIF_TEND  0x0040
#define SCIF_TDFE  0x0020
#define SCIF_BRK   0x0010
#define SCIF_FER   0x0008
#define SCIF_PER   0x0004
#define SCIF_RDF   0x0002
#define SCIF_DR    0x0001

#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)

/* Offsets into the sci_port->irqs array */
enum {
	SCIx_ERI_IRQ,
	SCIx_RXI_IRQ,
	SCIx_TXI_IRQ,
	SCIx_BRI_IRQ,
	SCIx_NR_IRQS,

	SCIx_MUX_IRQ = SCIx_NR_IRQS,	/* special case */
};

enum {
	SCIx_PROBE_REGTYPE,

	SCIx_SCI_REGTYPE,
	SCIx_IRDA_REGTYPE,
	SCIx_SCIFA_REGTYPE,
	SCIx_SCIFB_REGTYPE,
	SCIx_SH2_SCIF_FIFODATA_REGTYPE,
	SCIx_SH3_SCIF_REGTYPE,
	SCIx_SH4_SCIF_REGTYPE,
	SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
	SCIx_SH4_SCIF_FIFODATA_REGTYPE,
	SCIx_SH7705_SCIF_REGTYPE,

	SCIx_NR_REGTYPES,
};

#define SCIx_IRQ_MUXED(irq)		\
{					\
	[SCIx_ERI_IRQ]	= (irq),	\
	[SCIx_RXI_IRQ]	= (irq),	\
	[SCIx_TXI_IRQ]	= (irq),	\
	[SCIx_BRI_IRQ]	= (irq),	\
}

#define SCIx_IRQ_IS_MUXED(port)			\
	((port)->cfg->irqs[SCIx_ERI_IRQ] ==	\
	 (port)->cfg->irqs[SCIx_RXI_IRQ]) ||	\
	((port)->cfg->irqs[SCIx_ERI_IRQ] &&	\
	 !(port)->cfg->irqs[SCIx_RXI_IRQ])
/*
 * SCI register subset common for all port types.
 * Not all registers will exist on all parts.
 */
enum {
	SCSMR, SCBRR, SCSCR, SCxSR,
	SCFCR, SCFDR, SCxTDR, SCxRDR,
	SCLSR, SCTFDR, SCRFDR, SCSPTR,

	SCIx_NR_REGS,
};

struct device;

struct plat_sci_port_ops {
	void (*init_pins)(struct uart_port *, unsigned int cflag);
};

/*
 * Platform device specific platform_data struct
 */
struct plat_sci_port {
	unsigned long	mapbase;		/* resource base */
	unsigned int	irqs[SCIx_NR_IRQS];	/* ERI, RXI, TXI, BRI */
	unsigned int	type;			/* SCI / SCIF / IRDA */
	upf_t		flags;			/* UPF_* flags */

	unsigned int	scbrr_algo_id;		/* SCBRR calculation algo */
	unsigned int	scscr;			/* SCSCR initialization */

	/*
	 * Platform overrides if necessary, defaults otherwise.
	 */
	int		overrun_bit;
	unsigned int	error_mask;

	int		port_reg;
	unsigned char	regshift;
	unsigned char	regtype;

	struct plat_sci_port_ops	*ops;

	unsigned int	dma_slave_tx;
	unsigned int	dma_slave_rx;
};

#endif /* __LINUX_SERIAL_SCI_H */
Commit	Line	Data
96de1a8f PM	1	#ifndef __LINUX_SERIAL_SCI_H
96de1a8f PM	2	#define __LINUX_SERIAL_SCI_H
ecd95616 PM	3
ecd95616 PM	4	#include <linux/serial_core.h>
14baf9d7	5	#include <linux/sh_dma.h>
ecd95616 PM	6
ecd95616 PM	7	/*
96de1a8f	8	* Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts)
ecd95616 PM	9	*/
ecd95616 PM	10
debf9507 PM	11	#define SCIx_NOT_SUPPORTED (-1)
debf9507 PM	12
26c92f37 PM	13	enum {
	14	SCBRR_ALGO_1, /* ((clk + 16 * bps) / (16 * bps) - 1) */
	15	SCBRR_ALGO_2, /* ((clk + 16 * bps) / (32 * bps) - 1) */
	16	SCBRR_ALGO_3, /* (((clk * 2) + 16 * bps) / (16 * bps) - 1) */
	17	SCBRR_ALGO_4, /* (((clk * 2) + 16 * bps) / (32 * bps) - 1) */
	18	SCBRR_ALGO_5, /* (((clk * 1000 / 32) / bps) - 1) */
	19	};
	20
00b9de9c PM	21	#define SCSCR_TIE (1 << 7)
	22	#define SCSCR_RIE (1 << 6)
	23	#define SCSCR_TE (1 << 5)
	24	#define SCSCR_RE (1 << 4)
f43dc23d	25	#define SCSCR_REIE (1 << 3) /* not supported by all parts */
00b9de9c PM	26	#define SCSCR_TOIE (1 << 2) /* not supported by all parts */
	27	#define SCSCR_CKE1 (1 << 1)
	28	#define SCSCR_CKE0 (1 << 0)
	29
debf9507 PM	30	/* SCxSR SCI */
	31	#define SCI_TDRE 0x80
	32	#define SCI_RDRF 0x40
	33	#define SCI_ORER 0x20
	34	#define SCI_FER 0x10
	35	#define SCI_PER 0x08
	36	#define SCI_TEND 0x04
	37
	38	#define SCI_DEFAULT_ERROR_MASK (SCI_PER \| SCI_FER)
	39
	40	/* SCxSR SCIF */
	41	#define SCIF_ER 0x0080
	42	#define SCIF_TEND 0x0040
	43	#define SCIF_TDFE 0x0020
	44	#define SCIF_BRK 0x0010
	45	#define SCIF_FER 0x0008
	46	#define SCIF_PER 0x0004
	47	#define SCIF_RDF 0x0002
	48	#define SCIF_DR 0x0001
	49
	50	#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER \| SCIF_FER \| SCIF_ER \| SCIF_BRK)
	51
ecd95616 PM	52	/* Offsets into the sci_port->irqs array */
	53	enum {
	54	SCIx_ERI_IRQ,
	55	SCIx_RXI_IRQ,
	56	SCIx_TXI_IRQ,
	57	SCIx_BRI_IRQ,
	58	SCIx_NR_IRQS,
9174fc8f PM	59
9174fc8f PM	60	SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
ecd95616 PM	61	};
ecd95616 PM	62
61a6976b PM	63	enum {
	64	SCIx_PROBE_REGTYPE,
	65
	66	SCIx_SCI_REGTYPE,
	67	SCIx_IRDA_REGTYPE,
	68	SCIx_SCIFA_REGTYPE,
	69	SCIx_SCIFB_REGTYPE,
3af1f8a4	70	SCIx_SH2_SCIF_FIFODATA_REGTYPE,
61a6976b PM	71	SCIx_SH3_SCIF_REGTYPE,
	72	SCIx_SH4_SCIF_REGTYPE,
	73	SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
	74	SCIx_SH4_SCIF_FIFODATA_REGTYPE,
	75	SCIx_SH7705_SCIF_REGTYPE,
	76
	77	SCIx_NR_REGTYPES,
	78	};
	79
22cc8378 PM	80	#define SCIx_IRQ_MUXED(irq) \
	81	{ \
	82	[SCIx_ERI_IRQ] = (irq), \
	83	[SCIx_RXI_IRQ] = (irq), \
	84	[SCIx_TXI_IRQ] = (irq), \
	85	[SCIx_BRI_IRQ] = (irq), \
	86	}
	87
9174fc8f PM	88	#define SCIx_IRQ_IS_MUXED(port) \
	89	((port)->cfg->irqs[SCIx_ERI_IRQ] == \
	90	(port)->cfg->irqs[SCIx_RXI_IRQ]) \|\| \
	91	((port)->cfg->irqs[SCIx_ERI_IRQ] && \
	92	!(port)->cfg->irqs[SCIx_RXI_IRQ])
61a6976b PM	93	/*
	94	* SCI register subset common for all port types.
	95	* Not all registers will exist on all parts.
	96	*/
	97	enum {
	98	SCSMR, SCBRR, SCSCR, SCxSR,
	99	SCFCR, SCFDR, SCxTDR, SCxRDR,
	100	SCLSR, SCTFDR, SCRFDR, SCSPTR,
	101
	102	SCIx_NR_REGS,
	103	};
	104
73a19e4c GL	105	struct device;
73a19e4c GL	106
61a6976b PM	107	struct plat_sci_port_ops {
	108	void (init_pins)(struct uart_port , unsigned int cflag);
	109	};
	110
ecd95616 PM	111	/*
	112	* Platform device specific platform_data struct
	113	*/
	114	struct plat_sci_port {
ecd95616 PM	115	unsigned long mapbase; /* resource base */
	116	unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */
	117	unsigned int type; /* SCI / SCIF / IRDA */
	118	upf_t flags; /* UPF_* flags */
00b9de9c	119
26c92f37	120	unsigned int scbrr_algo_id; /* SCBRR calculation algo */
00b9de9c	121	unsigned int scscr; /* SCSCR initialization */
f43dc23d	122
debf9507 PM	123	/*
	124	* Platform overrides if necessary, defaults otherwise.
	125	*/
	126	int overrun_bit;
	127	unsigned int error_mask;
	128
514820eb	129	int port_reg;
61a6976b PM	130	unsigned char regshift;
	131	unsigned char regtype;
	132
	133	struct plat_sci_port_ops *ops;
514820eb	134
27bd1075 PM	135	unsigned int dma_slave_tx;
27bd1075 PM	136	unsigned int dma_slave_rx;
ecd95616 PM	137	};
ecd95616 PM	138
96de1a8f	139	#endif /* __LINUX_SERIAL_SCI_H */