[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / serial_core.h

/*
 *  linux/drivers/char/serial_core.h
 *
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#ifndef LINUX_SERIAL_CORE_H
#define LINUX_SERIAL_CORE_H

/*
 * The type definitions.  These are from Ted Ts'o's serial.h
 */
#define PORT_UNKNOWN	0
#define PORT_8250	1
#define PORT_16450	2
#define PORT_16550	3
#define PORT_16550A	4
#define PORT_CIRRUS	5
#define PORT_16650	6
#define PORT_16650V2	7
#define PORT_16750	8
#define PORT_STARTECH	9
#define PORT_16C950	10
#define PORT_16654	11
#define PORT_16850	12
#define PORT_RSA	13
#define PORT_NS16550A	14
#define PORT_XSCALE	15
#define PORT_RM9000	16	/* PMC-Sierra RM9xxx internal UART */
#define PORT_OCTEON	17	/* Cavium OCTEON internal UART */
#define PORT_AR7	18	/* Texas Instruments AR7 internal UART */
#define PORT_MAX_8250	18	/* max port ID */

/*
 * ARM specific type numbers.  These are not currently guaranteed
 * to be implemented, and will change in the future.  These are
 * separate so any additions to the old serial.c that occur before
 * we are merged can be easily merged here.
 */
#define PORT_PXA	31
#define PORT_AMBA	32
#define PORT_CLPS711X	33
#define PORT_SA1100	34
#define PORT_UART00	35
#define PORT_21285	37

/* Sparc type numbers.  */
#define PORT_SUNZILOG	38
#define PORT_SUNSAB	39

/* DEC */
#define PORT_DZ		46
#define PORT_ZS		47

/* Parisc type numbers. */
#define PORT_MUX	48

/* Atmel AT91 / AT32 SoC */
#define PORT_ATMEL	49

/* Macintosh Zilog type numbers */
#define PORT_MAC_ZILOG	50	/* m68k : not yet implemented */
#define PORT_PMAC_ZILOG	51

/* SH-SCI */
#define PORT_SCI	52
#define PORT_SCIF	53
#define PORT_IRDA	54

/* Samsung S3C2410 SoC and derivatives thereof */
#define PORT_S3C2410    55

/* SGI IP22 aka Indy / Challenge S / Indigo 2 */
#define PORT_IP22ZILOG	56

/* Sharp LH7a40x -- an ARM9 SoC series */
#define PORT_LH7A40X	57

/* PPC CPM type number */
#define PORT_CPM        58

/* MPC52xx type numbers */
#define PORT_MPC52xx	59

/* IBM icom */
#define PORT_ICOM	60

/* Samsung S3C2440 SoC */
#define PORT_S3C2440	61

/* Motorola i.MX SoC */
#define PORT_IMX	62

/* Marvell MPSC */
#define PORT_MPSC	63

/* TXX9 type number */
#define PORT_TXX9	64

/* NEC VR4100 series SIU/DSIU */
#define PORT_VR41XX_SIU		65
#define PORT_VR41XX_DSIU	66

/* Samsung S3C2400 SoC */
#define PORT_S3C2400	67

/* M32R SIO */
#define PORT_M32R_SIO	68

/*Digi jsm */
#define PORT_JSM        69

#define PORT_PNX8XXX	70

/* Hilscher netx */
#define PORT_NETX	71

/* SUN4V Hypervisor Console */
#define PORT_SUNHV	72

#define PORT_S3C2412	73

/* Xilinx uartlite */
#define PORT_UARTLITE	74

/* Blackfin bf5xx */
#define PORT_BFIN	75

/* Micrel KS8695 */
#define PORT_KS8695	76

/* Broadcom SB1250, etc. SOC */
#define PORT_SB1250_DUART	77

/* Freescale ColdFire */
#define PORT_MCF	78

/* Blackfin SPORT */
#define PORT_BFIN_SPORT		79

/* MN10300 on-chip UART numbers */
#define PORT_MN10300		80
#define PORT_MN10300_CTS	81

#define PORT_SC26XX	82

/* SH-SCI */
#define PORT_SCIFA	83

#define PORT_S3C6400	84

/* NWPSERIAL */
#define PORT_NWPSERIAL	85

/* MAX3100 */
#define PORT_MAX3100    86

/* Timberdale UART */
#define PORT_TIMBUART	87

/* Qualcomm MSM SoCs */
#define PORT_MSM	88

#ifdef __KERNEL__

#include <linux/compiler.h>
#include <linux/interrupt.h>
#include <linux/circ_buf.h>
#include <linux/spinlock.h>
#include <linux/sched.h>
#include <linux/tty.h>
#include <linux/mutex.h>
#include <linux/sysrq.h>

struct uart_port;
struct serial_struct;
struct device;

/*
 * This structure describes all the operations that can be
 * done on the physical hardware.
 */
struct uart_ops {
	unsigned int	(*tx_empty)(struct uart_port *);
	void		(*set_mctrl)(struct uart_port *, unsigned int mctrl);
	unsigned int	(*get_mctrl)(struct uart_port *);
	void		(*stop_tx)(struct uart_port *);
	void		(*start_tx)(struct uart_port *);
	void		(*send_xchar)(struct uart_port *, char ch);
	void		(*stop_rx)(struct uart_port *);
	void		(*enable_ms)(struct uart_port *);
	void		(*break_ctl)(struct uart_port *, int ctl);
	int		(*startup)(struct uart_port *);
	void		(*shutdown)(struct uart_port *);
	void		(*flush_buffer)(struct uart_port *);
	void		(*set_termios)(struct uart_port *, struct ktermios *new,
				       struct ktermios *old);
	void		(*set_ldisc)(struct uart_port *);
	void		(*pm)(struct uart_port *, unsigned int state,
			      unsigned int oldstate);
	int		(*set_wake)(struct uart_port *, unsigned int state);

	/*
	 * Return a string describing the type of the port
	 */
	const char *(*type)(struct uart_port *);

	/*
	 * Release IO and memory resources used by the port.
	 * This includes iounmap if necessary.
	 */
	void		(*release_port)(struct uart_port *);

	/*
	 * Request IO and memory resources used by the port.
	 * This includes iomapping the port if necessary.
	 */
	int		(*request_port)(struct uart_port *);
	void		(*config_port)(struct uart_port *, int);
	int		(*verify_port)(struct uart_port *, struct serial_struct *);
	int		(*ioctl)(struct uart_port *, unsigned int, unsigned long);
#ifdef CONFIG_CONSOLE_POLL
	void	(*poll_put_char)(struct uart_port *, unsigned char);
	int		(*poll_get_char)(struct uart_port *);
#endif
};

#define UART_CONFIG_TYPE	(1 << 0)
#define UART_CONFIG_IRQ		(1 << 1)

struct uart_icount {
	__u32	cts;
	__u32	dsr;
	__u32	rng;
	__u32	dcd;
	__u32	rx;
	__u32	tx;
	__u32	frame;
	__u32	overrun;
	__u32	parity;
	__u32	brk;
	__u32	buf_overrun;
};

typedef unsigned int __bitwise__ upf_t;

struct uart_port {
	spinlock_t		lock;			/* port lock */
	unsigned long		iobase;			/* in/out[bwl] */
	unsigned char __iomem	*membase;		/* read/write[bwl] */
	unsigned int		(*serial_in)(struct uart_port *, int);
	void			(*serial_out)(struct uart_port *, int, int);
	unsigned int		irq;			/* irq number */
	unsigned long		irqflags;		/* irq flags  */
	unsigned int		uartclk;		/* base uart clock */
	unsigned int		fifosize;		/* tx fifo size */
	unsigned char		x_char;			/* xon/xoff char */
	unsigned char		regshift;		/* reg offset shift */
	unsigned char		iotype;			/* io access style */
	unsigned char		unused1;

#define UPIO_PORT		(0)
#define UPIO_HUB6		(1)
#define UPIO_MEM		(2)
#define UPIO_MEM32		(3)
#define UPIO_AU			(4)			/* Au1x00 type IO */
#define UPIO_TSI		(5)			/* Tsi108/109 type IO */
#define UPIO_DWAPB		(6)			/* DesignWare APB UART */
#define UPIO_RM9000		(7)			/* RM9000 type IO */

	unsigned int		read_status_mask;	/* driver specific */
	unsigned int		ignore_status_mask;	/* driver specific */
	struct uart_state	*state;			/* pointer to parent state */
	struct uart_icount	icount;			/* statistics */

	struct console		*cons;			/* struct console, if any */
#if defined(CONFIG_SERIAL_CORE_CONSOLE) || defined(SUPPORT_SYSRQ)
	unsigned long		sysrq;			/* sysrq timeout */
#endif

	upf_t			flags;

#define UPF_FOURPORT		((__force upf_t) (1 << 1))
#define UPF_SAK			((__force upf_t) (1 << 2))
#define UPF_SPD_MASK		((__force upf_t) (0x1030))
#define UPF_SPD_HI		((__force upf_t) (0x0010))
#define UPF_SPD_VHI		((__force upf_t) (0x0020))
#define UPF_SPD_CUST		((__force upf_t) (0x0030))
#define UPF_SPD_SHI		((__force upf_t) (0x1000))
#define UPF_SPD_WARP		((__force upf_t) (0x1010))
#define UPF_SKIP_TEST		((__force upf_t) (1 << 6))
#define UPF_AUTO_IRQ		((__force upf_t) (1 << 7))
#define UPF_HARDPPS_CD		((__force upf_t) (1 << 11))
#define UPF_LOW_LATENCY		((__force upf_t) (1 << 13))
#define UPF_BUGGY_UART		((__force upf_t) (1 << 14))
#define UPF_NO_TXEN_TEST	((__force upf_t) (1 << 15))
#define UPF_MAGIC_MULTIPLIER	((__force upf_t) (1 << 16))
#define UPF_CONS_FLOW		((__force upf_t) (1 << 23))
#define UPF_SHARE_IRQ		((__force upf_t) (1 << 24))
/* The exact UART type is known and should not be probed.  */
#define UPF_FIXED_TYPE		((__force upf_t) (1 << 27))
#define UPF_BOOT_AUTOCONF	((__force upf_t) (1 << 28))
#define UPF_FIXED_PORT		((__force upf_t) (1 << 29))
#define UPF_DEAD		((__force upf_t) (1 << 30))
#define UPF_IOREMAP		((__force upf_t) (1 << 31))

#define UPF_CHANGE_MASK		((__force upf_t) (0x17fff))
#define UPF_USR_MASK		((__force upf_t) (UPF_SPD_MASK|UPF_LOW_LATENCY))

	unsigned int		mctrl;			/* current modem ctrl settings */
	unsigned int		timeout;		/* character-based timeout */
	unsigned int		type;			/* port type */
	const struct uart_ops	*ops;
	unsigned int		custom_divisor;
	unsigned int		line;			/* port index */
	resource_size_t		mapbase;		/* for ioremap */
	struct device		*dev;			/* parent device */
	unsigned char		hub6;			/* this should be in the 8250 driver */
	unsigned char		suspended;
	unsigned char		unused[2];
	void			*private_data;		/* generic platform data pointer */
};

/*
 * This is the state information which is only valid when the port
 * is open; it may be cleared the core driver once the device has
 * been closed.  Either the low level driver or the core can modify
 * stuff here.
 */
typedef unsigned int __bitwise__ uif_t;


/*
 * This is the state information which is persistent across opens.
 * The low level driver must not to touch any elements contained
 * within.
 */
struct uart_state {
	struct tty_port		port;

#define USF_CLOSING_WAIT_INF	(0)
#define USF_CLOSING_WAIT_NONE	(~0U)

	int			pm_state;
	struct circ_buf		xmit;
	uif_t			flags;

/*
 * Definitions for info->flags.  These are _private_ to serial_core, and
 * are specific to this structure.  They may be queried by low level drivers.
 *
 * FIXME: use the ASY_ definitions
 */
#define UIF_CHECK_CD		((__force uif_t) (1 << 25))
#define UIF_CTS_FLOW		((__force uif_t) (1 << 26))
#define UIF_NORMAL_ACTIVE	((__force uif_t) (1 << 29))
#define UIF_INITIALIZED		((__force uif_t) (1 << 31))
#define UIF_SUSPENDED		((__force uif_t) (1 << 30))

	struct tasklet_struct	tlet;
	wait_queue_head_t	delta_msr_wait;
	struct uart_port	*uart_port;

	struct mutex		mutex;
};

#define UART_XMIT_SIZE	PAGE_SIZE


/* number of characters left in xmit buffer before we ask for more */
#define WAKEUP_CHARS		256

struct module;
struct tty_driver;

struct uart_driver {
	struct module		*owner;
	const char		*driver_name;
	const char		*dev_name;
	int			 major;
	int			 minor;
	int			 nr;
	struct console		*cons;

	/*
	 * these are private; the low level driver should not
	 * touch these; they should be initialised to NULL
	 */
	struct uart_state	*state;
	struct tty_driver	*tty_driver;
};

void uart_write_wakeup(struct uart_port *port);

/*
 * Baud rate helpers.
 */
void uart_update_timeout(struct uart_port *port, unsigned int cflag,
			 unsigned int baud);
unsigned int uart_get_baud_rate(struct uart_port *port, struct ktermios *termios,
				struct ktermios *old, unsigned int min,
				unsigned int max);
unsigned int uart_get_divisor(struct uart_port *port, unsigned int baud);

/*
 * Console helpers.
 */
struct uart_port *uart_get_console(struct uart_port *ports, int nr,
				   struct console *c);
void uart_parse_options(char *options, int *baud, int *parity, int *bits,
			int *flow);
int uart_set_options(struct uart_port *port, struct console *co, int baud,
		     int parity, int bits, int flow);
struct tty_driver *uart_console_device(struct console *co, int *index);
void uart_console_write(struct uart_port *port, const char *s,
			unsigned int count,
			void (*putchar)(struct uart_port *, int));

/*
 * Port/driver registration/removal
 */
int uart_register_driver(struct uart_driver *uart);
void uart_unregister_driver(struct uart_driver *uart);
int uart_add_one_port(struct uart_driver *reg, struct uart_port *port);
int uart_remove_one_port(struct uart_driver *reg, struct uart_port *port);
int uart_match_port(struct uart_port *port1, struct uart_port *port2);

/*
 * Power Management
 */
int uart_suspend_port(struct uart_driver *reg, struct uart_port *port);
int uart_resume_port(struct uart_driver *reg, struct uart_port *port);

#define uart_circ_empty(circ)		((circ)->head == (circ)->tail)
#define uart_circ_clear(circ)		((circ)->head = (circ)->tail = 0)

#define uart_circ_chars_pending(circ)	\
	(CIRC_CNT((circ)->head, (circ)->tail, UART_XMIT_SIZE))

#define uart_circ_chars_free(circ)	\
	(CIRC_SPACE((circ)->head, (circ)->tail, UART_XMIT_SIZE))

static inline int uart_tx_stopped(struct uart_port *port)
{
	struct tty_struct *tty = port->state->port.tty;
	if(tty->stopped || tty->hw_stopped)
		return 1;
	return 0;
}

/*
 * The following are helper functions for the low level drivers.
 */
static inline int
uart_handle_sysrq_char(struct uart_port *port, unsigned int ch)
{
#ifdef SUPPORT_SYSRQ
	if (port->sysrq) {
		if (ch && time_before(jiffies, port->sysrq)) {
			handle_sysrq(ch, port->state->port.tty);
			port->sysrq = 0;
			return 1;
		}
		port->sysrq = 0;
	}
#endif
	return 0;
}
#ifndef SUPPORT_SYSRQ
#define uart_handle_sysrq_char(port,ch) uart_handle_sysrq_char(port, 0)
#endif

/*
 * We do the SysRQ and SAK checking like this...
 */
static inline int uart_handle_break(struct uart_port *port)
{
	struct uart_state *state = port->state;
#ifdef SUPPORT_SYSRQ
	if (port->cons && port->cons->index == port->line) {
		if (!port->sysrq) {
			port->sysrq = jiffies + HZ*5;
			return 1;
		}
		port->sysrq = 0;
	}
#endif
	if (port->flags & UPF_SAK)
		do_SAK(state->port.tty);
	return 0;
}

/**
 *	uart_handle_dcd_change - handle a change of carrier detect state
 *	@port: uart_port structure for the open port
 *	@status: new carrier detect status, nonzero if active
 */
static inline void
uart_handle_dcd_change(struct uart_port *port, unsigned int status)
{
	struct uart_state *state = port->state;

	port->icount.dcd++;

#ifdef CONFIG_HARD_PPS
	if ((port->flags & UPF_HARDPPS_CD) && status)
		hardpps();
#endif

	if (state->flags & UIF_CHECK_CD) {
		if (status)
			wake_up_interruptible(&state->port.open_wait);
		else if (state->port.tty)
			tty_hangup(state->port.tty);
	}
}

/**
 *	uart_handle_cts_change - handle a change of clear-to-send state
 *	@port: uart_port structure for the open port
 *	@status: new clear to send status, nonzero if active
 */
static inline void
uart_handle_cts_change(struct uart_port *port, unsigned int status)
{
	struct uart_state *state = port->state;
	struct tty_struct *tty = state->port.tty;

	port->icount.cts++;

	if (state->flags & UIF_CTS_FLOW) {
		if (tty->hw_stopped) {
			if (status) {
				tty->hw_stopped = 0;
				port->ops->start_tx(port);
				uart_write_wakeup(port);
			}
		} else {
			if (!status) {
				tty->hw_stopped = 1;
				port->ops->stop_tx(port);
			}
		}
	}
}

#include <linux/tty_flip.h>

static inline void
uart_insert_char(struct uart_port *port, unsigned int status,
		 unsigned int overrun, unsigned int ch, unsigned int flag)
{
	struct tty_struct *tty = port->state->port.tty;

	if ((status & port->ignore_status_mask & ~overrun) == 0)
		tty_insert_flip_char(tty, ch, flag);

	/*
	 * Overrun is special.  Since it's reported immediately,
	 * it doesn't affect the current character.
	 */
	if (status & ~port->ignore_status_mask & overrun)
		tty_insert_flip_char(tty, 0, TTY_OVERRUN);
}

/*
 *	UART_ENABLE_MS - determine if port should enable modem status irqs
 */
#define UART_ENABLE_MS(port,cflag)	((port)->flags & UPF_HARDPPS_CD || \
					 (cflag) & CRTSCTS || \
					 !((cflag) & CLOCAL))

#endif

#endif /* LINUX_SERIAL_CORE_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/drivers/char/serial_core.h
	3	*
	4	* Copyright (C) 2000 Deep Blue Solutions Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#ifndef LINUX_SERIAL_CORE_H
	21	#define LINUX_SERIAL_CORE_H
	22
	23	/*
	24	* The type definitions. These are from Ted Ts'o's serial.h
	25	*/
	26	#define PORT_UNKNOWN 0
	27	#define PORT_8250 1
	28	#define PORT_16450 2
	29	#define PORT_16550 3
	30	#define PORT_16550A 4
	31	#define PORT_CIRRUS 5
	32	#define PORT_16650 6
	33	#define PORT_16650V2 7
	34	#define PORT_16750 8
	35	#define PORT_STARTECH 9
	36	#define PORT_16C950 10
	37	#define PORT_16654 11
	38	#define PORT_16850 12
	39	#define PORT_RSA 13
	40	#define PORT_NS16550A 14
	41	#define PORT_XSCALE 15
bd71c182	42	#define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
6b06f191	43	#define PORT_OCTEON 17 /* Cavium OCTEON internal UART */
08e0992f FF	44	#define PORT_AR7 18 /* Texas Instruments AR7 internal UART */
08e0992f FF	45	#define PORT_MAX_8250 18 /* max port ID */
1da177e4 LT	46
	47	/*
	48	* ARM specific type numbers. These are not currently guaranteed
	49	* to be implemented, and will change in the future. These are
	50	* separate so any additions to the old serial.c that occur before
	51	* we are merged can be easily merged here.
	52	*/
	53	#define PORT_PXA 31
	54	#define PORT_AMBA 32
	55	#define PORT_CLPS711X 33
	56	#define PORT_SA1100 34
	57	#define PORT_UART00 35
	58	#define PORT_21285 37
	59
	60	/* Sparc type numbers. */
	61	#define PORT_SUNZILOG 38
	62	#define PORT_SUNSAB 39
	63
8b4a4080 MR	64	/* DEC */
	65	#define PORT_DZ 46
	66	#define PORT_ZS 47
1da177e4 LT	67
	68	/* Parisc type numbers. */
	69	#define PORT_MUX 48
	70
9ab4f88b HS	71	/* Atmel AT91 / AT32 SoC */
9ab4f88b HS	72	#define PORT_ATMEL 49
1e6c9c28	73
1da177e4 LT	74	/* Macintosh Zilog type numbers */
	75	#define PORT_MAC_ZILOG 50 /* m68k : not yet implemented */
	76	#define PORT_PMAC_ZILOG 51
	77
	78	/* SH-SCI */
	79	#define PORT_SCI 52
	80	#define PORT_SCIF 53
	81	#define PORT_IRDA 54
	82
	83	/* Samsung S3C2410 SoC and derivatives thereof */
	84	#define PORT_S3C2410 55
	85
	86	/* SGI IP22 aka Indy / Challenge S / Indigo 2 */
	87	#define PORT_IP22ZILOG 56
	88
	89	/* Sharp LH7a40x -- an ARM9 SoC series */
	90	#define PORT_LH7A40X 57
	91
	92	/* PPC CPM type number */
	93	#define PORT_CPM 58
	94
	95	/* MPC52xx type numbers */
	96	#define PORT_MPC52xx 59
	97
	98	/* IBM icom */
	99	#define PORT_ICOM 60
	100
	101	/* Samsung S3C2440 SoC */
	102	#define PORT_S3C2440 61
	103
	104	/* Motorola i.MX SoC */
	105	#define PORT_IMX 62
	106
	107	/* Marvell MPSC */
	108	#define PORT_MPSC 63
	109
	110	/* TXX9 type number */
e5c2d749	111	#define PORT_TXX9 64
1da177e4 LT	112
	113	/* NEC VR4100 series SIU/DSIU */
	114	#define PORT_VR41XX_SIU 65
	115	#define PORT_VR41XX_DSIU 66
	116
	117	/* Samsung S3C2400 SoC */
	118	#define PORT_S3C2400 67
	119
	120	/* M32R SIO */
	121	#define PORT_M32R_SIO 68
	122
	123	/Digi jsm /
913ade51 RK	124	#define PORT_JSM 69
913ade51 RK	125
e6fa0ba3	126	#define PORT_PNX8XXX 70
1da177e4	127
f5417612 SH	128	/* Hilscher netx */
	129	#define PORT_NETX 71
	130
02fd473b DM	131	/* SUN4V Hypervisor Console */
	132	#define PORT_SUNHV 72
	133
73e55cb3 BD	134	#define PORT_S3C2412 73
73e55cb3 BD	135
238b8721 PK	136	/* Xilinx uartlite */
238b8721 PK	137	#define PORT_UARTLITE 74
73e55cb3	138
194de561 BW	139	/* Blackfin bf5xx */
	140	#define PORT_BFIN 75
	141
2c7ee6ab AV	142	/* Micrel KS8695 */
	143	#define PORT_KS8695 76
	144
b45d5279 MR	145	/* Broadcom SB1250, etc. SOC */
	146	#define PORT_SB1250_DUART 77
	147
f0c15f48 GU	148	/* Freescale ColdFire */
	149	#define PORT_MCF 78
	150
2f351741 BW	151	/* Blackfin SPORT */
2f351741 BW	152	#define PORT_BFIN_SPORT 79
2c7ee6ab	153
ef3d5347 DH	154	/* MN10300 on-chip UART numbers */
	155	#define PORT_MN10300 80
	156	#define PORT_MN10300_CTS 81
	157
2f351741 BW	158	#define PORT_SC26XX 82
2f351741 BW	159
1a22f08d YS	160	/* SH-SCI */
	161	#define PORT_SCIFA 83
	162
b690ace5 BD	163	#define PORT_S3C6400 84
b690ace5 BD	164
5886188d BK	165	/* NWPSERIAL */
	166	#define PORT_NWPSERIAL 85
	167
1dcb884c CP	168	/* MAX3100 */
	169	#define PORT_MAX3100 86
	170
34aec591 RR	171	/* Timberdale UART */
	172	#define PORT_TIMBUART 87
	173
04896a77 RL	174	/* Qualcomm MSM SoCs */
	175	#define PORT_MSM 88
	176
1da177e4 LT	177	#ifdef __KERNEL__
1da177e4 LT	178
661f83a6	179	#include <linux/compiler.h>
1da177e4 LT	180	#include <linux/interrupt.h>
	181	#include <linux/circ_buf.h>
	182	#include <linux/spinlock.h>
	183	#include <linux/sched.h>
	184	#include <linux/tty.h>
e2862f6a	185	#include <linux/mutex.h>
b11115c1	186	#include <linux/sysrq.h>
1da177e4 LT	187
1da177e4 LT	188	struct uart_port;
1da177e4 LT	189	struct serial_struct;
	190	struct device;
	191
	192	/*
	193	* This structure describes all the operations that can be
	194	* done on the physical hardware.
	195	*/
	196	struct uart_ops {
	197	unsigned int (tx_empty)(struct uart_port );
	198	void (set_mctrl)(struct uart_port , unsigned int mctrl);
	199	unsigned int (get_mctrl)(struct uart_port );
b129a8cc RK	200	void (stop_tx)(struct uart_port );
b129a8cc RK	201	void (start_tx)(struct uart_port );
1da177e4 LT	202	void (send_xchar)(struct uart_port , char ch);
	203	void (stop_rx)(struct uart_port );
	204	void (enable_ms)(struct uart_port );
	205	void (break_ctl)(struct uart_port , int ctl);
	206	int (startup)(struct uart_port );
	207	void (shutdown)(struct uart_port );
6bb0e3a5	208	void (flush_buffer)(struct uart_port );
606d099c AC	209	void (set_termios)(struct uart_port , struct ktermios *new,
606d099c AC	210	struct ktermios *old);
64e9159f	211	void (set_ldisc)(struct uart_port );
1da177e4 LT	212	void (pm)(struct uart_port , unsigned int state,
	213	unsigned int oldstate);
	214	int (set_wake)(struct uart_port , unsigned int state);
	215
	216	/*
	217	* Return a string describing the type of the port
	218	*/
	219	const char (type)(struct uart_port *);
	220
	221	/*
	222	* Release IO and memory resources used by the port.
	223	* This includes iounmap if necessary.
	224	*/
	225	void (release_port)(struct uart_port );
	226
	227	/*
	228	* Request IO and memory resources used by the port.
	229	* This includes iomapping the port if necessary.
	230	*/
	231	int (request_port)(struct uart_port );
	232	void (config_port)(struct uart_port , int);
	233	int (verify_port)(struct uart_port , struct serial_struct *);
	234	int (ioctl)(struct uart_port , unsigned int, unsigned long);
f2d937f3 JW	235	#ifdef CONFIG_CONSOLE_POLL
	236	void (poll_put_char)(struct uart_port , unsigned char);
	237	int (poll_get_char)(struct uart_port );
	238	#endif
1da177e4 LT	239	};
	240
	241	#define UART_CONFIG_TYPE (1 << 0)
	242	#define UART_CONFIG_IRQ (1 << 1)
	243
	244	struct uart_icount {
	245	__u32 cts;
	246	__u32 dsr;
	247	__u32 rng;
	248	__u32 dcd;
	249	__u32 rx;
	250	__u32 tx;
	251	__u32 frame;
	252	__u32 overrun;
	253	__u32 parity;
	254	__u32 brk;
	255	__u32 buf_overrun;
	256	};
	257
0077d45e RK	258	typedef unsigned int __bitwise__ upf_t;
0077d45e RK	259
1da177e4 LT	260	struct uart_port {
1da177e4 LT	261	spinlock_t lock; /* port lock */
0c8946d9	262	unsigned long iobase; /* in/out[bwl] */
1da177e4	263	unsigned char __iomem membase; / read/write[bwl] */
7d6a07d1 DD	264	unsigned int (serial_in)(struct uart_port , int);
7d6a07d1 DD	265	void (serial_out)(struct uart_port , int, int);
1da177e4	266	unsigned int irq; /* irq number */
1c2f0493	267	unsigned long irqflags; /* irq flags */
1da177e4	268	unsigned int uartclk; /* base uart clock */
947deee8	269	unsigned int fifosize; /* tx fifo size */
1da177e4 LT	270	unsigned char x_char; /* xon/xoff char */
	271	unsigned char regshift; /* reg offset shift */
	272	unsigned char iotype; /* io access style */
947deee8	273	unsigned char unused1;
1da177e4 LT	274
	275	#define UPIO_PORT (0)
	276	#define UPIO_HUB6 (1)
	277	#define UPIO_MEM (2)
	278	#define UPIO_MEM32 (3)
21c614a7	279	#define UPIO_AU (4) /* Au1x00 type IO */
3be91ec7	280	#define UPIO_TSI (5) /* Tsi108/109 type IO */
beab697a	281	#define UPIO_DWAPB (6) /* DesignWare APB UART */
bd71c182	282	#define UPIO_RM9000 (7) /* RM9000 type IO */
1da177e4 LT	283
	284	unsigned int read_status_mask; /* driver specific */
	285	unsigned int ignore_status_mask; /* driver specific */
ebd2c8f6	286	struct uart_state state; / pointer to parent state */
1da177e4 LT	287	struct uart_icount icount; /* statistics */
	288
	289	struct console cons; / struct console, if any */
06e82df0	290	#if defined(CONFIG_SERIAL_CORE_CONSOLE) \|\| defined(SUPPORT_SYSRQ)
1da177e4 LT	291	unsigned long sysrq; /* sysrq timeout */
	292	#endif
	293
0077d45e RK	294	upf_t flags;
	295
	296	#define UPF_FOURPORT ((__force upf_t) (1 << 1))
	297	#define UPF_SAK ((__force upf_t) (1 << 2))
	298	#define UPF_SPD_MASK ((__force upf_t) (0x1030))
	299	#define UPF_SPD_HI ((__force upf_t) (0x0010))
	300	#define UPF_SPD_VHI ((__force upf_t) (0x0020))
	301	#define UPF_SPD_CUST ((__force upf_t) (0x0030))
	302	#define UPF_SPD_SHI ((__force upf_t) (0x1000))
	303	#define UPF_SPD_WARP ((__force upf_t) (0x1010))
	304	#define UPF_SKIP_TEST ((__force upf_t) (1 << 6))
	305	#define UPF_AUTO_IRQ ((__force upf_t) (1 << 7))
	306	#define UPF_HARDPPS_CD ((__force upf_t) (1 << 11))
	307	#define UPF_LOW_LATENCY ((__force upf_t) (1 << 13))
	308	#define UPF_BUGGY_UART ((__force upf_t) (1 << 14))
b6adea33	309	#define UPF_NO_TXEN_TEST ((__force upf_t) (1 << 15))
0077d45e RK	310	#define UPF_MAGIC_MULTIPLIER ((__force upf_t) (1 << 16))
	311	#define UPF_CONS_FLOW ((__force upf_t) (1 << 23))
	312	#define UPF_SHARE_IRQ ((__force upf_t) (1 << 24))
8e23fcc8 DD	313	/* The exact UART type is known and should not be probed. */
8e23fcc8 DD	314	#define UPF_FIXED_TYPE ((__force upf_t) (1 << 27))
0077d45e	315	#define UPF_BOOT_AUTOCONF ((__force upf_t) (1 << 28))
abb4a239	316	#define UPF_FIXED_PORT ((__force upf_t) (1 << 29))
68ac64cd	317	#define UPF_DEAD ((__force upf_t) (1 << 30))
0077d45e RK	318	#define UPF_IOREMAP ((__force upf_t) (1 << 31))
	319
	320	#define UPF_CHANGE_MASK ((__force upf_t) (0x17fff))
	321	#define UPF_USR_MASK ((__force upf_t) (UPF_SPD_MASK\|UPF_LOW_LATENCY))
1da177e4 LT	322
	323	unsigned int mctrl; /* current modem ctrl settings */
	324	unsigned int timeout; /* character-based timeout */
	325	unsigned int type; /* port type */
ba899dbc	326	const struct uart_ops *ops;
1da177e4 LT	327	unsigned int custom_divisor;
1da177e4 LT	328	unsigned int line; /* port index */
4f640efb	329	resource_size_t mapbase; /* for ioremap */
1da177e4 LT	330	struct device dev; / parent device */
1da177e4 LT	331	unsigned char hub6; /* this should be in the 8250 driver */
b3b708fa GL	332	unsigned char suspended;
b3b708fa GL	333	unsigned char unused[2];
beab697a	334	void private_data; / generic platform data pointer */
1da177e4 LT	335	};
1da177e4 LT	336
1da177e4 LT	337	/*
1da177e4 LT	338	* This is the state information which is only valid when the port
f751928e	339	* is open; it may be cleared the core driver once the device has
1da177e4 LT	340	* been closed. Either the low level driver or the core can modify
	341	* stuff here.
	342	*/
f751928e AC	343	typedef unsigned int __bitwise__ uif_t;
f751928e AC	344
ebd2c8f6 AC	345
	346	/*
	347	* This is the state information which is persistent across opens.
	348	* The low level driver must not to touch any elements contained
	349	* within.
	350	*/
	351	struct uart_state {
df4f4dd4	352	struct tty_port port;
ebd2c8f6 AC	353
	354	#define USF_CLOSING_WAIT_INF (0)
	355	#define USF_CLOSING_WAIT_NONE (~0U)
	356
ebd2c8f6	357	int pm_state;
1da177e4	358	struct circ_buf xmit;
747c8a55	359	uif_t flags;
1da177e4 LT	360
1da177e4 LT	361	/*
747c8a55 RK	362	* Definitions for info->flags. These are _private_ to serial_core, and
747c8a55 RK	363	* are specific to this structure. They may be queried by low level drivers.
df4f4dd4 AC	364	*
df4f4dd4 AC	365	* FIXME: use the ASY_ definitions
1da177e4	366	*/
747c8a55 RK	367	#define UIF_CHECK_CD ((__force uif_t) (1 << 25))
	368	#define UIF_CTS_FLOW ((__force uif_t) (1 << 26))
	369	#define UIF_NORMAL_ACTIVE ((__force uif_t) (1 << 29))
	370	#define UIF_INITIALIZED ((__force uif_t) (1 << 31))
a6b93a90	371	#define UIF_SUSPENDED ((__force uif_t) (1 << 30))
1da177e4	372
1da177e4	373	struct tasklet_struct tlet;
1da177e4	374	wait_queue_head_t delta_msr_wait;
ebd2c8f6	375	struct uart_port *uart_port;
f751928e AC	376
	377	struct mutex mutex;
	378	};
	379
	380	#define UART_XMIT_SIZE PAGE_SIZE
	381
	382
1da177e4 LT	383	/* number of characters left in xmit buffer before we ask for more */
	384	#define WAKEUP_CHARS 256
	385
	386	struct module;
	387	struct tty_driver;
	388
	389	struct uart_driver {
	390	struct module *owner;
	391	const char *driver_name;
	392	const char *dev_name;
1da177e4 LT	393	int major;
	394	int minor;
	395	int nr;
	396	struct console *cons;
	397
	398	/*
	399	* these are private; the low level driver should not
	400	* touch these; they should be initialised to NULL
	401	*/
	402	struct uart_state *state;
	403	struct tty_driver *tty_driver;
	404	};
	405
	406	void uart_write_wakeup(struct uart_port *port);
	407
	408	/*
	409	* Baud rate helpers.
	410	*/
	411	void uart_update_timeout(struct uart_port *port, unsigned int cflag,
	412	unsigned int baud);
606d099c AC	413	unsigned int uart_get_baud_rate(struct uart_port port, struct ktermios termios,
606d099c AC	414	struct ktermios *old, unsigned int min,
1da177e4 LT	415	unsigned int max);
	416	unsigned int uart_get_divisor(struct uart_port *port, unsigned int baud);
	417
	418	/*
	419	* Console helpers.
	420	*/
	421	struct uart_port uart_get_console(struct uart_port ports, int nr,
	422	struct console *c);
	423	void uart_parse_options(char options, int baud, int parity, int bits,
	424	int *flow);
	425	int uart_set_options(struct uart_port port, struct console co, int baud,
	426	int parity, int bits, int flow);
	427	struct tty_driver uart_console_device(struct console co, int *index);
d358788f RK	428	void uart_console_write(struct uart_port port, const char s,
	429	unsigned int count,
	430	void (putchar)(struct uart_port , int));
1da177e4 LT	431
	432	/*
	433	* Port/driver registration/removal
	434	*/
	435	int uart_register_driver(struct uart_driver *uart);
	436	void uart_unregister_driver(struct uart_driver *uart);
1da177e4 LT	437	int uart_add_one_port(struct uart_driver reg, struct uart_port port);
	438	int uart_remove_one_port(struct uart_driver reg, struct uart_port port);
	439	int uart_match_port(struct uart_port port1, struct uart_port port2);
	440
	441	/*
	442	* Power Management
	443	*/
	444	int uart_suspend_port(struct uart_driver reg, struct uart_port port);
	445	int uart_resume_port(struct uart_driver reg, struct uart_port port);
	446
	447	#define uart_circ_empty(circ) ((circ)->head == (circ)->tail)
	448	#define uart_circ_clear(circ) ((circ)->head = (circ)->tail = 0)
	449
	450	#define uart_circ_chars_pending(circ) \
	451	(CIRC_CNT((circ)->head, (circ)->tail, UART_XMIT_SIZE))
	452
	453	#define uart_circ_chars_free(circ) \
	454	(CIRC_SPACE((circ)->head, (circ)->tail, UART_XMIT_SIZE))
	455
f751928e AC	456	static inline int uart_tx_stopped(struct uart_port *port)
f751928e AC	457	{
ebd2c8f6	458	struct tty_struct *tty = port->state->port.tty;
f751928e AC	459	if(tty->stopped \|\| tty->hw_stopped)
	460	return 1;
	461	return 0;
	462	}
1da177e4 LT	463
	464	/*
	465	* The following are helper functions for the low level drivers.
	466	*/
1da177e4	467	static inline int
7d12e780	468	uart_handle_sysrq_char(struct uart_port *port, unsigned int ch)
1da177e4	469	{
93c37f29	470	#ifdef SUPPORT_SYSRQ
1da177e4 LT	471	if (port->sysrq) {
1da177e4 LT	472	if (ch && time_before(jiffies, port->sysrq)) {
ebd2c8f6	473	handle_sysrq(ch, port->state->port.tty);
1da177e4 LT	474	port->sysrq = 0;
	475	return 1;
	476	}
	477	port->sysrq = 0;
	478	}
93c37f29	479	#endif
1da177e4 LT	480	return 0;
1da177e4 LT	481	}
4e149184	482	#ifndef SUPPORT_SYSRQ
7d12e780	483	#define uart_handle_sysrq_char(port,ch) uart_handle_sysrq_char(port, 0)
4e149184	484	#endif
1da177e4 LT	485
	486	/*
	487	* We do the SysRQ and SAK checking like this...
	488	*/
	489	static inline int uart_handle_break(struct uart_port *port)
	490	{
ebd2c8f6	491	struct uart_state *state = port->state;
1da177e4 LT	492	#ifdef SUPPORT_SYSRQ
	493	if (port->cons && port->cons->index == port->line) {
	494	if (!port->sysrq) {
	495	port->sysrq = jiffies + HZ*5;
	496	return 1;
	497	}
	498	port->sysrq = 0;
	499	}
	500	#endif
27ae7a74	501	if (port->flags & UPF_SAK)
ebd2c8f6	502	do_SAK(state->port.tty);
1da177e4 LT	503	return 0;
	504	}
	505
	506	/**
	507	* uart_handle_dcd_change - handle a change of carrier detect state
	508	* @port: uart_port structure for the open port
	509	* @status: new carrier detect status, nonzero if active
	510	*/
	511	static inline void
	512	uart_handle_dcd_change(struct uart_port *port, unsigned int status)
	513	{
ebd2c8f6	514	struct uart_state *state = port->state;
1da177e4 LT	515
	516	port->icount.dcd++;
	517
	518	#ifdef CONFIG_HARD_PPS
	519	if ((port->flags & UPF_HARDPPS_CD) && status)
	520	hardpps();
	521	#endif
	522
ebd2c8f6	523	if (state->flags & UIF_CHECK_CD) {
1da177e4	524	if (status)
ebd2c8f6 AC	525	wake_up_interruptible(&state->port.open_wait);
	526	else if (state->port.tty)
	527	tty_hangup(state->port.tty);
1da177e4 LT	528	}
	529	}
	530
	531	/**
	532	* uart_handle_cts_change - handle a change of clear-to-send state
	533	* @port: uart_port structure for the open port
	534	* @status: new clear to send status, nonzero if active
	535	*/
	536	static inline void
	537	uart_handle_cts_change(struct uart_port *port, unsigned int status)
	538	{
ebd2c8f6 AC	539	struct uart_state *state = port->state;
ebd2c8f6 AC	540	struct tty_struct *tty = state->port.tty;
1da177e4 LT	541
	542	port->icount.cts++;
	543
ebd2c8f6	544	if (state->flags & UIF_CTS_FLOW) {
1da177e4 LT	545	if (tty->hw_stopped) {
	546	if (status) {
	547	tty->hw_stopped = 0;
b129a8cc	548	port->ops->start_tx(port);
1da177e4 LT	549	uart_write_wakeup(port);
	550	}
	551	} else {
	552	if (!status) {
	553	tty->hw_stopped = 1;
b129a8cc	554	port->ops->stop_tx(port);
1da177e4 LT	555	}
	556	}
	557	}
	558	}
	559
05ab3014 RK	560	#include <linux/tty_flip.h>
	561
	562	static inline void
	563	uart_insert_char(struct uart_port *port, unsigned int status,
	564	unsigned int overrun, unsigned int ch, unsigned int flag)
	565	{
ebd2c8f6	566	struct tty_struct *tty = port->state->port.tty;
05ab3014 RK	567
	568	if ((status & port->ignore_status_mask & ~overrun) == 0)
	569	tty_insert_flip_char(tty, ch, flag);
	570
	571	/*
	572	* Overrun is special. Since it's reported immediately,
	573	* it doesn't affect the current character.
	574	*/
	575	if (status & ~port->ignore_status_mask & overrun)
	576	tty_insert_flip_char(tty, 0, TTY_OVERRUN);
	577	}
	578
1da177e4 LT	579	/*
	580	* UART_ENABLE_MS - determine if port should enable modem status irqs
	581	*/
	582	#define UART_ENABLE_MS(port,cflag) ((port)->flags & UPF_HARDPPS_CD \|\| \
	583	(cflag) & CRTSCTS \|\| \
	584	!((cflag) & CLOCAL))
	585
	586	#endif
	587
	588	#endif /* LINUX_SERIAL_CORE_H */