[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / serial_core.h

/*
 *  linux/drivers/char/serial_core.h
 *
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#ifndef LINUX_SERIAL_CORE_H
#define LINUX_SERIAL_CORE_H

#include <linux/serial.h>

/*
 * The type definitions.  These are from Ted Ts'o's serial.h
 */
#define PORT_UNKNOWN	0
#define PORT_8250	1
#define PORT_16450	2
#define PORT_16550	3
#define PORT_16550A	4
#define PORT_CIRRUS	5
#define PORT_16650	6
#define PORT_16650V2	7
#define PORT_16750	8
#define PORT_STARTECH	9
#define PORT_16C950	10
#define PORT_16654	11
#define PORT_16850	12
#define PORT_RSA	13
#define PORT_NS16550A	14
#define PORT_XSCALE	15
#define PORT_RM9000	16	/* PMC-Sierra RM9xxx internal UART */
#define PORT_OCTEON	17	/* Cavium OCTEON internal UART */
#define PORT_AR7	18	/* Texas Instruments AR7 internal UART */
#define PORT_U6_16550A	19	/* ST-Ericsson U6xxx internal UART */
#define PORT_MAX_8250	19	/* max port ID */

/*
 * ARM specific type numbers.  These are not currently guaranteed
 * to be implemented, and will change in the future.  These are
 * separate so any additions to the old serial.c that occur before
 * we are merged can be easily merged here.
 */
#define PORT_PXA	31
#define PORT_AMBA	32
#define PORT_CLPS711X	33
#define PORT_SA1100	34
#define PORT_UART00	35
#define PORT_21285	37

/* Sparc type numbers.  */
#define PORT_SUNZILOG	38
#define PORT_SUNSAB	39

/* DEC */
#define PORT_DZ		46
#define PORT_ZS		47

/* Parisc type numbers. */
#define PORT_MUX	48

/* Atmel AT91 / AT32 SoC */
#define PORT_ATMEL	49

/* Macintosh Zilog type numbers */
#define PORT_MAC_ZILOG	50	/* m68k : not yet implemented */
#define PORT_PMAC_ZILOG	51

/* SH-SCI */
#define PORT_SCI	52
#define PORT_SCIF	53
#define PORT_IRDA	54

/* Samsung S3C2410 SoC and derivatives thereof */
#define PORT_S3C2410    55

/* SGI IP22 aka Indy / Challenge S / Indigo 2 */
#define PORT_IP22ZILOG	56

/* Sharp LH7a40x -- an ARM9 SoC series */
#define PORT_LH7A40X	57

/* PPC CPM type number */
#define PORT_CPM        58

/* MPC52xx (and MPC512x) type numbers */
#define PORT_MPC52xx	59

/* IBM icom */
#define PORT_ICOM	60

/* Samsung S3C2440 SoC */
#define PORT_S3C2440	61

/* Motorola i.MX SoC */
#define PORT_IMX	62

/* Marvell MPSC */
#define PORT_MPSC	63

/* TXX9 type number */
#define PORT_TXX9	64

/* NEC VR4100 series SIU/DSIU */
#define PORT_VR41XX_SIU		65
#define PORT_VR41XX_DSIU	66

/* Samsung S3C2400 SoC */
#define PORT_S3C2400	67

/* M32R SIO */
#define PORT_M32R_SIO	68

/*Digi jsm */
#define PORT_JSM        69

#define PORT_PNX8XXX	70

/* Hilscher netx */
#define PORT_NETX	71

/* SUN4V Hypervisor Console */
#define PORT_SUNHV	72

#define PORT_S3C2412	73

/* Xilinx uartlite */
#define PORT_UARTLITE	74

/* Blackfin bf5xx */
#define PORT_BFIN	75

/* Micrel KS8695 */
#define PORT_KS8695	76

/* Broadcom SB1250, etc. SOC */
#define PORT_SB1250_DUART	77

/* Freescale ColdFire */
#define PORT_MCF	78

/* Blackfin SPORT */
#define PORT_BFIN_SPORT		79

/* MN10300 on-chip UART numbers */
#define PORT_MN10300		80
#define PORT_MN10300_CTS	81

#define PORT_SC26XX	82

/* SH-SCI */
#define PORT_SCIFA	83

#define PORT_S3C6400	84

/* NWPSERIAL */
#define PORT_NWPSERIAL	85

/* MAX3100 */
#define PORT_MAX3100    86

/* Timberdale UART */
#define PORT_TIMBUART	87

/* Qualcomm MSM SoCs */
#define PORT_MSM	88

/* BCM63xx family SoCs */
#define PORT_BCM63XX	89

/* Aeroflex Gaisler GRLIB APBUART */
#define PORT_APBUART    90

/* Altera UARTs */
#define PORT_ALTERA_JTAGUART	91
#define PORT_ALTERA_UART	92

/* SH-SCI */
#define PORT_SCIFB	93

/* MAX3107 */
#define PORT_MAX3107	94

/* High Speed UART for Medfield */
#define PORT_MFD	95

/* TI OMAP-UART */
#define PORT_OMAP	96

/* VIA VT8500 SoC */
#define PORT_VT8500	97

#ifdef __KERNEL__

#include <linux/compiler.h>
#include <linux/interrupt.h>
#include <linux/circ_buf.h>
#include <linux/spinlock.h>
#include <linux/sched.h>
#include <linux/tty.h>
#include <linux/mutex.h>
#include <linux/sysrq.h>

struct uart_port;
struct serial_struct;
struct device;

/*
 * This structure describes all the operations that can be
 * done on the physical hardware.
 */
struct uart_ops {
	unsigned int	(*tx_empty)(struct uart_port *);
	void		(*set_mctrl)(struct uart_port *, unsigned int mctrl);
	unsigned int	(*get_mctrl)(struct uart_port *);
	void		(*stop_tx)(struct uart_port *);
	void		(*start_tx)(struct uart_port *);
	void		(*send_xchar)(struct uart_port *, char ch);
	void		(*stop_rx)(struct uart_port *);
	void		(*enable_ms)(struct uart_port *);
	void		(*break_ctl)(struct uart_port *, int ctl);
	int		(*startup)(struct uart_port *);
	void		(*shutdown)(struct uart_port *);
	void		(*flush_buffer)(struct uart_port *);
	void		(*set_termios)(struct uart_port *, struct ktermios *new,
				       struct ktermios *old);
	void		(*set_ldisc)(struct uart_port *, int new);
	void		(*pm)(struct uart_port *, unsigned int state,
			      unsigned int oldstate);
	int		(*set_wake)(struct uart_port *, unsigned int state);

	/*
	 * Return a string describing the type of the port
	 */
	const char *(*type)(struct uart_port *);

	/*
	 * Release IO and memory resources used by the port.
	 * This includes iounmap if necessary.
	 */
	void		(*release_port)(struct uart_port *);

	/*
	 * Request IO and memory resources used by the port.
	 * This includes iomapping the port if necessary.
	 */
	int		(*request_port)(struct uart_port *);
	void		(*config_port)(struct uart_port *, int);
	int		(*verify_port)(struct uart_port *, struct serial_struct *);
	int		(*ioctl)(struct uart_port *, unsigned int, unsigned long);
#ifdef CONFIG_CONSOLE_POLL
	void	(*poll_put_char)(struct uart_port *, unsigned char);
	int		(*poll_get_char)(struct uart_port *);
#endif
};

#define NO_POLL_CHAR		0x00ff0000
#define UART_CONFIG_TYPE	(1 << 0)
#define UART_CONFIG_IRQ		(1 << 1)

struct uart_icount {
	__u32	cts;
	__u32	dsr;
	__u32	rng;
	__u32	dcd;
	__u32	rx;
	__u32	tx;
	__u32	frame;
	__u32	overrun;
	__u32	parity;
	__u32	brk;
	__u32	buf_overrun;
};

typedef unsigned int __bitwise__ upf_t;

struct uart_port {
	spinlock_t		lock;			/* port lock */
	unsigned long		iobase;			/* in/out[bwl] */
	unsigned char __iomem	*membase;		/* read/write[bwl] */
	unsigned int		(*serial_in)(struct uart_port *, int);
	void			(*serial_out)(struct uart_port *, int, int);
	void			(*set_termios)(struct uart_port *,
				               struct ktermios *new,
				               struct ktermios *old);
	void			(*pm)(struct uart_port *, unsigned int state,
				      unsigned int old);
	unsigned int		irq;			/* irq number */
	unsigned long		irqflags;		/* irq flags  */
	unsigned int		uartclk;		/* base uart clock */
	unsigned int		fifosize;		/* tx fifo size */
	unsigned char		x_char;			/* xon/xoff char */
	unsigned char		regshift;		/* reg offset shift */
	unsigned char		iotype;			/* io access style */
	unsigned char		unused1;

#define UPIO_PORT		(0)
#define UPIO_HUB6		(1)
#define UPIO_MEM		(2)
#define UPIO_MEM32		(3)
#define UPIO_AU			(4)			/* Au1x00 type IO */
#define UPIO_TSI		(5)			/* Tsi108/109 type IO */
#define UPIO_DWAPB		(6)			/* DesignWare APB UART */
#define UPIO_RM9000		(7)			/* RM9000 type IO */
#define UPIO_DWAPB32		(8)			/* DesignWare APB UART (32 bit accesses) */

	unsigned int		read_status_mask;	/* driver specific */
	unsigned int		ignore_status_mask;	/* driver specific */
	struct uart_state	*state;			/* pointer to parent state */
	struct uart_icount	icount;			/* statistics */

	struct console		*cons;			/* struct console, if any */
#if defined(CONFIG_SERIAL_CORE_CONSOLE) || defined(SUPPORT_SYSRQ)
	unsigned long		sysrq;			/* sysrq timeout */
#endif

	upf_t			flags;

#define UPF_FOURPORT		((__force upf_t) (1 << 1))
#define UPF_SAK			((__force upf_t) (1 << 2))
#define UPF_SPD_MASK		((__force upf_t) (0x1030))
#define UPF_SPD_HI		((__force upf_t) (0x0010))
#define UPF_SPD_VHI		((__force upf_t) (0x0020))
#define UPF_SPD_CUST		((__force upf_t) (0x0030))
#define UPF_SPD_SHI		((__force upf_t) (0x1000))
#define UPF_SPD_WARP		((__force upf_t) (0x1010))
#define UPF_SKIP_TEST		((__force upf_t) (1 << 6))
#define UPF_AUTO_IRQ		((__force upf_t) (1 << 7))
#define UPF_HARDPPS_CD		((__force upf_t) (1 << 11))
#define UPF_LOW_LATENCY		((__force upf_t) (1 << 13))
#define UPF_BUGGY_UART		((__force upf_t) (1 << 14))
#define UPF_NO_TXEN_TEST	((__force upf_t) (1 << 15))
#define UPF_MAGIC_MULTIPLIER	((__force upf_t) (1 << 16))
#define UPF_CONS_FLOW		((__force upf_t) (1 << 23))
#define UPF_SHARE_IRQ		((__force upf_t) (1 << 24))
/* The exact UART type is known and should not be probed.  */
#define UPF_FIXED_TYPE		((__force upf_t) (1 << 27))
#define UPF_BOOT_AUTOCONF	((__force upf_t) (1 << 28))
#define UPF_FIXED_PORT		((__force upf_t) (1 << 29))
#define UPF_DEAD		((__force upf_t) (1 << 30))
#define UPF_IOREMAP		((__force upf_t) (1 << 31))

#define UPF_CHANGE_MASK		((__force upf_t) (0x17fff))
#define UPF_USR_MASK		((__force upf_t) (UPF_SPD_MASK|UPF_LOW_LATENCY))

	unsigned int		mctrl;			/* current modem ctrl settings */
	unsigned int		timeout;		/* character-based timeout */
	unsigned int		type;			/* port type */
	const struct uart_ops	*ops;
	unsigned int		custom_divisor;
	unsigned int		line;			/* port index */
	resource_size_t		mapbase;		/* for ioremap */
	struct device		*dev;			/* parent device */
	unsigned char		hub6;			/* this should be in the 8250 driver */
	unsigned char		suspended;
	unsigned char		unused[2];
	void			*private_data;		/* generic platform data pointer */
};

/*
 * This is the state information which is persistent across opens.
 */
struct uart_state {
	struct tty_port		port;

	int			pm_state;
	struct circ_buf		xmit;

	struct tasklet_struct	tlet;
	struct uart_port	*uart_port;
};

#define UART_XMIT_SIZE	PAGE_SIZE


/* number of characters left in xmit buffer before we ask for more */
#define WAKEUP_CHARS		256

struct module;
struct tty_driver;

struct uart_driver {
	struct module		*owner;
	const char		*driver_name;
	const char		*dev_name;
	int			 major;
	int			 minor;
	int			 nr;
	struct console		*cons;

	/*
	 * these are private; the low level driver should not
	 * touch these; they should be initialised to NULL
	 */
	struct uart_state	*state;
	struct tty_driver	*tty_driver;
};

void uart_write_wakeup(struct uart_port *port);

/*
 * Baud rate helpers.
 */
void uart_update_timeout(struct uart_port *port, unsigned int cflag,
			 unsigned int baud);
unsigned int uart_get_baud_rate(struct uart_port *port, struct ktermios *termios,
				struct ktermios *old, unsigned int min,
				unsigned int max);
unsigned int uart_get_divisor(struct uart_port *port, unsigned int baud);

/* Base timer interval for polling */
static inline int uart_poll_timeout(struct uart_port *port)
{
	int timeout = port->timeout;

	return timeout > 6 ? (timeout / 2 - 2) : 1;
}

/*
 * Console helpers.
 */
struct uart_port *uart_get_console(struct uart_port *ports, int nr,
				   struct console *c);
void uart_parse_options(char *options, int *baud, int *parity, int *bits,
			int *flow);
int uart_set_options(struct uart_port *port, struct console *co, int baud,
		     int parity, int bits, int flow);
struct tty_driver *uart_console_device(struct console *co, int *index);
void uart_console_write(struct uart_port *port, const char *s,
			unsigned int count,
			void (*putchar)(struct uart_port *, int));

/*
 * Port/driver registration/removal
 */
int uart_register_driver(struct uart_driver *uart);
void uart_unregister_driver(struct uart_driver *uart);
int uart_add_one_port(struct uart_driver *reg, struct uart_port *port);
int uart_remove_one_port(struct uart_driver *reg, struct uart_port *port);
int uart_match_port(struct uart_port *port1, struct uart_port *port2);

/*
 * Power Management
 */
int uart_suspend_port(struct uart_driver *reg, struct uart_port *port);
int uart_resume_port(struct uart_driver *reg, struct uart_port *port);

#define uart_circ_empty(circ)		((circ)->head == (circ)->tail)
#define uart_circ_clear(circ)		((circ)->head = (circ)->tail = 0)

#define uart_circ_chars_pending(circ)	\
	(CIRC_CNT((circ)->head, (circ)->tail, UART_XMIT_SIZE))

#define uart_circ_chars_free(circ)	\
	(CIRC_SPACE((circ)->head, (circ)->tail, UART_XMIT_SIZE))

static inline int uart_tx_stopped(struct uart_port *port)
{
	struct tty_struct *tty = port->state->port.tty;
	if(tty->stopped || tty->hw_stopped)
		return 1;
	return 0;
}

/*
 * The following are helper functions for the low level drivers.
 */
static inline int
uart_handle_sysrq_char(struct uart_port *port, unsigned int ch)
{
#ifdef SUPPORT_SYSRQ
	if (port->sysrq) {
		if (ch && time_before(jiffies, port->sysrq)) {
			handle_sysrq(ch);
			port->sysrq = 0;
			return 1;
		}
		port->sysrq = 0;
	}
#endif
	return 0;
}
#ifndef SUPPORT_SYSRQ
#define uart_handle_sysrq_char(port,ch) uart_handle_sysrq_char(port, 0)
#endif

/*
 * We do the SysRQ and SAK checking like this...
 */
static inline int uart_handle_break(struct uart_port *port)
{
	struct uart_state *state = port->state;
#ifdef SUPPORT_SYSRQ
	if (port->cons && port->cons->index == port->line) {
		if (!port->sysrq) {
			port->sysrq = jiffies + HZ*5;
			return 1;
		}
		port->sysrq = 0;
	}
#endif
	if (port->flags & UPF_SAK)
		do_SAK(state->port.tty);
	return 0;
}

/**
 *	uart_handle_dcd_change - handle a change of carrier detect state
 *	@uport: uart_port structure for the open port
 *	@status: new carrier detect status, nonzero if active
 */
static inline void
uart_handle_dcd_change(struct uart_port *uport, unsigned int status)
{
	struct uart_state *state = uport->state;
	struct tty_port *port = &state->port;
	struct tty_ldisc *ld = tty_ldisc_ref(port->tty);
	struct timespec ts;

	if (ld && ld->ops->dcd_change)
		getnstimeofday(&ts);

	uport->icount.dcd++;
#ifdef CONFIG_HARD_PPS
	if ((uport->flags & UPF_HARDPPS_CD) && status)
		hardpps();
#endif

	if (port->flags & ASYNC_CHECK_CD) {
		if (status)
			wake_up_interruptible(&port->open_wait);
		else if (port->tty)
			tty_hangup(port->tty);
	}

	if (ld && ld->ops->dcd_change)
		ld->ops->dcd_change(port->tty, status, &ts);
	if (ld)
		tty_ldisc_deref(ld);
}

/**
 *	uart_handle_cts_change - handle a change of clear-to-send state
 *	@uport: uart_port structure for the open port
 *	@status: new clear to send status, nonzero if active
 */
static inline void
uart_handle_cts_change(struct uart_port *uport, unsigned int status)
{
	struct tty_port *port = &uport->state->port;
	struct tty_struct *tty = port->tty;

	uport->icount.cts++;

	if (port->flags & ASYNC_CTS_FLOW) {
		if (tty->hw_stopped) {
			if (status) {
				tty->hw_stopped = 0;
				uport->ops->start_tx(uport);
				uart_write_wakeup(uport);
			}
		} else {
			if (!status) {
				tty->hw_stopped = 1;
				uport->ops->stop_tx(uport);
			}
		}
	}
}

#include <linux/tty_flip.h>

static inline void
uart_insert_char(struct uart_port *port, unsigned int status,
		 unsigned int overrun, unsigned int ch, unsigned int flag)
{
	struct tty_struct *tty = port->state->port.tty;

	if ((status & port->ignore_status_mask & ~overrun) == 0)
		tty_insert_flip_char(tty, ch, flag);

	/*
	 * Overrun is special.  Since it's reported immediately,
	 * it doesn't affect the current character.
	 */
	if (status & ~port->ignore_status_mask & overrun)
		tty_insert_flip_char(tty, 0, TTY_OVERRUN);
}

/*
 *	UART_ENABLE_MS - determine if port should enable modem status irqs
 */
#define UART_ENABLE_MS(port,cflag)	((port)->flags & UPF_HARDPPS_CD || \
					 (cflag) & CRTSCTS || \
					 !((cflag) & CLOCAL))

#endif

#endif /* LINUX_SERIAL_CORE_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/drivers/char/serial_core.h
	3	*
	4	* Copyright (C) 2000 Deep Blue Solutions Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#ifndef LINUX_SERIAL_CORE_H
	21	#define LINUX_SERIAL_CORE_H
	22
ccce6deb AC	23	#include <linux/serial.h>
ccce6deb AC	24
1da177e4 LT	25	/*
	26	* The type definitions. These are from Ted Ts'o's serial.h
	27	*/
	28	#define PORT_UNKNOWN 0
	29	#define PORT_8250 1
	30	#define PORT_16450 2
	31	#define PORT_16550 3
	32	#define PORT_16550A 4
	33	#define PORT_CIRRUS 5
	34	#define PORT_16650 6
	35	#define PORT_16650V2 7
	36	#define PORT_16750 8
	37	#define PORT_STARTECH 9
	38	#define PORT_16C950 10
	39	#define PORT_16654 11
	40	#define PORT_16850 12
	41	#define PORT_RSA 13
	42	#define PORT_NS16550A 14
	43	#define PORT_XSCALE 15
bd71c182	44	#define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
6b06f191	45	#define PORT_OCTEON 17 /* Cavium OCTEON internal UART */
08e0992f	46	#define PORT_AR7 18 /* Texas Instruments AR7 internal UART */
71cad055 PL	47	#define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
71cad055 PL	48	#define PORT_MAX_8250 19 /* max port ID */
1da177e4 LT	49
	50	/*
	51	* ARM specific type numbers. These are not currently guaranteed
	52	* to be implemented, and will change in the future. These are
	53	* separate so any additions to the old serial.c that occur before
	54	* we are merged can be easily merged here.
	55	*/
	56	#define PORT_PXA 31
	57	#define PORT_AMBA 32
	58	#define PORT_CLPS711X 33
	59	#define PORT_SA1100 34
	60	#define PORT_UART00 35
	61	#define PORT_21285 37
	62
	63	/* Sparc type numbers. */
	64	#define PORT_SUNZILOG 38
	65	#define PORT_SUNSAB 39
	66
8b4a4080 MR	67	/* DEC */
	68	#define PORT_DZ 46
	69	#define PORT_ZS 47
1da177e4 LT	70
	71	/* Parisc type numbers. */
	72	#define PORT_MUX 48
	73
9ab4f88b HS	74	/* Atmel AT91 / AT32 SoC */
9ab4f88b HS	75	#define PORT_ATMEL 49
1e6c9c28	76
1da177e4 LT	77	/* Macintosh Zilog type numbers */
	78	#define PORT_MAC_ZILOG 50 /* m68k : not yet implemented */
	79	#define PORT_PMAC_ZILOG 51
	80
	81	/* SH-SCI */
	82	#define PORT_SCI 52
	83	#define PORT_SCIF 53
	84	#define PORT_IRDA 54
	85
	86	/* Samsung S3C2410 SoC and derivatives thereof */
	87	#define PORT_S3C2410 55
	88
	89	/* SGI IP22 aka Indy / Challenge S / Indigo 2 */
	90	#define PORT_IP22ZILOG 56
	91
	92	/* Sharp LH7a40x -- an ARM9 SoC series */
	93	#define PORT_LH7A40X 57
	94
	95	/* PPC CPM type number */
	96	#define PORT_CPM 58
	97
e44dcb6c	98	/* MPC52xx (and MPC512x) type numbers */
1da177e4 LT	99	#define PORT_MPC52xx 59
	100
	101	/* IBM icom */
	102	#define PORT_ICOM 60
	103
	104	/* Samsung S3C2440 SoC */
	105	#define PORT_S3C2440 61
	106
	107	/* Motorola i.MX SoC */
	108	#define PORT_IMX 62
	109
	110	/* Marvell MPSC */
	111	#define PORT_MPSC 63
	112
	113	/* TXX9 type number */
e5c2d749	114	#define PORT_TXX9 64
1da177e4 LT	115
	116	/* NEC VR4100 series SIU/DSIU */
	117	#define PORT_VR41XX_SIU 65
	118	#define PORT_VR41XX_DSIU 66
	119
	120	/* Samsung S3C2400 SoC */
	121	#define PORT_S3C2400 67
	122
	123	/* M32R SIO */
	124	#define PORT_M32R_SIO 68
	125
	126	/Digi jsm /
913ade51 RK	127	#define PORT_JSM 69
913ade51 RK	128
e6fa0ba3	129	#define PORT_PNX8XXX 70
1da177e4	130
f5417612 SH	131	/* Hilscher netx */
	132	#define PORT_NETX 71
	133
02fd473b DM	134	/* SUN4V Hypervisor Console */
	135	#define PORT_SUNHV 72
	136
73e55cb3 BD	137	#define PORT_S3C2412 73
73e55cb3 BD	138
238b8721 PK	139	/* Xilinx uartlite */
238b8721 PK	140	#define PORT_UARTLITE 74
73e55cb3	141
194de561 BW	142	/* Blackfin bf5xx */
	143	#define PORT_BFIN 75
	144
2c7ee6ab AV	145	/* Micrel KS8695 */
	146	#define PORT_KS8695 76
	147
b45d5279 MR	148	/* Broadcom SB1250, etc. SOC */
	149	#define PORT_SB1250_DUART 77
	150
f0c15f48 GU	151	/* Freescale ColdFire */
	152	#define PORT_MCF 78
	153
2f351741 BW	154	/* Blackfin SPORT */
2f351741 BW	155	#define PORT_BFIN_SPORT 79
2c7ee6ab	156
ef3d5347 DH	157	/* MN10300 on-chip UART numbers */
	158	#define PORT_MN10300 80
	159	#define PORT_MN10300_CTS 81
	160
2f351741 BW	161	#define PORT_SC26XX 82
2f351741 BW	162
1a22f08d YS	163	/* SH-SCI */
	164	#define PORT_SCIFA 83
	165
b690ace5 BD	166	#define PORT_S3C6400 84
b690ace5 BD	167
5886188d BK	168	/* NWPSERIAL */
	169	#define PORT_NWPSERIAL 85
	170
1dcb884c CP	171	/* MAX3100 */
	172	#define PORT_MAX3100 86
	173
34aec591 RR	174	/* Timberdale UART */
	175	#define PORT_TIMBUART 87
	176
04896a77 RL	177	/* Qualcomm MSM SoCs */
	178	#define PORT_MSM 88
	179
9fcd66e5 MB	180	/* BCM63xx family SoCs */
	181	#define PORT_BCM63XX 89
	182
d4ac42a5 KG	183	/* Aeroflex Gaisler GRLIB APBUART */
	184	#define PORT_APBUART 90
	185
5bcd6010 TK	186	/* Altera UARTs */
5bcd6010 TK	187	#define PORT_ALTERA_JTAGUART 91
6b7d8f8b	188	#define PORT_ALTERA_UART 92
5bcd6010	189
75b93489 GL	190	/* SH-SCI */
	191	#define PORT_SCIFB 93
	192
61fd1526 AC	193	/* MAX3107 */
	194	#define PORT_MAX3107 94
	195
d843fc6e FT	196	/* High Speed UART for Medfield */
d843fc6e FT	197	#define PORT_MFD 95
61fd1526	198
b612633b G	199	/* TI OMAP-UART */
	200	#define PORT_OMAP 96
	201
304e1266 AC	202	/* VIA VT8500 SoC */
	203	#define PORT_VT8500 97
	204
1da177e4 LT	205	#ifdef __KERNEL__
1da177e4 LT	206
661f83a6	207	#include <linux/compiler.h>
1da177e4 LT	208	#include <linux/interrupt.h>
	209	#include <linux/circ_buf.h>
	210	#include <linux/spinlock.h>
	211	#include <linux/sched.h>
	212	#include <linux/tty.h>
e2862f6a	213	#include <linux/mutex.h>
b11115c1	214	#include <linux/sysrq.h>
1da177e4 LT	215
1da177e4 LT	216	struct uart_port;
1da177e4 LT	217	struct serial_struct;
	218	struct device;
	219
	220	/*
	221	* This structure describes all the operations that can be
	222	* done on the physical hardware.
	223	*/
	224	struct uart_ops {
	225	unsigned int (tx_empty)(struct uart_port );
	226	void (set_mctrl)(struct uart_port , unsigned int mctrl);
	227	unsigned int (get_mctrl)(struct uart_port );
b129a8cc RK	228	void (stop_tx)(struct uart_port );
b129a8cc RK	229	void (start_tx)(struct uart_port );
1da177e4 LT	230	void (send_xchar)(struct uart_port , char ch);
	231	void (stop_rx)(struct uart_port );
	232	void (enable_ms)(struct uart_port );
	233	void (break_ctl)(struct uart_port , int ctl);
	234	int (startup)(struct uart_port );
	235	void (shutdown)(struct uart_port );
6bb0e3a5	236	void (flush_buffer)(struct uart_port );
606d099c AC	237	void (set_termios)(struct uart_port , struct ktermios *new,
606d099c AC	238	struct ktermios *old);
d87d9b7d	239	void (set_ldisc)(struct uart_port , int new);
1da177e4 LT	240	void (pm)(struct uart_port , unsigned int state,
	241	unsigned int oldstate);
	242	int (set_wake)(struct uart_port , unsigned int state);
	243
	244	/*
	245	* Return a string describing the type of the port
	246	*/
	247	const char (type)(struct uart_port *);
	248
	249	/*
	250	* Release IO and memory resources used by the port.
	251	* This includes iounmap if necessary.
	252	*/
	253	void (release_port)(struct uart_port );
	254
	255	/*
	256	* Request IO and memory resources used by the port.
	257	* This includes iomapping the port if necessary.
	258	*/
	259	int (request_port)(struct uart_port );
	260	void (config_port)(struct uart_port , int);
	261	int (verify_port)(struct uart_port , struct serial_struct *);
	262	int (ioctl)(struct uart_port , unsigned int, unsigned long);
f2d937f3 JW	263	#ifdef CONFIG_CONSOLE_POLL
	264	void (poll_put_char)(struct uart_port , unsigned char);
	265	int (poll_get_char)(struct uart_port );
	266	#endif
1da177e4 LT	267	};
1da177e4 LT	268
f5316b4a	269	#define NO_POLL_CHAR 0x00ff0000
1da177e4 LT	270	#define UART_CONFIG_TYPE (1 << 0)
	271	#define UART_CONFIG_IRQ (1 << 1)
	272
	273	struct uart_icount {
	274	__u32 cts;
	275	__u32 dsr;
	276	__u32 rng;
	277	__u32 dcd;
	278	__u32 rx;
	279	__u32 tx;
	280	__u32 frame;
	281	__u32 overrun;
	282	__u32 parity;
	283	__u32 brk;
	284	__u32 buf_overrun;
	285	};
	286
0077d45e RK	287	typedef unsigned int __bitwise__ upf_t;
0077d45e RK	288
1da177e4 LT	289	struct uart_port {
1da177e4 LT	290	spinlock_t lock; /* port lock */
0c8946d9	291	unsigned long iobase; /* in/out[bwl] */
1da177e4	292	unsigned char __iomem membase; / read/write[bwl] */
7d6a07d1 DD	293	unsigned int (serial_in)(struct uart_port , int);
7d6a07d1 DD	294	void (serial_out)(struct uart_port , int, int);
235dae5d PL	295	void (set_termios)(struct uart_port ,
	296	struct ktermios *new,
	297	struct ktermios *old);
c161afe9 ML	298	void (pm)(struct uart_port , unsigned int state,
c161afe9 ML	299	unsigned int old);
1da177e4	300	unsigned int irq; /* irq number */
1c2f0493	301	unsigned long irqflags; /* irq flags */
1da177e4	302	unsigned int uartclk; /* base uart clock */
947deee8	303	unsigned int fifosize; /* tx fifo size */
1da177e4 LT	304	unsigned char x_char; /* xon/xoff char */
	305	unsigned char regshift; /* reg offset shift */
	306	unsigned char iotype; /* io access style */
947deee8	307	unsigned char unused1;
1da177e4 LT	308
	309	#define UPIO_PORT (0)
	310	#define UPIO_HUB6 (1)
	311	#define UPIO_MEM (2)
	312	#define UPIO_MEM32 (3)
21c614a7	313	#define UPIO_AU (4) /* Au1x00 type IO */
3be91ec7	314	#define UPIO_TSI (5) /* Tsi108/109 type IO */
beab697a	315	#define UPIO_DWAPB (6) /* DesignWare APB UART */
bd71c182	316	#define UPIO_RM9000 (7) /* RM9000 type IO */
a3ae0fc3	317	#define UPIO_DWAPB32 (8) /* DesignWare APB UART (32 bit accesses) */
1da177e4 LT	318
	319	unsigned int read_status_mask; /* driver specific */
	320	unsigned int ignore_status_mask; /* driver specific */
ebd2c8f6	321	struct uart_state state; / pointer to parent state */
1da177e4 LT	322	struct uart_icount icount; /* statistics */
	323
	324	struct console cons; / struct console, if any */
06e82df0	325	#if defined(CONFIG_SERIAL_CORE_CONSOLE) \|\| defined(SUPPORT_SYSRQ)
1da177e4 LT	326	unsigned long sysrq; /* sysrq timeout */
	327	#endif
	328
0077d45e RK	329	upf_t flags;
	330
	331	#define UPF_FOURPORT ((__force upf_t) (1 << 1))
	332	#define UPF_SAK ((__force upf_t) (1 << 2))
	333	#define UPF_SPD_MASK ((__force upf_t) (0x1030))
	334	#define UPF_SPD_HI ((__force upf_t) (0x0010))
	335	#define UPF_SPD_VHI ((__force upf_t) (0x0020))
	336	#define UPF_SPD_CUST ((__force upf_t) (0x0030))
	337	#define UPF_SPD_SHI ((__force upf_t) (0x1000))
	338	#define UPF_SPD_WARP ((__force upf_t) (0x1010))
	339	#define UPF_SKIP_TEST ((__force upf_t) (1 << 6))
	340	#define UPF_AUTO_IRQ ((__force upf_t) (1 << 7))
	341	#define UPF_HARDPPS_CD ((__force upf_t) (1 << 11))
	342	#define UPF_LOW_LATENCY ((__force upf_t) (1 << 13))
	343	#define UPF_BUGGY_UART ((__force upf_t) (1 << 14))
b6adea33	344	#define UPF_NO_TXEN_TEST ((__force upf_t) (1 << 15))
0077d45e RK	345	#define UPF_MAGIC_MULTIPLIER ((__force upf_t) (1 << 16))
	346	#define UPF_CONS_FLOW ((__force upf_t) (1 << 23))
	347	#define UPF_SHARE_IRQ ((__force upf_t) (1 << 24))
8e23fcc8 DD	348	/* The exact UART type is known and should not be probed. */
8e23fcc8 DD	349	#define UPF_FIXED_TYPE ((__force upf_t) (1 << 27))
0077d45e	350	#define UPF_BOOT_AUTOCONF ((__force upf_t) (1 << 28))
abb4a239	351	#define UPF_FIXED_PORT ((__force upf_t) (1 << 29))
68ac64cd	352	#define UPF_DEAD ((__force upf_t) (1 << 30))
0077d45e RK	353	#define UPF_IOREMAP ((__force upf_t) (1 << 31))
	354
	355	#define UPF_CHANGE_MASK ((__force upf_t) (0x17fff))
	356	#define UPF_USR_MASK ((__force upf_t) (UPF_SPD_MASK\|UPF_LOW_LATENCY))
1da177e4 LT	357
	358	unsigned int mctrl; /* current modem ctrl settings */
	359	unsigned int timeout; /* character-based timeout */
	360	unsigned int type; /* port type */
ba899dbc	361	const struct uart_ops *ops;
1da177e4 LT	362	unsigned int custom_divisor;
1da177e4 LT	363	unsigned int line; /* port index */
4f640efb	364	resource_size_t mapbase; /* for ioremap */
1da177e4 LT	365	struct device dev; / parent device */
1da177e4 LT	366	unsigned char hub6; /* this should be in the 8250 driver */
b3b708fa GL	367	unsigned char suspended;
b3b708fa GL	368	unsigned char unused[2];
beab697a	369	void private_data; / generic platform data pointer */
1da177e4 LT	370	};
1da177e4 LT	371
ebd2c8f6 AC	372	/*
ebd2c8f6 AC	373	* This is the state information which is persistent across opens.
ebd2c8f6 AC	374	*/
ebd2c8f6 AC	375	struct uart_state {
df4f4dd4	376	struct tty_port port;
ebd2c8f6	377
ebd2c8f6	378	int pm_state;
1da177e4	379	struct circ_buf xmit;
1da177e4	380
1da177e4	381	struct tasklet_struct tlet;
ebd2c8f6	382	struct uart_port *uart_port;
f751928e AC	383	};
	384
	385	#define UART_XMIT_SIZE PAGE_SIZE
	386
	387
1da177e4 LT	388	/* number of characters left in xmit buffer before we ask for more */
	389	#define WAKEUP_CHARS 256
	390
	391	struct module;
	392	struct tty_driver;
	393
	394	struct uart_driver {
	395	struct module *owner;
	396	const char *driver_name;
	397	const char *dev_name;
1da177e4 LT	398	int major;
	399	int minor;
	400	int nr;
	401	struct console *cons;
	402
	403	/*
	404	* these are private; the low level driver should not
	405	* touch these; they should be initialised to NULL
	406	*/
	407	struct uart_state *state;
	408	struct tty_driver *tty_driver;
	409	};
	410
	411	void uart_write_wakeup(struct uart_port *port);
	412
	413	/*
	414	* Baud rate helpers.
	415	*/
	416	void uart_update_timeout(struct uart_port *port, unsigned int cflag,
	417	unsigned int baud);
606d099c AC	418	unsigned int uart_get_baud_rate(struct uart_port port, struct ktermios termios,
606d099c AC	419	struct ktermios *old, unsigned int min,
1da177e4 LT	420	unsigned int max);
	421	unsigned int uart_get_divisor(struct uart_port *port, unsigned int baud);
	422
54381067 AV	423	/* Base timer interval for polling */
	424	static inline int uart_poll_timeout(struct uart_port *port)
	425	{
	426	int timeout = port->timeout;
	427
	428	return timeout > 6 ? (timeout / 2 - 2) : 1;
	429	}
	430
1da177e4 LT	431	/*
	432	* Console helpers.
	433	*/
	434	struct uart_port uart_get_console(struct uart_port ports, int nr,
	435	struct console *c);
	436	void uart_parse_options(char options, int baud, int parity, int bits,
	437	int *flow);
	438	int uart_set_options(struct uart_port port, struct console co, int baud,
	439	int parity, int bits, int flow);
	440	struct tty_driver uart_console_device(struct console co, int *index);
d358788f RK	441	void uart_console_write(struct uart_port port, const char s,
	442	unsigned int count,
	443	void (putchar)(struct uart_port , int));
1da177e4 LT	444
	445	/*
	446	* Port/driver registration/removal
	447	*/
	448	int uart_register_driver(struct uart_driver *uart);
	449	void uart_unregister_driver(struct uart_driver *uart);
1da177e4 LT	450	int uart_add_one_port(struct uart_driver reg, struct uart_port port);
	451	int uart_remove_one_port(struct uart_driver reg, struct uart_port port);
	452	int uart_match_port(struct uart_port port1, struct uart_port port2);
	453
	454	/*
	455	* Power Management
	456	*/
	457	int uart_suspend_port(struct uart_driver reg, struct uart_port port);
	458	int uart_resume_port(struct uart_driver reg, struct uart_port port);
	459
	460	#define uart_circ_empty(circ) ((circ)->head == (circ)->tail)
	461	#define uart_circ_clear(circ) ((circ)->head = (circ)->tail = 0)
	462
	463	#define uart_circ_chars_pending(circ) \
	464	(CIRC_CNT((circ)->head, (circ)->tail, UART_XMIT_SIZE))
	465
	466	#define uart_circ_chars_free(circ) \
	467	(CIRC_SPACE((circ)->head, (circ)->tail, UART_XMIT_SIZE))
	468
f751928e AC	469	static inline int uart_tx_stopped(struct uart_port *port)
f751928e AC	470	{
ebd2c8f6	471	struct tty_struct *tty = port->state->port.tty;
f751928e AC	472	if(tty->stopped \|\| tty->hw_stopped)
	473	return 1;
	474	return 0;
	475	}
1da177e4 LT	476
	477	/*
	478	* The following are helper functions for the low level drivers.
	479	*/
1da177e4	480	static inline int
7d12e780	481	uart_handle_sysrq_char(struct uart_port *port, unsigned int ch)
1da177e4	482	{
93c37f29	483	#ifdef SUPPORT_SYSRQ
1da177e4 LT	484	if (port->sysrq) {
1da177e4 LT	485	if (ch && time_before(jiffies, port->sysrq)) {
f335397d	486	handle_sysrq(ch);
1da177e4 LT	487	port->sysrq = 0;
	488	return 1;
	489	}
	490	port->sysrq = 0;
	491	}
93c37f29	492	#endif
1da177e4 LT	493	return 0;
1da177e4 LT	494	}
4e149184	495	#ifndef SUPPORT_SYSRQ
7d12e780	496	#define uart_handle_sysrq_char(port,ch) uart_handle_sysrq_char(port, 0)
4e149184	497	#endif
1da177e4 LT	498
	499	/*
	500	* We do the SysRQ and SAK checking like this...
	501	*/
	502	static inline int uart_handle_break(struct uart_port *port)
	503	{
ebd2c8f6	504	struct uart_state *state = port->state;
1da177e4 LT	505	#ifdef SUPPORT_SYSRQ
	506	if (port->cons && port->cons->index == port->line) {
	507	if (!port->sysrq) {
	508	port->sysrq = jiffies + HZ*5;
	509	return 1;
	510	}
	511	port->sysrq = 0;
	512	}
	513	#endif
27ae7a74	514	if (port->flags & UPF_SAK)
ebd2c8f6	515	do_SAK(state->port.tty);
1da177e4 LT	516	return 0;
	517	}
	518
	519	/**
	520	* uart_handle_dcd_change - handle a change of carrier detect state
1b9894f3	521	* @uport: uart_port structure for the open port
1da177e4 LT	522	* @status: new carrier detect status, nonzero if active
	523	*/
	524	static inline void
ccce6deb	525	uart_handle_dcd_change(struct uart_port *uport, unsigned int status)
1da177e4	526	{
ccce6deb AC	527	struct uart_state *state = uport->state;
ccce6deb AC	528	struct tty_port *port = &state->port;
a0880df0 RG	529	struct tty_ldisc *ld = tty_ldisc_ref(port->tty);
a0880df0 RG	530	struct timespec ts;
1da177e4	531
a0880df0 RG	532	if (ld && ld->ops->dcd_change)
a0880df0 RG	533	getnstimeofday(&ts);
1da177e4	534
a0880df0	535	uport->icount.dcd++;
1da177e4	536	#ifdef CONFIG_HARD_PPS
ccce6deb	537	if ((uport->flags & UPF_HARDPPS_CD) && status)
1da177e4 LT	538	hardpps();
	539	#endif
	540
ccce6deb	541	if (port->flags & ASYNC_CHECK_CD) {
1da177e4	542	if (status)
ccce6deb AC	543	wake_up_interruptible(&port->open_wait);
	544	else if (port->tty)
	545	tty_hangup(port->tty);
1da177e4	546	}
a0880df0 RG	547
	548	if (ld && ld->ops->dcd_change)
	549	ld->ops->dcd_change(port->tty, status, &ts);
	550	if (ld)
	551	tty_ldisc_deref(ld);
1da177e4 LT	552	}
	553
	554	/**
	555	* uart_handle_cts_change - handle a change of clear-to-send state
1b9894f3	556	* @uport: uart_port structure for the open port
1da177e4 LT	557	* @status: new clear to send status, nonzero if active
	558	*/
	559	static inline void
ccce6deb	560	uart_handle_cts_change(struct uart_port *uport, unsigned int status)
1da177e4	561	{
ccce6deb AC	562	struct tty_port *port = &uport->state->port;
ccce6deb AC	563	struct tty_struct *tty = port->tty;
1da177e4	564
ccce6deb	565	uport->icount.cts++;
1da177e4	566
ccce6deb	567	if (port->flags & ASYNC_CTS_FLOW) {
1da177e4 LT	568	if (tty->hw_stopped) {
	569	if (status) {
	570	tty->hw_stopped = 0;
ccce6deb AC	571	uport->ops->start_tx(uport);
ccce6deb AC	572	uart_write_wakeup(uport);
1da177e4 LT	573	}
	574	} else {
	575	if (!status) {
	576	tty->hw_stopped = 1;
ccce6deb	577	uport->ops->stop_tx(uport);
1da177e4 LT	578	}
	579	}
	580	}
	581	}
	582
05ab3014 RK	583	#include <linux/tty_flip.h>
	584
	585	static inline void
	586	uart_insert_char(struct uart_port *port, unsigned int status,
	587	unsigned int overrun, unsigned int ch, unsigned int flag)
	588	{
ebd2c8f6	589	struct tty_struct *tty = port->state->port.tty;
05ab3014 RK	590
	591	if ((status & port->ignore_status_mask & ~overrun) == 0)
	592	tty_insert_flip_char(tty, ch, flag);
	593
	594	/*
	595	* Overrun is special. Since it's reported immediately,
	596	* it doesn't affect the current character.
	597	*/
	598	if (status & ~port->ignore_status_mask & overrun)
	599	tty_insert_flip_char(tty, 0, TTY_OVERRUN);
	600	}
	601
1da177e4 LT	602	/*
	603	* UART_ENABLE_MS - determine if port should enable modem status irqs
	604	*/
	605	#define UART_ENABLE_MS(port,cflag) ((port)->flags & UPF_HARDPPS_CD \|\| \
	606	(cflag) & CRTSCTS \|\| \
	607	!((cflag) & CLOCAL))
	608
	609	#endif
	610
	611	#endif /* LINUX_SERIAL_CORE_H */