[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / pcieport_if.h

/*
 * File:	pcieport_if.h
 * Purpose:	PCI Express Port Bus Driver's IF Data Structure
 *
 * Copyright (C) 2004 Intel
 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
 */

#ifndef _PCIEPORT_IF_H_
#define _PCIEPORT_IF_H_

/* Port Type */
#define PCIE_RC_PORT			4	/* Root port of RC */
#define PCIE_SW_UPSTREAM_PORT		5	/* Upstream port of Switch */
#define PCIE_SW_DOWNSTREAM_PORT		6	/* Downstream port of Switch */
#define PCIE_ANY_PORT			7

/* Service Type */
#define PCIE_PORT_SERVICE_PME		1	/* Power Management Event */
#define PCIE_PORT_SERVICE_AER		2	/* Advanced Error Reporting */
#define PCIE_PORT_SERVICE_HP		4	/* Native Hotplug */
#define PCIE_PORT_SERVICE_VC		8	/* Virtual Channel */

/* Root/Upstream/Downstream Port's Interrupt Mode */
#define PCIE_PORT_INTx_MODE		0
#define PCIE_PORT_MSI_MODE		1
#define PCIE_PORT_MSIX_MODE		2

struct pcie_port_service_id {
	__u32 vendor, device;		/* Vendor and device ID or PCI_ANY_ID*/
	__u32 subvendor, subdevice;	/* Subsystem ID's or PCI_ANY_ID */
	__u32 class, class_mask;	/* (class,subclass,prog-if) triplet */
	__u32 port_type, service_type;	/* Port Entity */
	kernel_ulong_t driver_data;
};

struct pcie_device {
	int 		irq;	    /* Service IRQ/MSI/MSI-X Vector */
	int 		interrupt_mode;	/* [0:INTx | 1:MSI | 2:MSI-X] */	
	struct pcie_port_service_id id;	/* Service ID */
	struct pci_dev	*port;	    /* Root/Upstream/Downstream Port */
	void		*priv_data; /* Service Private Data */
	struct device	device;     /* Generic Device Interface */
};
#define to_pcie_device(d) container_of(d, struct pcie_device, device)

static inline void set_service_data(struct pcie_device *dev, void *data)
{
	dev->priv_data = data;
}

static inline void* get_service_data(struct pcie_device *dev)
{
	return dev->priv_data;
}

struct pcie_port_service_driver {
	const char *name;
	int (*probe) (struct pcie_device *dev, 
		const struct pcie_port_service_id *id);
	void (*remove) (struct pcie_device *dev);
	int (*suspend) (struct pcie_device *dev, pm_message_t state);
	int (*resume) (struct pcie_device *dev);

	/* Service Error Recovery Handler */
	struct pci_error_handlers *err_handler;

	/* Link Reset Capability - AER service driver specific */
	pci_ers_result_t (*reset_link) (struct pci_dev *dev);

	const struct pcie_port_service_id *id_table;
	struct device_driver driver;
};
#define to_service_driver(d) \
	container_of(d, struct pcie_port_service_driver, driver)

extern int pcie_port_service_register(struct pcie_port_service_driver *new);
extern void pcie_port_service_unregister(struct pcie_port_service_driver *new);

#endif /* _PCIEPORT_IF_H_ */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* File: pcieport_if.h
	3	* Purpose: PCI Express Port Bus Driver's IF Data Structure
	4	*
	5	* Copyright (C) 2004 Intel
	6	* Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
	7	*/
	8
	9	#ifndef _PCIEPORT_IF_H_
	10	#define _PCIEPORT_IF_H_
	11
	12	/* Port Type */
	13	#define PCIE_RC_PORT 4 /* Root port of RC */
	14	#define PCIE_SW_UPSTREAM_PORT 5 /* Upstream port of Switch */
	15	#define PCIE_SW_DOWNSTREAM_PORT 6 /* Downstream port of Switch */
	16	#define PCIE_ANY_PORT 7
	17
	18	/* Service Type */
	19	#define PCIE_PORT_SERVICE_PME 1 /* Power Management Event */
	20	#define PCIE_PORT_SERVICE_AER 2 /* Advanced Error Reporting */
	21	#define PCIE_PORT_SERVICE_HP 4 /* Native Hotplug */
	22	#define PCIE_PORT_SERVICE_VC 8 /* Virtual Channel */
	23
	24	/* Root/Upstream/Downstream Port's Interrupt Mode */
	25	#define PCIE_PORT_INTx_MODE 0
	26	#define PCIE_PORT_MSI_MODE 1
	27	#define PCIE_PORT_MSIX_MODE 2
	28
	29	struct pcie_port_service_id {
	30	__u32 vendor, device; /* Vendor and device ID or PCI_ANY_ID*/
	31	__u32 subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
	32	__u32 class, class_mask; /* (class,subclass,prog-if) triplet */
	33	__u32 port_type, service_type; /* Port Entity */
	34	kernel_ulong_t driver_data;
	35	};
	36
	37	struct pcie_device {
	38	int irq; /* Service IRQ/MSI/MSI-X Vector */
	39	int interrupt_mode; /* [0:INTx \| 1:MSI \| 2:MSI-X] */
	40	struct pcie_port_service_id id; /* Service ID */
	41	struct pci_dev port; / Root/Upstream/Downstream Port */
	42	void priv_data; / Service Private Data */
	43	struct device device; /* Generic Device Interface */
	44	};
	45	#define to_pcie_device(d) container_of(d, struct pcie_device, device)
	46
	47	static inline void set_service_data(struct pcie_device dev, void data)
	48	{
	49	dev->priv_data = data;
	50	}
	51
	52	static inline void* get_service_data(struct pcie_device *dev)
	53	{
	54	return dev->priv_data;
	55	}
	56
	57	struct pcie_port_service_driver {
	58	const char *name;
	59	int (probe) (struct pcie_device dev,
	60	const struct pcie_port_service_id *id);
	61	void (remove) (struct pcie_device dev);
7f4927c1	62	int (suspend) (struct pcie_device dev, pm_message_t state);
1da177e4 LT	63	int (resume) (struct pcie_device dev);
1da177e4 LT	64
6c2b374d ZY	65	/* Service Error Recovery Handler */
	66	struct pci_error_handlers *err_handler;
	67
	68	/* Link Reset Capability - AER service driver specific */
	69	pci_ers_result_t (reset_link) (struct pci_dev dev);
	70
1da177e4 LT	71	const struct pcie_port_service_id *id_table;
	72	struct device_driver driver;
	73	};
	74	#define to_service_driver(d) \
	75	container_of(d, struct pcie_port_service_driver, driver)
	76
	77	extern int pcie_port_service_register(struct pcie_port_service_driver *new);
	78	extern void pcie_port_service_unregister(struct pcie_port_service_driver *new);
	79
	80	#endif /* _PCIEPORT_IF_H_ */