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[PATCH] sort the devres mess out
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / pci.h
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1da177e4
LT		 1/*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17#ifndef LINUX_PCI_H
18#define LINUX_PCI_H
19
4352dfd5
GKH		 20/* Include the pci register defines */
21#include <linux/pci_regs.h>
1da177e4 22
1da177e4
LT		 23/*
24 * The PCI interface treats multi-function devices as independent
25 * devices. The slot/function address of each device is encoded
26 * in a single byte as follows:
27 *
28 * 7:3 = slot
29 * 2:0 = function
30 */
31#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
32#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
33#define PCI_FUNC(devfn) ((devfn) & 0x07)
34
35/* Ioctls for /proc/bus/pci/X/Y nodes. */
36#define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
37#define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
38#define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
39#define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
40#define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
41
42#ifdef __KERNEL__
43
778382e0
DW		 44#include <linux/mod_devicetable.h>
45
1da177e4 46#include <linux/types.h>
1da177e4
LT		 47#include <linux/ioport.h>
48#include <linux/list.h>
4a7fb636 49#include <linux/compiler.h>
1da177e4 50#include <linux/errno.h>
bae94d02 51#include <asm/atomic.h>
1da177e4
LT		 52#include <linux/device.h>
53
7e7a43c3
AB		 54/* Include the ID list */
55#include <linux/pci_ids.h>
56
1da177e4
LT		 57/* File state for mmap()s on /proc/bus/pci/X/Y */
58enum pci_mmap_state {
59 pci_mmap_io,
60 pci_mmap_mem
61};
62
63/* This defines the direction arg to the DMA mapping routines. */
64#define PCI_DMA_BIDIRECTIONAL 0
65#define PCI_DMA_TODEVICE 1
66#define PCI_DMA_FROMDEVICE 2
67#define PCI_DMA_NONE 3
68
69#define DEVICE_COUNT_COMPATIBLE 4
70#define DEVICE_COUNT_RESOURCE 12
71
72typedef int __bitwise pci_power_t;
73
4352dfd5
GKH		 74#define PCI_D0 ((pci_power_t __force) 0)
75#define PCI_D1 ((pci_power_t __force) 1)
76#define PCI_D2 ((pci_power_t __force) 2)
1da177e4
LT		 77#define PCI_D3hot ((pci_power_t __force) 3)
78#define PCI_D3cold ((pci_power_t __force) 4)
3fe9d19f 79#define PCI_UNKNOWN ((pci_power_t __force) 5)
438510f6 80#define PCI_POWER_ERROR ((pci_power_t __force) -1)
1da177e4 81
392a1ce7
LV		 82/** The pci_channel state describes connectivity between the CPU and
83 * the pci device. If some PCI bus between here and the pci device
84 * has crashed or locked up, this info is reflected here.
85 */
86typedef unsigned int __bitwise pci_channel_state_t;
87
88enum pci_channel_state {
89 /* I/O channel is in normal state */
90 pci_channel_io_normal = (__force pci_channel_state_t) 1,
91
92 /* I/O to channel is blocked */
93 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
94
95 /* PCI card is dead */
96 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
97};
98
6e325a62
MT		 99typedef unsigned short __bitwise pci_bus_flags_t;
100enum pci_bus_flags {
e778272d 101 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
6e325a62
MT		 102};
103
41017f0c
SL		 104struct pci_cap_saved_state {
105 struct hlist_node next;
106 char cap_nr;
107 u32 data[0];
108};
109
1da177e4
LT		 110/*
111 * The pci_dev structure is used to describe PCI devices.
112 */
113struct pci_dev {
114 struct list_head global_list; /* node in list of all PCI devices */
115 struct list_head bus_list; /* node in per-bus list */
116 struct pci_bus *bus; /* bus this device is on */
117 struct pci_bus *subordinate; /* bus this device bridges to */
118
119 void *sysdata; /* hook for sys-specific extension */
120 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
121
122 unsigned int devfn; /* encoded device & function index */
123 unsigned short vendor;
124 unsigned short device;
125 unsigned short subsystem_vendor;
126 unsigned short subsystem_device;
127 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
128 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
129 u8 rom_base_reg; /* which config register controls the ROM */
ffeff788 130 u8 pin; /* which interrupt pin this device uses */
1da177e4
LT		 131
132 struct pci_driver *driver; /* which driver has allocated this device */
133 u64 dma_mask; /* Mask of the bits of bus address this
134 device implements. Normally this is
135 0xffffffff. You only need to change
136 this if your device has broken DMA
137 or supports 64-bit transfers. */
138
139 pci_power_t current_state; /* Current operating state. In ACPI-speak,
140 this is D0-D3, D0 being fully functional,
141 and D3 being off. */
142
392a1ce7 143 pci_channel_state_t error_state; /* current connectivity state */
1da177e4
LT		 144 struct device dev; /* Generic device interface */
145
146 /* device is compatible with these IDs */
147 unsigned short vendor_compatible[DEVICE_COUNT_COMPATIBLE];
148 unsigned short device_compatible[DEVICE_COUNT_COMPATIBLE];
149
150 int cfg_size; /* Size of configuration space */
151
152 /*
153 * Instead of touching interrupt line and base address registers
154 * directly, use the values stored here. They might be different!
155 */
156 unsigned int irq;
157 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
158
159 /* These fields are used by common fixups */
160 unsigned int transparent:1; /* Transparent PCI bridge */
161 unsigned int multifunction:1;/* Part of multi-function device */
162 /* keep track of device state */
1da177e4 163 unsigned int is_busmaster:1; /* device is busmaster */
4602b88d 164 unsigned int no_msi:1; /* device may not use msi */
ffadcc2f 165 unsigned int no_d1d2:1; /* only allow d0 or d3 */
e04b0ea2 166 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
bd8481e1 167 unsigned int broken_parity_status:1; /* Device generates false positive parity */
99dc804d
SL		 168 unsigned int msi_enabled:1;
169 unsigned int msix_enabled:1;
9ac7849e 170 unsigned int is_managed:1;
bae94d02 171 atomic_t enable_cnt; /* pci_enable_device has been called */
4602b88d 172
1da177e4 173 u32 saved_config_space[16]; /* config space saved at suspend time */
41017f0c 174 struct hlist_head saved_cap_space;
1da177e4
LT		 175 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
176 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
177 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
ded86d8d
EB		 178#ifdef CONFIG_PCI_MSI
179 unsigned int first_msi_irq;
180#endif
1da177e4
LT		 181};
182
183#define pci_dev_g(n) list_entry(n, struct pci_dev, global_list)
184#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
185#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
186#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
187
a7369f1f
LV		 188static inline int pci_channel_offline(struct pci_dev *pdev)
189{
190 return (pdev->error_state != pci_channel_io_normal);
191}
192
41017f0c
SL		 193static inline struct pci_cap_saved_state *pci_find_saved_cap(
194 struct pci_dev *pci_dev,char cap)
195{
196 struct pci_cap_saved_state *tmp;
197 struct hlist_node *pos;
198
199 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
200 if (tmp->cap_nr == cap)
201 return tmp;
202 }
203 return NULL;
204}
205
206static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
207 struct pci_cap_saved_state *new_cap)
208{
209 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
210}
211
212static inline void pci_remove_saved_cap(struct pci_cap_saved_state *cap)
213{
214 hlist_del(&cap->next);
215}
216
1da177e4
LT		 217/*
218 * For PCI devices, the region numbers are assigned this way:
219 *
220 * 0-5 standard PCI regions
221 * 6 expansion ROM
222 * 7-10 bridges: address space assigned to buses behind the bridge
223 */
224
4352dfd5
GKH		 225#define PCI_ROM_RESOURCE 6
226#define PCI_BRIDGE_RESOURCES 7
227#define PCI_NUM_RESOURCES 11
1da177e4
LT		 228
229#ifndef PCI_BUS_NUM_RESOURCES
4352dfd5 230#define PCI_BUS_NUM_RESOURCES 8
1da177e4 231#endif
4352dfd5
GKH		 232
233#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
1da177e4
LT		 234
235struct pci_bus {
236 struct list_head node; /* node in list of buses */
237 struct pci_bus *parent; /* parent bus this bridge is on */
238 struct list_head children; /* list of child buses */
239 struct list_head devices; /* list of devices on this bus */
240 struct pci_dev *self; /* bridge device as seen by parent */
241 struct resource *resource[PCI_BUS_NUM_RESOURCES];
242 /* address space routed to this bus */
243
244 struct pci_ops *ops; /* configuration access functions */
245 void *sysdata; /* hook for sys-specific extension */
246 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
247
248 unsigned char number; /* bus number */
249 unsigned char primary; /* number of primary bridge */
250 unsigned char secondary; /* number of secondary bridge */
251 unsigned char subordinate; /* max number of subordinate buses */
252
253 char name[48];
254
255 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
6e325a62 256 pci_bus_flags_t bus_flags; /* Inherited by child busses */
1da177e4
LT		 257 struct device *bridge;
258 struct class_device class_dev;
259 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
260 struct bin_attribute *legacy_mem; /* legacy mem */
261};
262
263#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
264#define to_pci_bus(n) container_of(n, struct pci_bus, class_dev)
265
266/*
267 * Error values that may be returned by PCI functions.
268 */
269#define PCIBIOS_SUCCESSFUL 0x00
270#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
271#define PCIBIOS_BAD_VENDOR_ID 0x83
272#define PCIBIOS_DEVICE_NOT_FOUND 0x86
273#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
274#define PCIBIOS_SET_FAILED 0x88
275#define PCIBIOS_BUFFER_TOO_SMALL 0x89
276
277/* Low-level architecture-dependent routines */
278
279struct pci_ops {
280 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
281 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
282};
283
284struct pci_raw_ops {
285 int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
286 int reg, int len, u32 *val);
287 int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
288 int reg, int len, u32 val);
289};
290
291extern struct pci_raw_ops *raw_pci_ops;
292
293struct pci_bus_region {
294 unsigned long start;
295 unsigned long end;
296};
297
298struct pci_dynids {
299 spinlock_t lock; /* protects list, index */
300 struct list_head list; /* for IDs added at runtime */
301 unsigned int use_driver_data:1; /* pci_driver->driver_data is used */
302};
303
392a1ce7
LV		 304/* ---------------------------------------------------------------- */
305/** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
306 * a set fof callbacks in struct pci_error_handlers, then that device driver
307 * will be notified of PCI bus errors, and will be driven to recovery
308 * when an error occurs.
309 */
310
311typedef unsigned int __bitwise pci_ers_result_t;
312
313enum pci_ers_result {
314 /* no result/none/not supported in device driver */
315 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
316
317 /* Device driver can recover without slot reset */
318 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
319
320 /* Device driver wants slot to be reset. */
321 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
322
323 /* Device has completely failed, is unrecoverable */
324 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
325
326 /* Device driver is fully recovered and operational */
327 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
328};
329
330/* PCI bus error event callbacks */
331struct pci_error_handlers
332{
333 /* PCI bus error detected on this device */
334 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
335 enum pci_channel_state error);
336
337 /* MMIO has been re-enabled, but not DMA */
338 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
339
340 /* PCI Express link has been reset */
341 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
342
343 /* PCI slot has been reset */
344 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
345
346 /* Device driver may resume normal operations */
347 void (*resume)(struct pci_dev *dev);
348};
349
350/* ---------------------------------------------------------------- */
351
1da177e4
LT		 352struct module;
353struct pci_driver {
354 struct list_head node;
355 char *name;
1da177e4
LT		 356 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
357 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
358 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
359 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
cbd69dbb
LT		 360 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
361 int (*resume_early) (struct pci_dev *dev);
1da177e4 362 int (*resume) (struct pci_dev *dev); /* Device woken up */
438510f6 363 int (*enable_wake) (struct pci_dev *dev, pci_power_t state, int enable); /* Enable wake event */
c8958177 364 void (*shutdown) (struct pci_dev *dev);
1da177e4 365
392a1ce7 366 struct pci_error_handlers *err_handler;
1da177e4
LT		 367 struct device_driver driver;
368 struct pci_dynids dynids;
50b00755
AC		 369
370 int multithread_probe;
1da177e4
LT		 371};
372
373#define to_pci_driver(drv) container_of(drv,struct pci_driver, driver)
374
375/**
376 * PCI_DEVICE - macro used to describe a specific pci device
377 * @vend: the 16 bit PCI Vendor ID
378 * @dev: the 16 bit PCI Device ID
379 *
380 * This macro is used to create a struct pci_device_id that matches a
381 * specific device. The subvendor and subdevice fields will be set to
382 * PCI_ANY_ID.
383 */
384#define PCI_DEVICE(vend,dev) \
385 .vendor = (vend), .device = (dev), \
386 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
387
388/**
389 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
390 * @dev_class: the class, subclass, prog-if triple for this device
391 * @dev_class_mask: the class mask for this device
392 *
393 * This macro is used to create a struct pci_device_id that matches a
4352dfd5 394 * specific PCI class. The vendor, device, subvendor, and subdevice
1da177e4
LT		 395 * fields will be set to PCI_ANY_ID.
396 */
397#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
398 .class = (dev_class), .class_mask = (dev_class_mask), \
399 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
400 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
401
4352dfd5 402/*
1da177e4
LT		 403 * pci_module_init is obsolete, this stays here till we fix up all usages of it
404 * in the tree.
405 */
406#define pci_module_init pci_register_driver
407
1597cacb
AC		 408/**
409 * PCI_VDEVICE - macro used to describe a specific pci device in short form
410 * @vend: the vendor name
411 * @dev: the 16 bit PCI Device ID
412 *
413 * This macro is used to create a struct pci_device_id that matches a
414 * specific PCI device. The subvendor, and subdevice fields will be set
415 * to PCI_ANY_ID. The macro allows the next field to follow as the device
416 * private data.
417 */
418
419#define PCI_VDEVICE(vendor, device) \
420 PCI_VENDOR_ID_##vendor, (device), \
421 PCI_ANY_ID, PCI_ANY_ID, 0, 0
422
1da177e4
LT		 423/* these external functions are only available when PCI support is enabled */
424#ifdef CONFIG_PCI
425
426extern struct bus_type pci_bus_type;
427
428/* Do NOT directly access these two variables, unless you are arch specific pci
429 * code, or pci core code. */
430extern struct list_head pci_root_buses; /* list of all known PCI buses */
431extern struct list_head pci_devices; /* list of all devices */
432
433void pcibios_fixup_bus(struct pci_bus *);
4a7fb636 434int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1da177e4
LT		 435char *pcibios_setup (char *str);
436
437/* Used only when drivers/pci/setup.c is used */
e31dd6e4
GKH		 438void pcibios_align_resource(void *, struct resource *, resource_size_t,
439 resource_size_t);
1da177e4
LT		 440void pcibios_update_irq(struct pci_dev *, int irq);
441
442/* Generic PCI functions used internally */
443
444extern struct pci_bus *pci_find_bus(int domain, int busnr);
c431ada4 445void pci_bus_add_devices(struct pci_bus *bus);
1da177e4
LT		 446struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata);
447static inline struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata)
448{
c431ada4
RS		 449 struct pci_bus *root_bus;
450 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
451 if (root_bus)
452 pci_bus_add_devices(root_bus);
453 return root_bus;
1da177e4 454}
cdb9b9f7
PM		 455struct pci_bus *pci_create_bus(struct device *parent, int bus, struct pci_ops *ops, void *sysdata);
456struct pci_bus * pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr);
1da177e4
LT		 457int pci_scan_slot(struct pci_bus *bus, int devfn);
458struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn);
cdb9b9f7 459void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1da177e4 460unsigned int pci_scan_child_bus(struct pci_bus *bus);
b19441af 461int __must_check pci_bus_add_device(struct pci_dev *dev);
1da177e4
LT		 462void pci_read_bridge_bases(struct pci_bus *child);
463struct resource *pci_find_parent_resource(const struct pci_dev *dev, struct resource *res);
464int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
465extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
466extern void pci_dev_put(struct pci_dev *dev);
467extern void pci_remove_bus(struct pci_bus *b);
468extern void pci_remove_bus_device(struct pci_dev *dev);
24f8aa9b 469extern void pci_stop_bus_device(struct pci_dev *dev);
b3743fa4 470void pci_setup_cardbus(struct pci_bus *bus);
6b4b78fe 471extern void pci_sort_breadthfirst(void);
1da177e4
LT		 472
473/* Generic PCI functions exported to card drivers */
474
429538ad 475struct pci_dev __deprecated *pci_find_device (unsigned int vendor, unsigned int device, const struct pci_dev *from);
1da177e4
LT		 476struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn);
477int pci_find_capability (struct pci_dev *dev, int cap);
24a4e377 478int pci_find_next_capability (struct pci_dev *dev, u8 pos, int cap);
3a720d72 479int pci_find_ext_capability (struct pci_dev *dev, int cap);
687d5fe3
ME		 480int pci_find_ht_capability (struct pci_dev *dev, int ht_cap);
481int pci_find_next_ht_capability (struct pci_dev *dev, int pos, int ht_cap);
29f3eb64 482struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1da177e4 483
d42552c3
AM		 484struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
485 struct pci_dev *from);
486struct pci_dev *pci_get_device_reverse(unsigned int vendor, unsigned int device,
487 struct pci_dev *from);
488
1da177e4
LT		 489struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
490 unsigned int ss_vendor, unsigned int ss_device,
491 struct pci_dev *from);
492struct pci_dev *pci_get_slot (struct pci_bus *bus, unsigned int devfn);
29f3eb64 493struct pci_dev *pci_get_bus_and_slot (unsigned int bus, unsigned int devfn);
1da177e4
LT		 494struct pci_dev *pci_get_class (unsigned int class, struct pci_dev *from);
495int pci_dev_present(const struct pci_device_id *ids);
d86f90f9 496const struct pci_device_id *pci_find_present(const struct pci_device_id *ids);
1da177e4
LT		 497
498int pci_bus_read_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 *val);
499int pci_bus_read_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 *val);
500int pci_bus_read_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 *val);
501int pci_bus_write_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 val);
502int pci_bus_write_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 val);
503int pci_bus_write_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 val);
504
505static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
506{
507 return pci_bus_read_config_byte (dev->bus, dev->devfn, where, val);
508}
509static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
510{
511 return pci_bus_read_config_word (dev->bus, dev->devfn, where, val);
512}
513static inline int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val)
514{
515 return pci_bus_read_config_dword (dev->bus, dev->devfn, where, val);
516}
517static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
518{
519 return pci_bus_write_config_byte (dev->bus, dev->devfn, where, val);
520}
521static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
522{
523 return pci_bus_write_config_word (dev->bus, dev->devfn, where, val);
524}
525static inline int pci_write_config_dword(struct pci_dev *dev, int where, u32 val)
526{
527 return pci_bus_write_config_dword (dev->bus, dev->devfn, where, val);
528}
529
4a7fb636
AM		 530int __must_check pci_enable_device(struct pci_dev *dev);
531int __must_check pci_enable_device_bars(struct pci_dev *dev, int mask);
9ac7849e
TH		 532int __must_check pcim_enable_device(struct pci_dev *pdev);
533void pcim_pin_device(struct pci_dev *pdev);
534
535static inline int pci_is_managed(struct pci_dev *pdev)
536{
537 return pdev->is_managed;
538}
539
1da177e4
LT		 540void pci_disable_device(struct pci_dev *dev);
541void pci_set_master(struct pci_dev *dev);
542#define HAVE_PCI_SET_MWI
4a7fb636 543int __must_check pci_set_mwi(struct pci_dev *dev);
1da177e4 544void pci_clear_mwi(struct pci_dev *dev);
a04ce0ff 545void pci_intx(struct pci_dev *dev, int enable);
9c8550ee
LT		 546int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
547int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
064b53db 548void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno);
4a7fb636
AM		 549int __must_check pci_assign_resource(struct pci_dev *dev, int i);
550int __must_check pci_assign_resource_fixed(struct pci_dev *dev, int i);
064b53db 551void pci_restore_bars(struct pci_dev *dev);
c87deff7 552int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1da177e4
LT		 553
554/* ROM control related routines */
144a50ea
DJ		 555void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
556void __iomem __must_check *pci_map_rom_copy(struct pci_dev *pdev, size_t *size);
1da177e4
LT		 557void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
558void pci_remove_rom(struct pci_dev *pdev);
559
560/* Power management related routines */
561int pci_save_state(struct pci_dev *dev);
562int pci_restore_state(struct pci_dev *dev);
9c8550ee
LT		 563int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
564pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
565int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable);
1da177e4
LT		 566
567/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
568void pci_bus_assign_resources(struct pci_bus *bus);
569void pci_bus_size_bridges(struct pci_bus *bus);
570int pci_claim_resource(struct pci_dev *, int);
571void pci_assign_unassigned_resources(void);
572void pdev_enable_device(struct pci_dev *);
573void pdev_sort_resources(struct pci_dev *, struct resource_list *);
574void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
575 int (*)(struct pci_dev *, u8, u8));
576#define HAVE_PCI_REQ_REGIONS 2
4a7fb636 577int __must_check pci_request_regions(struct pci_dev *, const char *);
1da177e4 578void pci_release_regions(struct pci_dev *);
4a7fb636 579int __must_check pci_request_region(struct pci_dev *, int, const char *);
1da177e4 580void pci_release_region(struct pci_dev *, int);
c87deff7
HS		 581int pci_request_selected_regions(struct pci_dev *, int, const char *);
582void pci_release_selected_regions(struct pci_dev *, int);
1da177e4
LT		 583
584/* drivers/pci/bus.c */
4a7fb636
AM		 585int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
586 struct resource *res, resource_size_t size,
587 resource_size_t align, resource_size_t min,
588 unsigned int type_mask,
589 void (*alignf)(void *, struct resource *,
590 resource_size_t, resource_size_t),
591 void *alignf_data);
1da177e4
LT		 592void pci_enable_bridges(struct pci_bus *bus);
593
863b18f4 594/* Proper probing supporting hot-pluggable devices */
725522b5
GKH		 595int __must_check __pci_register_driver(struct pci_driver *, struct module *,
596 const char *mod_name);
4a7fb636 597static inline int __must_check pci_register_driver(struct pci_driver *driver)
863b18f4 598{
725522b5 599 return __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME);
863b18f4
L		 600}
601
1da177e4
LT		 602void pci_unregister_driver(struct pci_driver *);
603void pci_remove_behind_bridge(struct pci_dev *);
604struct pci_driver *pci_dev_driver(const struct pci_dev *);
75865858
GKH		 605const struct pci_device_id *pci_match_device(struct pci_driver *drv, struct pci_dev *dev);
606const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, struct pci_dev *dev);
1da177e4
LT		 607int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass);
608
cecf4864
PM		 609void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *),
610 void *userdata);
ac7dc65a 611int pci_cfg_space_size(struct pci_dev *dev);
b82db5ce 612unsigned char pci_bus_max_busnr(struct pci_bus* bus);
cecf4864 613
1da177e4
LT		 614/* kmem_cache style wrapper around pci_alloc_consistent() */
615
616#include <linux/dmapool.h>
617
618#define pci_pool dma_pool
619#define pci_pool_create(name, pdev, size, align, allocation) \
620 dma_pool_create(name, &pdev->dev, size, align, allocation)
621#define pci_pool_destroy(pool) dma_pool_destroy(pool)
622#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
623#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
624
e24c2d96
DM		 625enum pci_dma_burst_strategy {
626 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
627 strategy_parameter is N/A */
628 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
629 byte boundaries */
630 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
631 strategy_parameter byte boundaries */
632};
633
1da177e4
LT		 634struct msix_entry {
635 u16 vector; /* kernel uses to write allocated vector */
636 u16 entry; /* driver uses to specify entry, OS writes */
637};
638
0366f8f7 639
1da177e4 640#ifndef CONFIG_PCI_MSI
1da177e4
LT		 641static inline int pci_enable_msi(struct pci_dev *dev) {return -1;}
642static inline void pci_disable_msi(struct pci_dev *dev) {}
643static inline int pci_enable_msix(struct pci_dev* dev,
644 struct msix_entry *entries, int nvec) {return -1;}
645static inline void pci_disable_msix(struct pci_dev *dev) {}
646static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) {}
647#else
1da177e4
LT		 648extern int pci_enable_msi(struct pci_dev *dev);
649extern void pci_disable_msi(struct pci_dev *dev);
650extern int pci_enable_msix(struct pci_dev* dev,
651 struct msix_entry *entries, int nvec);
652extern void pci_disable_msix(struct pci_dev *dev);
653extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
654#endif
655
8b955b0d 656#ifdef CONFIG_HT_IRQ
8b955b0d
EB		 657/* The functions a driver should call */
658int ht_create_irq(struct pci_dev *dev, int idx);
659void ht_destroy_irq(unsigned int irq);
8b955b0d
EB		 660#endif /* CONFIG_HT_IRQ */
661
e04b0ea2
BK		 662extern void pci_block_user_cfg_access(struct pci_dev *dev);
663extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
664
4352dfd5
GKH		 665/*
666 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
667 * a PCI domain is defined to be a set of PCI busses which share
668 * configuration space.
669 */
670#ifndef CONFIG_PCI_DOMAINS
671static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
672static inline int pci_proc_domain(struct pci_bus *bus)
673{
674 return 0;
675}
676#endif
1da177e4 677
4352dfd5 678#else /* CONFIG_PCI is not enabled */
1da177e4
LT		 679
680/*
681 * If the system does not have PCI, clearly these return errors. Define
682 * these as simple inline functions to avoid hair in drivers.
683 */
684
1da177e4
LT		 685#define _PCI_NOP(o,s,t) \
686 static inline int pci_##o##_config_##s (struct pci_dev *dev, int where, t val) \
687 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
688#define _PCI_NOP_ALL(o,x) _PCI_NOP(o,byte,u8 x) \
689 _PCI_NOP(o,word,u16 x) \
690 _PCI_NOP(o,dword,u32 x)
691_PCI_NOP_ALL(read, *)
692_PCI_NOP_ALL(write,)
693
694static inline struct pci_dev *pci_find_device(unsigned int vendor, unsigned int device, const struct pci_dev *from)
695{ return NULL; }
696
697static inline struct pci_dev *pci_find_slot(unsigned int bus, unsigned int devfn)
698{ return NULL; }
699
d42552c3
AM		 700static inline struct pci_dev *pci_get_device(unsigned int vendor,
701 unsigned int device, struct pci_dev *from)
702{ return NULL; }
703
704static inline struct pci_dev *pci_get_device_reverse(unsigned int vendor,
705 unsigned int device, struct pci_dev *from)
1da177e4
LT		 706{ return NULL; }
707
708static inline struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
709unsigned int ss_vendor, unsigned int ss_device, struct pci_dev *from)
710{ return NULL; }
711
712static inline struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from)
713{ return NULL; }
714
715#define pci_dev_present(ids) (0)
d86f90f9 716#define pci_find_present(ids) (NULL)
1da177e4
LT		 717#define pci_dev_put(dev) do { } while (0)
718
719static inline void pci_set_master(struct pci_dev *dev) { }
720static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
721static inline void pci_disable_device(struct pci_dev *dev) { }
722static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; }
1da177e4 723static inline int pci_assign_resource(struct pci_dev *dev, int i) { return -EBUSY;}
863b18f4 724static inline int __pci_register_driver(struct pci_driver *drv, struct module *owner) { return 0;}
1da177e4
LT		 725static inline int pci_register_driver(struct pci_driver *drv) { return 0;}
726static inline void pci_unregister_driver(struct pci_driver *drv) { }
727static inline int pci_find_capability (struct pci_dev *dev, int cap) {return 0; }
24a4e377 728static inline int pci_find_next_capability (struct pci_dev *dev, u8 post, int cap) { return 0; }
3a720d72 729static inline int pci_find_ext_capability (struct pci_dev *dev, int cap) {return 0; }
1da177e4
LT		 730static inline const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev) { return NULL; }
731
732/* Power management related routines */
733static inline int pci_save_state(struct pci_dev *dev) { return 0; }
734static inline int pci_restore_state(struct pci_dev *dev) { return 0; }
735static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) { return 0; }
438510f6 736static inline pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) { return PCI_D0; }
1da177e4
LT		 737static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) { return 0; }
738
a46e8126
KG		 739#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
740
e04b0ea2
BK		 741static inline void pci_block_user_cfg_access(struct pci_dev *dev) { }
742static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) { }
743
4352dfd5 744#endif /* CONFIG_PCI */
1da177e4 745
4352dfd5
GKH		 746/* Include architecture-dependent settings and functions */
747
748#include <asm/pci.h>
1da177e4
LT		 749
750/* these helpers provide future and backwards compatibility
751 * for accessing popular PCI BAR info */
752#define pci_resource_start(dev,bar) ((dev)->resource[(bar)].start)
753#define pci_resource_end(dev,bar) ((dev)->resource[(bar)].end)
754#define pci_resource_flags(dev,bar) ((dev)->resource[(bar)].flags)
755#define pci_resource_len(dev,bar) \
756 ((pci_resource_start((dev),(bar)) == 0 && \
757 pci_resource_end((dev),(bar)) == \
758 pci_resource_start((dev),(bar))) ? 0 : \
759 \
760 (pci_resource_end((dev),(bar)) - \
761 pci_resource_start((dev),(bar)) + 1))
762
763/* Similar to the helpers above, these manipulate per-pci_dev
764 * driver-specific data. They are really just a wrapper around
765 * the generic device structure functions of these calls.
766 */
767static inline void *pci_get_drvdata (struct pci_dev *pdev)
768{
769 return dev_get_drvdata(&pdev->dev);
770}
771
772static inline void pci_set_drvdata (struct pci_dev *pdev, void *data)
773{
774 dev_set_drvdata(&pdev->dev, data);
775}
776
777/* If you want to know what to call your pci_dev, ask this function.
778 * Again, it's a wrapper around the generic device.
779 */
780static inline char *pci_name(struct pci_dev *pdev)
781{
782 return pdev->dev.bus_id;
783}
784
2311b1f2
ME		 785
786/* Some archs don't want to expose struct resource to userland as-is
787 * in sysfs and /proc
788 */
789#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
790static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
e31dd6e4
GKH		 791 const struct resource *rsrc, resource_size_t *start,
792 resource_size_t *end)
2311b1f2
ME		 793{
794 *start = rsrc->start;
795 *end = rsrc->end;
796}
797#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
798
799
1da177e4
LT		 800/*
801 * The world is not perfect and supplies us with broken PCI devices.
802 * For at least a part of these bugs we need a work-around, so both
803 * generic (drivers/pci/quirks.c) and per-architecture code can define
804 * fixup hooks to be called for particular buggy devices.
805 */
806
807struct pci_fixup {
808 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
809 void (*hook)(struct pci_dev *dev);
810};
811
812enum pci_fixup_pass {
813 pci_fixup_early, /* Before probing BARs */
814 pci_fixup_header, /* After reading configuration header */
815 pci_fixup_final, /* Final phase of device fixups */
816 pci_fixup_enable, /* pci_enable_device() time */
1597cacb 817 pci_fixup_resume, /* pci_enable_device() time */
1da177e4
LT		 818};
819
820/* Anonymous variables would be nice... */
821#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
74d863ee 822 static const struct pci_fixup __pci_fixup_##name __attribute_used__ \
1da177e4
LT		 823 __attribute__((__section__(#section))) = { vendor, device, hook };
824#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
825 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
826 vendor##device##hook, vendor, device, hook)
827#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
828 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
829 vendor##device##hook, vendor, device, hook)
830#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
831 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
832 vendor##device##hook, vendor, device, hook)
833#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
834 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
835 vendor##device##hook, vendor, device, hook)
1597cacb
AC		 836#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
837 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
838 resume##vendor##device##hook, vendor, device, hook)
1da177e4
LT		 839
840
841void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
842
5ea81769
AV		 843void __iomem * pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
844void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
845void __iomem * const * pcim_iomap_table(struct pci_dev *pdev);
846int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
847
1da177e4 848extern int pci_pci_problems;
236561e5 849#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1da177e4
LT		 850#define PCIPCI_TRITON 2
851#define PCIPCI_NATOMA 4
852#define PCIPCI_VIAETBF 8
853#define PCIPCI_VSFX 16
236561e5
AC		 854#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
855#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1da177e4
LT		 856
857#endif /* __KERNEL__ */
858#endif /* LINUX_PCI_H */
kernel source for telekom puls (alcatel/mediatek)