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ipc, msg: forbid negative values for "msg{max,mnb,mni}"
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / pci.h
CommitLineData
1da177e4
LT		 1/*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
1da177e4
LT		 16#ifndef LINUX_PCI_H
17#define LINUX_PCI_H
18
1da177e4 19
778382e0
DW		 20#include <linux/mod_devicetable.h>
21
1da177e4 22#include <linux/types.h>
98db6f19 23#include <linux/init.h>
1da177e4
LT		 24#include <linux/ioport.h>
25#include <linux/list.h>
4a7fb636 26#include <linux/compiler.h>
1da177e4 27#include <linux/errno.h>
f46753c5 28#include <linux/kobject.h>
60063497 29#include <linux/atomic.h>
1da177e4 30#include <linux/device.h>
1388cc96 31#include <linux/io.h>
74bb1bcc 32#include <linux/irqreturn.h>
607ca46e 33#include <uapi/linux/pci.h>
1da177e4 34
7e7a43c3
AB		 35/* Include the ID list */
36#include <linux/pci_ids.h>
37
85467136
SK		 38/*
39 * The PCI interface treats multi-function devices as independent
40 * devices. The slot/function address of each device is encoded
41 * in a single byte as follows:
42 *
43 * 7:3 = slot
44 * 2:0 = function
45 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined uapi/linux/pci.h
46 * In the interest of not exposing interfaces to user-space unnecessarily,
47 * the following kernel only defines are being added here.
48 */
49#define PCI_DEVID(bus, devfn) ((((u16)bus) << 8) | devfn)
50/* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
51#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
52
f46753c5
AC		 53/* pci_slot represents a physical slot */
54struct pci_slot {
55 struct pci_bus *bus; /* The bus this slot is on */
56 struct list_head list; /* node in list of slots on this bus */
57 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
58 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
59 struct kobject kobj;
60};
61
0ad772ec
AC		 62static inline const char *pci_slot_name(const struct pci_slot *slot)
63{
64 return kobject_name(&slot->kobj);
65}
66
1da177e4
LT		 67/* File state for mmap()s on /proc/bus/pci/X/Y */
68enum pci_mmap_state {
69 pci_mmap_io,
70 pci_mmap_mem
71};
72
73/* This defines the direction arg to the DMA mapping routines. */
74#define PCI_DMA_BIDIRECTIONAL 0
75#define PCI_DMA_TODEVICE 1
76#define PCI_DMA_FROMDEVICE 2
77#define PCI_DMA_NONE 3
78
fde09c6d
YZ		 79/*
80 * For PCI devices, the region numbers are assigned this way:
81 */
82enum {
83 /* #0-5: standard PCI resources */
84 PCI_STD_RESOURCES,
85 PCI_STD_RESOURCE_END = 5,
86
87 /* #6: expansion ROM resource */
88 PCI_ROM_RESOURCE,
89
d1b054da
YZ		 90 /* device specific resources */
91#ifdef CONFIG_PCI_IOV
92 PCI_IOV_RESOURCES,
93 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
94#endif
95
fde09c6d
YZ		 96 /* resources assigned to buses behind the bridge */
97#define PCI_BRIDGE_RESOURCE_NUM 4
98
99 PCI_BRIDGE_RESOURCES,
100 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
101 PCI_BRIDGE_RESOURCE_NUM - 1,
102
103 /* total resources associated with a PCI device */
104 PCI_NUM_RESOURCES,
105
106 /* preserve this for compatibility */
cda57bf9 107 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
fde09c6d 108};
1da177e4
LT		 109
110typedef int __bitwise pci_power_t;
111
4352dfd5
GKH		 112#define PCI_D0 ((pci_power_t __force) 0)
113#define PCI_D1 ((pci_power_t __force) 1)
114#define PCI_D2 ((pci_power_t __force) 2)
1da177e4
LT		 115#define PCI_D3hot ((pci_power_t __force) 3)
116#define PCI_D3cold ((pci_power_t __force) 4)
3fe9d19f 117#define PCI_UNKNOWN ((pci_power_t __force) 5)
438510f6 118#define PCI_POWER_ERROR ((pci_power_t __force) -1)
1da177e4 119
00240c38
AS		 120/* Remember to update this when the list above changes! */
121extern const char *pci_power_names[];
122
123static inline const char *pci_power_name(pci_power_t state)
124{
125 return pci_power_names[1 + (int) state];
126}
127
448bd857
HY		 128#define PCI_PM_D2_DELAY 200
129#define PCI_PM_D3_WAIT 10
130#define PCI_PM_D3COLD_WAIT 100
131#define PCI_PM_BUS_WAIT 50
aa8c6c93 132
392a1ce7
LV		 133/** The pci_channel state describes connectivity between the CPU and
134 * the pci device. If some PCI bus between here and the pci device
135 * has crashed or locked up, this info is reflected here.
136 */
137typedef unsigned int __bitwise pci_channel_state_t;
138
139enum pci_channel_state {
140 /* I/O channel is in normal state */
141 pci_channel_io_normal = (__force pci_channel_state_t) 1,
142
143 /* I/O to channel is blocked */
144 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
145
146 /* PCI card is dead */
147 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
148};
149
f7bdd12d
BK		 150typedef unsigned int __bitwise pcie_reset_state_t;
151
152enum pcie_reset_state {
153 /* Reset is NOT asserted (Use to deassert reset) */
154 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
155
156 /* Use #PERST to reset PCI-E device */
157 pcie_warm_reset = (__force pcie_reset_state_t) 2,
158
159 /* Use PCI-E Hot Reset to reset device */
160 pcie_hot_reset = (__force pcie_reset_state_t) 3
161};
162
ba698ad4
DM		 163typedef unsigned short __bitwise pci_dev_flags_t;
164enum pci_dev_flags {
165 /* INTX_DISABLE in PCI_COMMAND register disables MSI
166 * generation too.
167 */
168 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
979b1791
AC		 169 /* Device configuration is irrevocably lost if disabled into D3 */
170 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
6777829c
GR		 171 /* Provide indication device is assigned by a Virtual Machine Manager */
172 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
ba698ad4
DM		 173};
174
e1d3a908
SA		 175enum pci_irq_reroute_variant {
176 INTEL_IRQ_REROUTE_VARIANT = 1,
177 MAX_IRQ_REROUTE_VARIANTS = 3
178};
179
6e325a62
MT		 180typedef unsigned short __bitwise pci_bus_flags_t;
181enum pci_bus_flags {
d556ad4b
PO		 182 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
183 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
6e325a62
MT		 184};
185
536c8cb4
MW		 186/* Based on the PCI Hotplug Spec, but some values are made up by us */
187enum pci_bus_speed {
188 PCI_SPEED_33MHz = 0x00,
189 PCI_SPEED_66MHz = 0x01,
190 PCI_SPEED_66MHz_PCIX = 0x02,
191 PCI_SPEED_100MHz_PCIX = 0x03,
192 PCI_SPEED_133MHz_PCIX = 0x04,
193 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
194 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
195 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
196 PCI_SPEED_66MHz_PCIX_266 = 0x09,
197 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
198 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
45b4cdd5
MW		 199 AGP_UNKNOWN = 0x0c,
200 AGP_1X = 0x0d,
201 AGP_2X = 0x0e,
202 AGP_4X = 0x0f,
203 AGP_8X = 0x10,
536c8cb4
MW		 204 PCI_SPEED_66MHz_PCIX_533 = 0x11,
205 PCI_SPEED_100MHz_PCIX_533 = 0x12,
206 PCI_SPEED_133MHz_PCIX_533 = 0x13,
207 PCIE_SPEED_2_5GT = 0x14,
208 PCIE_SPEED_5_0GT = 0x15,
9dfd97fe 209 PCIE_SPEED_8_0GT = 0x16,
536c8cb4
MW		 210 PCI_SPEED_UNKNOWN = 0xff,
211};
212
24a4742f 213struct pci_cap_saved_data {
41017f0c 214 char cap_nr;
24a4742f 215 unsigned int size;
41017f0c
SL		 216 u32 data[0];
217};
218
24a4742f
AW		 219struct pci_cap_saved_state {
220 struct hlist_node next;
221 struct pci_cap_saved_data cap;
222};
223
7d715a6c 224struct pcie_link_state;
ee69439c 225struct pci_vpd;
d1b054da 226struct pci_sriov;
302b4215 227struct pci_ats;
ee69439c 228
1da177e4
LT		 229/*
230 * The pci_dev structure is used to describe PCI devices.
231 */
232struct pci_dev {
1da177e4
LT		 233 struct list_head bus_list; /* node in per-bus list */
234 struct pci_bus *bus; /* bus this device is on */
235 struct pci_bus *subordinate; /* bus this device bridges to */
236
237 void *sysdata; /* hook for sys-specific extension */
238 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
f46753c5 239 struct pci_slot *slot; /* Physical slot this device is in */
1da177e4
LT		 240
241 unsigned int devfn; /* encoded device & function index */
242 unsigned short vendor;
243 unsigned short device;
244 unsigned short subsystem_vendor;
245 unsigned short subsystem_device;
246 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
b8a3a521 247 u8 revision; /* PCI revision, low byte of class word */
1da177e4 248 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
0efea000 249 u8 pcie_cap; /* PCI-E capability offset */
e375b561
GS		 250 u8 msi_cap; /* MSI capability offset */
251 u8 msix_cap; /* MSI-X capability offset */
b03e7495 252 u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */
1da177e4 253 u8 rom_base_reg; /* which config register controls the ROM */
ffeff788 254 u8 pin; /* which interrupt pin this device uses */
786e2288 255 u16 pcie_flags_reg; /* cached PCI-E Capabilities Register */
1da177e4
LT		 256
257 struct pci_driver *driver; /* which driver has allocated this device */
258 u64 dma_mask; /* Mask of the bits of bus address this
259 device implements. Normally this is
260 0xffffffff. You only need to change
261 this if your device has broken DMA
262 or supports 64-bit transfers. */
263
4d57cdfa
FT		 264 struct device_dma_parameters dma_parms;
265
1da177e4
LT		 266 pci_power_t current_state; /* Current operating state. In ACPI-speak,
267 this is D0-D3, D0 being fully functional,
268 and D3 being off. */
703860ed 269 u8 pm_cap; /* PM capability offset */
337001b6
RW		 270 unsigned int pme_support:5; /* Bitmask of states from which PME#
271 can be generated */
c7f48656 272 unsigned int pme_interrupt:1;
379021d5 273 unsigned int pme_poll:1; /* Poll device's PME status bit */
337001b6
RW		 274 unsigned int d1_support:1; /* Low power state D1 is supported */
275 unsigned int d2_support:1; /* Low power state D2 is supported */
448bd857
HY		 276 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
277 unsigned int no_d3cold:1; /* D3cold is forbidden */
278 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
253d2e54
JP		 279 unsigned int mmio_always_on:1; /* disallow turning off io/mem
280 decoding during bar sizing */
e80bb09d 281 unsigned int wakeup_prepared:1;
448bd857
HY		 282 unsigned int runtime_d3cold:1; /* whether go through runtime
283 D3cold, not set for devices
284 powered on/off by the
285 corresponding bridge */
1ae861e6 286 unsigned int d3_delay; /* D3->D0 transition time in ms */
448bd857 287 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
1da177e4 288
7d715a6c
SL		 289#ifdef CONFIG_PCIEASPM
290 struct pcie_link_state *link_state; /* ASPM link state. */
291#endif
292
392a1ce7 293 pci_channel_state_t error_state; /* current connectivity state */
1da177e4
LT		 294 struct device dev; /* Generic device interface */
295
1da177e4
LT		 296 int cfg_size; /* Size of configuration space */
297
298 /*
299 * Instead of touching interrupt line and base address registers
300 * directly, use the values stored here. They might be different!
301 */
302 unsigned int irq;
303 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
304
58d9a38f 305 bool match_driver; /* Skip attaching driver */
1da177e4
LT		 306 /* These fields are used by common fixups */
307 unsigned int transparent:1; /* Transparent PCI bridge */
308 unsigned int multifunction:1;/* Part of multi-function device */
309 /* keep track of device state */
8a1bc901 310 unsigned int is_added:1;
1da177e4 311 unsigned int is_busmaster:1; /* device is busmaster */
4602b88d 312 unsigned int no_msi:1; /* device may not use msi */
fb51ccbf 313 unsigned int block_cfg_access:1; /* config space access is blocked */
bd8481e1 314 unsigned int broken_parity_status:1; /* Device generates false positive parity */
e1d3a908 315 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
99dc804d
SL		 316 unsigned int msi_enabled:1;
317 unsigned int msix_enabled:1;
58c3a727 318 unsigned int ari_enabled:1; /* ARI forwarding */
9ac7849e 319 unsigned int is_managed:1;
6d3be84a
KK		 320 unsigned int is_pcie:1; /* Obsolete. Will be removed.
321 Use pci_is_pcie() instead */
260d703a 322 unsigned int needs_freset:1; /* Dev requires fundamental reset */
aa8c6c93 323 unsigned int state_saved:1;
d1b054da 324 unsigned int is_physfn:1;
dd7cc44d 325 unsigned int is_virtfn:1;
711d5779 326 unsigned int reset_fn:1;
28760489 327 unsigned int is_hotplug_bridge:1;
affb72c3
HY		 328 unsigned int __aer_firmware_first_valid:1;
329 unsigned int __aer_firmware_first:1;
fbebb9fd 330 unsigned int broken_intx_masking:1;
2b28ae19 331 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
ba698ad4 332 pci_dev_flags_t dev_flags;
bae94d02 333 atomic_t enable_cnt; /* pci_enable_device has been called */
4602b88d 334
1da177e4 335 u32 saved_config_space[16]; /* config space saved at suspend time */
41017f0c 336 struct hlist_head saved_cap_space;
1da177e4
LT		 337 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
338 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
339 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
45aec1ae 340 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
ded86d8d 341#ifdef CONFIG_PCI_MSI
4aa9bc95 342 struct list_head msi_list;
da8d1c8b 343 struct kset *msi_kset;
ded86d8d 344#endif
94e61088 345 struct pci_vpd *vpd;
466b3ddf 346#ifdef CONFIG_PCI_ATS
dd7cc44d
YZ		 347 union {
348 struct pci_sriov *sriov; /* SR-IOV capability related */
349 struct pci_dev *physfn; /* the PF this VF is associated with */
350 };
302b4215 351 struct pci_ats *ats; /* Address Translation Service */
d1b054da 352#endif
dbd3fc33 353 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
84c1b80e 354 size_t romlen; /* Length of ROM if it's not from the BAR */
1da177e4
LT		 355};
356
dda56549
Y		 357static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
358{
359#ifdef CONFIG_PCI_IOV
360 if (dev->is_virtfn)
361 dev = dev->physfn;
362#endif
363
364 return dev;
365}
366
f39d5b72 367struct pci_dev *alloc_pci_dev(void);
65891215 368
1da177e4
LT		 369#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
370#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
371
a7369f1f
LV		 372static inline int pci_channel_offline(struct pci_dev *pdev)
373{
374 return (pdev->error_state != pci_channel_io_normal);
375}
376
67cdc827
YL		 377extern struct resource busn_resource;
378
0efd5aab
BH		 379struct pci_host_bridge_window {
380 struct list_head list;
381 struct resource *res; /* host bridge aperture (CPU address) */
382 resource_size_t offset; /* bus address + offset = CPU address */
383};
41017f0c 384
5a21d70d 385struct pci_host_bridge {
7b543663 386 struct device dev;
5a21d70d 387 struct pci_bus *bus; /* root bus */
0efd5aab 388 struct list_head windows; /* pci_host_bridge_windows */
4fa2649a
YL		 389 void (*release_fn)(struct pci_host_bridge *);
390 void *release_data;
5a21d70d 391};
41017f0c 392
7b543663 393#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
4fa2649a
YL		 394void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
395 void (*release_fn)(struct pci_host_bridge *),
396 void *release_data);
7b543663 397
6c0cc950
RW		 398int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
399
2fe2abf8
BH		 400/*
401 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
402 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
403 * buses below host bridges or subtractive decode bridges) go in the list.
404 * Use pci_bus_for_each_resource() to iterate through all the resources.
405 */
406
407/*
408 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
409 * and there's no way to program the bridge with the details of the window.
410 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
411 * decode bit set, because they are explicit and can be programmed with _SRS.
412 */
413#define PCI_SUBTRACTIVE_DECODE 0x1
414
415struct pci_bus_resource {
416 struct list_head list;
417 struct resource *res;
418 unsigned int flags;
419};
4352dfd5
GKH		 420
421#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
1da177e4
LT		 422
423struct pci_bus {
424 struct list_head node; /* node in list of buses */
425 struct pci_bus *parent; /* parent bus this bridge is on */
426 struct list_head children; /* list of child buses */
427 struct list_head devices; /* list of devices on this bus */
428 struct pci_dev *self; /* bridge device as seen by parent */
f46753c5 429 struct list_head slots; /* list of slots on this bus */
2fe2abf8
BH		 430 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
431 struct list_head resources; /* address space routed to this bus */
92f02430 432 struct resource busn_res; /* bus numbers routed to this bus */
1da177e4
LT		 433
434 struct pci_ops *ops; /* configuration access functions */
435 void *sysdata; /* hook for sys-specific extension */
436 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
437
438 unsigned char number; /* bus number */
439 unsigned char primary; /* number of primary bridge */
3749c51a
MW		 440 unsigned char max_bus_speed; /* enum pci_bus_speed */
441 unsigned char cur_bus_speed; /* enum pci_bus_speed */
1da177e4
LT		 442
443 char name[48];
444
445 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
6e325a62 446 pci_bus_flags_t bus_flags; /* Inherited by child busses */
1da177e4 447 struct device *bridge;
fd7d1ced 448 struct device dev;
1da177e4
LT		 449 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
450 struct bin_attribute *legacy_mem; /* legacy mem */
cc74d96f 451 unsigned int is_added:1;
1da177e4
LT		 452};
453
454#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
fd7d1ced 455#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
1da177e4 456
79af72d7
KK		 457/*
458 * Returns true if the pci bus is root (behind host-pci bridge),
459 * false otherwise
460 */
461static inline bool pci_is_root_bus(struct pci_bus *pbus)
462{
463 return !(pbus->parent);
464}
465
16cf0ebc
RW		 466#ifdef CONFIG_PCI_MSI
467static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
468{
469 return pci_dev->msi_enabled || pci_dev->msix_enabled;
470}
471#else
472static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
473#endif
474
1da177e4
LT		 475/*
476 * Error values that may be returned by PCI functions.
477 */
478#define PCIBIOS_SUCCESSFUL 0x00
479#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
480#define PCIBIOS_BAD_VENDOR_ID 0x83
481#define PCIBIOS_DEVICE_NOT_FOUND 0x86
482#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
483#define PCIBIOS_SET_FAILED 0x88
484#define PCIBIOS_BUFFER_TOO_SMALL 0x89
485
a6961651
AW		 486/*
487 * Translate above to generic errno for passing back through non-pci.
488 */
489static inline int pcibios_err_to_errno(int err)
490{
491 if (err <= PCIBIOS_SUCCESSFUL)
492 return err; /* Assume already errno */
493
494 switch (err) {
495 case PCIBIOS_FUNC_NOT_SUPPORTED:
496 return -ENOENT;
497 case PCIBIOS_BAD_VENDOR_ID:
498 return -EINVAL;
499 case PCIBIOS_DEVICE_NOT_FOUND:
500 return -ENODEV;
501 case PCIBIOS_BAD_REGISTER_NUMBER:
502 return -EFAULT;
503 case PCIBIOS_SET_FAILED:
504 return -EIO;
505 case PCIBIOS_BUFFER_TOO_SMALL:
506 return -ENOSPC;
507 }
508
509 return -ENOTTY;
510}
511
1da177e4
LT		 512/* Low-level architecture-dependent routines */
513
514struct pci_ops {
515 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
516 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
517};
518
b6ce068a
MW		 519/*
520 * ACPI needs to be able to access PCI config space before we've done a
521 * PCI bus scan and created pci_bus structures.
522 */
f39d5b72
BH		 523int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
524 int reg, int len, u32 *val);
525int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
526 int reg, int len, u32 val);
1da177e4
LT		 527
528struct pci_bus_region {
c40a22e0
BH		 529 resource_size_t start;
530 resource_size_t end;
1da177e4
LT		 531};
532
533struct pci_dynids {
534 spinlock_t lock; /* protects list, index */
535 struct list_head list; /* for IDs added at runtime */
1da177e4
LT		 536};
537
392a1ce7
LV		 538/* ---------------------------------------------------------------- */
539/** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
579082df 540 * a set of callbacks in struct pci_error_handlers, then that device driver
392a1ce7
LV		 541 * will be notified of PCI bus errors, and will be driven to recovery
542 * when an error occurs.
543 */
544
545typedef unsigned int __bitwise pci_ers_result_t;
546
547enum pci_ers_result {
548 /* no result/none/not supported in device driver */
549 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
550
551 /* Device driver can recover without slot reset */
552 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
553
554 /* Device driver wants slot to be reset. */
555 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
556
557 /* Device has completely failed, is unrecoverable */
558 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
559
560 /* Device driver is fully recovered and operational */
561 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
918b4053
VMP		 562
563 /* No AER capabilities registered for the driver */
564 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
392a1ce7
LV		 565};
566
567/* PCI bus error event callbacks */
05cca6e5 568struct pci_error_handlers {
392a1ce7
LV		 569 /* PCI bus error detected on this device */
570 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
05cca6e5 571 enum pci_channel_state error);
392a1ce7
LV		 572
573 /* MMIO has been re-enabled, but not DMA */
574 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
575
576 /* PCI Express link has been reset */
577 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
578
579 /* PCI slot has been reset */
580 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
581
582 /* Device driver may resume normal operations */
583 void (*resume)(struct pci_dev *dev);
584};
585
586/* ---------------------------------------------------------------- */
587
1da177e4
LT		 588struct module;
589struct pci_driver {
590 struct list_head node;
42b21932 591 const char *name;
1da177e4
LT		 592 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
593 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
594 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
595 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
cbd69dbb
LT		 596 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
597 int (*resume_early) (struct pci_dev *dev);
1da177e4 598 int (*resume) (struct pci_dev *dev); /* Device woken up */
c8958177 599 void (*shutdown) (struct pci_dev *dev);
1789382a 600 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
49453028 601 const struct pci_error_handlers *err_handler;
1da177e4
LT		 602 struct device_driver driver;
603 struct pci_dynids dynids;
604};
605
05cca6e5 606#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
1da177e4 607
90a1ba0c 608/**
9f9351bb 609 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
90a1ba0c
JB		 610 * @_table: device table name
611 *
612 * This macro is used to create a struct pci_device_id array (a device table)
613 * in a generic manner.
614 */
9f9351bb 615#define DEFINE_PCI_DEVICE_TABLE(_table) \
15856ad5 616 const struct pci_device_id _table[]
90a1ba0c 617
1da177e4
LT		 618/**
619 * PCI_DEVICE - macro used to describe a specific pci device
620 * @vend: the 16 bit PCI Vendor ID
621 * @dev: the 16 bit PCI Device ID
622 *
623 * This macro is used to create a struct pci_device_id that matches a
624 * specific device. The subvendor and subdevice fields will be set to
625 * PCI_ANY_ID.
626 */
627#define PCI_DEVICE(vend,dev) \
628 .vendor = (vend), .device = (dev), \
629 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
630
3d567e0e
NNS		 631/**
632 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
633 * @vend: the 16 bit PCI Vendor ID
634 * @dev: the 16 bit PCI Device ID
635 * @subvend: the 16 bit PCI Subvendor ID
636 * @subdev: the 16 bit PCI Subdevice ID
637 *
638 * This macro is used to create a struct pci_device_id that matches a
639 * specific device with subsystem information.
640 */
641#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
642 .vendor = (vend), .device = (dev), \
643 .subvendor = (subvend), .subdevice = (subdev)
644
1da177e4
LT		 645/**
646 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
647 * @dev_class: the class, subclass, prog-if triple for this device
648 * @dev_class_mask: the class mask for this device
649 *
650 * This macro is used to create a struct pci_device_id that matches a
4352dfd5 651 * specific PCI class. The vendor, device, subvendor, and subdevice
1da177e4
LT		 652 * fields will be set to PCI_ANY_ID.
653 */
654#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
655 .class = (dev_class), .class_mask = (dev_class_mask), \
656 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
657 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
658
1597cacb
AC		 659/**
660 * PCI_VDEVICE - macro used to describe a specific pci device in short form
c322b28a
ZY		 661 * @vendor: the vendor name
662 * @device: the 16 bit PCI Device ID
1597cacb
AC		 663 *
664 * This macro is used to create a struct pci_device_id that matches a
665 * specific PCI device. The subvendor, and subdevice fields will be set
666 * to PCI_ANY_ID. The macro allows the next field to follow as the device
667 * private data.
668 */
669
670#define PCI_VDEVICE(vendor, device) \
671 PCI_VENDOR_ID_##vendor, (device), \
672 PCI_ANY_ID, PCI_ANY_ID, 0, 0
673
1da177e4
LT		 674/* these external functions are only available when PCI support is enabled */
675#ifdef CONFIG_PCI
676
f39d5b72 677void pcie_bus_configure_settings(struct pci_bus *bus, u8 smpss);
b03e7495
JM		 678
679enum pcie_bus_config_types {
5f39e670 680 PCIE_BUS_TUNE_OFF,
b03e7495 681 PCIE_BUS_SAFE,
5f39e670 682 PCIE_BUS_PERFORMANCE,
b03e7495
JM		 683 PCIE_BUS_PEER2PEER,
684};
685
686extern enum pcie_bus_config_types pcie_bus_config;
687
1da177e4
LT		 688extern struct bus_type pci_bus_type;
689
690/* Do NOT directly access these two variables, unless you are arch specific pci
691 * code, or pci core code. */
692extern struct list_head pci_root_buses; /* list of all known PCI buses */
ed4aaadb 693/* Some device drivers need know if pci is initiated */
f39d5b72 694int no_pci_devices(void);
1da177e4 695
3c449ed0 696void pcibios_resource_survey_bus(struct pci_bus *bus);
10a95747
JL		 697void pcibios_add_bus(struct pci_bus *bus);
698void pcibios_remove_bus(struct pci_bus *bus);
1da177e4 699void pcibios_fixup_bus(struct pci_bus *);
4a7fb636 700int __must_check pcibios_enable_device(struct pci_dev *, int mask);
2b6f2c35 701/* Architecture specific versions may override this (weak) */
05cca6e5 702char *pcibios_setup(char *str);
1da177e4
LT		 703
704/* Used only when drivers/pci/setup.c is used */
3b7a17fc 705resource_size_t pcibios_align_resource(void *, const struct resource *,
b26b2d49 706 resource_size_t,
e31dd6e4 707 resource_size_t);
1da177e4
LT		 708void pcibios_update_irq(struct pci_dev *, int irq);
709
2d1c8618
BH		 710/* Weak but can be overriden by arch */
711void pci_fixup_cardbus(struct pci_bus *);
712
1da177e4
LT		 713/* Generic PCI functions used internally */
714
36a66cd6
BH		 715void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
716 struct resource *res);
717void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
718 struct pci_bus_region *region);
d1fd4fb6 719void pcibios_scan_specific_bus(int busn);
f39d5b72 720struct pci_bus *pci_find_bus(int domain, int busnr);
c48f1670 721void pci_bus_add_devices(const struct pci_bus *bus);
05cca6e5
GKH		 722struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
723 struct pci_ops *ops, void *sysdata);
de4b2f76 724struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
166c6370
BH		 725struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
726 struct pci_ops *ops, void *sysdata,
727 struct list_head *resources);
98a35831
YL		 728int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
729int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
730void pci_bus_release_busn_res(struct pci_bus *b);
15856ad5 731struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
a2ebb827
BH		 732 struct pci_ops *ops, void *sysdata,
733 struct list_head *resources);
05cca6e5
GKH		 734struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
735 int busnr);
3749c51a 736void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
f46753c5 737struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
828f3768
AC		 738 const char *name,
739 struct hotplug_slot *hotplug);
f46753c5 740void pci_destroy_slot(struct pci_slot *slot);
d25b7c8d 741void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
1da177e4 742int pci_scan_slot(struct pci_bus *bus, int devfn);
05cca6e5 743struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
cdb9b9f7 744void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1da177e4 745unsigned int pci_scan_child_bus(struct pci_bus *bus);
b19441af 746int __must_check pci_bus_add_device(struct pci_dev *dev);
1da177e4 747void pci_read_bridge_bases(struct pci_bus *child);
05cca6e5
GKH		 748struct resource *pci_find_parent_resource(const struct pci_dev *dev,
749 struct resource *res);
3df425f3 750u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1da177e4 751int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
68feac87 752u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
f39d5b72
BH		 753struct pci_dev *pci_dev_get(struct pci_dev *dev);
754void pci_dev_put(struct pci_dev *dev);
755void pci_remove_bus(struct pci_bus *b);
756void pci_stop_and_remove_bus_device(struct pci_dev *dev);
cdfcc572
YL		 757void pci_stop_root_bus(struct pci_bus *bus);
758void pci_remove_root_bus(struct pci_bus *bus);
b3743fa4 759void pci_setup_cardbus(struct pci_bus *bus);
f39d5b72 760void pci_sort_breadthfirst(void);
fb8a0d9d
WM		 761#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
762#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
763#define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
1da177e4
LT		 764
765/* Generic PCI functions exported to card drivers */
766
388c8c16
JB		 767enum pci_lost_interrupt_reason {
768 PCI_LOST_IRQ_NO_INFORMATION = 0,
769 PCI_LOST_IRQ_DISABLE_MSI,
770 PCI_LOST_IRQ_DISABLE_MSIX,
771 PCI_LOST_IRQ_DISABLE_ACPI,
772};
773enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
05cca6e5
GKH		 774int pci_find_capability(struct pci_dev *dev, int cap);
775int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
776int pci_find_ext_capability(struct pci_dev *dev, int cap);
44a9a36f 777int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
05cca6e5
GKH		 778int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
779int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
29f3eb64 780struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1da177e4 781
d42552c3
AM		 782struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
783 struct pci_dev *from);
05cca6e5 784struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1da177e4 785 unsigned int ss_vendor, unsigned int ss_device,
b08508c4 786 struct pci_dev *from);
05cca6e5 787struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
3c299dc2
AP		 788struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
789 unsigned int devfn);
790static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
791 unsigned int devfn)
792{
793 return pci_get_domain_bus_and_slot(0, bus, devfn);
794}
05cca6e5 795struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1da177e4
LT		 796int pci_dev_present(const struct pci_device_id *ids);
797
05cca6e5
GKH		 798int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
799 int where, u8 *val);
800int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
801 int where, u16 *val);
802int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
803 int where, u32 *val);
804int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
805 int where, u8 val);
806int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
807 int where, u16 val);
808int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
809 int where, u32 val);
a72b46c3 810struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1da177e4 811
bf362f75 812static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
1da177e4 813{
05cca6e5 814 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
1da177e4 815}
bf362f75 816static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
1da177e4 817{
05cca6e5 818 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
1da177e4 819}
bf362f75 820static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
05cca6e5 821 u32 *val)
1da177e4 822{
05cca6e5 823 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
1da177e4 824}
bf362f75 825static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
1da177e4 826{
05cca6e5 827 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
1da177e4 828}
bf362f75 829static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
1da177e4 830{
05cca6e5 831 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
1da177e4 832}
bf362f75 833static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
05cca6e5 834 u32 val)
1da177e4 835{
05cca6e5 836 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
1da177e4
LT		 837}
838
8c0d3a02
JL		 839int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
840int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
841int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
842int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
843int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
844 u16 clear, u16 set);
845int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
846 u32 clear, u32 set);
847
848static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
849 u16 set)
850{
851 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
852}
853
854static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
855 u32 set)
856{
857 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
858}
859
860static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
861 u16 clear)
862{
863 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
864}
865
866static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
867 u32 clear)
868{
869 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
870}
871
c63587d7
AW		 872/* user-space driven config access */
873int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
874int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
875int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
876int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
877int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
878int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
879
4a7fb636 880int __must_check pci_enable_device(struct pci_dev *dev);
b718989d
BH		 881int __must_check pci_enable_device_io(struct pci_dev *dev);
882int __must_check pci_enable_device_mem(struct pci_dev *dev);
0b62e13b 883int __must_check pci_reenable_device(struct pci_dev *);
9ac7849e
TH		 884int __must_check pcim_enable_device(struct pci_dev *pdev);
885void pcim_pin_device(struct pci_dev *pdev);
886
296ccb08
YS		 887static inline int pci_is_enabled(struct pci_dev *pdev)
888{
889 return (atomic_read(&pdev->enable_cnt) > 0);
890}
891
9ac7849e
TH		 892static inline int pci_is_managed(struct pci_dev *pdev)
893{
894 return pdev->is_managed;
895}
896
1da177e4 897void pci_disable_device(struct pci_dev *dev);
96c55900
MS		 898
899extern unsigned int pcibios_max_latency;
1da177e4 900void pci_set_master(struct pci_dev *dev);
6a479079 901void pci_clear_master(struct pci_dev *dev);
96c55900 902
f7bdd12d 903int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
15ea76d4 904int pci_set_cacheline_size(struct pci_dev *dev);
1da177e4 905#define HAVE_PCI_SET_MWI
4a7fb636 906int __must_check pci_set_mwi(struct pci_dev *dev);
694625c0 907int pci_try_set_mwi(struct pci_dev *dev);
1da177e4 908void pci_clear_mwi(struct pci_dev *dev);
a04ce0ff 909void pci_intx(struct pci_dev *dev, int enable);
a2e27787
JK		 910bool pci_intx_mask_supported(struct pci_dev *dev);
911bool pci_check_and_mask_intx(struct pci_dev *dev);
912bool pci_check_and_unmask_intx(struct pci_dev *dev);
f5f2b131 913void pci_msi_off(struct pci_dev *dev);
4d57cdfa 914int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
59fc67de 915int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
d556ad4b
PO		 916int pcix_get_max_mmrbc(struct pci_dev *dev);
917int pcix_get_mmrbc(struct pci_dev *dev);
918int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
2637e5b5 919int pcie_get_readrq(struct pci_dev *dev);
d556ad4b 920int pcie_set_readrq(struct pci_dev *dev, int rq);
b03e7495
JM		 921int pcie_get_mps(struct pci_dev *dev);
922int pcie_set_mps(struct pci_dev *dev, int mps);
8c1c699f 923int __pci_reset_function(struct pci_dev *dev);
a96d627a 924int __pci_reset_function_locked(struct pci_dev *dev);
8dd7f803 925int pci_reset_function(struct pci_dev *dev);
14add80b 926void pci_update_resource(struct pci_dev *dev, int resno);
4a7fb636 927int __must_check pci_assign_resource(struct pci_dev *dev, int i);
2bbc6942 928int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
c87deff7 929int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1da177e4
LT		 930
931/* ROM control related routines */
e416de5e
AC		 932int pci_enable_rom(struct pci_dev *pdev);
933void pci_disable_rom(struct pci_dev *pdev);
144a50ea 934void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1da177e4 935void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
97c44836 936size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
fffe01f7 937void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1da177e4
LT		 938
939/* Power management related routines */
940int pci_save_state(struct pci_dev *dev);
1d3c16a8 941void pci_restore_state(struct pci_dev *dev);
ffbdd3f7
AW		 942struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
943int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
944int pci_load_and_free_saved_state(struct pci_dev *dev,
945 struct pci_saved_state **state);
0e5dd46b 946int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
9c8550ee
LT		 947int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
948pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
e5899e1b 949bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
5a6c9b60 950void pci_pme_active(struct pci_dev *dev, bool enable);
6cbf8214
RW		 951int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
952 bool runtime, bool enable);
0235c4fc 953int pci_wake_from_d3(struct pci_dev *dev, bool enable);
e5899e1b 954pci_power_t pci_target_state(struct pci_dev *dev);
404cc2d8
RW		 955int pci_prepare_to_sleep(struct pci_dev *dev);
956int pci_back_from_sleep(struct pci_dev *dev);
b67ea761 957bool pci_dev_run_wake(struct pci_dev *dev);
bf4d2908 958bool pci_check_pme_status(struct pci_dev *dev);
bf4d2908 959void pci_pme_wakeup_bus(struct pci_bus *bus);
1da177e4 960
6cbf8214
RW		 961static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
962 bool enable)
963{
964 return __pci_enable_wake(dev, state, false, enable);
965}
1da177e4 966
b48d4425
JB		 967#define PCI_EXP_IDO_REQUEST (1<<0)
968#define PCI_EXP_IDO_COMPLETION (1<<1)
969void pci_enable_ido(struct pci_dev *dev, unsigned long type);
970void pci_disable_ido(struct pci_dev *dev, unsigned long type);
971
48a92a81 972enum pci_obff_signal_type {
688398bb
MS		 973 PCI_EXP_OBFF_SIGNAL_L0 = 0,
974 PCI_EXP_OBFF_SIGNAL_ALWAYS = 1,
48a92a81
JB		 975};
976int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
977void pci_disable_obff(struct pci_dev *dev);
978
51c2e0a7
JB		 979int pci_enable_ltr(struct pci_dev *dev);
980void pci_disable_ltr(struct pci_dev *dev);
981int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
982
bb209c82
BH		 983/* For use by arch with custom probe code */
984void set_pcie_port_type(struct pci_dev *pdev);
985void set_pcie_hotplug_bridge(struct pci_dev *pdev);
986
ce5ccdef 987/* Functions for PCI Hotplug drivers to use */
05cca6e5 988int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
2f320521 989unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
3ed4fd96 990unsigned int pci_rescan_bus(struct pci_bus *bus);
ce5ccdef 991
287d19ce
SH		 992/* Vital product data routines */
993ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
994ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
db567943 995int pci_vpd_truncate(struct pci_dev *dev, size_t size);
287d19ce 996
1da177e4 997/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
925845bd 998resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
ea741551 999void pci_bus_assign_resources(const struct pci_bus *bus);
1da177e4
LT		 1000void pci_bus_size_bridges(struct pci_bus *bus);
1001int pci_claim_resource(struct pci_dev *, int);
1002void pci_assign_unassigned_resources(void);
6841ec68 1003void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
17787940 1004void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1da177e4 1005void pdev_enable_device(struct pci_dev *);
842de40d 1006int pci_enable_resources(struct pci_dev *, int mask);
1da177e4 1007void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
d5341942 1008 int (*)(const struct pci_dev *, u8, u8));
1da177e4 1009#define HAVE_PCI_REQ_REGIONS 2
4a7fb636 1010int __must_check pci_request_regions(struct pci_dev *, const char *);
e8de1481 1011int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1da177e4 1012void pci_release_regions(struct pci_dev *);
4a7fb636 1013int __must_check pci_request_region(struct pci_dev *, int, const char *);
e8de1481 1014int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1da177e4 1015void pci_release_region(struct pci_dev *, int);
c87deff7 1016int pci_request_selected_regions(struct pci_dev *, int, const char *);
e8de1481 1017int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
c87deff7 1018void pci_release_selected_regions(struct pci_dev *, int);
1da177e4
LT		 1019
1020/* drivers/pci/bus.c */
45ca9e97 1021void pci_add_resource(struct list_head *resources, struct resource *res);
0efd5aab
BH		 1022void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1023 resource_size_t offset);
45ca9e97 1024void pci_free_resource_list(struct list_head *resources);
2fe2abf8
BH		 1025void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
1026struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1027void pci_bus_remove_resources(struct pci_bus *bus);
1028
89a74ecc 1029#define pci_bus_for_each_resource(bus, res, i) \
2fe2abf8
BH		 1030 for (i = 0; \
1031 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1032 i++)
89a74ecc 1033
4a7fb636
AM		 1034int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1035 struct resource *res, resource_size_t size,
1036 resource_size_t align, resource_size_t min,
1037 unsigned int type_mask,
3b7a17fc
DB		 1038 resource_size_t (*alignf)(void *,
1039 const struct resource *,
b26b2d49
DB		 1040 resource_size_t,
1041 resource_size_t),
4a7fb636 1042 void *alignf_data);
1da177e4
LT		 1043void pci_enable_bridges(struct pci_bus *bus);
1044
863b18f4 1045/* Proper probing supporting hot-pluggable devices */
725522b5
GKH		 1046int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1047 const char *mod_name);
bba81165
AM		 1048
1049/*
1050 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1051 */
1052#define pci_register_driver(driver) \
1053 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
863b18f4 1054
05cca6e5 1055void pci_unregister_driver(struct pci_driver *dev);
aad4f400
GKH		 1056
1057/**
1058 * module_pci_driver() - Helper macro for registering a PCI driver
1059 * @__pci_driver: pci_driver struct
1060 *
1061 * Helper macro for PCI drivers which do not do anything special in module
1062 * init/exit. This eliminates a lot of boilerplate. Each module may only
1063 * use this macro once, and calling it replaces module_init() and module_exit()
1064 */
1065#define module_pci_driver(__pci_driver) \
1066 module_driver(__pci_driver, pci_register_driver, \
1067 pci_unregister_driver)
1068
05cca6e5 1069struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
9dba910e
TH		 1070int pci_add_dynid(struct pci_driver *drv,
1071 unsigned int vendor, unsigned int device,
1072 unsigned int subvendor, unsigned int subdevice,
1073 unsigned int class, unsigned int class_mask,
1074 unsigned long driver_data);
05cca6e5
GKH		 1075const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1076 struct pci_dev *dev);
1077int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1078 int pass);
1da177e4 1079
70298c6e 1080void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
cecf4864 1081 void *userdata);
70b9f7dc 1082int pci_cfg_space_size_ext(struct pci_dev *dev);
ac7dc65a 1083int pci_cfg_space_size(struct pci_dev *dev);
05cca6e5 1084unsigned char pci_bus_max_busnr(struct pci_bus *bus);
e2444273 1085void pci_setup_bridge(struct pci_bus *bus);
ac5ad93e
GS		 1086resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1087 unsigned long type);
cecf4864 1088
3448a19d
DA		 1089#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1090#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1091
deb2d2ec 1092int pci_set_vga_state(struct pci_dev *pdev, bool decode,
3448a19d 1093 unsigned int command_bits, u32 flags);
1da177e4
LT		 1094/* kmem_cache style wrapper around pci_alloc_consistent() */
1095
f41b1771 1096#include <linux/pci-dma.h>
1da177e4
LT		 1097#include <linux/dmapool.h>
1098
1099#define pci_pool dma_pool
1100#define pci_pool_create(name, pdev, size, align, allocation) \
1101 dma_pool_create(name, &pdev->dev, size, align, allocation)
1102#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1103#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1104#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1105
e24c2d96
DM		 1106enum pci_dma_burst_strategy {
1107 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
1108 strategy_parameter is N/A */
1109 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
1110 byte boundaries */
1111 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
1112 strategy_parameter byte boundaries */
1113};
1114
1da177e4 1115struct msix_entry {
16dbef4a 1116 u32 vector; /* kernel uses to write allocated vector */
1da177e4
LT		 1117 u16 entry; /* driver uses to specify entry, OS writes */
1118};
1119
0366f8f7 1120
1da177e4 1121#ifndef CONFIG_PCI_MSI
1c8d7b0a 1122static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
05cca6e5
GKH		 1123{
1124 return -1;
1125}
1126
08261d87
AG		 1127static inline int
1128pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec)
1129{
1130 return -1;
1131}
1132
d52877c7
YL		 1133static inline void pci_msi_shutdown(struct pci_dev *dev)
1134{ }
05cca6e5
GKH		 1135static inline void pci_disable_msi(struct pci_dev *dev)
1136{ }
1137
a52e2e35
RW		 1138static inline int pci_msix_table_size(struct pci_dev *dev)
1139{
1140 return 0;
1141}
05cca6e5
GKH		 1142static inline int pci_enable_msix(struct pci_dev *dev,
1143 struct msix_entry *entries, int nvec)
1144{
1145 return -1;
1146}
1147
d52877c7
YL		 1148static inline void pci_msix_shutdown(struct pci_dev *dev)
1149{ }
05cca6e5
GKH		 1150static inline void pci_disable_msix(struct pci_dev *dev)
1151{ }
1152
1153static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1154{ }
1155
1156static inline void pci_restore_msi_state(struct pci_dev *dev)
1157{ }
07ae95f9
AP		 1158static inline int pci_msi_enabled(void)
1159{
1160 return 0;
1161}
1da177e4 1162#else
f39d5b72
BH		 1163int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
1164int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec);
1165void pci_msi_shutdown(struct pci_dev *dev);
1166void pci_disable_msi(struct pci_dev *dev);
1167int pci_msix_table_size(struct pci_dev *dev);
1168int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec);
1169void pci_msix_shutdown(struct pci_dev *dev);
1170void pci_disable_msix(struct pci_dev *dev);
1171void msi_remove_pci_irq_vectors(struct pci_dev *dev);
1172void pci_restore_msi_state(struct pci_dev *dev);
1173int pci_msi_enabled(void);
1da177e4
LT		 1174#endif
1175
ab0724ff 1176#ifdef CONFIG_PCIEPORTBUS
415e12b2
RW		 1177extern bool pcie_ports_disabled;
1178extern bool pcie_ports_auto;
ab0724ff
MT		 1179#else
1180#define pcie_ports_disabled true
1181#define pcie_ports_auto false
1182#endif
415e12b2 1183
3e1b1600 1184#ifndef CONFIG_PCIEASPM
8b8bae90
RW		 1185static inline int pcie_aspm_enabled(void) { return 0; }
1186static inline bool pcie_aspm_support_enabled(void) { return false; }
3e1b1600 1187#else
f39d5b72
BH		 1188int pcie_aspm_enabled(void);
1189bool pcie_aspm_support_enabled(void);
3e1b1600
AP		 1190#endif
1191
415e12b2
RW		 1192#ifdef CONFIG_PCIEAER
1193void pci_no_aer(void);
1194bool pci_aer_available(void);
1195#else
1196static inline void pci_no_aer(void) { }
1197static inline bool pci_aer_available(void) { return false; }
1198#endif
1199
43c16408
AP		 1200#ifndef CONFIG_PCIE_ECRC
1201static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1202{
1203 return;
1204}
1205static inline void pcie_ecrc_get_policy(char *str) {};
1206#else
f39d5b72
BH		 1207void pcie_set_ecrc_checking(struct pci_dev *dev);
1208void pcie_ecrc_get_policy(char *str);
43c16408
AP		 1209#endif
1210
1c8d7b0a
MW		 1211#define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1212
8b955b0d 1213#ifdef CONFIG_HT_IRQ
8b955b0d
EB		 1214/* The functions a driver should call */
1215int ht_create_irq(struct pci_dev *dev, int idx);
1216void ht_destroy_irq(unsigned int irq);
8b955b0d
EB		 1217#endif /* CONFIG_HT_IRQ */
1218
f39d5b72
BH		 1219void pci_cfg_access_lock(struct pci_dev *dev);
1220bool pci_cfg_access_trylock(struct pci_dev *dev);
1221void pci_cfg_access_unlock(struct pci_dev *dev);
e04b0ea2 1222
4352dfd5
GKH		 1223/*
1224 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1225 * a PCI domain is defined to be a set of PCI busses which share
1226 * configuration space.
1227 */
32a2eea7
JG		 1228#ifdef CONFIG_PCI_DOMAINS
1229extern int pci_domains_supported;
1230#else
1231enum { pci_domains_supported = 0 };
05cca6e5
GKH		 1232static inline int pci_domain_nr(struct pci_bus *bus)
1233{
1234 return 0;
1235}
1236
4352dfd5
GKH		 1237static inline int pci_proc_domain(struct pci_bus *bus)
1238{
1239 return 0;
1240}
32a2eea7 1241#endif /* CONFIG_PCI_DOMAINS */
1da177e4 1242
95a8b6ef
MT		 1243/* some architectures require additional setup to direct VGA traffic */
1244typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
3448a19d 1245 unsigned int command_bits, u32 flags);
f39d5b72 1246void pci_register_set_vga_state(arch_set_vga_state_t func);
95a8b6ef 1247
4352dfd5 1248#else /* CONFIG_PCI is not enabled */
1da177e4
LT		 1249
1250/*
1251 * If the system does not have PCI, clearly these return errors. Define
1252 * these as simple inline functions to avoid hair in drivers.
1253 */
1254
05cca6e5
GKH		 1255#define _PCI_NOP(o, s, t) \
1256 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1257 int where, t val) \
1da177e4 1258 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
05cca6e5
GKH		 1259
1260#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1261 _PCI_NOP(o, word, u16 x) \
1262 _PCI_NOP(o, dword, u32 x)
1da177e4
LT		 1263_PCI_NOP_ALL(read, *)
1264_PCI_NOP_ALL(write,)
1265
d42552c3 1266static inline struct pci_dev *pci_get_device(unsigned int vendor,
05cca6e5
GKH		 1267 unsigned int device,
1268 struct pci_dev *from)
1269{
1270 return NULL;
1271}
d42552c3 1272
05cca6e5
GKH		 1273static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1274 unsigned int device,
1275 unsigned int ss_vendor,
1276 unsigned int ss_device,
b08508c4 1277 struct pci_dev *from)
05cca6e5
GKH		 1278{
1279 return NULL;
1280}
1da177e4 1281
05cca6e5
GKH		 1282static inline struct pci_dev *pci_get_class(unsigned int class,
1283 struct pci_dev *from)
1284{
1285 return NULL;
1286}
1da177e4
LT		 1287
1288#define pci_dev_present(ids) (0)
ed4aaadb 1289#define no_pci_devices() (1)
1da177e4
LT		 1290#define pci_dev_put(dev) do { } while (0)
1291
05cca6e5
GKH		 1292static inline void pci_set_master(struct pci_dev *dev)
1293{ }
1294
1295static inline int pci_enable_device(struct pci_dev *dev)
1296{
1297 return -EIO;
1298}
1299
1300static inline void pci_disable_device(struct pci_dev *dev)
1301{ }
1302
1303static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1304{
1305 return -EIO;
1306}
1307
80be0385
RD		 1308static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1309{
1310 return -EIO;
1311}
1312
4d57cdfa
FT		 1313static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1314 unsigned int size)
1315{
1316 return -EIO;
1317}
1318
59fc67de
FT		 1319static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1320 unsigned long mask)
1321{
1322 return -EIO;
1323}
1324
05cca6e5
GKH		 1325static inline int pci_assign_resource(struct pci_dev *dev, int i)
1326{
1327 return -EBUSY;
1328}
1329
1330static inline int __pci_register_driver(struct pci_driver *drv,
1331 struct module *owner)
1332{
1333 return 0;
1334}
1335
1336static inline int pci_register_driver(struct pci_driver *drv)
1337{
1338 return 0;
1339}
1340
1341static inline void pci_unregister_driver(struct pci_driver *drv)
1342{ }
1343
1344static inline int pci_find_capability(struct pci_dev *dev, int cap)
1345{
1346 return 0;
1347}
1348
1349static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1350 int cap)
1351{
1352 return 0;
1353}
1354
1355static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1356{
1357 return 0;
1358}
1359
1da177e4 1360/* Power management related routines */
05cca6e5
GKH		 1361static inline int pci_save_state(struct pci_dev *dev)
1362{
1363 return 0;
1364}
1365
1d3c16a8
JM		 1366static inline void pci_restore_state(struct pci_dev *dev)
1367{ }
1da177e4 1368
05cca6e5
GKH		 1369static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1370{
1371 return 0;
1372}
1373
3449248c
RD		 1374static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1375{
1376 return 0;
1377}
1378
05cca6e5
GKH		 1379static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1380 pm_message_t state)
1381{
1382 return PCI_D0;
1383}
1384
1385static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1386 int enable)
1387{
1388 return 0;
1389}
1390
b48d4425
JB		 1391static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1392{
1393}
1394
1395static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1396{
1397}
1398
48a92a81
JB		 1399static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type)
1400{
1401 return 0;
1402}
1403
1404static inline void pci_disable_obff(struct pci_dev *dev)
1405{
1406}
1407
05cca6e5
GKH		 1408static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1409{
1410 return -EIO;
1411}
1412
1413static inline void pci_release_regions(struct pci_dev *dev)
1414{ }
0da0ead9 1415
a46e8126
KG		 1416#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1417
fb51ccbf 1418static inline void pci_block_cfg_access(struct pci_dev *dev)
05cca6e5
GKH		 1419{ }
1420
fb51ccbf
JK		 1421static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1422{ return 0; }
1423
1424static inline void pci_unblock_cfg_access(struct pci_dev *dev)
05cca6e5 1425{ }
e04b0ea2 1426
d80d0217
RD		 1427static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1428{ return NULL; }
1429
1430static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1431 unsigned int devfn)
1432{ return NULL; }
1433
1434static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1435 unsigned int devfn)
1436{ return NULL; }
1437
92298e66
DA		 1438static inline int pci_domain_nr(struct pci_bus *bus)
1439{ return 0; }
1440
12ea6cad
AW		 1441static inline struct pci_dev *pci_dev_get(struct pci_dev *dev)
1442{ return NULL; }
1443
fb8a0d9d
WM		 1444#define dev_is_pci(d) (false)
1445#define dev_is_pf(d) (false)
1446#define dev_num_vf(d) (0)
4352dfd5 1447#endif /* CONFIG_PCI */
1da177e4 1448
4352dfd5
GKH		 1449/* Include architecture-dependent settings and functions */
1450
1451#include <asm/pci.h>
1da177e4 1452
1f82de10
YL		 1453#ifndef PCIBIOS_MAX_MEM_32
1454#define PCIBIOS_MAX_MEM_32 (-1)
1455#endif
1456
1da177e4
LT		 1457/* these helpers provide future and backwards compatibility
1458 * for accessing popular PCI BAR info */
05cca6e5
GKH		 1459#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1460#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1461#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1da177e4 1462#define pci_resource_len(dev,bar) \
05cca6e5
GKH		 1463 ((pci_resource_start((dev), (bar)) == 0 && \
1464 pci_resource_end((dev), (bar)) == \
1465 pci_resource_start((dev), (bar))) ? 0 : \
1466 \
1467 (pci_resource_end((dev), (bar)) - \
1468 pci_resource_start((dev), (bar)) + 1))
1da177e4
LT		 1469
1470/* Similar to the helpers above, these manipulate per-pci_dev
1471 * driver-specific data. They are really just a wrapper around
1472 * the generic device structure functions of these calls.
1473 */
05cca6e5 1474static inline void *pci_get_drvdata(struct pci_dev *pdev)
1da177e4
LT		 1475{
1476 return dev_get_drvdata(&pdev->dev);
1477}
1478
05cca6e5 1479static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1da177e4
LT		 1480{
1481 dev_set_drvdata(&pdev->dev, data);
1482}
1483
1484/* If you want to know what to call your pci_dev, ask this function.
1485 * Again, it's a wrapper around the generic device.
1486 */
2fc90f61 1487static inline const char *pci_name(const struct pci_dev *pdev)
1da177e4 1488{
c6c4f070 1489 return dev_name(&pdev->dev);
1da177e4
LT		 1490}
1491
2311b1f2
ME		 1492
1493/* Some archs don't want to expose struct resource to userland as-is
1494 * in sysfs and /proc
1495 */
1496#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1497static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
05cca6e5 1498 const struct resource *rsrc, resource_size_t *start,
e31dd6e4 1499 resource_size_t *end)
2311b1f2
ME		 1500{
1501 *start = rsrc->start;
1502 *end = rsrc->end;
1503}
1504#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1505
1506
1da177e4
LT		 1507/*
1508 * The world is not perfect and supplies us with broken PCI devices.
1509 * For at least a part of these bugs we need a work-around, so both
1510 * generic (drivers/pci/quirks.c) and per-architecture code can define
1511 * fixup hooks to be called for particular buggy devices.
1512 */
1513
1514struct pci_fixup {
f4ca5c6a
YL		 1515 u16 vendor; /* You can use PCI_ANY_ID here of course */
1516 u16 device; /* You can use PCI_ANY_ID here of course */
1517 u32 class; /* You can use PCI_ANY_ID here too */
1518 unsigned int class_shift; /* should be 0, 8, 16 */
1da177e4
LT		 1519 void (*hook)(struct pci_dev *dev);
1520};
1521
1522enum pci_fixup_pass {
1523 pci_fixup_early, /* Before probing BARs */
1524 pci_fixup_header, /* After reading configuration header */
1525 pci_fixup_final, /* Final phase of device fixups */
1526 pci_fixup_enable, /* pci_enable_device() time */
e1a2a51e
RW		 1527 pci_fixup_resume, /* pci_device_resume() */
1528 pci_fixup_suspend, /* pci_device_suspend */
1529 pci_fixup_resume_early, /* pci_device_resume_early() */
1da177e4
LT		 1530};
1531
1532/* Anonymous variables would be nice... */
f4ca5c6a
YL		 1533#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1534 class_shift, hook) \
769ae543 1535 static const struct pci_fixup __pci_fixup_##name __used \
f4ca5c6a
YL		 1536 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1537 = { vendor, device, class, class_shift, hook };
1538
1539#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1540 class_shift, hook) \
1541 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1542 vendor##device##hook, vendor, device, class, class_shift, hook)
1543#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1544 class_shift, hook) \
1545 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1546 vendor##device##hook, vendor, device, class, class_shift, hook)
1547#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1548 class_shift, hook) \
1549 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1550 vendor##device##hook, vendor, device, class, class_shift, hook)
1551#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1552 class_shift, hook) \
1553 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1554 vendor##device##hook, vendor, device, class, class_shift, hook)
1555#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1556 class_shift, hook) \
1557 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1558 resume##vendor##device##hook, vendor, device, class, \
1559 class_shift, hook)
1560#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1561 class_shift, hook) \
1562 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1563 resume_early##vendor##device##hook, vendor, device, \
1564 class, class_shift, hook)
1565#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1566 class_shift, hook) \
1567 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1568 suspend##vendor##device##hook, vendor, device, class, \
1569 class_shift, hook)
1570
1da177e4
LT		 1571#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1572 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
f4ca5c6a 1573 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1574#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1575 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
f4ca5c6a 1576 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1577#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1578 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
f4ca5c6a 1579 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1580#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1581 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
f4ca5c6a 1582 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1597cacb
AC		 1583#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1584 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
f4ca5c6a
YL		 1585 resume##vendor##device##hook, vendor, device, \
1586 PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1587#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1588 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
f4ca5c6a
YL		 1589 resume_early##vendor##device##hook, vendor, device, \
1590 PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1591#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1592 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
f4ca5c6a
YL		 1593 suspend##vendor##device##hook, vendor, device, \
1594 PCI_ANY_ID, 0, hook)
1da177e4 1595
93177a74 1596#ifdef CONFIG_PCI_QUIRKS
1da177e4 1597void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
12ea6cad 1598struct pci_dev *pci_get_dma_source(struct pci_dev *dev);
ad805758 1599int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
93177a74
RW		 1600#else
1601static inline void pci_fixup_device(enum pci_fixup_pass pass,
1602 struct pci_dev *dev) {}
12ea6cad
AW		 1603static inline struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
1604{
1605 return pci_dev_get(dev);
1606}
ad805758
AW		 1607static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1608 u16 acs_flags)
1609{
1610 return -ENOTTY;
1611}
93177a74 1612#endif
1da177e4 1613
05cca6e5 1614void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
5ea81769 1615void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
05cca6e5 1616void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
fb7ebfe4
YL		 1617int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1618int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
916fbfb7 1619 const char *name);
fb7ebfe4 1620void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
5ea81769 1621
1da177e4 1622extern int pci_pci_problems;
236561e5 1623#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1da177e4
LT		 1624#define PCIPCI_TRITON 2
1625#define PCIPCI_NATOMA 4
1626#define PCIPCI_VIAETBF 8
1627#define PCIPCI_VSFX 16
236561e5
AC		 1628#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1629#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1da177e4 1630
4516a618
AN		 1631extern unsigned long pci_cardbus_io_size;
1632extern unsigned long pci_cardbus_mem_size;
15856ad5 1633extern u8 pci_dfl_cache_line_size;
ac1aa47b 1634extern u8 pci_cache_line_size;
4516a618 1635
28760489
EB		 1636extern unsigned long pci_hotplug_io_size;
1637extern unsigned long pci_hotplug_mem_size;
1638
cfce9fb8 1639/* Architecture specific versions may override these (weak) */
19792a08
AB		 1640int pcibios_add_platform_entries(struct pci_dev *dev);
1641void pcibios_disable_device(struct pci_dev *dev);
cfce9fb8 1642void pcibios_set_master(struct pci_dev *dev);
19792a08
AB		 1643int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1644 enum pcie_reset_state state);
eca0d467 1645int pcibios_add_device(struct pci_dev *dev);
575e3348 1646
7752d5cf 1647#ifdef CONFIG_PCI_MMCONFIG
f39d5b72
BH		 1648void __init pci_mmcfg_early_init(void);
1649void __init pci_mmcfg_late_init(void);
7752d5cf 1650#else
bb63b421 1651static inline void pci_mmcfg_early_init(void) { }
7752d5cf
RH		 1652static inline void pci_mmcfg_late_init(void) { }
1653#endif
1654
642c92da 1655int pci_ext_cfg_avail(void);
0ef5f8f6 1656
1684f5dd 1657void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
aa42d7c6 1658
dd7cc44d 1659#ifdef CONFIG_PCI_IOV
f39d5b72
BH		 1660int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1661void pci_disable_sriov(struct pci_dev *dev);
1662irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1663int pci_num_vf(struct pci_dev *dev);
5a8eb242 1664int pci_vfs_assigned(struct pci_dev *dev);
f39d5b72
BH		 1665int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1666int pci_sriov_get_totalvfs(struct pci_dev *dev);
dd7cc44d
YZ		 1667#else
1668static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1669{
1670 return -ENODEV;
1671}
1672static inline void pci_disable_sriov(struct pci_dev *dev)
1673{
1674}
74bb1bcc
YZ		 1675static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1676{
1677 return IRQ_NONE;
1678}
fb8a0d9d
WM		 1679static inline int pci_num_vf(struct pci_dev *dev)
1680{
1681 return 0;
1682}
5a8eb242
AD		 1683static inline int pci_vfs_assigned(struct pci_dev *dev)
1684{
1685 return 0;
1686}
bff73156
DD		 1687static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1688{
1689 return 0;
1690}
1691static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1692{
1693 return 0;
1694}
dd7cc44d
YZ		 1695#endif
1696
c825bc94 1697#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
f39d5b72
BH		 1698void pci_hp_create_module_link(struct pci_slot *pci_slot);
1699void pci_hp_remove_module_link(struct pci_slot *pci_slot);
c825bc94
KK		 1700#endif
1701
d7b7e605
KK		 1702/**
1703 * pci_pcie_cap - get the saved PCIe capability offset
1704 * @dev: PCI device
1705 *
1706 * PCIe capability offset is calculated at PCI device initialization
1707 * time and saved in the data structure. This function returns saved
1708 * PCIe capability offset. Using this instead of pci_find_capability()
1709 * reduces unnecessary search in the PCI configuration space. If you
1710 * need to calculate PCIe capability offset from raw device for some
1711 * reasons, please use pci_find_capability() instead.
1712 */
1713static inline int pci_pcie_cap(struct pci_dev *dev)
1714{
1715 return dev->pcie_cap;
1716}
1717
7eb776c4
KK		 1718/**
1719 * pci_is_pcie - check if the PCI device is PCI Express capable
1720 * @dev: PCI device
1721 *
1722 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1723 */
1724static inline bool pci_is_pcie(struct pci_dev *dev)
1725{
1726 return !!pci_pcie_cap(dev);
1727}
1728
7c9c003c
MS		 1729/**
1730 * pcie_caps_reg - get the PCIe Capabilities Register
1731 * @dev: PCI device
1732 */
1733static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1734{
1735 return dev->pcie_flags_reg;
1736}
1737
786e2288
YW		 1738/**
1739 * pci_pcie_type - get the PCIe device/port type
1740 * @dev: PCI device
1741 */
1742static inline int pci_pcie_type(const struct pci_dev *dev)
1743{
1c531d82 1744 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
786e2288
YW		 1745}
1746
5d990b62 1747void pci_request_acs(void);
ad805758
AW		 1748bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1749bool pci_acs_path_enabled(struct pci_dev *start,
1750 struct pci_dev *end, u16 acs_flags);
a2ce7662 1751
7ad506fa
MC		 1752#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1753#define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1754
1755/* Large Resource Data Type Tag Item Names */
1756#define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1757#define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1758#define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1759
1760#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1761#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1762#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1763
1764/* Small Resource Data Type Tag Item Names */
1765#define PCI_VPD_STIN_END 0x78 /* End */
1766
1767#define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1768
1769#define PCI_VPD_SRDT_TIN_MASK 0x78
1770#define PCI_VPD_SRDT_LEN_MASK 0x07
1771
1772#define PCI_VPD_LRDT_TAG_SIZE 3
1773#define PCI_VPD_SRDT_TAG_SIZE 1
a2ce7662 1774
e1d5bdab
MC		 1775#define PCI_VPD_INFO_FLD_HDR_SIZE 3
1776
4067a854
MC		 1777#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1778#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1779#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
d4894f3e 1780#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
4067a854 1781
a2ce7662
MC		 1782/**
1783 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1784 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1785 *
1786 * Returns the extracted Large Resource Data Type length.
1787 */
1788static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1789{
1790 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1791}
1792
7ad506fa
MC		 1793/**
1794 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1795 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1796 *
1797 * Returns the extracted Small Resource Data Type length.
1798 */
1799static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1800{
1801 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1802}
1803
e1d5bdab
MC		 1804/**
1805 * pci_vpd_info_field_size - Extracts the information field length
1806 * @lrdt: Pointer to the beginning of an information field header
1807 *
1808 * Returns the extracted information field length.
1809 */
1810static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1811{
1812 return info_field[2];
1813}
1814
b55ac1b2
MC		 1815/**
1816 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1817 * @buf: Pointer to buffered vpd data
1818 * @off: The offset into the buffer at which to begin the search
1819 * @len: The length of the vpd buffer
1820 * @rdt: The Resource Data Type to search for
1821 *
1822 * Returns the index where the Resource Data Type was found or
1823 * -ENOENT otherwise.
1824 */
1825int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1826
4067a854
MC		 1827/**
1828 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1829 * @buf: Pointer to buffered vpd data
1830 * @off: The offset into the buffer at which to begin the search
1831 * @len: The length of the buffer area, relative to off, in which to search
1832 * @kw: The keyword to search for
1833 *
1834 * Returns the index where the information field keyword was found or
1835 * -ENOENT otherwise.
1836 */
1837int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1838 unsigned int len, const char *kw);
1839
98d9f30c
BH		 1840/* PCI <-> OF binding helpers */
1841#ifdef CONFIG_OF
1842struct device_node;
f39d5b72
BH		 1843void pci_set_of_node(struct pci_dev *dev);
1844void pci_release_of_node(struct pci_dev *dev);
1845void pci_set_bus_of_node(struct pci_bus *bus);
1846void pci_release_bus_of_node(struct pci_bus *bus);
98d9f30c
BH		 1847
1848/* Arch may override this (weak) */
723ec4d0 1849struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
98d9f30c 1850
3df425f3
JC		 1851static inline struct device_node *
1852pci_device_to_OF_node(const struct pci_dev *pdev)
64099d98
BH		 1853{
1854 return pdev ? pdev->dev.of_node : NULL;
1855}
1856
ef3b4f8c
BH		 1857static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1858{
1859 return bus ? bus->dev.of_node : NULL;
1860}
1861
98d9f30c
BH		 1862#else /* CONFIG_OF */
1863static inline void pci_set_of_node(struct pci_dev *dev) { }
1864static inline void pci_release_of_node(struct pci_dev *dev) { }
1865static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1866static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1867#endif /* CONFIG_OF */
1868
eb740b5f
GS		 1869#ifdef CONFIG_EEH
1870static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1871{
1872 return pdev->dev.archdata.edev;
1873}
1874#endif
1875
166e9278
OBC		 1876/**
1877 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1878 * @pdev: the PCI device
1879 *
1880 * if the device is PCIE, return NULL
1881 * if the device isn't connected to a PCIe bridge (that is its parent is a
1882 * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1883 * parent
1884 */
1885struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1886
1da177e4 1887#endif /* LINUX_PCI_H */
kernel source for telekom puls (alcatel/mediatek)