[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / nvme.h

/*
 * Definitions for the NVM Express interface
 * Copyright (c) 2011, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 
 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 */

#ifndef _LINUX_NVME_H
#define _LINUX_NVME_H

#include <linux/types.h>

struct nvme_bar {
	__u64			cap;	/* Controller Capabilities */
	__u32			vs;	/* Version */
	__u32			ims;	/* Interrupt Mask Set */
	__u32			imc;	/* Interrupt Mask Clear */
	__u32			cc;	/* Controller Configuration */
	__u32			csts;	/* Controller Status */
	__u32			aqa;	/* Admin Queue Attributes */
	__u64			asq;	/* Admin SQ Base Address */
	__u64			acq;	/* Admin CQ Base Address */
};

enum {
	NVME_CC_ENABLE		= 1 << 0,
	NVME_CC_CSS_NVM		= 0 << 4,
	NVME_CC_MPS_SHIFT	= 7,
	NVME_CC_ARB_RR		= 0 << 11,
	NVME_CC_ARB_WRRU	= 1 << 11,
	NVME_CC_ARB_VS		= 3 << 11,
	NVME_CC_SHN_NONE	= 0 << 13,
	NVME_CC_SHN_NORMAL	= 1 << 13,
	NVME_CC_SHN_ABRUPT	= 2 << 13,
	NVME_CSTS_RDY		= 1 << 0,
	NVME_CSTS_CFS		= 1 << 1,
	NVME_CSTS_SHST_NORMAL	= 0 << 2,
	NVME_CSTS_SHST_OCCUR	= 1 << 2,
	NVME_CSTS_SHST_CMPLT	= 2 << 2,
};

#define NVME_VS(major, minor)	(major << 16 | minor)

struct nvme_id_ctrl {
	__le16			vid;
	__le16			ssvid;
	char			sn[20];
	char			mn[40];
	char			fr[8];
	__le32			nn;
	__u8			rab;
	__u8			rsvd77[178];
	__le16			oacs;
	__u8			acl;
	__u8			aerl;
	__u8			frmw;
	__u8			lpa;
	__u8			elpe;
	__u8			npss;
	__u8			rsvd264[248];
	__le64			psd[32];
	__le16			oncs;
	__le16			fuses;
	__u8			fna;
	__u8			vwc;
	__le16			awun;
	__le16			awupf;
	__u8			rsvd778[246];
	__u8			cmdset[2048];
	__u8			vs[1024];
};

struct nvme_lbaf {
	__le16			ms;
	__u8			ds;
	__u8			rp;
};

struct nvme_id_ns {
	__le64			nsze;
	__le64			ncap;
	__le64			nuse;
	__u8			nsfeat;
	__u8			nlbaf;
	__u8			flbas;
	__u8			mc;
	__u8			dpc;
	__u8			dps;
	__u8			rsvd30[98];
	struct nvme_lbaf	lbaf[16];
	__u8			rsvd192[192];
	__u8			vs[3712];
};

enum {
	NVME_NS_FEAT_THIN	= 1 << 0,
	NVME_LBAF_RP_BEST	= 0,
	NVME_LBAF_RP_BETTER	= 1,
	NVME_LBAF_RP_GOOD	= 2,
	NVME_LBAF_RP_DEGRADED	= 3,
};

struct nvme_lba_range_type {
	__u8			type;
	__u8			attributes;
	__u8			rsvd2[14];
	__u64			slba;
	__u64			nlb;
	__u8			guid[16];
	__u8			rsvd48[16];
};

enum {
	NVME_LBART_TYPE_FS	= 0x01,
	NVME_LBART_TYPE_RAID	= 0x02,
	NVME_LBART_TYPE_CACHE	= 0x03,
	NVME_LBART_TYPE_SWAP	= 0x04,

	NVME_LBART_ATTRIB_TEMP	= 1 << 0,
	NVME_LBART_ATTRIB_HIDE	= 1 << 1,
};

/* I/O commands */

enum nvme_opcode {
	nvme_cmd_flush		= 0x00,
	nvme_cmd_write		= 0x01,
	nvme_cmd_read		= 0x02,
	nvme_cmd_write_uncor	= 0x04,
	nvme_cmd_compare	= 0x05,
	nvme_cmd_dsm		= 0x09,
};

struct nvme_common_command {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			nsid;
	__u64			rsvd2;
	__le64			metadata;
	__le64			prp1;
	__le64			prp2;
	__u32			rsvd10[6];
};

struct nvme_rw_command {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			nsid;
	__u64			rsvd2;
	__le64			metadata;
	__le64			prp1;
	__le64			prp2;
	__le64			slba;
	__le16			length;
	__le16			control;
	__le32			dsmgmt;
	__le32			reftag;
	__le16			apptag;
	__le16			appmask;
};

enum {
	NVME_RW_LR			= 1 << 15,
	NVME_RW_FUA			= 1 << 14,
	NVME_RW_DSM_FREQ_UNSPEC		= 0,
	NVME_RW_DSM_FREQ_TYPICAL	= 1,
	NVME_RW_DSM_FREQ_RARE		= 2,
	NVME_RW_DSM_FREQ_READS		= 3,
	NVME_RW_DSM_FREQ_WRITES		= 4,
	NVME_RW_DSM_FREQ_RW		= 5,
	NVME_RW_DSM_FREQ_ONCE		= 6,
	NVME_RW_DSM_FREQ_PREFETCH	= 7,
	NVME_RW_DSM_FREQ_TEMP		= 8,
	NVME_RW_DSM_LATENCY_NONE	= 0 << 4,
	NVME_RW_DSM_LATENCY_IDLE	= 1 << 4,
	NVME_RW_DSM_LATENCY_NORM	= 2 << 4,
	NVME_RW_DSM_LATENCY_LOW		= 3 << 4,
	NVME_RW_DSM_SEQ_REQ		= 1 << 6,
	NVME_RW_DSM_COMPRESSED		= 1 << 7,
};

/* Admin commands */

enum nvme_admin_opcode {
	nvme_admin_delete_sq		= 0x00,
	nvme_admin_create_sq		= 0x01,
	nvme_admin_get_features		= 0x02,
	nvme_admin_delete_cq		= 0x04,
	nvme_admin_create_cq		= 0x05,
	nvme_admin_identify		= 0x06,
	nvme_admin_abort_cmd		= 0x08,
	nvme_admin_set_features		= 0x09,
	nvme_admin_get_log_page		= 0x0a,
	nvme_admin_async_event		= 0x0c,
	nvme_admin_download_fw		= 0x0d,
	nvme_admin_security_recv	= 0x0e,
	nvme_admin_format_nvm		= 0x10,
	nvme_admin_security_send	= 0x11,
	nvme_admin_activate_fw		= 0x14,
};

enum {
	NVME_QUEUE_PHYS_CONTIG	= (1 << 0),
	NVME_CQ_IRQ_ENABLED	= (1 << 1),
	NVME_SQ_PRIO_URGENT	= (0 << 1),
	NVME_SQ_PRIO_HIGH	= (1 << 1),
	NVME_SQ_PRIO_MEDIUM	= (2 << 1),
	NVME_SQ_PRIO_LOW	= (3 << 1),
	NVME_FEAT_ARBITRATION	= 0x01,
	NVME_FEAT_POWER_MGMT	= 0x02,
	NVME_FEAT_LBA_RANGE	= 0x03,
	NVME_FEAT_TEMP_THRESH	= 0x04,
	NVME_FEAT_ERR_RECOVERY	= 0x05,
	NVME_FEAT_VOLATILE_WC	= 0x06,
	NVME_FEAT_NUM_QUEUES	= 0x07,
	NVME_FEAT_IRQ_COALESCE	= 0x08,
	NVME_FEAT_IRQ_CONFIG	= 0x09,
	NVME_FEAT_WRITE_ATOMIC	= 0x0a,
	NVME_FEAT_ASYNC_EVENT	= 0x0b,
	NVME_FEAT_SW_PROGRESS	= 0x0c,
};

struct nvme_identify {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			nsid;
	__u64			rsvd2[2];
	__le64			prp1;
	__le64			prp2;
	__le32			cns;
	__u32			rsvd11[5];
};

struct nvme_features {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			nsid;
	__u64			rsvd2[2];
	__le64			prp1;
	__le64			prp2;
	__le32			fid;
	__le32			dword11;
	__u32			rsvd12[4];
};

struct nvme_create_cq {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			rsvd1[5];
	__le64			prp1;
	__u64			rsvd8;
	__le16			cqid;
	__le16			qsize;
	__le16			cq_flags;
	__le16			irq_vector;
	__u32			rsvd12[4];
};

struct nvme_create_sq {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			rsvd1[5];
	__le64			prp1;
	__u64			rsvd8;
	__le16			sqid;
	__le16			qsize;
	__le16			sq_flags;
	__le16			cqid;
	__le32			rsvd12[4];
};

struct nvme_delete_queue {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__u32			rsvd1[9];
	__le16			qid;
	__le16			rsvd10;
	__le32			rsvd11[5];
};

struct nvme_command {
	union {
		struct nvme_common_command common;
		struct nvme_rw_command rw;
		struct nvme_identify identify;
		struct nvme_features features;
		struct nvme_create_cq create_cq;
		struct nvme_create_sq create_sq;
		struct nvme_delete_queue delete_queue;
	};
};

/* XXX: Sync with spec */
enum {
	NVME_SC_SUCCESS			= 0x0,
	NVME_SC_INVALID_OPCODE		= 0x1,
	NVME_SC_INVALID_FIELD		= 0x2,
	NVME_SC_CMDID_CONFLICT		= 0x3,
	NVME_SC_DATA_XFER_ERROR		= 0x4,
	NVME_SC_POWER_LOSS		= 0x5,
	NVME_SC_INTERNAL		= 0x6,
	NVME_SC_ABORT_REQ		= 0x7,
	NVME_SC_ABORT_QUEUE		= 0x8,
	NVME_SC_FUSED_FAIL		= 0x9,
	NVME_SC_FUSED_MISSING		= 0xa,
	NVME_SC_INVALID_NS		= 0xb,
	NVME_SC_LBA_RANGE		= 0x80,
	NVME_SC_CAP_EXCEEDED		= 0x81,
	NVME_SC_NS_NOT_READY		= 0x82,
	NVME_SC_CQ_INVALID		= 0x100,
	NVME_SC_QID_INVALID		= 0x101,
	NVME_SC_QUEUE_SIZE		= 0x102,
	NVME_SC_ABORT_LIMIT		= 0x103,
	NVME_SC_ABORT_MISSING		= 0x104,
	NVME_SC_ASYNC_LIMIT		= 0x105,
	NVME_SC_FIRMWARE_SLOT		= 0x106,
	NVME_SC_FIRMWARE_IMAGE		= 0x107,
	NVME_SC_INVALID_VECTOR		= 0x108,
	NVME_SC_INVALID_LOG_PAGE	= 0x109,
	NVME_SC_INVALID_FORMAT		= 0x10a,
	NVME_SC_BAD_ATTRIBUTES		= 0x180,
	NVME_SC_WRITE_FAULT		= 0x280,
	NVME_SC_READ_ERROR		= 0x281,
	NVME_SC_GUARD_CHECK		= 0x282,
	NVME_SC_APPTAG_CHECK		= 0x283,
	NVME_SC_REFTAG_CHECK		= 0x284,
	NVME_SC_COMPARE_FAILED		= 0x285,
	NVME_SC_ACCESS_DENIED		= 0x286,
};

struct nvme_completion {
	__le32	result;		/* Used by admin commands to return data */
	__le32	rsvd;
	__le16	sq_head;	/* how much of this queue may be reclaimed */
	__le16	sq_id;		/* submission queue that generated this entry */
	__u16	command_id;	/* of the command which completed */
	__le16	status;		/* did the command fail, and if so, why? */
};

struct nvme_user_io {
	__u8	opcode;
	__u8	flags;
	__u16	control;
	__u32	nsid;
	__u64	metadata;
	__u64	addr;
	__u64	slba;
	__u16	nblocks;
	__u16	block_shift;
	__u32	dsmgmt;
	__u32	reftag;
	__u16	apptag;
	__u16	appmask;
	__u32	result;
};

#define NVME_IOCTL_IDENTIFY_NS	_IOW('N', 0x40, struct nvme_id_ns)
#define NVME_IOCTL_IDENTIFY_CTRL _IOW('N', 0x41, struct nvme_id_ctrl)
#define NVME_IOCTL_GET_RANGE_TYPE _IOW('N', 0x42, struct nvme_lba_range_type)
#define NVME_IOCTL_SUBMIT_IO	_IOWR('N', 0x43, struct nvme_rw_command)

#endif /* _LINUX_NVME_H */
Commit	Line	Data
b60503ba MW	1	/*
	2	* Definitions for the NVM Express interface
	3	* Copyright (c) 2011, Intel Corporation.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc.,
	16	* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	17	*/
	18
	19	#ifndef _LINUX_NVME_H
	20	#define _LINUX_NVME_H
	21
	22	#include <linux/types.h>
	23
	24	struct nvme_bar {
	25	__u64 cap; /* Controller Capabilities */
	26	__u32 vs; /* Version */
	27	__u32 ims; /* Interrupt Mask Set */
	28	__u32 imc; /* Interrupt Mask Clear */
	29	__u32 cc; /* Controller Configuration */
	30	__u32 csts; /* Controller Status */
	31	__u32 aqa; /* Admin Queue Attributes */
	32	__u64 asq; /* Admin SQ Base Address */
	33	__u64 acq; /* Admin CQ Base Address */
	34	};
	35
	36	enum {
	37	NVME_CC_ENABLE = 1 << 0,
	38	NVME_CC_CSS_NVM = 0 << 4,
	39	NVME_CC_MPS_SHIFT = 7,
	40	NVME_CC_ARB_RR = 0 << 11,
	41	NVME_CC_ARB_WRRU = 1 << 11,
	42	NVME_CC_ARB_VS = 3 << 11,
	43	NVME_CC_SHN_NONE = 0 << 13,
	44	NVME_CC_SHN_NORMAL = 1 << 13,
	45	NVME_CC_SHN_ABRUPT = 2 << 13,
	46	NVME_CSTS_RDY = 1 << 0,
	47	NVME_CSTS_CFS = 1 << 1,
	48	NVME_CSTS_SHST_NORMAL = 0 << 2,
	49	NVME_CSTS_SHST_OCCUR = 1 << 2,
	50	NVME_CSTS_SHST_CMPLT = 2 << 2,
	51	};
	52
	53	#define NVME_VS(major, minor) (major << 16 \| minor)
	54
	55	struct nvme_id_ctrl {
	56	__le16 vid;
	57	__le16 ssvid;
	58	char sn[20];
	59	char mn[40];
	60	char fr[8];
	61	__le32 nn;
	62	__u8 rab;
	63	__u8 rsvd77[178];
	64	__le16 oacs;
65	__u8 acl;
66	__u8 aerl;
67	__u8 frmw;
68	__u8 lpa;
69	__u8 elpe;
70	__u8 npss;
71	__u8 rsvd264[248];
72	__le64 psd[32];
73	__le16 oncs;
74	__le16 fuses;
75	__u8 fna;
76	__u8 vwc;
77	__le16 awun;
78	__le16 awupf;
79	__u8 rsvd778[246];
80	__u8 cmdset[2048];
81	__u8 vs[1024];
82	};
83
84	struct nvme_lbaf {
85	__le16 ms;
86	__u8 ds;
87	__u8 rp;
88	};
89
90	struct nvme_id_ns {
91	__le64 nsze;
92	__le64 ncap;
93	__le64 nuse;
94	__u8 nsfeat;
95	__u8 nlbaf;
96	__u8 flbas;
97	__u8 mc;
98	__u8 dpc;
99	__u8 dps;
100	__u8 rsvd30[98];
101	struct nvme_lbaf lbaf[16];
102	__u8 rsvd192[192];
103	__u8 vs[3712];
104	};
105
106	enum {
107	NVME_NS_FEAT_THIN = 1 << 0,
108	NVME_LBAF_RP_BEST = 0,
109	NVME_LBAF_RP_BETTER = 1,
110	NVME_LBAF_RP_GOOD = 2,
111	NVME_LBAF_RP_DEGRADED = 3,
112	};
113
114	struct nvme_lba_range_type {
115	__u8 type;
116	__u8 attributes;
117	__u8 rsvd2[14];
118	__u64 slba;
119	__u64 nlb;
120	__u8 guid[16];
121	__u8 rsvd48[16];
122	};
123
124	enum {
125	NVME_LBART_TYPE_FS = 0x01,
126	NVME_LBART_TYPE_RAID = 0x02,
127	NVME_LBART_TYPE_CACHE = 0x03,
128	NVME_LBART_TYPE_SWAP = 0x04,
129
130	NVME_LBART_ATTRIB_TEMP = 1 << 0,
131	NVME_LBART_ATTRIB_HIDE = 1 << 1,
132	};
133
134	/* I/O commands */
135
136	enum nvme_opcode {
137	nvme_cmd_flush = 0x00,
138	nvme_cmd_write = 0x01,
139	nvme_cmd_read = 0x02,
140	nvme_cmd_write_uncor = 0x04,
141	nvme_cmd_compare = 0x05,
142	nvme_cmd_dsm = 0x09,
143	};
144
7b4fe9b1 MW	145	struct nvme_common_command {
	146	__u8 opcode;
	147	__u8 flags;
	148	__u16 command_id;
	149	__le32 nsid;
	150	__u64 rsvd2;
	151	__le64 metadata;
	152	__le64 prp1;
	153	__le64 prp2;
	154	__u32 rsvd10[6];
	155	};
	156
b60503ba MW	157	struct nvme_rw_command {
	158	__u8 opcode;
	159	__u8 flags;
	160	__u16 command_id;
	161	__le32 nsid;
	162	__u64 rsvd2;
	163	__le64 metadata;
	164	__le64 prp1;
	165	__le64 prp2;
	166	__le64 slba;
	167	__le16 length;
	168	__le16 control;
	169	__le32 dsmgmt;
	170	__le32 reftag;
	171	__le16 apptag;
	172	__le16 appmask;
	173	};
	174
	175	enum {
	176	NVME_RW_LR = 1 << 15,
	177	NVME_RW_FUA = 1 << 14,
	178	NVME_RW_DSM_FREQ_UNSPEC = 0,
	179	NVME_RW_DSM_FREQ_TYPICAL = 1,
	180	NVME_RW_DSM_FREQ_RARE = 2,
	181	NVME_RW_DSM_FREQ_READS = 3,
	182	NVME_RW_DSM_FREQ_WRITES = 4,
	183	NVME_RW_DSM_FREQ_RW = 5,
	184	NVME_RW_DSM_FREQ_ONCE = 6,
	185	NVME_RW_DSM_FREQ_PREFETCH = 7,
	186	NVME_RW_DSM_FREQ_TEMP = 8,
	187	NVME_RW_DSM_LATENCY_NONE = 0 << 4,
	188	NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
	189	NVME_RW_DSM_LATENCY_NORM = 2 << 4,
	190	NVME_RW_DSM_LATENCY_LOW = 3 << 4,
	191	NVME_RW_DSM_SEQ_REQ = 1 << 6,
	192	NVME_RW_DSM_COMPRESSED = 1 << 7,
	193	};
	194
	195	/* Admin commands */
	196
	197	enum nvme_admin_opcode {
	198	nvme_admin_delete_sq = 0x00,
	199	nvme_admin_create_sq = 0x01,
	200	nvme_admin_get_features = 0x02,
	201	nvme_admin_delete_cq = 0x04,
	202	nvme_admin_create_cq = 0x05,
	203	nvme_admin_identify = 0x06,
	204	nvme_admin_abort_cmd = 0x08,
	205	nvme_admin_set_features = 0x09,
	206	nvme_admin_get_log_page = 0x0a,
	207	nvme_admin_async_event = 0x0c,
	208	nvme_admin_download_fw = 0x0d,
	209	nvme_admin_security_recv = 0x0e,
	210	nvme_admin_format_nvm = 0x10,
	211	nvme_admin_security_send = 0x11,
	212	nvme_admin_activate_fw = 0x14,
	213	};
	214
	215	enum {
	216	NVME_QUEUE_PHYS_CONTIG = (1 << 0),
	217	NVME_CQ_IRQ_ENABLED = (1 << 1),
	218	NVME_SQ_PRIO_URGENT = (0 << 1),
	219	NVME_SQ_PRIO_HIGH = (1 << 1),
	220	NVME_SQ_PRIO_MEDIUM = (2 << 1),
221	NVME_SQ_PRIO_LOW = (3 << 1),
222	NVME_FEAT_ARBITRATION = 0x01,
223	NVME_FEAT_POWER_MGMT = 0x02,
224	NVME_FEAT_LBA_RANGE = 0x03,
225	NVME_FEAT_TEMP_THRESH = 0x04,
226	NVME_FEAT_ERR_RECOVERY = 0x05,
227	NVME_FEAT_VOLATILE_WC = 0x06,
228	NVME_FEAT_NUM_QUEUES = 0x07,
229	NVME_FEAT_IRQ_COALESCE = 0x08,
230	NVME_FEAT_IRQ_CONFIG = 0x09,
231	NVME_FEAT_WRITE_ATOMIC = 0x0a,
232	NVME_FEAT_ASYNC_EVENT = 0x0b,
233	NVME_FEAT_SW_PROGRESS = 0x0c,
234	};
235
236	struct nvme_identify {
237	__u8 opcode;
238	__u8 flags;
239	__u16 command_id;
240	__le32 nsid;
241	__u64 rsvd2[2];
242	__le64 prp1;
243	__le64 prp2;
244	__le32 cns;
245	__u32 rsvd11[5];
246	};
247
248	struct nvme_features {
249	__u8 opcode;
250	__u8 flags;
251	__u16 command_id;
252	__le32 nsid;
253	__u64 rsvd2[2];
254	__le64 prp1;
255	__le64 prp2;
256	__le32 fid;
257	__le32 dword11;
258	__u32 rsvd12[4];
259	};
260
261	struct nvme_create_cq {
262	__u8 opcode;
263	__u8 flags;
264	__u16 command_id;
265	__le32 rsvd1[5];
266	__le64 prp1;
267	__u64 rsvd8;
268	__le16 cqid;
269	__le16 qsize;
270	__le16 cq_flags;
271	__le16 irq_vector;
272	__u32 rsvd12[4];
273	};
274
275	struct nvme_create_sq {
276	__u8 opcode;
277	__u8 flags;
278	__u16 command_id;
279	__le32 rsvd1[5];
280	__le64 prp1;
281	__u64 rsvd8;
282	__le16 sqid;
283	__le16 qsize;
284	__le16 sq_flags;
285	__le16 cqid;
286	__le32 rsvd12[4];
287	};
288
289	struct nvme_delete_queue {
290	__u8 opcode;
291	__u8 flags;
292	__u16 command_id;
293	__u32 rsvd1[9];
294	__le16 qid;
295	__le16 rsvd10;
296	__le32 rsvd11[5];
297	};
298
b60503ba MW	299	struct nvme_command {
	300	union {
	301	struct nvme_common_command common;
	302	struct nvme_rw_command rw;
	303	struct nvme_identify identify;
	304	struct nvme_features features;
	305	struct nvme_create_cq create_cq;
	306	struct nvme_create_sq create_sq;
	307	struct nvme_delete_queue delete_queue;
	308	};
	309	};
	310
	311	/* XXX: Sync with spec */
	312	enum {
	313	NVME_SC_SUCCESS = 0x0,
	314	NVME_SC_INVALID_OPCODE = 0x1,
	315	NVME_SC_INVALID_FIELD = 0x2,
	316	NVME_SC_CMDID_CONFLICT = 0x3,
	317	NVME_SC_DATA_XFER_ERROR = 0x4,
	318	NVME_SC_POWER_LOSS = 0x5,
	319	NVME_SC_INTERNAL = 0x6,
	320	NVME_SC_ABORT_REQ = 0x7,
	321	NVME_SC_ABORT_QUEUE = 0x8,
	322	NVME_SC_FUSED_FAIL = 0x9,
	323	NVME_SC_FUSED_MISSING = 0xa,
7a63e07b	324	NVME_SC_INVALID_NS = 0xb,
b60503ba MW	325	NVME_SC_LBA_RANGE = 0x80,
	326	NVME_SC_CAP_EXCEEDED = 0x81,
	327	NVME_SC_NS_NOT_READY = 0x82,
	328	NVME_SC_CQ_INVALID = 0x100,
	329	NVME_SC_QID_INVALID = 0x101,
	330	NVME_SC_QUEUE_SIZE = 0x102,
7a63e07b MW	331	NVME_SC_ABORT_LIMIT = 0x103,
	332	NVME_SC_ABORT_MISSING = 0x104,
	333	NVME_SC_ASYNC_LIMIT = 0x105,
	334	NVME_SC_FIRMWARE_SLOT = 0x106,
	335	NVME_SC_FIRMWARE_IMAGE = 0x107,
	336	NVME_SC_INVALID_VECTOR = 0x108,
	337	NVME_SC_INVALID_LOG_PAGE = 0x109,
	338	NVME_SC_INVALID_FORMAT = 0x10a,
	339	NVME_SC_BAD_ATTRIBUTES = 0x180,
b60503ba MW	340	NVME_SC_WRITE_FAULT = 0x280,
b60503ba MW	341	NVME_SC_READ_ERROR = 0x281,
7a63e07b MW	342	NVME_SC_GUARD_CHECK = 0x282,
	343	NVME_SC_APPTAG_CHECK = 0x283,
	344	NVME_SC_REFTAG_CHECK = 0x284,
	345	NVME_SC_COMPARE_FAILED = 0x285,
	346	NVME_SC_ACCESS_DENIED = 0x286,
b60503ba MW	347	};
	348
	349	struct nvme_completion {
	350	__le32 result; /* Used by admin commands to return data */
	351	__le32 rsvd;
	352	__le16 sq_head; /* how much of this queue may be reclaimed */
	353	__le16 sq_id; /* submission queue that generated this entry */
	354	__u16 command_id; /* of the command which completed */
	355	__le16 status; /* did the command fail, and if so, why? */
	356	};
	357
a53295b6 MW	358	struct nvme_user_io {
	359	__u8 opcode;
	360	__u8 flags;
	361	__u16 control;
	362	__u32 nsid;
	363	__u64 metadata;
	364	__u64 addr;
	365	__u64 slba;
	366	__u16 nblocks;
	367	__u16 block_shift;
	368	__u32 dsmgmt;
	369	__u32 reftag;
	370	__u16 apptag;
	371	__u16 appmask;
	372	__u32 result;
	373	};
	374
b60503ba MW	375	#define NVME_IOCTL_IDENTIFY_NS _IOW('N', 0x40, struct nvme_id_ns)
	376	#define NVME_IOCTL_IDENTIFY_CTRL _IOW('N', 0x41, struct nvme_id_ctrl)
	377	#define NVME_IOCTL_GET_RANGE_TYPE _IOW('N', 0x42, struct nvme_lba_range_type)
a53295b6	378	#define NVME_IOCTL_SUBMIT_IO _IOWR('N', 0x43, struct nvme_rw_command)
b60503ba MW	379
b60503ba MW	380	#endif /* _LINUX_NVME_H */