[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / mmc / sh_mmcif.h

/*
 * include/linux/mmc/sh_mmcif.h
 *
 * platform data for eMMC driver
 *
 * Copyright (C) 2010 Renesas Solutions Corp.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
 *
 */

#ifndef LINUX_MMC_SH_MMCIF_H
#define LINUX_MMC_SH_MMCIF_H

#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/sh_dma.h>

/*
 * MMCIF : CE_CLK_CTRL [19:16]
 * 1000 : Peripheral clock / 512
 * 0111 : Peripheral clock / 256
 * 0110 : Peripheral clock / 128
 * 0101 : Peripheral clock / 64
 * 0100 : Peripheral clock / 32
 * 0011 : Peripheral clock / 16
 * 0010 : Peripheral clock / 8
 * 0001 : Peripheral clock / 4
 * 0000 : Peripheral clock / 2
 * 1111 : Peripheral clock (sup_pclk set '1')
 */

struct sh_mmcif_plat_data {
	void (*set_pwr)(struct platform_device *pdev, int state);
	void (*down_pwr)(struct platform_device *pdev);
	int (*get_cd)(struct platform_device *pdef);
	unsigned int		slave_id_tx;	/* embedded slave_id_[tr]x */
	unsigned int		slave_id_rx;
	bool			use_cd_gpio : 1;
	unsigned int		cd_gpio;
	u8			sup_pclk;	/* 1 :SH7757, 0: SH7724/SH7372 */
	unsigned long		caps;
	u32			ocr;
};

#define MMCIF_CE_CMD_SET	0x00000000
#define MMCIF_CE_ARG		0x00000008
#define MMCIF_CE_ARG_CMD12	0x0000000C
#define MMCIF_CE_CMD_CTRL	0x00000010
#define MMCIF_CE_BLOCK_SET	0x00000014
#define MMCIF_CE_CLK_CTRL	0x00000018
#define MMCIF_CE_BUF_ACC	0x0000001C
#define MMCIF_CE_RESP3		0x00000020
#define MMCIF_CE_RESP2		0x00000024
#define MMCIF_CE_RESP1		0x00000028
#define MMCIF_CE_RESP0		0x0000002C
#define MMCIF_CE_RESP_CMD12	0x00000030
#define MMCIF_CE_DATA		0x00000034
#define MMCIF_CE_INT		0x00000040
#define MMCIF_CE_INT_MASK	0x00000044
#define MMCIF_CE_HOST_STS1	0x00000048
#define MMCIF_CE_HOST_STS2	0x0000004C
#define MMCIF_CE_VERSION	0x0000007C

/* CE_BUF_ACC */
#define BUF_ACC_DMAWEN		(1 << 25)
#define BUF_ACC_DMAREN		(1 << 24)
#define BUF_ACC_BUSW_32		(0 << 17)
#define BUF_ACC_BUSW_16		(1 << 17)
#define BUF_ACC_ATYP		(1 << 16)

/* CE_CLK_CTRL */
#define CLK_ENABLE		(1 << 24) /* 1: output mmc clock */
#define CLK_CLEAR		(0xf << 16)
#define CLK_SUP_PCLK		(0xf << 16)
#define CLKDIV_4		(1 << 16) /* mmc clock frequency.
					   * n: bus clock/(2^(n+1)) */
#define CLKDIV_256		(7 << 16) /* mmc clock frequency. (see above) */
#define SRSPTO_256		(2 << 12) /* resp timeout */
#define SRBSYTO_29		(0xf << 8) /* resp busy timeout */
#define SRWDTO_29		(0xf << 4) /* read/write timeout */
#define SCCSTO_29		(0xf << 0) /* ccs timeout */

/* CE_VERSION */
#define SOFT_RST_ON		(1 << 31)
#define SOFT_RST_OFF		0

static inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
{
	return __raw_readl(addr + reg);
}

static inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val)
{
	__raw_writel(val, addr + reg);
}

#define SH_MMCIF_BBS 512 /* boot block size */

static inline void sh_mmcif_boot_cmd_send(void __iomem *base,
					  unsigned long cmd, unsigned long arg)
{
	sh_mmcif_writel(base, MMCIF_CE_INT, 0);
	sh_mmcif_writel(base, MMCIF_CE_ARG, arg);
	sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd);
}

static inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask)
{
	unsigned long tmp;
	int cnt;

	for (cnt = 0; cnt < 1000000; cnt++) {
		tmp = sh_mmcif_readl(base, MMCIF_CE_INT);
		if (tmp & mask) {
			sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask);
			return 0;
		}
	}

	return -1;
}

static inline int sh_mmcif_boot_cmd(void __iomem *base,
				    unsigned long cmd, unsigned long arg)
{
	sh_mmcif_boot_cmd_send(base, cmd, arg);
	return sh_mmcif_boot_cmd_poll(base, 0x00010000);
}

static inline int sh_mmcif_boot_do_read_single(void __iomem *base,
					       unsigned int block_nr,
					       unsigned long *buf)
{
	int k;

	/* CMD13 - Status */
	sh_mmcif_boot_cmd(base, 0x0d400000, 0x00010000);

	if (sh_mmcif_readl(base, MMCIF_CE_RESP0) != 0x0900)
		return -1;

	/* CMD17 - Read */
	sh_mmcif_boot_cmd(base, 0x11480000, block_nr * SH_MMCIF_BBS);
	if (sh_mmcif_boot_cmd_poll(base, 0x00100000) < 0)
		return -1;

	for (k = 0; k < (SH_MMCIF_BBS / 4); k++)
		buf[k] = sh_mmcif_readl(base, MMCIF_CE_DATA);

	return 0;
}

static inline int sh_mmcif_boot_do_read(void __iomem *base,
					unsigned long first_block,
					unsigned long nr_blocks,
					void *buf)
{
	unsigned long k;
	int ret = 0;

	/* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
	sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
			CLK_ENABLE | CLKDIV_4 | SRSPTO_256 |
			SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);

	/* CMD9 - Get CSD */
	sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);

	/* CMD7 - Select the card */
	sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000);

	/* CMD16 - Set the block size */
	sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS);

	for (k = 0; !ret && k < nr_blocks; k++)
		ret = sh_mmcif_boot_do_read_single(base, first_block + k,
						   buf + (k * SH_MMCIF_BBS));

	return ret;
}

static inline void sh_mmcif_boot_init(void __iomem *base)
{
	/* reset */
	sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_ON);
	sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_OFF);

	/* byte swap */
	sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);

	/* Set block size in MMCIF hardware */
	sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);

	/* Enable the clock, set it to Bus clock/256 (about 325Khz). */
	sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
			CLK_ENABLE | CLKDIV_256 | SRSPTO_256 |
			SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);

	/* CMD0 */
	sh_mmcif_boot_cmd(base, 0x00000040, 0);

	/* CMD1 - Get OCR */
	do {
		sh_mmcif_boot_cmd(base, 0x01405040, 0x40300000); /* CMD1 */
	} while ((sh_mmcif_readl(base, MMCIF_CE_RESP0) & 0x80000000)
		 != 0x80000000);

	/* CMD2 - Get CID */
	sh_mmcif_boot_cmd(base, 0x02806040, 0);

	/* CMD3 - Set card relative address */
	sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000);
}

#endif /* LINUX_MMC_SH_MMCIF_H */
Commit	Line	Data
fdc50a94 YG	1	/*
	2	* include/linux/mmc/sh_mmcif.h
	3	*
	4	* platform data for eMMC driver
	5	*
	6	* Copyright (C) 2010 Renesas Solutions Corp.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License.
	11	*
	12	*/
	13
100e9186 RD	14	#ifndef LINUX_MMC_SH_MMCIF_H
100e9186 RD	15	#define LINUX_MMC_SH_MMCIF_H
fdc50a94	16
487d9fc5	17	#include <linux/io.h>
a782d688 GL	18	#include <linux/platform_device.h>
a782d688 GL	19	#include <linux/sh_dma.h>
487d9fc5	20
fdc50a94 YG	21	/*
	22	* MMCIF : CE_CLK_CTRL [19:16]
	23	* 1000 : Peripheral clock / 512
	24	* 0111 : Peripheral clock / 256
	25	* 0110 : Peripheral clock / 128
	26	* 0101 : Peripheral clock / 64
	27	* 0100 : Peripheral clock / 32
	28	* 0011 : Peripheral clock / 16
	29	* 0010 : Peripheral clock / 8
	30	* 0001 : Peripheral clock / 4
	31	* 0000 : Peripheral clock / 2
	32	* 1111 : Peripheral clock (sup_pclk set '1')
	33	*/
	34
	35	struct sh_mmcif_plat_data {
	36	void (set_pwr)(struct platform_device pdev, int state);
	37	void (down_pwr)(struct platform_device pdev);
777271d0	38	int (get_cd)(struct platform_device pdef);
916001fe	39	unsigned int slave_id_tx; /* embedded slave_id_[tr]x */
714c4a6e	40	unsigned int slave_id_rx;
e480606a GL	41	bool use_cd_gpio : 1;
e480606a GL	42	unsigned int cd_gpio;
a782d688 GL	43	u8 sup_pclk; /* 1 :SH7757, 0: SH7724/SH7372 */
	44	unsigned long caps;
	45	u32 ocr;
fdc50a94 YG	46	};
fdc50a94 YG	47
487d9fc5 MD	48	#define MMCIF_CE_CMD_SET 0x00000000
	49	#define MMCIF_CE_ARG 0x00000008
	50	#define MMCIF_CE_ARG_CMD12 0x0000000C
	51	#define MMCIF_CE_CMD_CTRL 0x00000010
	52	#define MMCIF_CE_BLOCK_SET 0x00000014
	53	#define MMCIF_CE_CLK_CTRL 0x00000018
	54	#define MMCIF_CE_BUF_ACC 0x0000001C
	55	#define MMCIF_CE_RESP3 0x00000020
	56	#define MMCIF_CE_RESP2 0x00000024
	57	#define MMCIF_CE_RESP1 0x00000028
	58	#define MMCIF_CE_RESP0 0x0000002C
	59	#define MMCIF_CE_RESP_CMD12 0x00000030
	60	#define MMCIF_CE_DATA 0x00000034
	61	#define MMCIF_CE_INT 0x00000040
	62	#define MMCIF_CE_INT_MASK 0x00000044
	63	#define MMCIF_CE_HOST_STS1 0x00000048
	64	#define MMCIF_CE_HOST_STS2 0x0000004C
	65	#define MMCIF_CE_VERSION 0x0000007C
	66
da1d39e3 SH	67	/* CE_BUF_ACC */
	68	#define BUF_ACC_DMAWEN (1 << 25)
	69	#define BUF_ACC_DMAREN (1 << 24)
	70	#define BUF_ACC_BUSW_32 (0 << 17)
	71	#define BUF_ACC_BUSW_16 (1 << 17)
	72	#define BUF_ACC_ATYP (1 << 16)
	73
	74	/* CE_CLK_CTRL */
	75	#define CLK_ENABLE (1 << 24) /* 1: output mmc clock */
135111cc GL	76	#define CLK_CLEAR (0xf << 16)
	77	#define CLK_SUP_PCLK (0xf << 16)
	78	#define CLKDIV_4 (1 << 16) /* mmc clock frequency.
	79	* n: bus clock/(2^(n+1)) */
	80	#define CLKDIV_256 (7 << 16) /* mmc clock frequency. (see above) */
	81	#define SRSPTO_256 (2 << 12) /* resp timeout */
	82	#define SRBSYTO_29 (0xf << 8) /* resp busy timeout */
	83	#define SRWDTO_29 (0xf << 4) /* read/write timeout */
	84	#define SCCSTO_29 (0xf << 0) /* ccs timeout */
da1d39e3 SH	85
	86	/* CE_VERSION */
	87	#define SOFT_RST_ON (1 << 31)
1ae0affe	88	#define SOFT_RST_OFF 0
da1d39e3	89
2f6ba579	90	static inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
487d9fc5	91	{
bba95878	92	return __raw_readl(addr + reg);
487d9fc5 MD	93	}
487d9fc5 MD	94
2f6ba579	95	static inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val)
487d9fc5	96	{
bba95878	97	__raw_writel(val, addr + reg);
487d9fc5 MD	98	}
487d9fc5 MD	99
8a768952 MD	100	#define SH_MMCIF_BBS 512 /* boot block size */
8a768952 MD	101
2f6ba579	102	static inline void sh_mmcif_boot_cmd_send(void __iomem *base,
8a768952 MD	103	unsigned long cmd, unsigned long arg)
	104	{
	105	sh_mmcif_writel(base, MMCIF_CE_INT, 0);
	106	sh_mmcif_writel(base, MMCIF_CE_ARG, arg);
	107	sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd);
	108	}
	109
2f6ba579	110	static inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask)
8a768952 MD	111	{
	112	unsigned long tmp;
	113	int cnt;
	114
	115	for (cnt = 0; cnt < 1000000; cnt++) {
	116	tmp = sh_mmcif_readl(base, MMCIF_CE_INT);
	117	if (tmp & mask) {
	118	sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask);
	119	return 0;
	120	}
	121	}
	122
	123	return -1;
	124	}
	125
2f6ba579	126	static inline int sh_mmcif_boot_cmd(void __iomem *base,
8a768952 MD	127	unsigned long cmd, unsigned long arg)
	128	{
	129	sh_mmcif_boot_cmd_send(base, cmd, arg);
	130	return sh_mmcif_boot_cmd_poll(base, 0x00010000);
	131	}
	132
2f6ba579	133	static inline int sh_mmcif_boot_do_read_single(void __iomem *base,
8a768952 MD	134	unsigned int block_nr,
	135	unsigned long *buf)
	136	{
	137	int k;
	138
	139	/* CMD13 - Status */
	140	sh_mmcif_boot_cmd(base, 0x0d400000, 0x00010000);
	141
	142	if (sh_mmcif_readl(base, MMCIF_CE_RESP0) != 0x0900)
	143	return -1;
	144
	145	/* CMD17 - Read */
	146	sh_mmcif_boot_cmd(base, 0x11480000, block_nr * SH_MMCIF_BBS);
	147	if (sh_mmcif_boot_cmd_poll(base, 0x00100000) < 0)
	148	return -1;
	149
	150	for (k = 0; k < (SH_MMCIF_BBS / 4); k++)
	151	buf[k] = sh_mmcif_readl(base, MMCIF_CE_DATA);
	152
	153	return 0;
	154	}
	155
2f6ba579	156	static inline int sh_mmcif_boot_do_read(void __iomem *base,
8a768952 MD	157	unsigned long first_block,
	158	unsigned long nr_blocks,
	159	void *buf)
	160	{
	161	unsigned long k;
	162	int ret = 0;
	163
54b38463 SH	164	/* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
	165	sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
	166	CLK_ENABLE \| CLKDIV_4 \| SRSPTO_256 \|
	167	SRBSYTO_29 \| SRWDTO_29 \| SCCSTO_29);
	168
	169	/* CMD9 - Get CSD */
	170	sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);
	171
	172	/* CMD7 - Select the card */
	173	sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000);
	174
8a768952 MD	175	/* CMD16 - Set the block size */
	176	sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS);
	177
	178	for (k = 0; !ret && k < nr_blocks; k++)
	179	ret = sh_mmcif_boot_do_read_single(base, first_block + k,
	180	buf + (k * SH_MMCIF_BBS));
	181
	182	return ret;
	183	}
	184
2f6ba579	185	static inline void sh_mmcif_boot_init(void __iomem *base)
8a768952	186	{
8a768952	187	/* reset */
1ae0affe SH	188	sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_ON);
1ae0affe SH	189	sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_OFF);
8a768952 MD	190
8a768952 MD	191	/* byte swap */
da1d39e3	192	sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
8a768952 MD	193
	194	/* Set block size in MMCIF hardware */
	195	sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);
	196
22efa0fe	197	/* Enable the clock, set it to Bus clock/256 (about 325Khz). */
da1d39e3	198	sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
22efa0fe SH	199	CLK_ENABLE \| CLKDIV_256 \| SRSPTO_256 \|
22efa0fe SH	200	SRBSYTO_29 \| SRWDTO_29 \| SCCSTO_29);
8a768952 MD	201
	202	/* CMD0 */
	203	sh_mmcif_boot_cmd(base, 0x00000040, 0);
	204
	205	/* CMD1 - Get OCR */
	206	do {
	207	sh_mmcif_boot_cmd(base, 0x01405040, 0x40300000); /* CMD1 */
	208	} while ((sh_mmcif_readl(base, MMCIF_CE_RESP0) & 0x80000000)
	209	!= 0x80000000);
	210
	211	/* CMD2 - Get CID */
	212	sh_mmcif_boot_cmd(base, 0x02806040, 0);
	213
	214	/* CMD3 - Set card relative address */
	215	sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000);
	216	}
	217
100e9186	218	#endif /* LINUX_MMC_SH_MMCIF_H */