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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX4_DEVICE_H | |
34 | #define MLX4_DEVICE_H | |
35 | ||
36 | #include <linux/pci.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/radix-tree.h> | |
39 | ||
60063497 | 40 | #include <linux/atomic.h> |
225c7b1f | 41 | |
0b7ca5a9 YP |
42 | #define MAX_MSIX_P_PORT 17 |
43 | #define MAX_MSIX 64 | |
44 | #define MSIX_LEGACY_SZ 4 | |
45 | #define MIN_MSIX_P_PORT 5 | |
46 | ||
225c7b1f RD |
47 | enum { |
48 | MLX4_FLAG_MSI_X = 1 << 0, | |
5ae2a7a8 | 49 | MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, |
225c7b1f RD |
50 | }; |
51 | ||
52 | enum { | |
53 | MLX4_MAX_PORTS = 2 | |
54 | }; | |
55 | ||
cd9281d8 JM |
56 | enum { |
57 | MLX4_BOARD_ID_LEN = 64 | |
58 | }; | |
59 | ||
225c7b1f | 60 | enum { |
52eafc68 OG |
61 | MLX4_DEV_CAP_FLAG_RC = 1LL << 0, |
62 | MLX4_DEV_CAP_FLAG_UC = 1LL << 1, | |
63 | MLX4_DEV_CAP_FLAG_UD = 1LL << 2, | |
012a8ff5 | 64 | MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, |
52eafc68 OG |
65 | MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, |
66 | MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, | |
67 | MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, | |
68 | MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, | |
69 | MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, | |
70 | MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, | |
71 | MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, | |
72 | MLX4_DEV_CAP_FLAG_APM = 1LL << 17, | |
73 | MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, | |
74 | MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, | |
75 | MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, | |
76 | MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, | |
ccf86321 OG |
77 | MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, |
78 | MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, | |
79 | MLX4_DEV_CAP_FLAG_WOL = 1LL << 38, | |
80 | MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, | |
81 | MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, | |
f2a3f6a3 OG |
82 | MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, |
83 | MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48 | |
225c7b1f RD |
84 | }; |
85 | ||
95d04f07 RD |
86 | enum { |
87 | MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, | |
88 | MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, | |
89 | MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, | |
90 | MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, | |
91 | MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, | |
92 | }; | |
93 | ||
225c7b1f RD |
94 | enum mlx4_event { |
95 | MLX4_EVENT_TYPE_COMP = 0x00, | |
96 | MLX4_EVENT_TYPE_PATH_MIG = 0x01, | |
97 | MLX4_EVENT_TYPE_COMM_EST = 0x02, | |
98 | MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, | |
99 | MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, | |
100 | MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, | |
101 | MLX4_EVENT_TYPE_CQ_ERROR = 0x04, | |
102 | MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, | |
103 | MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, | |
104 | MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, | |
105 | MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, | |
106 | MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, | |
107 | MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, | |
108 | MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, | |
109 | MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, | |
110 | MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, | |
111 | MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, | |
112 | MLX4_EVENT_TYPE_CMD = 0x0a | |
113 | }; | |
114 | ||
115 | enum { | |
116 | MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, | |
117 | MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 | |
118 | }; | |
119 | ||
120 | enum { | |
121 | MLX4_PERM_LOCAL_READ = 1 << 10, | |
122 | MLX4_PERM_LOCAL_WRITE = 1 << 11, | |
123 | MLX4_PERM_REMOTE_READ = 1 << 12, | |
124 | MLX4_PERM_REMOTE_WRITE = 1 << 13, | |
125 | MLX4_PERM_ATOMIC = 1 << 14 | |
126 | }; | |
127 | ||
128 | enum { | |
129 | MLX4_OPCODE_NOP = 0x00, | |
130 | MLX4_OPCODE_SEND_INVAL = 0x01, | |
131 | MLX4_OPCODE_RDMA_WRITE = 0x08, | |
132 | MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, | |
133 | MLX4_OPCODE_SEND = 0x0a, | |
134 | MLX4_OPCODE_SEND_IMM = 0x0b, | |
135 | MLX4_OPCODE_LSO = 0x0e, | |
136 | MLX4_OPCODE_RDMA_READ = 0x10, | |
137 | MLX4_OPCODE_ATOMIC_CS = 0x11, | |
138 | MLX4_OPCODE_ATOMIC_FA = 0x12, | |
6fa8f719 VS |
139 | MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, |
140 | MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, | |
225c7b1f RD |
141 | MLX4_OPCODE_BIND_MW = 0x18, |
142 | MLX4_OPCODE_FMR = 0x19, | |
143 | MLX4_OPCODE_LOCAL_INVAL = 0x1b, | |
144 | MLX4_OPCODE_CONFIG_CMD = 0x1f, | |
145 | ||
146 | MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, | |
147 | MLX4_RECV_OPCODE_SEND = 0x01, | |
148 | MLX4_RECV_OPCODE_SEND_IMM = 0x02, | |
149 | MLX4_RECV_OPCODE_SEND_INVAL = 0x03, | |
150 | ||
151 | MLX4_CQE_OPCODE_ERROR = 0x1e, | |
152 | MLX4_CQE_OPCODE_RESIZE = 0x16, | |
153 | }; | |
154 | ||
155 | enum { | |
156 | MLX4_STAT_RATE_OFFSET = 5 | |
157 | }; | |
158 | ||
da995a8a | 159 | enum mlx4_protocol { |
0345584e YP |
160 | MLX4_PROT_IB_IPV6 = 0, |
161 | MLX4_PROT_ETH, | |
162 | MLX4_PROT_IB_IPV4, | |
163 | MLX4_PROT_FCOE | |
da995a8a AS |
164 | }; |
165 | ||
29bdc883 VS |
166 | enum { |
167 | MLX4_MTT_FLAG_PRESENT = 1 | |
168 | }; | |
169 | ||
93fc9e1b YP |
170 | enum mlx4_qp_region { |
171 | MLX4_QP_REGION_FW = 0, | |
172 | MLX4_QP_REGION_ETH_ADDR, | |
173 | MLX4_QP_REGION_FC_ADDR, | |
174 | MLX4_QP_REGION_FC_EXCH, | |
175 | MLX4_NUM_QP_REGION | |
176 | }; | |
177 | ||
7ff93f8b | 178 | enum mlx4_port_type { |
27bf91d6 YP |
179 | MLX4_PORT_TYPE_IB = 1, |
180 | MLX4_PORT_TYPE_ETH = 2, | |
181 | MLX4_PORT_TYPE_AUTO = 3 | |
7ff93f8b YP |
182 | }; |
183 | ||
2a2336f8 YP |
184 | enum mlx4_special_vlan_idx { |
185 | MLX4_NO_VLAN_IDX = 0, | |
186 | MLX4_VLAN_MISS_IDX, | |
187 | MLX4_VLAN_REGULAR | |
188 | }; | |
189 | ||
0345584e YP |
190 | enum mlx4_steer_type { |
191 | MLX4_MC_STEER = 0, | |
192 | MLX4_UC_STEER, | |
193 | MLX4_NUM_STEERS | |
194 | }; | |
195 | ||
93fc9e1b YP |
196 | enum { |
197 | MLX4_NUM_FEXCH = 64 * 1024, | |
198 | }; | |
199 | ||
5a0fd094 EC |
200 | enum { |
201 | MLX4_MAX_FAST_REG_PAGES = 511, | |
202 | }; | |
203 | ||
ea54b10c JM |
204 | static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) |
205 | { | |
206 | return (major << 32) | (minor << 16) | subminor; | |
207 | } | |
208 | ||
225c7b1f RD |
209 | struct mlx4_caps { |
210 | u64 fw_ver; | |
211 | int num_ports; | |
5ae2a7a8 | 212 | int vl_cap[MLX4_MAX_PORTS + 1]; |
b79acb49 | 213 | int ib_mtu_cap[MLX4_MAX_PORTS + 1]; |
9a5aa622 | 214 | __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; |
b79acb49 YP |
215 | u64 def_mac[MLX4_MAX_PORTS + 1]; |
216 | int eth_mtu_cap[MLX4_MAX_PORTS + 1]; | |
5ae2a7a8 RD |
217 | int gid_table_len[MLX4_MAX_PORTS + 1]; |
218 | int pkey_table_len[MLX4_MAX_PORTS + 1]; | |
7699517d YP |
219 | int trans_type[MLX4_MAX_PORTS + 1]; |
220 | int vendor_oui[MLX4_MAX_PORTS + 1]; | |
221 | int wavelength[MLX4_MAX_PORTS + 1]; | |
222 | u64 trans_code[MLX4_MAX_PORTS + 1]; | |
225c7b1f RD |
223 | int local_ca_ack_delay; |
224 | int num_uars; | |
225 | int bf_reg_size; | |
226 | int bf_regs_per_page; | |
227 | int max_sq_sg; | |
228 | int max_rq_sg; | |
229 | int num_qps; | |
230 | int max_wqes; | |
231 | int max_sq_desc_sz; | |
232 | int max_rq_desc_sz; | |
233 | int max_qp_init_rdma; | |
234 | int max_qp_dest_rdma; | |
225c7b1f RD |
235 | int sqp_start; |
236 | int num_srqs; | |
237 | int max_srq_wqes; | |
238 | int max_srq_sge; | |
239 | int reserved_srqs; | |
240 | int num_cqs; | |
241 | int max_cqes; | |
242 | int reserved_cqs; | |
243 | int num_eqs; | |
244 | int reserved_eqs; | |
b8dd786f | 245 | int num_comp_vectors; |
0b7ca5a9 | 246 | int comp_pool; |
225c7b1f RD |
247 | int num_mpts; |
248 | int num_mtt_segs; | |
ab6bf42e | 249 | int mtts_per_seg; |
225c7b1f RD |
250 | int fmr_reserved_mtts; |
251 | int reserved_mtts; | |
252 | int reserved_mrws; | |
253 | int reserved_uars; | |
254 | int num_mgms; | |
255 | int num_amgms; | |
256 | int reserved_mcgs; | |
257 | int num_qp_per_mgm; | |
258 | int num_pds; | |
259 | int reserved_pds; | |
012a8ff5 SH |
260 | int max_xrcds; |
261 | int reserved_xrcds; | |
225c7b1f | 262 | int mtt_entry_sz; |
149983af | 263 | u32 max_msg_sz; |
225c7b1f | 264 | u32 page_size_cap; |
52eafc68 | 265 | u64 flags; |
95d04f07 RD |
266 | u32 bmme_flags; |
267 | u32 reserved_lkey; | |
225c7b1f | 268 | u16 stat_rate_support; |
5ae2a7a8 | 269 | u8 port_width_cap[MLX4_MAX_PORTS + 1]; |
b832be1e | 270 | int max_gso_sz; |
93fc9e1b YP |
271 | int reserved_qps_cnt[MLX4_NUM_QP_REGION]; |
272 | int reserved_qps; | |
273 | int reserved_qps_base[MLX4_NUM_QP_REGION]; | |
274 | int log_num_macs; | |
275 | int log_num_vlans; | |
276 | int log_num_prios; | |
7ff93f8b YP |
277 | enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; |
278 | u8 supported_type[MLX4_MAX_PORTS + 1]; | |
279 | u32 port_mask; | |
27bf91d6 | 280 | enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; |
f2a3f6a3 | 281 | u32 max_counters; |
225c7b1f RD |
282 | }; |
283 | ||
284 | struct mlx4_buf_list { | |
285 | void *buf; | |
286 | dma_addr_t map; | |
287 | }; | |
288 | ||
289 | struct mlx4_buf { | |
b57aacfa RD |
290 | struct mlx4_buf_list direct; |
291 | struct mlx4_buf_list *page_list; | |
225c7b1f RD |
292 | int nbufs; |
293 | int npages; | |
294 | int page_shift; | |
295 | }; | |
296 | ||
297 | struct mlx4_mtt { | |
298 | u32 first_seg; | |
299 | int order; | |
300 | int page_shift; | |
301 | }; | |
302 | ||
6296883c YP |
303 | enum { |
304 | MLX4_DB_PER_PAGE = PAGE_SIZE / 4 | |
305 | }; | |
306 | ||
307 | struct mlx4_db_pgdir { | |
308 | struct list_head list; | |
309 | DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); | |
310 | DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); | |
311 | unsigned long *bits[2]; | |
312 | __be32 *db_page; | |
313 | dma_addr_t db_dma; | |
314 | }; | |
315 | ||
316 | struct mlx4_ib_user_db_page; | |
317 | ||
318 | struct mlx4_db { | |
319 | __be32 *db; | |
320 | union { | |
321 | struct mlx4_db_pgdir *pgdir; | |
322 | struct mlx4_ib_user_db_page *user_page; | |
323 | } u; | |
324 | dma_addr_t dma; | |
325 | int index; | |
326 | int order; | |
327 | }; | |
328 | ||
38ae6a53 YP |
329 | struct mlx4_hwq_resources { |
330 | struct mlx4_db db; | |
331 | struct mlx4_mtt mtt; | |
332 | struct mlx4_buf buf; | |
333 | }; | |
334 | ||
225c7b1f RD |
335 | struct mlx4_mr { |
336 | struct mlx4_mtt mtt; | |
337 | u64 iova; | |
338 | u64 size; | |
339 | u32 key; | |
340 | u32 pd; | |
341 | u32 access; | |
342 | int enabled; | |
343 | }; | |
344 | ||
8ad11fb6 JM |
345 | struct mlx4_fmr { |
346 | struct mlx4_mr mr; | |
347 | struct mlx4_mpt_entry *mpt; | |
348 | __be64 *mtts; | |
349 | dma_addr_t dma_handle; | |
350 | int max_pages; | |
351 | int max_maps; | |
352 | int maps; | |
353 | u8 page_shift; | |
354 | }; | |
355 | ||
225c7b1f RD |
356 | struct mlx4_uar { |
357 | unsigned long pfn; | |
358 | int index; | |
c1b43dca EC |
359 | struct list_head bf_list; |
360 | unsigned free_bf_bmap; | |
361 | void __iomem *map; | |
362 | void __iomem *bf_map; | |
363 | }; | |
364 | ||
365 | struct mlx4_bf { | |
366 | unsigned long offset; | |
367 | int buf_size; | |
368 | struct mlx4_uar *uar; | |
369 | void __iomem *reg; | |
225c7b1f RD |
370 | }; |
371 | ||
372 | struct mlx4_cq { | |
373 | void (*comp) (struct mlx4_cq *); | |
374 | void (*event) (struct mlx4_cq *, enum mlx4_event); | |
375 | ||
376 | struct mlx4_uar *uar; | |
377 | ||
378 | u32 cons_index; | |
379 | ||
380 | __be32 *set_ci_db; | |
381 | __be32 *arm_db; | |
382 | int arm_sn; | |
383 | ||
384 | int cqn; | |
b8dd786f | 385 | unsigned vector; |
225c7b1f RD |
386 | |
387 | atomic_t refcount; | |
388 | struct completion free; | |
389 | }; | |
390 | ||
391 | struct mlx4_qp { | |
392 | void (*event) (struct mlx4_qp *, enum mlx4_event); | |
393 | ||
394 | int qpn; | |
395 | ||
396 | atomic_t refcount; | |
397 | struct completion free; | |
398 | }; | |
399 | ||
400 | struct mlx4_srq { | |
401 | void (*event) (struct mlx4_srq *, enum mlx4_event); | |
402 | ||
403 | int srqn; | |
404 | int max; | |
405 | int max_gs; | |
406 | int wqe_shift; | |
407 | ||
408 | atomic_t refcount; | |
409 | struct completion free; | |
410 | }; | |
411 | ||
412 | struct mlx4_av { | |
413 | __be32 port_pd; | |
414 | u8 reserved1; | |
415 | u8 g_slid; | |
416 | __be16 dlid; | |
417 | u8 reserved2; | |
418 | u8 gid_index; | |
419 | u8 stat_rate; | |
420 | u8 hop_limit; | |
421 | __be32 sl_tclass_flowlabel; | |
422 | u8 dgid[16]; | |
423 | }; | |
424 | ||
fa417f7b EC |
425 | struct mlx4_eth_av { |
426 | __be32 port_pd; | |
427 | u8 reserved1; | |
428 | u8 smac_idx; | |
429 | u16 reserved2; | |
430 | u8 reserved3; | |
431 | u8 gid_index; | |
432 | u8 stat_rate; | |
433 | u8 hop_limit; | |
434 | __be32 sl_tclass_flowlabel; | |
435 | u8 dgid[16]; | |
436 | u32 reserved4[2]; | |
437 | __be16 vlan; | |
438 | u8 mac[6]; | |
439 | }; | |
440 | ||
441 | union mlx4_ext_av { | |
442 | struct mlx4_av ib; | |
443 | struct mlx4_eth_av eth; | |
444 | }; | |
445 | ||
f2a3f6a3 OG |
446 | struct mlx4_counter { |
447 | u8 reserved1[3]; | |
448 | u8 counter_mode; | |
449 | __be32 num_ifc; | |
450 | u32 reserved2[2]; | |
451 | __be64 rx_frames; | |
452 | __be64 rx_bytes; | |
453 | __be64 tx_frames; | |
454 | __be64 tx_bytes; | |
455 | }; | |
456 | ||
225c7b1f RD |
457 | struct mlx4_dev { |
458 | struct pci_dev *pdev; | |
459 | unsigned long flags; | |
460 | struct mlx4_caps caps; | |
461 | struct radix_tree_root qp_table_tree; | |
725c8999 | 462 | u8 rev_id; |
cd9281d8 | 463 | char board_id[MLX4_BOARD_ID_LEN]; |
225c7b1f RD |
464 | }; |
465 | ||
466 | struct mlx4_init_port_param { | |
467 | int set_guid0; | |
468 | int set_node_guid; | |
469 | int set_si_guid; | |
470 | u16 mtu; | |
471 | int port_width_cap; | |
472 | u16 vl_cap; | |
473 | u16 max_gid; | |
474 | u16 max_pkey; | |
475 | u64 guid0; | |
476 | u64 node_guid; | |
477 | u64 si_guid; | |
478 | }; | |
479 | ||
7ff93f8b YP |
480 | #define mlx4_foreach_port(port, dev, type) \ |
481 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
482 | if (((type) == MLX4_PORT_TYPE_IB ? (dev)->caps.port_mask : \ | |
483 | ~(dev)->caps.port_mask) & 1 << ((port) - 1)) | |
484 | ||
fa417f7b EC |
485 | #define mlx4_foreach_ib_transport_port(port, dev) \ |
486 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
487 | if (((dev)->caps.port_mask & 1 << ((port) - 1)) || \ | |
488 | ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) | |
489 | ||
490 | ||
225c7b1f RD |
491 | int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, |
492 | struct mlx4_buf *buf); | |
493 | void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); | |
1c69fc2a RD |
494 | static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) |
495 | { | |
313abe55 | 496 | if (BITS_PER_LONG == 64 || buf->nbufs == 1) |
b57aacfa | 497 | return buf->direct.buf + offset; |
1c69fc2a | 498 | else |
b57aacfa | 499 | return buf->page_list[offset >> PAGE_SHIFT].buf + |
1c69fc2a RD |
500 | (offset & (PAGE_SIZE - 1)); |
501 | } | |
225c7b1f RD |
502 | |
503 | int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); | |
504 | void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); | |
012a8ff5 SH |
505 | int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); |
506 | void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); | |
225c7b1f RD |
507 | |
508 | int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); | |
509 | void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); | |
c1b43dca EC |
510 | int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf); |
511 | void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); | |
225c7b1f RD |
512 | |
513 | int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, | |
514 | struct mlx4_mtt *mtt); | |
515 | void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); | |
516 | u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); | |
517 | ||
518 | int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, | |
519 | int npages, int page_shift, struct mlx4_mr *mr); | |
520 | void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); | |
521 | int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); | |
522 | int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, | |
523 | int start_index, int npages, u64 *page_list); | |
524 | int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, | |
525 | struct mlx4_buf *buf); | |
526 | ||
6296883c YP |
527 | int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order); |
528 | void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); | |
529 | ||
38ae6a53 YP |
530 | int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, |
531 | int size, int max_direct); | |
532 | void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, | |
533 | int size); | |
534 | ||
225c7b1f | 535 | int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, |
e463c7b1 | 536 | struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, |
b8dd786f | 537 | unsigned vector, int collapsed); |
225c7b1f RD |
538 | void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); |
539 | ||
a3cdcbfa YP |
540 | int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base); |
541 | void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); | |
542 | ||
543 | int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp); | |
225c7b1f RD |
544 | void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); |
545 | ||
546 | int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt, | |
547 | u64 db_rec, struct mlx4_srq *srq); | |
548 | void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); | |
549 | int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); | |
65541cb7 | 550 | int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); |
225c7b1f | 551 | |
5ae2a7a8 | 552 | int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); |
225c7b1f RD |
553 | int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); |
554 | ||
521e575b | 555 | int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
da995a8a AS |
556 | int block_mcast_loopback, enum mlx4_protocol protocol); |
557 | int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], | |
558 | enum mlx4_protocol protocol); | |
1679200f YP |
559 | int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); |
560 | int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); | |
561 | int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); | |
562 | int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); | |
563 | int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); | |
564 | ||
565 | int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn, u8 wrap); | |
566 | void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int qpn); | |
567 | int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac, u8 wrap); | |
2a2336f8 | 568 | |
4c3eb3ca | 569 | int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); |
2a2336f8 YP |
570 | int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); |
571 | void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index); | |
572 | ||
8ad11fb6 JM |
573 | int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, |
574 | int npages, u64 iova, u32 *lkey, u32 *rkey); | |
575 | int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, | |
576 | int max_maps, u8 page_shift, struct mlx4_fmr *fmr); | |
577 | int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); | |
578 | void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, | |
579 | u32 *lkey, u32 *rkey); | |
580 | int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); | |
581 | int mlx4_SYNC_TPT(struct mlx4_dev *dev); | |
e7c1c2c4 | 582 | int mlx4_test_interrupts(struct mlx4_dev *dev); |
0b7ca5a9 YP |
583 | int mlx4_assign_eq(struct mlx4_dev *dev, char* name , int* vector); |
584 | void mlx4_release_eq(struct mlx4_dev *dev, int vec); | |
8ad11fb6 | 585 | |
14c07b13 YP |
586 | int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); |
587 | int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); | |
588 | ||
f2a3f6a3 OG |
589 | int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); |
590 | void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); | |
591 | ||
225c7b1f | 592 | #endif /* MLX4_DEVICE_H */ |