[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / mdio.h

/*
 * linux/mdio.h: definitions for MDIO (clause 45) transceivers
 * Copyright 2006-2009 Solarflare Communications Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation, incorporated herein by reference.
 */

#ifndef __LINUX_MDIO_H__
#define __LINUX_MDIO_H__

#include <linux/mii.h>

/* MDIO Manageable Devices (MMDs). */
#define MDIO_MMD_PMAPMD		1	/* Physical Medium Attachment/
					 * Physical Medium Dependent */
#define MDIO_MMD_WIS		2	/* WAN Interface Sublayer */
#define MDIO_MMD_PCS		3	/* Physical Coding Sublayer */
#define MDIO_MMD_PHYXS		4	/* PHY Extender Sublayer */
#define MDIO_MMD_DTEXS		5	/* DTE Extender Sublayer */
#define MDIO_MMD_TC		6	/* Transmission Convergence */
#define MDIO_MMD_AN		7	/* Auto-Negotiation */
#define MDIO_MMD_C22EXT		29	/* Clause 22 extension */
#define MDIO_MMD_VEND1		30	/* Vendor specific 1 */
#define MDIO_MMD_VEND2		31	/* Vendor specific 2 */

/* Generic MDIO registers. */
#define MDIO_CTRL1		MII_BMCR
#define MDIO_STAT1		MII_BMSR
#define MDIO_DEVID1		MII_PHYSID1
#define MDIO_DEVID2		MII_PHYSID2
#define MDIO_SPEED		4	/* Speed ability */
#define MDIO_DEVS1		5	/* Devices in package */
#define MDIO_DEVS2		6
#define MDIO_CTRL2		7	/* 10G control 2 */
#define MDIO_STAT2		8	/* 10G status 2 */
#define MDIO_PMA_TXDIS		9	/* 10G PMA/PMD transmit disable */
#define MDIO_PMA_RXDET		10	/* 10G PMA/PMD receive signal detect */
#define MDIO_PMA_EXTABLE	11	/* 10G PMA/PMD extended ability */
#define MDIO_PKGID1		14	/* Package identifier */
#define MDIO_PKGID2		15
#define MDIO_AN_ADVERTISE	16	/* AN advertising (base page) */
#define MDIO_AN_LPA		19	/* AN LP abilities (base page) */
#define MDIO_PHYXS_LNSTAT	24	/* PHY XGXS lane state */

/* Media-dependent registers. */
#define MDIO_PMA_10GBT_TXPWR	131	/* 10GBASE-T TX power control */
#define MDIO_PCS_10GBX_STAT1	24	/* 10GBASE-X PCS status 1 */
#define MDIO_PCS_10GBRT_STAT1	32	/* 10GBASE-R/-T PCS status 1 */
#define MDIO_PCS_10GBRT_STAT2	33	/* 10GBASE-R/-T PCS status 2 */
#define MDIO_AN_10GBT_CTRL	32	/* 10GBASE-T auto-negotiation control */
#define MDIO_AN_10GBT_STAT	33	/* 10GBASE-T auto-negotiation status */

/* Control register 1. */
/* Enable extended speed selection */
#define MDIO_CTRL1_SPEEDSELEXT		(BMCR_SPEED1000 | BMCR_SPEED100)
/* All speed selection bits */
#define MDIO_CTRL1_SPEEDSEL		(MDIO_CTRL1_SPEEDSELEXT | 0x003c)
#define MDIO_CTRL1_FULLDPLX		BMCR_FULLDPLX
#define MDIO_CTRL1_LPOWER		BMCR_PDOWN
#define MDIO_CTRL1_RESET		BMCR_RESET
#define MDIO_PMA_CTRL1_LOOPBACK		0x0001
#define MDIO_PMA_CTRL1_SPEED1000	BMCR_SPEED1000
#define MDIO_PMA_CTRL1_SPEED100		BMCR_SPEED100
#define MDIO_PCS_CTRL1_LOOPBACK		BMCR_LOOPBACK
#define MDIO_PHYXS_CTRL1_LOOPBACK	BMCR_LOOPBACK
#define MDIO_AN_CTRL1_RESTART		BMCR_ANRESTART
#define MDIO_AN_CTRL1_ENABLE		BMCR_ANENABLE
#define MDIO_AN_CTRL1_XNP		0x2000	/* Enable extended next page */

/* 10 Gb/s */
#define MDIO_CTRL1_SPEED10G		(MDIO_CTRL1_SPEEDSELEXT | 0x00)
/* 10PASS-TS/2BASE-TL */
#define MDIO_CTRL1_SPEED10P2B		(MDIO_CTRL1_SPEEDSELEXT | 0x04)

/* Status register 1. */
#define MDIO_STAT1_LPOWERABLE		0x0002	/* Low-power ability */
#define MDIO_STAT1_LSTATUS		BMSR_LSTATUS
#define MDIO_STAT1_FAULT		0x0080	/* Fault */
#define MDIO_AN_STAT1_LPABLE		0x0001	/* Link partner AN ability */
#define MDIO_AN_STAT1_ABLE		BMSR_ANEGCAPABLE
#define MDIO_AN_STAT1_RFAULT		BMSR_RFAULT
#define MDIO_AN_STAT1_COMPLETE		BMSR_ANEGCOMPLETE
#define MDIO_AN_STAT1_PAGE		0x0040	/* Page received */
#define MDIO_AN_STAT1_XNP		0x0080	/* Extended next page status */

/* Speed register. */
#define MDIO_SPEED_10G			0x0001	/* 10G capable */
#define MDIO_PMA_SPEED_2B		0x0002	/* 2BASE-TL capable */
#define MDIO_PMA_SPEED_10P		0x0004	/* 10PASS-TS capable */
#define MDIO_PMA_SPEED_1000		0x0010	/* 1000M capable */
#define MDIO_PMA_SPEED_100		0x0020	/* 100M capable */
#define MDIO_PMA_SPEED_10		0x0040	/* 10M capable */
#define MDIO_PCS_SPEED_10P2B		0x0002	/* 10PASS-TS/2BASE-TL capable */

/* Device present registers. */
#define MDIO_DEVS_PRESENT(devad)	(1 << (devad))
#define MDIO_DEVS_PMAPMD		MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD)
#define MDIO_DEVS_WIS			MDIO_DEVS_PRESENT(MDIO_MMD_WIS)
#define MDIO_DEVS_PCS			MDIO_DEVS_PRESENT(MDIO_MMD_PCS)
#define MDIO_DEVS_PHYXS			MDIO_DEVS_PRESENT(MDIO_MMD_PHYXS)
#define MDIO_DEVS_DTEXS			MDIO_DEVS_PRESENT(MDIO_MMD_DTEXS)
#define MDIO_DEVS_TC			MDIO_DEVS_PRESENT(MDIO_MMD_TC)
#define MDIO_DEVS_AN			MDIO_DEVS_PRESENT(MDIO_MMD_AN)
#define MDIO_DEVS_C22EXT		MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT)

/* Control register 2. */
#define MDIO_PMA_CTRL2_TYPE		0x000f	/* PMA/PMD type selection */
#define MDIO_PMA_CTRL2_10GBCX4		0x0000	/* 10GBASE-CX4 type */
#define MDIO_PMA_CTRL2_10GBEW		0x0001	/* 10GBASE-EW type */
#define MDIO_PMA_CTRL2_10GBLW		0x0002	/* 10GBASE-LW type */
#define MDIO_PMA_CTRL2_10GBSW		0x0003	/* 10GBASE-SW type */
#define MDIO_PMA_CTRL2_10GBLX4		0x0004	/* 10GBASE-LX4 type */
#define MDIO_PMA_CTRL2_10GBER		0x0005	/* 10GBASE-ER type */
#define MDIO_PMA_CTRL2_10GBLR		0x0006	/* 10GBASE-LR type */
#define MDIO_PMA_CTRL2_10GBSR		0x0007	/* 10GBASE-SR type */
#define MDIO_PMA_CTRL2_10GBLRM		0x0008	/* 10GBASE-LRM type */
#define MDIO_PMA_CTRL2_10GBT		0x0009	/* 10GBASE-T type */
#define MDIO_PMA_CTRL2_10GBKX4		0x000a	/* 10GBASE-KX4 type */
#define MDIO_PMA_CTRL2_10GBKR		0x000b	/* 10GBASE-KR type */
#define MDIO_PMA_CTRL2_1000BT		0x000c	/* 1000BASE-T type */
#define MDIO_PMA_CTRL2_1000BKX		0x000d	/* 1000BASE-KX type */
#define MDIO_PMA_CTRL2_100BTX		0x000e	/* 100BASE-TX type */
#define MDIO_PMA_CTRL2_10BT		0x000f	/* 10BASE-T type */
#define MDIO_PCS_CTRL2_TYPE		0x0003	/* PCS type selection */
#define MDIO_PCS_CTRL2_10GBR		0x0000	/* 10GBASE-R type */
#define MDIO_PCS_CTRL2_10GBX		0x0001	/* 10GBASE-X type */
#define MDIO_PCS_CTRL2_10GBW		0x0002	/* 10GBASE-W type */
#define MDIO_PCS_CTRL2_10GBT		0x0003	/* 10GBASE-T type */

/* Status register 2. */
#define MDIO_STAT2_RXFAULT		0x0400	/* Receive fault */
#define MDIO_STAT2_TXFAULT		0x0800	/* Transmit fault */
#define MDIO_STAT2_DEVPRST		0xc000	/* Device present */
#define MDIO_STAT2_DEVPRST_VAL		0x8000	/* Device present value */
#define MDIO_PMA_STAT2_LBABLE		0x0001	/* PMA loopback ability */
#define MDIO_PMA_STAT2_10GBEW		0x0002	/* 10GBASE-EW ability */
#define MDIO_PMA_STAT2_10GBLW		0x0004	/* 10GBASE-LW ability */
#define MDIO_PMA_STAT2_10GBSW		0x0008	/* 10GBASE-SW ability */
#define MDIO_PMA_STAT2_10GBLX4		0x0010	/* 10GBASE-LX4 ability */
#define MDIO_PMA_STAT2_10GBER		0x0020	/* 10GBASE-ER ability */
#define MDIO_PMA_STAT2_10GBLR		0x0040	/* 10GBASE-LR ability */
#define MDIO_PMA_STAT2_10GBSR		0x0080	/* 10GBASE-SR ability */
#define MDIO_PMD_STAT2_TXDISAB		0x0100	/* PMD TX disable ability */
#define MDIO_PMA_STAT2_EXTABLE		0x0200	/* Extended abilities */
#define MDIO_PMA_STAT2_RXFLTABLE	0x1000	/* Receive fault ability */
#define MDIO_PMA_STAT2_TXFLTABLE	0x2000	/* Transmit fault ability */
#define MDIO_PCS_STAT2_10GBR		0x0001	/* 10GBASE-R capable */
#define MDIO_PCS_STAT2_10GBX		0x0002	/* 10GBASE-X capable */
#define MDIO_PCS_STAT2_10GBW		0x0004	/* 10GBASE-W capable */
#define MDIO_PCS_STAT2_RXFLTABLE	0x1000	/* Receive fault ability */
#define MDIO_PCS_STAT2_TXFLTABLE	0x2000	/* Transmit fault ability */

/* Transmit disable register. */
#define MDIO_PMD_TXDIS_GLOBAL		0x0001	/* Global PMD TX disable */
#define MDIO_PMD_TXDIS_0		0x0002	/* PMD TX disable 0 */
#define MDIO_PMD_TXDIS_1		0x0004	/* PMD TX disable 1 */
#define MDIO_PMD_TXDIS_2		0x0008	/* PMD TX disable 2 */
#define MDIO_PMD_TXDIS_3		0x0010	/* PMD TX disable 3 */

/* Receive signal detect register. */
#define MDIO_PMD_RXDET_GLOBAL		0x0001	/* Global PMD RX signal detect */
#define MDIO_PMD_RXDET_0		0x0002	/* PMD RX signal detect 0 */
#define MDIO_PMD_RXDET_1		0x0004	/* PMD RX signal detect 1 */
#define MDIO_PMD_RXDET_2		0x0008	/* PMD RX signal detect 2 */
#define MDIO_PMD_RXDET_3		0x0010	/* PMD RX signal detect 3 */

/* Extended abilities register. */
#define MDIO_PMA_EXTABLE_10GCX4		0x0001	/* 10GBASE-CX4 ability */
#define MDIO_PMA_EXTABLE_10GBLRM	0x0002	/* 10GBASE-LRM ability */
#define MDIO_PMA_EXTABLE_10GBT		0x0004	/* 10GBASE-T ability */
#define MDIO_PMA_EXTABLE_10GBKX4	0x0008	/* 10GBASE-KX4 ability */
#define MDIO_PMA_EXTABLE_10GBKR		0x0010	/* 10GBASE-KR ability */
#define MDIO_PMA_EXTABLE_1000BT		0x0020	/* 1000BASE-T ability */
#define MDIO_PMA_EXTABLE_1000BKX	0x0040	/* 1000BASE-KX ability */
#define MDIO_PMA_EXTABLE_100BTX		0x0080	/* 100BASE-TX ability */
#define MDIO_PMA_EXTABLE_10BT		0x0100	/* 10BASE-T ability */

/* PHY XGXS lane state register. */
#define MDIO_PHYXS_LNSTAT_SYNC0		0x0001
#define MDIO_PHYXS_LNSTAT_SYNC1		0x0002
#define MDIO_PHYXS_LNSTAT_SYNC2		0x0004
#define MDIO_PHYXS_LNSTAT_SYNC3		0x0008
#define MDIO_PHYXS_LNSTAT_ALIGN		0x1000

/* PMA 10GBASE-T TX power register. */
#define MDIO_PMA_10GBT_TXPWR_SHORT	0x0001	/* Short-reach mode */

/* PCS 10GBASE-R/-T status register 1. */
#define MDIO_PCS_10GBRT_STAT1_BLKLK	0x0001	/* Block lock attained */

/* PCS 10GBASE-R/-T status register 2. */
#define MDIO_PCS_10GBRT_STAT2_ERR	0x00ff
#define MDIO_PCS_10GBRT_STAT2_BER	0x3f00

/* AN 10GBASE-T control register. */
#define MDIO_AN_10GBT_CTRL_ADV10G	0x1000	/* Advertise 10GBASE-T */

/* AN 10GBASE-T status register. */
#define MDIO_AN_10GBT_STAT_LPTRR	0x0200	/* LP training reset req. */
#define MDIO_AN_10GBT_STAT_LPLTABLE	0x0400	/* LP loop timing ability */
#define MDIO_AN_10GBT_STAT_LP10G	0x0800	/* LP is 10GBT capable */
#define MDIO_AN_10GBT_STAT_REMOK	0x1000	/* Remote OK */
#define MDIO_AN_10GBT_STAT_LOCOK	0x2000	/* Local OK */
#define MDIO_AN_10GBT_STAT_MS		0x4000	/* Master/slave config */
#define MDIO_AN_10GBT_STAT_MSFLT	0x8000	/* Master/slave config fault */

/* Mapping between MDIO PRTAD/DEVAD and mii_ioctl_data::phy_id */

#define MDIO_PHY_ID_C45			0x8000
#define MDIO_PHY_ID_PRTAD		0x03e0
#define MDIO_PHY_ID_DEVAD		0x001f
#define MDIO_PHY_ID_C45_MASK						\
	(MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD)

static inline __u16 mdio_phy_id_c45(int prtad, int devad)
{
	return MDIO_PHY_ID_C45 | (prtad << 5) | devad;
}

static inline bool mdio_phy_id_is_c45(int phy_id)
{
	return (phy_id & MDIO_PHY_ID_C45) && !(phy_id & ~MDIO_PHY_ID_C45_MASK);
}

static inline __u16 mdio_phy_id_prtad(int phy_id)
{
	return (phy_id & MDIO_PHY_ID_PRTAD) >> 5;
}

static inline __u16 mdio_phy_id_devad(int phy_id)
{
	return phy_id & MDIO_PHY_ID_DEVAD;
}

#ifdef __KERNEL__ 

/**
 * struct mdio_if_info - Ethernet controller MDIO interface
 * @prtad: PRTAD of the PHY (%MDIO_PRTAD_NONE if not present/unknown)
 * @mmds: Mask of MMDs expected to be present in the PHY.  This must be
 *	non-zero unless @prtad = %MDIO_PRTAD_NONE.
 * @mode_support: MDIO modes supported.  If %MDIO_SUPPORTS_C22 is set then
 *	MII register access will be passed through with @devad =
 *	%MDIO_DEVAD_NONE.  If %MDIO_EMULATE_C22 is set then access to
 *	commonly used clause 22 registers will be translated into
 *	clause 45 registers.
 * @dev: Net device structure
 * @mdio_read: Register read function; returns value or negative error code
 * @mdio_write: Register write function; returns 0 or negative error code
 */
struct mdio_if_info {
	int prtad;
	u32 __bitwise mmds;
	unsigned mode_support;

	struct net_device *dev;
	int (*mdio_read)(struct net_device *dev, int prtad, int devad,
			 u16 addr);
	int (*mdio_write)(struct net_device *dev, int prtad, int devad,
			  u16 addr, u16 val);
};

#define MDIO_PRTAD_NONE			(-1)
#define MDIO_DEVAD_NONE			(-1)
#define MDIO_SUPPORTS_C22		1
#define MDIO_SUPPORTS_C45		2
#define MDIO_EMULATE_C22		4

struct ethtool_cmd;
struct ethtool_pauseparam;
extern int mdio45_probe(struct mdio_if_info *mdio, int prtad);
extern int mdio_set_flag(const struct mdio_if_info *mdio,
			 int prtad, int devad, u16 addr, int mask,
			 bool sense);
extern int mdio45_links_ok(const struct mdio_if_info *mdio, u32 mmds);
extern int mdio45_nway_restart(const struct mdio_if_info *mdio);
extern void mdio45_ethtool_gset_npage(const struct mdio_if_info *mdio,
				      struct ethtool_cmd *ecmd,
				      u32 npage_adv, u32 npage_lpa);
extern void
mdio45_ethtool_spauseparam_an(const struct mdio_if_info *mdio,
			      const struct ethtool_pauseparam *ecmd);

/**
 * mdio45_ethtool_gset - get settings for ETHTOOL_GSET
 * @mdio: MDIO interface
 * @ecmd: Ethtool request structure
 *
 * Since the CSRs for auto-negotiation using next pages are not fully
 * standardised, this function does not attempt to decode them.  Use
 * mdio45_ethtool_gset_npage() to specify advertisement bits from next
 * pages.
 */
static inline void mdio45_ethtool_gset(const struct mdio_if_info *mdio,
				       struct ethtool_cmd *ecmd)
{
	mdio45_ethtool_gset_npage(mdio, ecmd, 0, 0);
}

extern int mdio_mii_ioctl(const struct mdio_if_info *mdio,
			  struct mii_ioctl_data *mii_data, int cmd);

#endif /* __KERNEL__ */
#endif /* __LINUX_MDIO_H__ */
Commit	Line	Data
52c94dfa BH	1	/*
	2	* linux/mdio.h: definitions for MDIO (clause 45) transceivers
	3	* Copyright 2006-2009 Solarflare Communications Inc.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License version 2 as published
	7	* by the Free Software Foundation, incorporated herein by reference.
	8	*/
	9
	10	#ifndef __LINUX_MDIO_H__
	11	#define __LINUX_MDIO_H__
	12
	13	#include <linux/mii.h>
	14
	15	/* MDIO Manageable Devices (MMDs). */
	16	#define MDIO_MMD_PMAPMD 1 /* Physical Medium Attachment/
	17	* Physical Medium Dependent */
	18	#define MDIO_MMD_WIS 2 /* WAN Interface Sublayer */
	19	#define MDIO_MMD_PCS 3 /* Physical Coding Sublayer */
	20	#define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */
	21	#define MDIO_MMD_DTEXS 5 /* DTE Extender Sublayer */
	22	#define MDIO_MMD_TC 6 /* Transmission Convergence */
	23	#define MDIO_MMD_AN 7 /* Auto-Negotiation */
	24	#define MDIO_MMD_C22EXT 29 /* Clause 22 extension */
	25	#define MDIO_MMD_VEND1 30 /* Vendor specific 1 */
	26	#define MDIO_MMD_VEND2 31 /* Vendor specific 2 */
	27
	28	/* Generic MDIO registers. */
	29	#define MDIO_CTRL1 MII_BMCR
	30	#define MDIO_STAT1 MII_BMSR
	31	#define MDIO_DEVID1 MII_PHYSID1
	32	#define MDIO_DEVID2 MII_PHYSID2
	33	#define MDIO_SPEED 4 /* Speed ability */
	34	#define MDIO_DEVS1 5 /* Devices in package */
	35	#define MDIO_DEVS2 6
	36	#define MDIO_CTRL2 7 /* 10G control 2 */
	37	#define MDIO_STAT2 8 /* 10G status 2 */
	38	#define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
	39	#define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
	40	#define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
	41	#define MDIO_PKGID1 14 /* Package identifier */
	42	#define MDIO_PKGID2 15
	43	#define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */
	44	#define MDIO_AN_LPA 19 /* AN LP abilities (base page) */
	45	#define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */
	46
	47	/* Media-dependent registers. */
	48	#define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
	49	#define MDIO_PCS_10GBX_STAT1 24 /* 10GBASE-X PCS status 1 */
	50	#define MDIO_PCS_10GBRT_STAT1 32 /* 10GBASE-R/-T PCS status 1 */
	51	#define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */
	52	#define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */
	53	#define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */
	54
	55	/* Control register 1. */
	56	/* Enable extended speed selection */
	57	#define MDIO_CTRL1_SPEEDSELEXT (BMCR_SPEED1000 \| BMCR_SPEED100)
	58	/* All speed selection bits */
	59	#define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT \| 0x003c)
	60	#define MDIO_CTRL1_FULLDPLX BMCR_FULLDPLX
	61	#define MDIO_CTRL1_LPOWER BMCR_PDOWN
	62	#define MDIO_CTRL1_RESET BMCR_RESET
	63	#define MDIO_PMA_CTRL1_LOOPBACK 0x0001
	64	#define MDIO_PMA_CTRL1_SPEED1000 BMCR_SPEED1000
65	#define MDIO_PMA_CTRL1_SPEED100 BMCR_SPEED100
66	#define MDIO_PCS_CTRL1_LOOPBACK BMCR_LOOPBACK
67	#define MDIO_PHYXS_CTRL1_LOOPBACK BMCR_LOOPBACK
68	#define MDIO_AN_CTRL1_RESTART BMCR_ANRESTART
69	#define MDIO_AN_CTRL1_ENABLE BMCR_ANENABLE
70	#define MDIO_AN_CTRL1_XNP 0x2000 /* Enable extended next page */
71
72	/* 10 Gb/s */
73	#define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT \| 0x00)
74	/* 10PASS-TS/2BASE-TL */
75	#define MDIO_CTRL1_SPEED10P2B (MDIO_CTRL1_SPEEDSELEXT \| 0x04)
76
77	/* Status register 1. */
78	#define MDIO_STAT1_LPOWERABLE 0x0002 /* Low-power ability */
79	#define MDIO_STAT1_LSTATUS BMSR_LSTATUS
80	#define MDIO_STAT1_FAULT 0x0080 /* Fault */
81	#define MDIO_AN_STAT1_LPABLE 0x0001 /* Link partner AN ability */
82	#define MDIO_AN_STAT1_ABLE BMSR_ANEGCAPABLE
83	#define MDIO_AN_STAT1_RFAULT BMSR_RFAULT
84	#define MDIO_AN_STAT1_COMPLETE BMSR_ANEGCOMPLETE
85	#define MDIO_AN_STAT1_PAGE 0x0040 /* Page received */
86	#define MDIO_AN_STAT1_XNP 0x0080 /* Extended next page status */
87
88	/* Speed register. */
89	#define MDIO_SPEED_10G 0x0001 /* 10G capable */
90	#define MDIO_PMA_SPEED_2B 0x0002 /* 2BASE-TL capable */
91	#define MDIO_PMA_SPEED_10P 0x0004 /* 10PASS-TS capable */
92	#define MDIO_PMA_SPEED_1000 0x0010 /* 1000M capable */
93	#define MDIO_PMA_SPEED_100 0x0020 /* 100M capable */
94	#define MDIO_PMA_SPEED_10 0x0040 /* 10M capable */
95	#define MDIO_PCS_SPEED_10P2B 0x0002 /* 10PASS-TS/2BASE-TL capable */
96
97	/* Device present registers. */
98	#define MDIO_DEVS_PRESENT(devad) (1 << (devad))
99	#define MDIO_DEVS_PMAPMD MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD)
100	#define MDIO_DEVS_WIS MDIO_DEVS_PRESENT(MDIO_MMD_WIS)
101	#define MDIO_DEVS_PCS MDIO_DEVS_PRESENT(MDIO_MMD_PCS)
102	#define MDIO_DEVS_PHYXS MDIO_DEVS_PRESENT(MDIO_MMD_PHYXS)
103	#define MDIO_DEVS_DTEXS MDIO_DEVS_PRESENT(MDIO_MMD_DTEXS)
104	#define MDIO_DEVS_TC MDIO_DEVS_PRESENT(MDIO_MMD_TC)
105	#define MDIO_DEVS_AN MDIO_DEVS_PRESENT(MDIO_MMD_AN)
106	#define MDIO_DEVS_C22EXT MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT)
107
108	/* Control register 2. */
109	#define MDIO_PMA_CTRL2_TYPE 0x000f /* PMA/PMD type selection */
110	#define MDIO_PMA_CTRL2_10GBCX4 0x0000 /* 10GBASE-CX4 type */
111	#define MDIO_PMA_CTRL2_10GBEW 0x0001 /* 10GBASE-EW type */
112	#define MDIO_PMA_CTRL2_10GBLW 0x0002 /* 10GBASE-LW type */
113	#define MDIO_PMA_CTRL2_10GBSW 0x0003 /* 10GBASE-SW type */
114	#define MDIO_PMA_CTRL2_10GBLX4 0x0004 /* 10GBASE-LX4 type */
115	#define MDIO_PMA_CTRL2_10GBER 0x0005 /* 10GBASE-ER type */
116	#define MDIO_PMA_CTRL2_10GBLR 0x0006 /* 10GBASE-LR type */
117	#define MDIO_PMA_CTRL2_10GBSR 0x0007 /* 10GBASE-SR type */
118	#define MDIO_PMA_CTRL2_10GBLRM 0x0008 /* 10GBASE-LRM type */
119	#define MDIO_PMA_CTRL2_10GBT 0x0009 /* 10GBASE-T type */
120	#define MDIO_PMA_CTRL2_10GBKX4 0x000a /* 10GBASE-KX4 type */
121	#define MDIO_PMA_CTRL2_10GBKR 0x000b /* 10GBASE-KR type */
122	#define MDIO_PMA_CTRL2_1000BT 0x000c /* 1000BASE-T type */
123	#define MDIO_PMA_CTRL2_1000BKX 0x000d /* 1000BASE-KX type */
124	#define MDIO_PMA_CTRL2_100BTX 0x000e /* 100BASE-TX type */
125	#define MDIO_PMA_CTRL2_10BT 0x000f /* 10BASE-T type */
126	#define MDIO_PCS_CTRL2_TYPE 0x0003 /* PCS type selection */
127	#define MDIO_PCS_CTRL2_10GBR 0x0000 /* 10GBASE-R type */
128	#define MDIO_PCS_CTRL2_10GBX 0x0001 /* 10GBASE-X type */
129	#define MDIO_PCS_CTRL2_10GBW 0x0002 /* 10GBASE-W type */
130	#define MDIO_PCS_CTRL2_10GBT 0x0003 /* 10GBASE-T type */
131
132	/* Status register 2. */
133	#define MDIO_STAT2_RXFAULT 0x0400 /* Receive fault */
134	#define MDIO_STAT2_TXFAULT 0x0800 /* Transmit fault */
135	#define MDIO_STAT2_DEVPRST 0xc000 /* Device present */
136	#define MDIO_STAT2_DEVPRST_VAL 0x8000 /* Device present value */
137	#define MDIO_PMA_STAT2_LBABLE 0x0001 /* PMA loopback ability */
138	#define MDIO_PMA_STAT2_10GBEW 0x0002 /* 10GBASE-EW ability */
139	#define MDIO_PMA_STAT2_10GBLW 0x0004 /* 10GBASE-LW ability */
140	#define MDIO_PMA_STAT2_10GBSW 0x0008 /* 10GBASE-SW ability */
141	#define MDIO_PMA_STAT2_10GBLX4 0x0010 /* 10GBASE-LX4 ability */
142	#define MDIO_PMA_STAT2_10GBER 0x0020 /* 10GBASE-ER ability */
143	#define MDIO_PMA_STAT2_10GBLR 0x0040 /* 10GBASE-LR ability */
144	#define MDIO_PMA_STAT2_10GBSR 0x0080 /* 10GBASE-SR ability */
145	#define MDIO_PMD_STAT2_TXDISAB 0x0100 /* PMD TX disable ability */
146	#define MDIO_PMA_STAT2_EXTABLE 0x0200 /* Extended abilities */
147	#define MDIO_PMA_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */
148	#define MDIO_PMA_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */
149	#define MDIO_PCS_STAT2_10GBR 0x0001 /* 10GBASE-R capable */
150	#define MDIO_PCS_STAT2_10GBX 0x0002 /* 10GBASE-X capable */
151	#define MDIO_PCS_STAT2_10GBW 0x0004 /* 10GBASE-W capable */
152	#define MDIO_PCS_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */
153	#define MDIO_PCS_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */
154
155	/* Transmit disable register. */
156	#define MDIO_PMD_TXDIS_GLOBAL 0x0001 /* Global PMD TX disable */
157	#define MDIO_PMD_TXDIS_0 0x0002 /* PMD TX disable 0 */
158	#define MDIO_PMD_TXDIS_1 0x0004 /* PMD TX disable 1 */
159	#define MDIO_PMD_TXDIS_2 0x0008 /* PMD TX disable 2 */
160	#define MDIO_PMD_TXDIS_3 0x0010 /* PMD TX disable 3 */
161
162	/* Receive signal detect register. */
163	#define MDIO_PMD_RXDET_GLOBAL 0x0001 /* Global PMD RX signal detect */
164	#define MDIO_PMD_RXDET_0 0x0002 /* PMD RX signal detect 0 */
165	#define MDIO_PMD_RXDET_1 0x0004 /* PMD RX signal detect 1 */
166	#define MDIO_PMD_RXDET_2 0x0008 /* PMD RX signal detect 2 */
167	#define MDIO_PMD_RXDET_3 0x0010 /* PMD RX signal detect 3 */
168
169	/* Extended abilities register. */
170	#define MDIO_PMA_EXTABLE_10GCX4 0x0001 /* 10GBASE-CX4 ability */
171	#define MDIO_PMA_EXTABLE_10GBLRM 0x0002 /* 10GBASE-LRM ability */
172	#define MDIO_PMA_EXTABLE_10GBT 0x0004 /* 10GBASE-T ability */
173	#define MDIO_PMA_EXTABLE_10GBKX4 0x0008 /* 10GBASE-KX4 ability */
174	#define MDIO_PMA_EXTABLE_10GBKR 0x0010 /* 10GBASE-KR ability */
175	#define MDIO_PMA_EXTABLE_1000BT 0x0020 /* 1000BASE-T ability */
176	#define MDIO_PMA_EXTABLE_1000BKX 0x0040 /* 1000BASE-KX ability */
177	#define MDIO_PMA_EXTABLE_100BTX 0x0080 /* 100BASE-TX ability */
178	#define MDIO_PMA_EXTABLE_10BT 0x0100 /* 10BASE-T ability */
179
180	/* PHY XGXS lane state register. */
181	#define MDIO_PHYXS_LNSTAT_SYNC0 0x0001
182	#define MDIO_PHYXS_LNSTAT_SYNC1 0x0002
183	#define MDIO_PHYXS_LNSTAT_SYNC2 0x0004
184	#define MDIO_PHYXS_LNSTAT_SYNC3 0x0008
185	#define MDIO_PHYXS_LNSTAT_ALIGN 0x1000
186
187	/* PMA 10GBASE-T TX power register. */
188	#define MDIO_PMA_10GBT_TXPWR_SHORT 0x0001 /* Short-reach mode */
189
190	/* PCS 10GBASE-R/-T status register 1. */
191	#define MDIO_PCS_10GBRT_STAT1_BLKLK 0x0001 /* Block lock attained */
192
193	/* PCS 10GBASE-R/-T status register 2. */
194	#define MDIO_PCS_10GBRT_STAT2_ERR 0x00ff
195	#define MDIO_PCS_10GBRT_STAT2_BER 0x3f00
196
197	/* AN 10GBASE-T control register. */
198	#define MDIO_AN_10GBT_CTRL_ADV10G 0x1000 /* Advertise 10GBASE-T */
199
200	/* AN 10GBASE-T status register. */
201	#define MDIO_AN_10GBT_STAT_LPTRR 0x0200 /* LP training reset req. */
202	#define MDIO_AN_10GBT_STAT_LPLTABLE 0x0400 /* LP loop timing ability */
203	#define MDIO_AN_10GBT_STAT_LP10G 0x0800 /* LP is 10GBT capable */
204	#define MDIO_AN_10GBT_STAT_REMOK 0x1000 /* Remote OK */
205	#define MDIO_AN_10GBT_STAT_LOCOK 0x2000 /* Local OK */
206	#define MDIO_AN_10GBT_STAT_MS 0x4000 /* Master/slave config */
207	#define MDIO_AN_10GBT_STAT_MSFLT 0x8000 /* Master/slave config fault */
208
209	/* Mapping between MDIO PRTAD/DEVAD and mii_ioctl_data::phy_id */
210
211	#define MDIO_PHY_ID_C45 0x8000
212	#define MDIO_PHY_ID_PRTAD 0x03e0
213	#define MDIO_PHY_ID_DEVAD 0x001f
214	#define MDIO_PHY_ID_C45_MASK \
215	(MDIO_PHY_ID_C45 \| MDIO_PHY_ID_PRTAD \| MDIO_PHY_ID_DEVAD)
216
217	static inline __u16 mdio_phy_id_c45(int prtad, int devad)
218	{
219	return MDIO_PHY_ID_C45 \| (prtad << 5) \| devad;
220	}
221
222	static inline bool mdio_phy_id_is_c45(int phy_id)
223	{
224	return (phy_id & MDIO_PHY_ID_C45) && !(phy_id & ~MDIO_PHY_ID_C45_MASK);
225	}
226
227	static inline __u16 mdio_phy_id_prtad(int phy_id)
228	{
229	return (phy_id & MDIO_PHY_ID_PRTAD) >> 5;
230	}
231
232	static inline __u16 mdio_phy_id_devad(int phy_id)
233	{
234	return phy_id & MDIO_PHY_ID_DEVAD;
235	}
236
1b1c2e95 BH	237	#ifdef __KERNEL__
	238
	239	/**
	240	* struct mdio_if_info - Ethernet controller MDIO interface
	241	* @prtad: PRTAD of the PHY (%MDIO_PRTAD_NONE if not present/unknown)
	242	* @mmds: Mask of MMDs expected to be present in the PHY. This must be
	243	* non-zero unless @prtad = %MDIO_PRTAD_NONE.
	244	* @mode_support: MDIO modes supported. If %MDIO_SUPPORTS_C22 is set then
	245	* MII register access will be passed through with @devad =
	246	* %MDIO_DEVAD_NONE. If %MDIO_EMULATE_C22 is set then access to
	247	* commonly used clause 22 registers will be translated into
	248	* clause 45 registers.
	249	* @dev: Net device structure
	250	* @mdio_read: Register read function; returns value or negative error code
	251	* @mdio_write: Register write function; returns 0 or negative error code
	252	*/
	253	struct mdio_if_info {
	254	int prtad;
	255	u32 __bitwise mmds;
	256	unsigned mode_support;
	257
	258	struct net_device *dev;
	259	int (mdio_read)(struct net_device dev, int prtad, int devad,
	260	u16 addr);
	261	int (mdio_write)(struct net_device dev, int prtad, int devad,
	262	u16 addr, u16 val);
	263	};
	264
	265	#define MDIO_PRTAD_NONE (-1)
	266	#define MDIO_DEVAD_NONE (-1)
	267	#define MDIO_SUPPORTS_C22 1
	268	#define MDIO_SUPPORTS_C45 2
	269	#define MDIO_EMULATE_C22 4
	270
	271	struct ethtool_cmd;
	272	struct ethtool_pauseparam;
	273	extern int mdio45_probe(struct mdio_if_info *mdio, int prtad);
	274	extern int mdio_set_flag(const struct mdio_if_info *mdio,
	275	int prtad, int devad, u16 addr, int mask,
	276	bool sense);
	277	extern int mdio45_links_ok(const struct mdio_if_info *mdio, u32 mmds);
	278	extern int mdio45_nway_restart(const struct mdio_if_info *mdio);
	279	extern void mdio45_ethtool_gset_npage(const struct mdio_if_info *mdio,
	280	struct ethtool_cmd *ecmd,
	281	u32 npage_adv, u32 npage_lpa);
af2a3eac BH	282	extern void
	283	mdio45_ethtool_spauseparam_an(const struct mdio_if_info *mdio,
	284	const struct ethtool_pauseparam *ecmd);
1b1c2e95 BH	285
	286	/**
	287	* mdio45_ethtool_gset - get settings for ETHTOOL_GSET
	288	* @mdio: MDIO interface
	289	* @ecmd: Ethtool request structure
	290	*
	291	* Since the CSRs for auto-negotiation using next pages are not fully
	292	* standardised, this function does not attempt to decode them. Use
	293	* mdio45_ethtool_gset_npage() to specify advertisement bits from next
	294	* pages.
	295	*/
	296	static inline void mdio45_ethtool_gset(const struct mdio_if_info *mdio,
	297	struct ethtool_cmd *ecmd)
	298	{
	299	mdio45_ethtool_gset_npage(mdio, ecmd, 0, 0);
	300	}
	301
	302	extern int mdio_mii_ioctl(const struct mdio_if_info *mdio,
	303	struct mii_ioctl_data *mii_data, int cmd);
	304
	305	#endif /* __KERNEL__ */
52c94dfa	306	#endif /* __LINUX_MDIO_H__ */