Commit | Line | Data |
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f27ecacc | 1 | /* |
520f7bd7 | 2 | * include/linux/irqchip/arm-gic.h |
f27ecacc RK |
3 | * |
4 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
520f7bd7 RH |
10 | #ifndef __LINUX_IRQCHIP_ARM_GIC_H |
11 | #define __LINUX_IRQCHIP_ARM_GIC_H | |
f27ecacc | 12 | |
f27ecacc RK |
13 | #define GIC_CPU_CTRL 0x00 |
14 | #define GIC_CPU_PRIMASK 0x04 | |
15 | #define GIC_CPU_BINPOINT 0x08 | |
16 | #define GIC_CPU_INTACK 0x0c | |
17 | #define GIC_CPU_EOI 0x10 | |
18 | #define GIC_CPU_RUNNINGPRI 0x14 | |
19 | #define GIC_CPU_HIGHPRI 0x18 | |
6fa3eb70 S |
20 | #define GIC_CPU_AIAR 0x20 |
21 | #define GIC_CPU_AEOI 0x24 | |
f27ecacc RK |
22 | |
23 | #define GIC_DIST_CTRL 0x000 | |
24 | #define GIC_DIST_CTR 0x004 | |
7c7945a8 | 25 | #define GIC_DIST_IGROUP 0x080 |
f27ecacc RK |
26 | #define GIC_DIST_ENABLE_SET 0x100 |
27 | #define GIC_DIST_ENABLE_CLEAR 0x180 | |
28 | #define GIC_DIST_PENDING_SET 0x200 | |
29 | #define GIC_DIST_PENDING_CLEAR 0x280 | |
7c7945a8 CD |
30 | #define GIC_DIST_ACTIVE_SET 0x300 |
31 | #define GIC_DIST_ACTIVE_CLEAR 0x380 | |
f27ecacc RK |
32 | #define GIC_DIST_PRI 0x400 |
33 | #define GIC_DIST_TARGET 0x800 | |
34 | #define GIC_DIST_CONFIG 0xc00 | |
35 | #define GIC_DIST_SOFTINT 0xf00 | |
36 | ||
fdf77a72 MZ |
37 | #define GICH_HCR 0x0 |
38 | #define GICH_VTR 0x4 | |
39 | #define GICH_VMCR 0x8 | |
40 | #define GICH_MISR 0x10 | |
41 | #define GICH_EISR0 0x20 | |
42 | #define GICH_EISR1 0x24 | |
43 | #define GICH_ELRSR0 0x30 | |
44 | #define GICH_ELRSR1 0x34 | |
45 | #define GICH_APR 0xf0 | |
46 | #define GICH_LR0 0x100 | |
47 | ||
48 | #define GICH_HCR_EN (1 << 0) | |
49 | #define GICH_HCR_UIE (1 << 1) | |
50 | ||
51 | #define GICH_LR_VIRTUALID (0x3ff << 0) | |
52 | #define GICH_LR_PHYSID_CPUID_SHIFT (10) | |
53 | #define GICH_LR_PHYSID_CPUID (7 << GICH_LR_PHYSID_CPUID_SHIFT) | |
54 | #define GICH_LR_STATE (3 << 28) | |
55 | #define GICH_LR_PENDING_BIT (1 << 28) | |
56 | #define GICH_LR_ACTIVE_BIT (1 << 29) | |
57 | #define GICH_LR_EOI (1 << 19) | |
58 | ||
59 | #define GICH_MISR_EOI (1 << 0) | |
60 | #define GICH_MISR_U (1 << 1) | |
61 | ||
a96ab039 MZ |
62 | #ifndef __ASSEMBLY__ |
63 | ||
4294f8ba RH |
64 | struct device_node; |
65 | ||
d7ed36a4 | 66 | extern struct irq_chip gic_arch_extn; |
ff2e27ae | 67 | |
db0d4db2 | 68 | void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *, |
75294957 | 69 | u32 offset, struct device_node *); |
b3a1bde4 | 70 | void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); |
6fa3eb70 S |
71 | void gic_raise_softirq(const struct cpumask *mask, unsigned int irq); |
72 | void gic_register_sgi(unsigned int gic_nr, int irq); | |
e807acbc | 73 | |
db0d4db2 MZ |
74 | static inline void gic_init(unsigned int nr, int start, |
75 | void __iomem *dist , void __iomem *cpu) | |
76 | { | |
75294957 | 77 | gic_init_bases(nr, start, dist, cpu, 0, NULL); |
db0d4db2 MZ |
78 | } |
79 | ||
a96ab039 MZ |
80 | #endif /* __ASSEMBLY */ |
81 | ||
f27ecacc | 82 | #endif |