[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / irq.h

#ifndef _LINUX_IRQ_H
#define _LINUX_IRQ_H

/*
 * Please do not include this file in generic code.  There is currently
 * no requirement for any architecture to implement anything held
 * within this file.
 *
 * Thanks. --rmk
 */

#include <linux/smp.h>

#ifndef CONFIG_S390

#include <linux/linkage.h>
#include <linux/cache.h>
#include <linux/spinlock.h>
#include <linux/cpumask.h>
#include <linux/irqreturn.h>

#include <asm/irq.h>
#include <asm/ptrace.h>

/*
 * IRQ line status.
 *
 * Bits 0-16 are reserved for the IRQF_* bits in linux/interrupt.h
 *
 * IRQ types
 */
#define IRQ_TYPE_NONE		0x00000000	/* Default, unspecified type */
#define IRQ_TYPE_EDGE_RISING	0x00000001	/* Edge rising type */
#define IRQ_TYPE_EDGE_FALLING	0x00000002	/* Edge falling type */
#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
#define IRQ_TYPE_LEVEL_HIGH	0x00000004	/* Level high type */
#define IRQ_TYPE_LEVEL_LOW	0x00000008	/* Level low type */
#define IRQ_TYPE_SENSE_MASK	0x0000000f	/* Mask of the above */
#define IRQ_TYPE_PROBE		0x00000010	/* Probing in progress */

/* Internal flags */
#define IRQ_INPROGRESS		0x00010000	/* IRQ handler active - do not enter! */
#define IRQ_DISABLED		0x00020000	/* IRQ disabled - do not enter! */
#define IRQ_PENDING		0x00040000	/* IRQ pending - replay on enable */
#define IRQ_REPLAY		0x00080000	/* IRQ has been replayed but not acked yet */
#define IRQ_AUTODETECT		0x00100000	/* IRQ is being autodetected */
#define IRQ_WAITING		0x00200000	/* IRQ not yet seen - for autodetection */
#define IRQ_LEVEL		0x00400000	/* IRQ level triggered */
#define IRQ_MASKED		0x00800000	/* IRQ masked - shouldn't be seen again */
#ifdef CONFIG_IRQ_PER_CPU
# define IRQ_PER_CPU		0x01000000	/* IRQ is per CPU */
# define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU)
#else
# define CHECK_IRQ_PER_CPU(var) 0
#endif

#define IRQ_NOPROBE		0x02000000	/* IRQ is not valid for probing */
#define IRQ_NOREQUEST		0x04000000	/* IRQ cannot be requested */
#define IRQ_NOAUTOEN		0x08000000	/* IRQ will not be enabled on request irq */
#define IRQ_DELAYED_DISABLE	0x10000000	/* IRQ disable (masking) happens delayed. */

struct proc_dir_entry;

/**
 * struct irq_chip - hardware interrupt chip descriptor
 *
 * @name:		name for /proc/interrupts
 * @startup:		start up the interrupt (defaults to ->enable if NULL)
 * @shutdown:		shut down the interrupt (defaults to ->disable if NULL)
 * @enable:		enable the interrupt (defaults to chip->unmask if NULL)
 * @disable:		disable the interrupt (defaults to chip->mask if NULL)
 * @ack:		start of a new interrupt
 * @mask:		mask an interrupt source
 * @mask_ack:		ack and mask an interrupt source
 * @unmask:		unmask an interrupt source
 * @eoi:		end of interrupt - chip level
 * @end:		end of interrupt - flow level
 * @set_affinity:	set the CPU affinity on SMP machines
 * @retrigger:		resend an IRQ to the CPU
 * @set_type:		set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
 * @set_wake:		enable/disable power-management wake-on of an IRQ
 *
 * @release:		release function solely used by UML
 * @typename:		obsoleted by name, kept as migration helper
 */
struct irq_chip {
	const char	*name;
	unsigned int	(*startup)(unsigned int irq);
	void		(*shutdown)(unsigned int irq);
	void		(*enable)(unsigned int irq);
	void		(*disable)(unsigned int irq);

	void		(*ack)(unsigned int irq);
	void		(*mask)(unsigned int irq);
	void		(*mask_ack)(unsigned int irq);
	void		(*unmask)(unsigned int irq);
	void		(*eoi)(unsigned int irq);

	void		(*end)(unsigned int irq);
	void		(*set_affinity)(unsigned int irq, cpumask_t dest);
	int		(*retrigger)(unsigned int irq);
	int		(*set_type)(unsigned int irq, unsigned int flow_type);
	int		(*set_wake)(unsigned int irq, unsigned int on);

	/* Currently used only by UML, might disappear one day.*/
#ifdef CONFIG_IRQ_RELEASE_METHOD
	void		(*release)(unsigned int irq, void *dev_id);
#endif
	/*
	 * For compatibility, ->typename is copied into ->name.
	 * Will disappear.
	 */
	const char	*typename;
};

/**
 * struct irq_desc - interrupt descriptor
 *
 * @handle_irq:		highlevel irq-events handler [if NULL, __do_IRQ()]
 * @chip:		low level interrupt hardware access
 * @handler_data:	per-IRQ data for the irq_chip methods
 * @chip_data:		platform-specific per-chip private data for the chip
 *			methods, to allow shared chip implementations
 * @action:		the irq action chain
 * @status:		status information
 * @depth:		disable-depth, for nested irq_disable() calls
 * @irq_count:		stats field to detect stalled irqs
 * @irqs_unhandled:	stats field for spurious unhandled interrupts
 * @lock:		locking for SMP
 * @affinity:		IRQ affinity on SMP
 * @cpu:		cpu index useful for balancing
 * @pending_mask:	pending rebalanced interrupts
 * @move_irq:		need to re-target IRQ destination
 * @dir:		/proc/irq/ procfs entry
 * @affinity_entry:	/proc/irq/smp_affinity procfs entry on SMP
 *
 * Pad this out to 32 bytes for cache and indexing reasons.
 */
struct irq_desc {
	void fastcall		(*handle_irq)(unsigned int irq,
					      struct irq_desc *desc,
					      struct pt_regs *regs);
	struct irq_chip		*chip;
	void			*handler_data;
	void			*chip_data;
	struct irqaction	*action;	/* IRQ action list */
	unsigned int		status;		/* IRQ status */

	unsigned int		depth;		/* nested irq disables */
	unsigned int		irq_count;	/* For detecting broken IRQs */
	unsigned int		irqs_unhandled;
	spinlock_t		lock;
#ifdef CONFIG_SMP
	cpumask_t		affinity;
	unsigned int		cpu;
#endif
#if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
	cpumask_t		pending_mask;
	unsigned int		move_irq;	/* need to re-target IRQ dest */
#endif
#ifdef CONFIG_PROC_FS
	struct proc_dir_entry *dir;
#endif
} ____cacheline_aligned;

extern struct irq_desc irq_desc[NR_IRQS];

/*
 * Migration helpers for obsolete names, they will go away:
 */
#define hw_interrupt_type	irq_chip
typedef struct irq_chip		hw_irq_controller;
#define no_irq_type		no_irq_chip
typedef struct irq_desc		irq_desc_t;

/*
 * Pick up the arch-dependent methods:
 */
#include <asm/hw_irq.h>

extern int setup_irq(unsigned int irq, struct irqaction *new);

#ifdef CONFIG_GENERIC_HARDIRQS

#ifdef CONFIG_SMP
static inline void set_native_irq_info(int irq, cpumask_t mask)
{
	irq_desc[irq].affinity = mask;
}
#else
static inline void set_native_irq_info(int irq, cpumask_t mask)
{
}
#endif

#ifdef CONFIG_SMP

#if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)

void set_pending_irq(unsigned int irq, cpumask_t mask);
void move_native_irq(int irq);

#ifdef CONFIG_PCI_MSI
/*
 * Wonder why these are dummies?
 * For e.g the set_ioapic_affinity_vector() calls the set_ioapic_affinity_irq()
 * counter part after translating the vector to irq info. We need to perform
 * this operation on the real irq, when we dont use vector, i.e when
 * pci_use_vector() is false.
 */
static inline void move_irq(int irq)
{
}

static inline void set_irq_info(int irq, cpumask_t mask)
{
}

#else /* CONFIG_PCI_MSI */

static inline void move_irq(int irq)
{
	move_native_irq(irq);
}

static inline void set_irq_info(int irq, cpumask_t mask)
{
	set_native_irq_info(irq, mask);
}

#endif /* CONFIG_PCI_MSI */

#else /* CONFIG_GENERIC_PENDING_IRQ || CONFIG_IRQBALANCE */

static inline void move_irq(int irq)
{
}

static inline void move_native_irq(int irq)
{
}

static inline void set_pending_irq(unsigned int irq, cpumask_t mask)
{
}

static inline void set_irq_info(int irq, cpumask_t mask)
{
	set_native_irq_info(irq, mask);
}

#endif /* CONFIG_GENERIC_PENDING_IRQ */

#else /* CONFIG_SMP */

#define move_irq(x)
#define move_native_irq(x)

#endif /* CONFIG_SMP */

#ifdef CONFIG_IRQBALANCE
extern void set_balance_irq_affinity(unsigned int irq, cpumask_t mask);
#else
static inline void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
{
}
#endif

#ifdef CONFIG_AUTO_IRQ_AFFINITY
extern int select_smp_affinity(unsigned int irq);
#else
static inline int select_smp_affinity(unsigned int irq)
{
	return 1;
}
#endif

extern int no_irq_affinity;

/* Handle irq action chains: */
extern int handle_IRQ_event(unsigned int irq, struct pt_regs *regs,
			    struct irqaction *action);

/*
 * Built-in IRQ handlers for various IRQ types,
 * callable via desc->chip->handle_irq()
 */
extern void fastcall
handle_level_irq(unsigned int irq, struct irq_desc *desc, struct pt_regs *regs);
extern void fastcall
handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc,
			 struct pt_regs *regs);
extern void fastcall
handle_edge_irq(unsigned int irq, struct irq_desc *desc, struct pt_regs *regs);
extern void fastcall
handle_simple_irq(unsigned int irq, struct irq_desc *desc,
		  struct pt_regs *regs);
extern void fastcall
handle_percpu_irq(unsigned int irq, struct irq_desc *desc,
		  struct pt_regs *regs);
extern void fastcall
handle_bad_irq(unsigned int irq, struct irq_desc *desc, struct pt_regs *regs);

/*
 * Get a descriptive string for the highlevel handler, for
 * /proc/interrupts output:
 */
extern const char *
handle_irq_name(void fastcall (*handle)(unsigned int, struct irq_desc *,
					struct pt_regs *));

/*
 * Monolithic do_IRQ implementation.
 * (is an explicit fastcall, because i386 4KSTACKS calls it from assembly)
 */
extern fastcall unsigned int __do_IRQ(unsigned int irq, struct pt_regs *regs);

/*
 * Architectures call this to let the generic IRQ layer
 * handle an interrupt. If the descriptor is attached to an
 * irqchip-style controller then we call the ->handle_irq() handler,
 * and it calls __do_IRQ() if it's attached to an irqtype-style controller.
 */
static inline void generic_handle_irq(unsigned int irq, struct pt_regs *regs)
{
	struct irq_desc *desc = irq_desc + irq;

	if (likely(desc->handle_irq))
		desc->handle_irq(irq, desc, regs);
	else
		__do_IRQ(irq, regs);
}

/* Handling of unhandled and spurious interrupts: */
extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
			   int action_ret, struct pt_regs *regs);

/* Resending of interrupts :*/
void check_irq_resend(struct irq_desc *desc, unsigned int irq);

/* Initialize /proc/irq/ */
extern void init_irq_proc(void);

/* Enable/disable irq debugging output: */
extern int noirqdebug_setup(char *str);

/* Checks whether the interrupt can be requested by request_irq(): */
extern int can_request_irq(unsigned int irq, unsigned long irqflags);

/* Dummy irq-chip implementations: */
extern struct irq_chip no_irq_chip;
extern struct irq_chip dummy_irq_chip;

extern void
set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip,
			 void fastcall (*handle)(unsigned int,
						 struct irq_desc *,
						 struct pt_regs *));
extern void
__set_irq_handler(unsigned int irq,
		  void fastcall (*handle)(unsigned int, struct irq_desc *,
					  struct pt_regs *),
		  int is_chained);

/*
 * Set a highlevel flow handler for a given IRQ:
 */
static inline void
set_irq_handler(unsigned int irq,
		void fastcall (*handle)(unsigned int, struct irq_desc *,
					struct pt_regs *))
{
	__set_irq_handler(irq, handle, 0);
}

/*
 * Set a highlevel chained flow handler for a given IRQ.
 * (a chained handler is automatically enabled and set to
 *  IRQ_NOREQUEST and IRQ_NOPROBE)
 */
static inline void
set_irq_chained_handler(unsigned int irq,
			void fastcall (*handle)(unsigned int, struct irq_desc *,
						struct pt_regs *))
{
	__set_irq_handler(irq, handle, 1);
}

/* Set/get chip/data for an IRQ: */

extern int set_irq_chip(unsigned int irq, struct irq_chip *chip);
extern int set_irq_data(unsigned int irq, void *data);
extern int set_irq_chip_data(unsigned int irq, void *data);
extern int set_irq_type(unsigned int irq, unsigned int type);

#define get_irq_chip(irq)	(irq_desc[irq].chip)
#define get_irq_chip_data(irq)	(irq_desc[irq].chip_data)
#define get_irq_data(irq)	(irq_desc[irq].handler_data)

#endif /* CONFIG_GENERIC_HARDIRQS */

#endif /* !CONFIG_S390 */

#endif /* _LINUX_IRQ_H */
Commit	Line	Data
06fcb0c6 IM	1	#ifndef _LINUX_IRQ_H
06fcb0c6 IM	2	#define _LINUX_IRQ_H
1da177e4 LT	3
	4	/*
	5	* Please do not include this file in generic code. There is currently
	6	* no requirement for any architecture to implement anything held
	7	* within this file.
	8	*
	9	* Thanks. --rmk
	10	*/
	11
23f9b317	12	#include <linux/smp.h>
1da177e4	13
06fcb0c6	14	#ifndef CONFIG_S390
1da177e4 LT	15
	16	#include <linux/linkage.h>
	17	#include <linux/cache.h>
	18	#include <linux/spinlock.h>
	19	#include <linux/cpumask.h>
908dcecd	20	#include <linux/irqreturn.h>
1da177e4 LT	21
	22	#include <asm/irq.h>
	23	#include <asm/ptrace.h>
	24
	25	/*
	26	* IRQ line status.
6e213616 TG	27	*
	28	* Bits 0-16 are reserved for the IRQF_* bits in linux/interrupt.h
	29	*
	30	* IRQ types
1da177e4	31	*/
6e213616 TG	32	#define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */
	33	#define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */
	34	#define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */
	35	#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING)
	36	#define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */
	37	#define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */
	38	#define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */
	39	#define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */
	40
	41	/* Internal flags */
	42	#define IRQ_INPROGRESS 0x00010000 /* IRQ handler active - do not enter! */
	43	#define IRQ_DISABLED 0x00020000 /* IRQ disabled - do not enter! */
	44	#define IRQ_PENDING 0x00040000 /* IRQ pending - replay on enable */
	45	#define IRQ_REPLAY 0x00080000 /* IRQ has been replayed but not acked yet */
	46	#define IRQ_AUTODETECT 0x00100000 /* IRQ is being autodetected */
	47	#define IRQ_WAITING 0x00200000 /* IRQ not yet seen - for autodetection */
	48	#define IRQ_LEVEL 0x00400000 /* IRQ level triggered */
	49	#define IRQ_MASKED 0x00800000 /* IRQ masked - shouldn't be seen again */
0d7012a9	50	#ifdef CONFIG_IRQ_PER_CPU
6e213616	51	# define IRQ_PER_CPU 0x01000000 /* IRQ is per CPU */
f26fdd59 KW	52	# define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU)
	53	#else
	54	# define CHECK_IRQ_PER_CPU(var) 0
	55	#endif
1da177e4	56
6e213616 TG	57	#define IRQ_NOPROBE 0x02000000 /* IRQ is not valid for probing */
	58	#define IRQ_NOREQUEST 0x04000000 /* IRQ cannot be requested */
	59	#define IRQ_NOAUTOEN 0x08000000 /* IRQ will not be enabled on request irq */
	60	#define IRQ_DELAYED_DISABLE 0x10000000 /* IRQ disable (masking) happens delayed. */
6a6de9ef TG	61
	62	struct proc_dir_entry;
	63
8fee5c36	64	/**
6a6de9ef	65	* struct irq_chip - hardware interrupt chip descriptor
8fee5c36 IM	66	*
	67	* @name: name for /proc/interrupts
	68	* @startup: start up the interrupt (defaults to ->enable if NULL)
	69	* @shutdown: shut down the interrupt (defaults to ->disable if NULL)
	70	* @enable: enable the interrupt (defaults to chip->unmask if NULL)
	71	* @disable: disable the interrupt (defaults to chip->mask if NULL)
8fee5c36 IM	72	* @ack: start of a new interrupt
	73	* @mask: mask an interrupt source
	74	* @mask_ack: ack and mask an interrupt source
	75	* @unmask: unmask an interrupt source
47c2a3aa IM	76	* @eoi: end of interrupt - chip level
47c2a3aa IM	77	* @end: end of interrupt - flow level
8fee5c36 IM	78	* @set_affinity: set the CPU affinity on SMP machines
	79	* @retrigger: resend an IRQ to the CPU
	80	* @set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
	81	* @set_wake: enable/disable power-management wake-on of an IRQ
	82	*
	83	* @release: release function solely used by UML
6a6de9ef	84	* @typename: obsoleted by name, kept as migration helper
1da177e4	85	*/
6a6de9ef TG	86	struct irq_chip {
6a6de9ef TG	87	const char *name;
71d218b7 IM	88	unsigned int (*startup)(unsigned int irq);
	89	void (*shutdown)(unsigned int irq);
	90	void (*enable)(unsigned int irq);
	91	void (*disable)(unsigned int irq);
6a6de9ef	92
71d218b7	93	void (*ack)(unsigned int irq);
6a6de9ef TG	94	void (*mask)(unsigned int irq);
	95	void (*mask_ack)(unsigned int irq);
	96	void (*unmask)(unsigned int irq);
47c2a3aa	97	void (*eoi)(unsigned int irq);
6a6de9ef	98
71d218b7 IM	99	void (*end)(unsigned int irq);
71d218b7 IM	100	void (*set_affinity)(unsigned int irq, cpumask_t dest);
c0ad90a3	101	int (*retrigger)(unsigned int irq);
6a6de9ef TG	102	int (*set_type)(unsigned int irq, unsigned int flow_type);
6a6de9ef TG	103	int (*set_wake)(unsigned int irq, unsigned int on);
c0ad90a3	104
b77d6adc PBG	105	/* Currently used only by UML, might disappear one day.*/
b77d6adc PBG	106	#ifdef CONFIG_IRQ_RELEASE_METHOD
71d218b7	107	void (release)(unsigned int irq, void dev_id);
b77d6adc	108	#endif
6a6de9ef TG	109	/*
	110	* For compatibility, ->typename is copied into ->name.
	111	* Will disappear.
	112	*/
	113	const char *typename;
1da177e4 LT	114	};
1da177e4 LT	115
8fee5c36 IM	116	/**
	117	* struct irq_desc - interrupt descriptor
	118	*
6a6de9ef TG	119	* @handle_irq: highlevel irq-events handler [if NULL, __do_IRQ()]
	120	* @chip: low level interrupt hardware access
	121	* @handler_data: per-IRQ data for the irq_chip methods
	122	* @chip_data: platform-specific per-chip private data for the chip
	123	* methods, to allow shared chip implementations
8fee5c36 IM	124	* @action: the irq action chain
	125	* @status: status information
	126	* @depth: disable-depth, for nested irq_disable() calls
	127	* @irq_count: stats field to detect stalled irqs
	128	* @irqs_unhandled: stats field for spurious unhandled interrupts
	129	* @lock: locking for SMP
	130	* @affinity: IRQ affinity on SMP
6a6de9ef	131	* @cpu: cpu index useful for balancing
8fee5c36 IM	132	* @pending_mask: pending rebalanced interrupts
	133	* @move_irq: need to re-target IRQ destination
	134	* @dir: /proc/irq/ procfs entry
	135	* @affinity_entry: /proc/irq/smp_affinity procfs entry on SMP
1da177e4 LT	136	*
	137	* Pad this out to 32 bytes for cache and indexing reasons.
	138	*/
34ffdb72	139	struct irq_desc {
6a6de9ef TG	140	void fastcall (*handle_irq)(unsigned int irq,
	141	struct irq_desc *desc,
	142	struct pt_regs *regs);
	143	struct irq_chip *chip;
	144	void *handler_data;
71d218b7 IM	145	void *chip_data;
	146	struct irqaction action; / IRQ action list */
	147	unsigned int status; /* IRQ status */
6a6de9ef	148
71d218b7 IM	149	unsigned int depth; /* nested irq disables */
	150	unsigned int irq_count; /* For detecting broken IRQs */
	151	unsigned int irqs_unhandled;
	152	spinlock_t lock;
a53da52f	153	#ifdef CONFIG_SMP
71d218b7	154	cpumask_t affinity;
6a6de9ef	155	unsigned int cpu;
a53da52f	156	#endif
06fcb0c6	157	#if defined(CONFIG_GENERIC_PENDING_IRQ) \|\| defined(CONFIG_IRQBALANCE)
cd916d31	158	cpumask_t pending_mask;
71d218b7	159	unsigned int move_irq; /* need to re-target IRQ dest */
54d5d424	160	#endif
4a733ee1 IM	161	#ifdef CONFIG_PROC_FS
	162	struct proc_dir_entry *dir;
	163	#endif
34ffdb72	164	} ____cacheline_aligned;
1da177e4	165
34ffdb72	166	extern struct irq_desc irq_desc[NR_IRQS];
1da177e4	167
34ffdb72 IM	168	/*
	169	* Migration helpers for obsolete names, they will go away:
	170	*/
6a6de9ef TG	171	#define hw_interrupt_type irq_chip
	172	typedef struct irq_chip hw_irq_controller;
	173	#define no_irq_type no_irq_chip
34ffdb72 IM	174	typedef struct irq_desc irq_desc_t;
	175
	176	/*
	177	* Pick up the arch-dependent methods:
	178	*/
	179	#include <asm/hw_irq.h>
1da177e4	180
06fcb0c6	181	extern int setup_irq(unsigned int irq, struct irqaction *new);
1da177e4 LT	182
1da177e4 LT	183	#ifdef CONFIG_GENERIC_HARDIRQS
06fcb0c6	184
54d5d424 AR	185	#ifdef CONFIG_SMP
	186	static inline void set_native_irq_info(int irq, cpumask_t mask)
	187	{
a53da52f	188	irq_desc[irq].affinity = mask;
54d5d424 AR	189	}
	190	#else
	191	static inline void set_native_irq_info(int irq, cpumask_t mask)
	192	{
	193	}
	194	#endif
	195
	196	#ifdef CONFIG_SMP
	197
06fcb0c6	198	#if defined(CONFIG_GENERIC_PENDING_IRQ) \|\| defined(CONFIG_IRQBALANCE)
54d5d424	199
c777ac55 AM	200	void set_pending_irq(unsigned int irq, cpumask_t mask);
c777ac55 AM	201	void move_native_irq(int irq);
54d5d424 AR	202
	203	#ifdef CONFIG_PCI_MSI
	204	/*
	205	* Wonder why these are dummies?
	206	* For e.g the set_ioapic_affinity_vector() calls the set_ioapic_affinity_irq()
	207	* counter part after translating the vector to irq info. We need to perform
	208	* this operation on the real irq, when we dont use vector, i.e when
	209	* pci_use_vector() is false.
	210	*/
	211	static inline void move_irq(int irq)
	212	{
	213	}
	214
	215	static inline void set_irq_info(int irq, cpumask_t mask)
	216	{
	217	}
	218
06fcb0c6	219	#else /* CONFIG_PCI_MSI */
54d5d424 AR	220
	221	static inline void move_irq(int irq)
	222	{
	223	move_native_irq(irq);
	224	}
	225
	226	static inline void set_irq_info(int irq, cpumask_t mask)
	227	{
	228	set_native_irq_info(irq, mask);
	229	}
54d5d424	230
06fcb0c6 IM	231	#endif /* CONFIG_PCI_MSI */
	232
	233	#else /* CONFIG_GENERIC_PENDING_IRQ \|\| CONFIG_IRQBALANCE */
	234
	235	static inline void move_irq(int irq)
	236	{
	237	}
	238
	239	static inline void move_native_irq(int irq)
	240	{
	241	}
	242
	243	static inline void set_pending_irq(unsigned int irq, cpumask_t mask)
	244	{
	245	}
54d5d424	246
54d5d424 AR	247	static inline void set_irq_info(int irq, cpumask_t mask)
	248	{
	249	set_native_irq_info(irq, mask);
	250	}
	251
06fcb0c6	252	#endif /* CONFIG_GENERIC_PENDING_IRQ */
54d5d424	253
06fcb0c6	254	#else /* CONFIG_SMP */
54d5d424 AR	255
	256	#define move_irq(x)
	257	#define move_native_irq(x)
	258
06fcb0c6	259	#endif /* CONFIG_SMP */
54d5d424	260
1b61b910 ZY	261	#ifdef CONFIG_IRQBALANCE
	262	extern void set_balance_irq_affinity(unsigned int irq, cpumask_t mask);
	263	#else
	264	static inline void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
	265	{
	266	}
	267	#endif
	268
71d218b7 IM	269	#ifdef CONFIG_AUTO_IRQ_AFFINITY
	270	extern int select_smp_affinity(unsigned int irq);
	271	#else
	272	static inline int select_smp_affinity(unsigned int irq)
	273	{
	274	return 1;
	275	}
	276	#endif
	277
1da177e4	278	extern int no_irq_affinity;
1da177e4	279
6a6de9ef TG	280	/* Handle irq action chains: */
	281	extern int handle_IRQ_event(unsigned int irq, struct pt_regs *regs,
	282	struct irqaction *action);
	283
	284	/*
	285	* Built-in IRQ handlers for various IRQ types,
	286	* callable via desc->chip->handle_irq()
	287	*/
	288	extern void fastcall
	289	handle_level_irq(unsigned int irq, struct irq_desc desc, struct pt_regs regs);
	290	extern void fastcall
47c2a3aa	291	handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc,
6a6de9ef TG	292	struct pt_regs *regs);
	293	extern void fastcall
	294	handle_edge_irq(unsigned int irq, struct irq_desc desc, struct pt_regs regs);
	295	extern void fastcall
	296	handle_simple_irq(unsigned int irq, struct irq_desc *desc,
	297	struct pt_regs *regs);
	298	extern void fastcall
	299	handle_percpu_irq(unsigned int irq, struct irq_desc *desc,
	300	struct pt_regs *regs);
	301	extern void fastcall
	302	handle_bad_irq(unsigned int irq, struct irq_desc desc, struct pt_regs regs);
	303
	304	/*
	305	* Get a descriptive string for the highlevel handler, for
	306	* /proc/interrupts output:
	307	*/
	308	extern const char *
	309	handle_irq_name(void fastcall (handle)(unsigned int, struct irq_desc ,
	310	struct pt_regs *));
	311
2e60bbb6	312	/*
6a6de9ef TG	313	* Monolithic do_IRQ implementation.
6a6de9ef TG	314	* (is an explicit fastcall, because i386 4KSTACKS calls it from assembly)
2e60bbb6	315	*/
1da177e4	316	extern fastcall unsigned int __do_IRQ(unsigned int irq, struct pt_regs *regs);
2e60bbb6	317
dae86204 IM	318	/*
	319	* Architectures call this to let the generic IRQ layer
	320	* handle an interrupt. If the descriptor is attached to an
	321	* irqchip-style controller then we call the ->handle_irq() handler,
	322	* and it calls __do_IRQ() if it's attached to an irqtype-style controller.
	323	*/
	324	static inline void generic_handle_irq(unsigned int irq, struct pt_regs *regs)
	325	{
	326	struct irq_desc *desc = irq_desc + irq;
	327
	328	if (likely(desc->handle_irq))
	329	desc->handle_irq(irq, desc, regs);
	330	else
	331	__do_IRQ(irq, regs);
	332	}
	333
6a6de9ef	334	/* Handling of unhandled and spurious interrupts: */
34ffdb72	335	extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
2e60bbb6	336	int action_ret, struct pt_regs *regs);
1da177e4	337
a4633adc TG	338	/* Resending of interrupts :*/
	339	void check_irq_resend(struct irq_desc *desc, unsigned int irq);
	340
6a6de9ef	341	/* Initialize /proc/irq/ */
1da177e4	342	extern void init_irq_proc(void);
eee45269	343
6a6de9ef TG	344	/* Enable/disable irq debugging output: */
	345	extern int noirqdebug_setup(char *str);
	346
	347	/* Checks whether the interrupt can be requested by request_irq(): */
	348	extern int can_request_irq(unsigned int irq, unsigned long irqflags);
	349
f8b5473f	350	/* Dummy irq-chip implementations: */
6a6de9ef	351	extern struct irq_chip no_irq_chip;
f8b5473f	352	extern struct irq_chip dummy_irq_chip;
6a6de9ef TG	353
	354	extern void
	355	set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip,
	356	void fastcall (*handle)(unsigned int,
	357	struct irq_desc *,
	358	struct pt_regs *));
	359	extern void
	360	__set_irq_handler(unsigned int irq,
	361	void fastcall (handle)(unsigned int, struct irq_desc ,
	362	struct pt_regs *),
	363	int is_chained);
1da177e4	364
6a6de9ef TG	365	/*
	366	* Set a highlevel flow handler for a given IRQ:
	367	*/
	368	static inline void
	369	set_irq_handler(unsigned int irq,
	370	void fastcall (handle)(unsigned int, struct irq_desc ,
	371	struct pt_regs *))
	372	{
	373	__set_irq_handler(irq, handle, 0);
	374	}
	375
	376	/*
	377	* Set a highlevel chained flow handler for a given IRQ.
	378	* (a chained handler is automatically enabled and set to
	379	* IRQ_NOREQUEST and IRQ_NOPROBE)
	380	*/
	381	static inline void
	382	set_irq_chained_handler(unsigned int irq,
	383	void fastcall (handle)(unsigned int, struct irq_desc ,
	384	struct pt_regs *))
	385	{
	386	__set_irq_handler(irq, handle, 1);
	387	}
	388
dd87eb3a TG	389	/* Set/get chip/data for an IRQ: */
	390
	391	extern int set_irq_chip(unsigned int irq, struct irq_chip *chip);
	392	extern int set_irq_data(unsigned int irq, void *data);
	393	extern int set_irq_chip_data(unsigned int irq, void *data);
	394	extern int set_irq_type(unsigned int irq, unsigned int type);
	395
	396	#define get_irq_chip(irq) (irq_desc[irq].chip)
	397	#define get_irq_chip_data(irq) (irq_desc[irq].chip_data)
	398	#define get_irq_data(irq) (irq_desc[irq].handler_data)
	399
6a6de9ef	400	#endif /* CONFIG_GENERIC_HARDIRQS */
1da177e4	401
06fcb0c6	402	#endif /* !CONFIG_S390 */
1da177e4	403
06fcb0c6	404	#endif /* _LINUX_IRQ_H */