[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / irq.h

#ifndef _LINUX_IRQ_H
#define _LINUX_IRQ_H

/*
 * Please do not include this file in generic code.  There is currently
 * no requirement for any architecture to implement anything held
 * within this file.
 *
 * Thanks. --rmk
 */

#include <linux/smp.h>

#ifndef CONFIG_S390

#include <linux/linkage.h>
#include <linux/cache.h>
#include <linux/spinlock.h>
#include <linux/cpumask.h>
#include <linux/irqreturn.h>

#include <asm/irq.h>
#include <asm/ptrace.h>

/*
 * IRQ line status.
 *
 * Bits 0-16 are reserved for the IRQF_* bits in linux/interrupt.h
 *
 * IRQ types
 */
#define IRQ_TYPE_NONE		0x00000000	/* Default, unspecified type */
#define IRQ_TYPE_EDGE_RISING	0x00000001	/* Edge rising type */
#define IRQ_TYPE_EDGE_FALLING	0x00000002	/* Edge falling type */
#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
#define IRQ_TYPE_LEVEL_HIGH	0x00000004	/* Level high type */
#define IRQ_TYPE_LEVEL_LOW	0x00000008	/* Level low type */
#define IRQ_TYPE_SENSE_MASK	0x0000000f	/* Mask of the above */
#define IRQ_TYPE_PROBE		0x00000010	/* Probing in progress */

/* Internal flags */
#define IRQ_INPROGRESS		0x00010000	/* IRQ handler active - do not enter! */
#define IRQ_DISABLED		0x00020000	/* IRQ disabled - do not enter! */
#define IRQ_PENDING		0x00040000	/* IRQ pending - replay on enable */
#define IRQ_REPLAY		0x00080000	/* IRQ has been replayed but not acked yet */
#define IRQ_AUTODETECT		0x00100000	/* IRQ is being autodetected */
#define IRQ_WAITING		0x00200000	/* IRQ not yet seen - for autodetection */
#define IRQ_LEVEL		0x00400000	/* IRQ level triggered */
#define IRQ_MASKED		0x00800000	/* IRQ masked - shouldn't be seen again */
#define IRQ_PER_CPU		0x01000000	/* IRQ is per CPU */
#ifdef CONFIG_IRQ_PER_CPU
# define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU)
#else
# define CHECK_IRQ_PER_CPU(var) 0
#endif

#define IRQ_NOPROBE		0x02000000	/* IRQ is not valid for probing */
#define IRQ_NOREQUEST		0x04000000	/* IRQ cannot be requested */
#define IRQ_NOAUTOEN		0x08000000	/* IRQ will not be enabled on request irq */
#define IRQ_DELAYED_DISABLE	0x10000000	/* IRQ disable (masking) happens delayed. */
#define IRQ_WAKEUP		0x20000000	/* IRQ triggers system wakeup */
#define IRQ_MOVE_PENDING	0x40000000	/* need to re-target IRQ destination */

struct proc_dir_entry;

/**
 * struct irq_chip - hardware interrupt chip descriptor
 *
 * @name:		name for /proc/interrupts
 * @startup:		start up the interrupt (defaults to ->enable if NULL)
 * @shutdown:		shut down the interrupt (defaults to ->disable if NULL)
 * @enable:		enable the interrupt (defaults to chip->unmask if NULL)
 * @disable:		disable the interrupt (defaults to chip->mask if NULL)
 * @ack:		start of a new interrupt
 * @mask:		mask an interrupt source
 * @mask_ack:		ack and mask an interrupt source
 * @unmask:		unmask an interrupt source
 * @eoi:		end of interrupt - chip level
 * @end:		end of interrupt - flow level
 * @set_affinity:	set the CPU affinity on SMP machines
 * @retrigger:		resend an IRQ to the CPU
 * @set_type:		set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
 * @set_wake:		enable/disable power-management wake-on of an IRQ
 *
 * @release:		release function solely used by UML
 * @typename:		obsoleted by name, kept as migration helper
 */
struct irq_chip {
	const char	*name;
	unsigned int	(*startup)(unsigned int irq);
	void		(*shutdown)(unsigned int irq);
	void		(*enable)(unsigned int irq);
	void		(*disable)(unsigned int irq);

	void		(*ack)(unsigned int irq);
	void		(*mask)(unsigned int irq);
	void		(*mask_ack)(unsigned int irq);
	void		(*unmask)(unsigned int irq);
	void		(*eoi)(unsigned int irq);

	void		(*end)(unsigned int irq);
	void		(*set_affinity)(unsigned int irq, cpumask_t dest);
	int		(*retrigger)(unsigned int irq);
	int		(*set_type)(unsigned int irq, unsigned int flow_type);
	int		(*set_wake)(unsigned int irq, unsigned int on);

	/* Currently used only by UML, might disappear one day.*/
#ifdef CONFIG_IRQ_RELEASE_METHOD
	void		(*release)(unsigned int irq, void *dev_id);
#endif
	/*
	 * For compatibility, ->typename is copied into ->name.
	 * Will disappear.
	 */
	const char	*typename;
};

/**
 * struct irq_desc - interrupt descriptor
 *
 * @handle_irq:		highlevel irq-events handler [if NULL, __do_IRQ()]
 * @chip:		low level interrupt hardware access
 * @handler_data:	per-IRQ data for the irq_chip methods
 * @chip_data:		platform-specific per-chip private data for the chip
 *			methods, to allow shared chip implementations
 * @action:		the irq action chain
 * @status:		status information
 * @depth:		disable-depth, for nested irq_disable() calls
 * @wake_depth:		enable depth, for multiple set_irq_wake() callers
 * @irq_count:		stats field to detect stalled irqs
 * @irqs_unhandled:	stats field for spurious unhandled interrupts
 * @lock:		locking for SMP
 * @affinity:		IRQ affinity on SMP
 * @cpu:		cpu index useful for balancing
 * @pending_mask:	pending rebalanced interrupts
 * @dir:		/proc/irq/ procfs entry
 * @affinity_entry:	/proc/irq/smp_affinity procfs entry on SMP
 *
 * Pad this out to 32 bytes for cache and indexing reasons.
 */
struct irq_desc {
	void fastcall		(*handle_irq)(unsigned int irq,
					      struct irq_desc *desc,
					      struct pt_regs *regs);
	struct irq_chip		*chip;
	void			*handler_data;
	void			*chip_data;
	struct irqaction	*action;	/* IRQ action list */
	unsigned int		status;		/* IRQ status */

	unsigned int		depth;		/* nested irq disables */
	unsigned int		wake_depth;	/* nested wake enables */
	unsigned int		irq_count;	/* For detecting broken IRQs */
	unsigned int		irqs_unhandled;
	spinlock_t		lock;
#ifdef CONFIG_SMP
	cpumask_t		affinity;
	unsigned int		cpu;
#endif
#if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
	cpumask_t		pending_mask;
#endif
#ifdef CONFIG_PROC_FS
	struct proc_dir_entry *dir;
#endif
} ____cacheline_aligned;

extern struct irq_desc irq_desc[NR_IRQS];

/*
 * Migration helpers for obsolete names, they will go away:
 */
#define hw_interrupt_type	irq_chip
typedef struct irq_chip		hw_irq_controller;
#define no_irq_type		no_irq_chip
typedef struct irq_desc		irq_desc_t;

/*
 * Pick up the arch-dependent methods:
 */
#include <asm/hw_irq.h>

extern int setup_irq(unsigned int irq, struct irqaction *new);

#ifdef CONFIG_GENERIC_HARDIRQS

#ifndef handle_dynamic_tick
# define handle_dynamic_tick(a)		do { } while (0)
#endif

#ifdef CONFIG_SMP
static inline void set_native_irq_info(int irq, cpumask_t mask)
{
	irq_desc[irq].affinity = mask;
}
#else
static inline void set_native_irq_info(int irq, cpumask_t mask)
{
}
#endif

#ifdef CONFIG_SMP

#if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)

void set_pending_irq(unsigned int irq, cpumask_t mask);
void move_native_irq(int irq);

#ifdef CONFIG_PCI_MSI
/*
 * Wonder why these are dummies?
 * For e.g the set_ioapic_affinity_vector() calls the set_ioapic_affinity_irq()
 * counter part after translating the vector to irq info. We need to perform
 * this operation on the real irq, when we dont use vector, i.e when
 * pci_use_vector() is false.
 */
static inline void move_irq(int irq)
{
}

static inline void set_irq_info(int irq, cpumask_t mask)
{
}

#else /* CONFIG_PCI_MSI */

static inline void move_irq(int irq)
{
	move_native_irq(irq);
}

static inline void set_irq_info(int irq, cpumask_t mask)
{
	set_native_irq_info(irq, mask);
}

#endif /* CONFIG_PCI_MSI */

#else /* CONFIG_GENERIC_PENDING_IRQ || CONFIG_IRQBALANCE */

static inline void move_irq(int irq)
{
}

static inline void move_native_irq(int irq)
{
}

static inline void set_pending_irq(unsigned int irq, cpumask_t mask)
{
}

static inline void set_irq_info(int irq, cpumask_t mask)
{
	set_native_irq_info(irq, mask);
}

#endif /* CONFIG_GENERIC_PENDING_IRQ */

#else /* CONFIG_SMP */

#define move_irq(x)
#define move_native_irq(x)

#endif /* CONFIG_SMP */

#ifdef CONFIG_IRQBALANCE
extern void set_balance_irq_affinity(unsigned int irq, cpumask_t mask);
#else
static inline void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
{
}
#endif

#ifdef CONFIG_AUTO_IRQ_AFFINITY
extern int select_smp_affinity(unsigned int irq);
#else
static inline int select_smp_affinity(unsigned int irq)
{
	return 1;
}
#endif

extern int no_irq_affinity;

/* Handle irq action chains: */
extern int handle_IRQ_event(unsigned int irq, struct pt_regs *regs,
			    struct irqaction *action);

/*
 * Built-in IRQ handlers for various IRQ types,
 * callable via desc->chip->handle_irq()
 */
extern void fastcall
handle_level_irq(unsigned int irq, struct irq_desc *desc, struct pt_regs *regs);
extern void fastcall
handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc,
			 struct pt_regs *regs);
extern void fastcall
handle_edge_irq(unsigned int irq, struct irq_desc *desc, struct pt_regs *regs);
extern void fastcall
handle_simple_irq(unsigned int irq, struct irq_desc *desc,
		  struct pt_regs *regs);
extern void fastcall
handle_percpu_irq(unsigned int irq, struct irq_desc *desc,
		  struct pt_regs *regs);
extern void fastcall
handle_bad_irq(unsigned int irq, struct irq_desc *desc, struct pt_regs *regs);

/*
 * Get a descriptive string for the highlevel handler, for
 * /proc/interrupts output:
 */
extern const char *
handle_irq_name(void fastcall (*handle)(unsigned int, struct irq_desc *,
					struct pt_regs *));

/*
 * Monolithic do_IRQ implementation.
 * (is an explicit fastcall, because i386 4KSTACKS calls it from assembly)
 */
#ifndef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ
extern fastcall unsigned int __do_IRQ(unsigned int irq, struct pt_regs *regs);
#endif

/*
 * Architectures call this to let the generic IRQ layer
 * handle an interrupt. If the descriptor is attached to an
 * irqchip-style controller then we call the ->handle_irq() handler,
 * and it calls __do_IRQ() if it's attached to an irqtype-style controller.
 */
static inline void generic_handle_irq(unsigned int irq, struct pt_regs *regs)
{
	struct irq_desc *desc = irq_desc + irq;

#ifdef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ
	desc->handle_irq(irq, desc, regs);
#else
	if (likely(desc->handle_irq))
		desc->handle_irq(irq, desc, regs);
	else
		__do_IRQ(irq, regs);
#endif
}

/* Handling of unhandled and spurious interrupts: */
extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
			   int action_ret, struct pt_regs *regs);

/* Resending of interrupts :*/
void check_irq_resend(struct irq_desc *desc, unsigned int irq);

/* Initialize /proc/irq/ */
extern void init_irq_proc(void);

/* Enable/disable irq debugging output: */
extern int noirqdebug_setup(char *str);

/* Checks whether the interrupt can be requested by request_irq(): */
extern int can_request_irq(unsigned int irq, unsigned long irqflags);

/* Dummy irq-chip implementations: */
extern struct irq_chip no_irq_chip;
extern struct irq_chip dummy_irq_chip;

extern void
set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip,
			 void fastcall (*handle)(unsigned int,
						 struct irq_desc *,
						 struct pt_regs *));
extern void
__set_irq_handler(unsigned int irq,
		  void fastcall (*handle)(unsigned int, struct irq_desc *,
					  struct pt_regs *),
		  int is_chained);

/*
 * Set a highlevel flow handler for a given IRQ:
 */
static inline void
set_irq_handler(unsigned int irq,
		void fastcall (*handle)(unsigned int, struct irq_desc *,
					struct pt_regs *))
{
	__set_irq_handler(irq, handle, 0);
}

/*
 * Set a highlevel chained flow handler for a given IRQ.
 * (a chained handler is automatically enabled and set to
 *  IRQ_NOREQUEST and IRQ_NOPROBE)
 */
static inline void
set_irq_chained_handler(unsigned int irq,
			void fastcall (*handle)(unsigned int, struct irq_desc *,
						struct pt_regs *))
{
	__set_irq_handler(irq, handle, 1);
}

/* Set/get chip/data for an IRQ: */

extern int set_irq_chip(unsigned int irq, struct irq_chip *chip);
extern int set_irq_data(unsigned int irq, void *data);
extern int set_irq_chip_data(unsigned int irq, void *data);
extern int set_irq_type(unsigned int irq, unsigned int type);

#define get_irq_chip(irq)	(irq_desc[irq].chip)
#define get_irq_chip_data(irq)	(irq_desc[irq].chip_data)
#define get_irq_data(irq)	(irq_desc[irq].handler_data)

#endif /* CONFIG_GENERIC_HARDIRQS */

#endif /* !CONFIG_S390 */

#endif /* _LINUX_IRQ_H */
Commit	Line	Data
06fcb0c6 IM	1	#ifndef _LINUX_IRQ_H
06fcb0c6 IM	2	#define _LINUX_IRQ_H
1da177e4 LT	3
	4	/*
	5	* Please do not include this file in generic code. There is currently
	6	* no requirement for any architecture to implement anything held
	7	* within this file.
	8	*
	9	* Thanks. --rmk
	10	*/
	11
23f9b317	12	#include <linux/smp.h>
1da177e4	13
06fcb0c6	14	#ifndef CONFIG_S390
1da177e4 LT	15
	16	#include <linux/linkage.h>
	17	#include <linux/cache.h>
	18	#include <linux/spinlock.h>
	19	#include <linux/cpumask.h>
908dcecd	20	#include <linux/irqreturn.h>
1da177e4 LT	21
	22	#include <asm/irq.h>
	23	#include <asm/ptrace.h>
	24
	25	/*
	26	* IRQ line status.
6e213616 TG	27	*
	28	* Bits 0-16 are reserved for the IRQF_* bits in linux/interrupt.h
	29	*
	30	* IRQ types
1da177e4	31	*/
6e213616 TG	32	#define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */
	33	#define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */
	34	#define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */
	35	#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING)
	36	#define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */
	37	#define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */
	38	#define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */
	39	#define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */
	40
	41	/* Internal flags */
	42	#define IRQ_INPROGRESS 0x00010000 /* IRQ handler active - do not enter! */
	43	#define IRQ_DISABLED 0x00020000 /* IRQ disabled - do not enter! */
	44	#define IRQ_PENDING 0x00040000 /* IRQ pending - replay on enable */
	45	#define IRQ_REPLAY 0x00080000 /* IRQ has been replayed but not acked yet */
	46	#define IRQ_AUTODETECT 0x00100000 /* IRQ is being autodetected */
	47	#define IRQ_WAITING 0x00200000 /* IRQ not yet seen - for autodetection */
	48	#define IRQ_LEVEL 0x00400000 /* IRQ level triggered */
	49	#define IRQ_MASKED 0x00800000 /* IRQ masked - shouldn't be seen again */
b8bdb460	50	#define IRQ_PER_CPU 0x01000000 /* IRQ is per CPU */
0d7012a9	51	#ifdef CONFIG_IRQ_PER_CPU
f26fdd59 KW	52	# define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU)
	53	#else
	54	# define CHECK_IRQ_PER_CPU(var) 0
	55	#endif
1da177e4	56
6e213616 TG	57	#define IRQ_NOPROBE 0x02000000 /* IRQ is not valid for probing */
	58	#define IRQ_NOREQUEST 0x04000000 /* IRQ cannot be requested */
	59	#define IRQ_NOAUTOEN 0x08000000 /* IRQ will not be enabled on request irq */
	60	#define IRQ_DELAYED_DISABLE 0x10000000 /* IRQ disable (masking) happens delayed. */
15a647eb	61	#define IRQ_WAKEUP 0x20000000 /* IRQ triggers system wakeup */
a24ceab4	62	#define IRQ_MOVE_PENDING 0x40000000 /* need to re-target IRQ destination */
6a6de9ef TG	63
	64	struct proc_dir_entry;
	65
8fee5c36	66	/**
6a6de9ef	67	* struct irq_chip - hardware interrupt chip descriptor
8fee5c36 IM	68	*
	69	* @name: name for /proc/interrupts
	70	* @startup: start up the interrupt (defaults to ->enable if NULL)
	71	* @shutdown: shut down the interrupt (defaults to ->disable if NULL)
	72	* @enable: enable the interrupt (defaults to chip->unmask if NULL)
	73	* @disable: disable the interrupt (defaults to chip->mask if NULL)
8fee5c36 IM	74	* @ack: start of a new interrupt
	75	* @mask: mask an interrupt source
	76	* @mask_ack: ack and mask an interrupt source
	77	* @unmask: unmask an interrupt source
47c2a3aa IM	78	* @eoi: end of interrupt - chip level
47c2a3aa IM	79	* @end: end of interrupt - flow level
8fee5c36 IM	80	* @set_affinity: set the CPU affinity on SMP machines
	81	* @retrigger: resend an IRQ to the CPU
	82	* @set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
	83	* @set_wake: enable/disable power-management wake-on of an IRQ
	84	*
	85	* @release: release function solely used by UML
6a6de9ef	86	* @typename: obsoleted by name, kept as migration helper
1da177e4	87	*/
6a6de9ef TG	88	struct irq_chip {
6a6de9ef TG	89	const char *name;
71d218b7 IM	90	unsigned int (*startup)(unsigned int irq);
	91	void (*shutdown)(unsigned int irq);
	92	void (*enable)(unsigned int irq);
	93	void (*disable)(unsigned int irq);
6a6de9ef	94
71d218b7	95	void (*ack)(unsigned int irq);
6a6de9ef TG	96	void (*mask)(unsigned int irq);
	97	void (*mask_ack)(unsigned int irq);
	98	void (*unmask)(unsigned int irq);
47c2a3aa	99	void (*eoi)(unsigned int irq);
6a6de9ef	100
71d218b7 IM	101	void (*end)(unsigned int irq);
71d218b7 IM	102	void (*set_affinity)(unsigned int irq, cpumask_t dest);
c0ad90a3	103	int (*retrigger)(unsigned int irq);
6a6de9ef TG	104	int (*set_type)(unsigned int irq, unsigned int flow_type);
6a6de9ef TG	105	int (*set_wake)(unsigned int irq, unsigned int on);
c0ad90a3	106
b77d6adc PBG	107	/* Currently used only by UML, might disappear one day.*/
b77d6adc PBG	108	#ifdef CONFIG_IRQ_RELEASE_METHOD
71d218b7	109	void (release)(unsigned int irq, void dev_id);
b77d6adc	110	#endif
6a6de9ef TG	111	/*
	112	* For compatibility, ->typename is copied into ->name.
	113	* Will disappear.
	114	*/
	115	const char *typename;
1da177e4 LT	116	};
1da177e4 LT	117
8fee5c36 IM	118	/**
	119	* struct irq_desc - interrupt descriptor
	120	*
6a6de9ef TG	121	* @handle_irq: highlevel irq-events handler [if NULL, __do_IRQ()]
	122	* @chip: low level interrupt hardware access
	123	* @handler_data: per-IRQ data for the irq_chip methods
	124	* @chip_data: platform-specific per-chip private data for the chip
	125	* methods, to allow shared chip implementations
8fee5c36 IM	126	* @action: the irq action chain
	127	* @status: status information
	128	* @depth: disable-depth, for nested irq_disable() calls
15a647eb	129	* @wake_depth: enable depth, for multiple set_irq_wake() callers
8fee5c36 IM	130	* @irq_count: stats field to detect stalled irqs
	131	* @irqs_unhandled: stats field for spurious unhandled interrupts
	132	* @lock: locking for SMP
	133	* @affinity: IRQ affinity on SMP
6a6de9ef	134	* @cpu: cpu index useful for balancing
8fee5c36	135	* @pending_mask: pending rebalanced interrupts
8fee5c36 IM	136	* @dir: /proc/irq/ procfs entry
8fee5c36 IM	137	* @affinity_entry: /proc/irq/smp_affinity procfs entry on SMP
1da177e4 LT	138	*
	139	* Pad this out to 32 bytes for cache and indexing reasons.
	140	*/
34ffdb72	141	struct irq_desc {
6a6de9ef TG	142	void fastcall (*handle_irq)(unsigned int irq,
	143	struct irq_desc *desc,
	144	struct pt_regs *regs);
	145	struct irq_chip *chip;
	146	void *handler_data;
71d218b7 IM	147	void *chip_data;
	148	struct irqaction action; / IRQ action list */
	149	unsigned int status; /* IRQ status */
6a6de9ef	150
71d218b7	151	unsigned int depth; /* nested irq disables */
15a647eb	152	unsigned int wake_depth; /* nested wake enables */
71d218b7 IM	153	unsigned int irq_count; /* For detecting broken IRQs */
	154	unsigned int irqs_unhandled;
	155	spinlock_t lock;
a53da52f	156	#ifdef CONFIG_SMP
71d218b7	157	cpumask_t affinity;
6a6de9ef	158	unsigned int cpu;
a53da52f	159	#endif
06fcb0c6	160	#if defined(CONFIG_GENERIC_PENDING_IRQ) \|\| defined(CONFIG_IRQBALANCE)
cd916d31	161	cpumask_t pending_mask;
54d5d424	162	#endif
4a733ee1 IM	163	#ifdef CONFIG_PROC_FS
	164	struct proc_dir_entry *dir;
	165	#endif
34ffdb72	166	} ____cacheline_aligned;
1da177e4	167
34ffdb72	168	extern struct irq_desc irq_desc[NR_IRQS];
1da177e4	169
34ffdb72 IM	170	/*
	171	* Migration helpers for obsolete names, they will go away:
	172	*/
6a6de9ef TG	173	#define hw_interrupt_type irq_chip
	174	typedef struct irq_chip hw_irq_controller;
	175	#define no_irq_type no_irq_chip
34ffdb72 IM	176	typedef struct irq_desc irq_desc_t;
	177
	178	/*
	179	* Pick up the arch-dependent methods:
	180	*/
	181	#include <asm/hw_irq.h>
1da177e4	182
06fcb0c6	183	extern int setup_irq(unsigned int irq, struct irqaction *new);
1da177e4 LT	184
1da177e4 LT	185	#ifdef CONFIG_GENERIC_HARDIRQS
06fcb0c6	186
d061daa0 TG	187	#ifndef handle_dynamic_tick
	188	# define handle_dynamic_tick(a) do { } while (0)
	189	#endif
	190
54d5d424 AR	191	#ifdef CONFIG_SMP
	192	static inline void set_native_irq_info(int irq, cpumask_t mask)
	193	{
a53da52f	194	irq_desc[irq].affinity = mask;
54d5d424 AR	195	}
	196	#else
	197	static inline void set_native_irq_info(int irq, cpumask_t mask)
	198	{
	199	}
	200	#endif
	201
	202	#ifdef CONFIG_SMP
	203
06fcb0c6	204	#if defined(CONFIG_GENERIC_PENDING_IRQ) \|\| defined(CONFIG_IRQBALANCE)
54d5d424	205
c777ac55 AM	206	void set_pending_irq(unsigned int irq, cpumask_t mask);
c777ac55 AM	207	void move_native_irq(int irq);
54d5d424 AR	208
	209	#ifdef CONFIG_PCI_MSI
	210	/*
	211	* Wonder why these are dummies?
	212	* For e.g the set_ioapic_affinity_vector() calls the set_ioapic_affinity_irq()
	213	* counter part after translating the vector to irq info. We need to perform
	214	* this operation on the real irq, when we dont use vector, i.e when
	215	* pci_use_vector() is false.
	216	*/
	217	static inline void move_irq(int irq)
	218	{
	219	}
	220
	221	static inline void set_irq_info(int irq, cpumask_t mask)
	222	{
	223	}
	224
06fcb0c6	225	#else /* CONFIG_PCI_MSI */
54d5d424 AR	226
	227	static inline void move_irq(int irq)
	228	{
	229	move_native_irq(irq);
	230	}
	231
	232	static inline void set_irq_info(int irq, cpumask_t mask)
	233	{
	234	set_native_irq_info(irq, mask);
	235	}
54d5d424	236
06fcb0c6 IM	237	#endif /* CONFIG_PCI_MSI */
	238
	239	#else /* CONFIG_GENERIC_PENDING_IRQ \|\| CONFIG_IRQBALANCE */
	240
	241	static inline void move_irq(int irq)
	242	{
	243	}
	244
	245	static inline void move_native_irq(int irq)
	246	{
	247	}
	248
	249	static inline void set_pending_irq(unsigned int irq, cpumask_t mask)
	250	{
	251	}
54d5d424	252
54d5d424 AR	253	static inline void set_irq_info(int irq, cpumask_t mask)
	254	{
	255	set_native_irq_info(irq, mask);
	256	}
	257
06fcb0c6	258	#endif /* CONFIG_GENERIC_PENDING_IRQ */
54d5d424	259
06fcb0c6	260	#else /* CONFIG_SMP */
54d5d424 AR	261
	262	#define move_irq(x)
	263	#define move_native_irq(x)
	264
06fcb0c6	265	#endif /* CONFIG_SMP */
54d5d424	266
1b61b910 ZY	267	#ifdef CONFIG_IRQBALANCE
	268	extern void set_balance_irq_affinity(unsigned int irq, cpumask_t mask);
	269	#else
	270	static inline void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
	271	{
	272	}
	273	#endif
	274
71d218b7 IM	275	#ifdef CONFIG_AUTO_IRQ_AFFINITY
	276	extern int select_smp_affinity(unsigned int irq);
	277	#else
	278	static inline int select_smp_affinity(unsigned int irq)
	279	{
	280	return 1;
	281	}
	282	#endif
	283
1da177e4	284	extern int no_irq_affinity;
1da177e4	285
6a6de9ef TG	286	/* Handle irq action chains: */
	287	extern int handle_IRQ_event(unsigned int irq, struct pt_regs *regs,
	288	struct irqaction *action);
	289
	290	/*
	291	* Built-in IRQ handlers for various IRQ types,
	292	* callable via desc->chip->handle_irq()
	293	*/
	294	extern void fastcall
	295	handle_level_irq(unsigned int irq, struct irq_desc desc, struct pt_regs regs);
	296	extern void fastcall
47c2a3aa	297	handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc,
6a6de9ef TG	298	struct pt_regs *regs);
	299	extern void fastcall
	300	handle_edge_irq(unsigned int irq, struct irq_desc desc, struct pt_regs regs);
	301	extern void fastcall
	302	handle_simple_irq(unsigned int irq, struct irq_desc *desc,
	303	struct pt_regs *regs);
	304	extern void fastcall
	305	handle_percpu_irq(unsigned int irq, struct irq_desc *desc,
	306	struct pt_regs *regs);
	307	extern void fastcall
	308	handle_bad_irq(unsigned int irq, struct irq_desc desc, struct pt_regs regs);
	309
	310	/*
	311	* Get a descriptive string for the highlevel handler, for
	312	* /proc/interrupts output:
	313	*/
	314	extern const char *
	315	handle_irq_name(void fastcall (handle)(unsigned int, struct irq_desc ,
	316	struct pt_regs *));
	317
2e60bbb6	318	/*
6a6de9ef TG	319	* Monolithic do_IRQ implementation.
6a6de9ef TG	320	* (is an explicit fastcall, because i386 4KSTACKS calls it from assembly)
2e60bbb6	321	*/
af8c65b5	322	#ifndef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ
1da177e4	323	extern fastcall unsigned int __do_IRQ(unsigned int irq, struct pt_regs *regs);
af8c65b5	324	#endif
2e60bbb6	325
dae86204 IM	326	/*
	327	* Architectures call this to let the generic IRQ layer
	328	* handle an interrupt. If the descriptor is attached to an
	329	* irqchip-style controller then we call the ->handle_irq() handler,
	330	* and it calls __do_IRQ() if it's attached to an irqtype-style controller.
	331	*/
	332	static inline void generic_handle_irq(unsigned int irq, struct pt_regs *regs)
	333	{
	334	struct irq_desc *desc = irq_desc + irq;
	335
af8c65b5 DH	336	#ifdef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ
	337	desc->handle_irq(irq, desc, regs);
	338	#else
dae86204 IM	339	if (likely(desc->handle_irq))
	340	desc->handle_irq(irq, desc, regs);
	341	else
	342	__do_IRQ(irq, regs);
af8c65b5	343	#endif
dae86204 IM	344	}
dae86204 IM	345
6a6de9ef	346	/* Handling of unhandled and spurious interrupts: */
34ffdb72	347	extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
2e60bbb6	348	int action_ret, struct pt_regs *regs);
1da177e4	349
a4633adc TG	350	/* Resending of interrupts :*/
	351	void check_irq_resend(struct irq_desc *desc, unsigned int irq);
	352
6a6de9ef	353	/* Initialize /proc/irq/ */
1da177e4	354	extern void init_irq_proc(void);
eee45269	355
6a6de9ef TG	356	/* Enable/disable irq debugging output: */
	357	extern int noirqdebug_setup(char *str);
	358
	359	/* Checks whether the interrupt can be requested by request_irq(): */
	360	extern int can_request_irq(unsigned int irq, unsigned long irqflags);
	361
f8b5473f	362	/* Dummy irq-chip implementations: */
6a6de9ef	363	extern struct irq_chip no_irq_chip;
f8b5473f	364	extern struct irq_chip dummy_irq_chip;
6a6de9ef TG	365
	366	extern void
	367	set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip,
	368	void fastcall (*handle)(unsigned int,
	369	struct irq_desc *,
	370	struct pt_regs *));
	371	extern void
	372	__set_irq_handler(unsigned int irq,
	373	void fastcall (handle)(unsigned int, struct irq_desc ,
	374	struct pt_regs *),
	375	int is_chained);
1da177e4	376
6a6de9ef TG	377	/*
	378	* Set a highlevel flow handler for a given IRQ:
	379	*/
	380	static inline void
	381	set_irq_handler(unsigned int irq,
	382	void fastcall (handle)(unsigned int, struct irq_desc ,
	383	struct pt_regs *))
	384	{
	385	__set_irq_handler(irq, handle, 0);
	386	}
	387
	388	/*
	389	* Set a highlevel chained flow handler for a given IRQ.
	390	* (a chained handler is automatically enabled and set to
	391	* IRQ_NOREQUEST and IRQ_NOPROBE)
	392	*/
	393	static inline void
	394	set_irq_chained_handler(unsigned int irq,
	395	void fastcall (handle)(unsigned int, struct irq_desc ,
	396	struct pt_regs *))
	397	{
	398	__set_irq_handler(irq, handle, 1);
	399	}
	400
dd87eb3a TG	401	/* Set/get chip/data for an IRQ: */
	402
	403	extern int set_irq_chip(unsigned int irq, struct irq_chip *chip);
	404	extern int set_irq_data(unsigned int irq, void *data);
	405	extern int set_irq_chip_data(unsigned int irq, void *data);
	406	extern int set_irq_type(unsigned int irq, unsigned int type);
	407
	408	#define get_irq_chip(irq) (irq_desc[irq].chip)
	409	#define get_irq_chip_data(irq) (irq_desc[irq].chip_data)
	410	#define get_irq_data(irq) (irq_desc[irq].handler_data)
	411
6a6de9ef	412	#endif /* CONFIG_GENERIC_HARDIRQS */
1da177e4	413
06fcb0c6	414	#endif /* !CONFIG_S390 */
1da177e4	415
06fcb0c6	416	#endif /* _LINUX_IRQ_H */