[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / irq.h

#ifndef _LINUX_IRQ_H
#define _LINUX_IRQ_H

/*
 * Please do not include this file in generic code.  There is currently
 * no requirement for any architecture to implement anything held
 * within this file.
 *
 * Thanks. --rmk
 */

#include <linux/smp.h>

#ifndef CONFIG_S390

#include <linux/linkage.h>
#include <linux/cache.h>
#include <linux/spinlock.h>
#include <linux/cpumask.h>
#include <linux/irqreturn.h>
#include <linux/irqnr.h>
#include <linux/errno.h>
#include <linux/wait.h>

#include <asm/irq.h>
#include <asm/ptrace.h>
#include <asm/irq_regs.h>

struct irq_desc;
typedef	void (*irq_flow_handler_t)(unsigned int irq,
					    struct irq_desc *desc);


/*
 * IRQ line status.
 *
 * Bits 0-7 are reserved for the IRQF_* bits in linux/interrupt.h
 *
 * IRQ types
 */
#define IRQ_TYPE_NONE		0x00000000	/* Default, unspecified type */
#define IRQ_TYPE_EDGE_RISING	0x00000001	/* Edge rising type */
#define IRQ_TYPE_EDGE_FALLING	0x00000002	/* Edge falling type */
#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
#define IRQ_TYPE_LEVEL_HIGH	0x00000004	/* Level high type */
#define IRQ_TYPE_LEVEL_LOW	0x00000008	/* Level low type */
#define IRQ_TYPE_SENSE_MASK	0x0000000f	/* Mask of the above */
#define IRQ_TYPE_PROBE		0x00000010	/* Probing in progress */

/* Internal flags */
#define IRQ_INPROGRESS		0x00000100	/* IRQ handler active - do not enter! */
#define IRQ_DISABLED		0x00000200	/* IRQ disabled - do not enter! */
#define IRQ_PENDING		0x00000400	/* IRQ pending - replay on enable */
#define IRQ_REPLAY		0x00000800	/* IRQ has been replayed but not acked yet */
#define IRQ_AUTODETECT		0x00001000	/* IRQ is being autodetected */
#define IRQ_WAITING		0x00002000	/* IRQ not yet seen - for autodetection */
#define IRQ_LEVEL		0x00004000	/* IRQ level triggered */
#define IRQ_MASKED		0x00008000	/* IRQ masked - shouldn't be seen again */
#define IRQ_PER_CPU		0x00010000	/* IRQ is per CPU */
#define IRQ_NOPROBE		0x00020000	/* IRQ is not valid for probing */
#define IRQ_NOREQUEST		0x00040000	/* IRQ cannot be requested */
#define IRQ_NOAUTOEN		0x00080000	/* IRQ will not be enabled on request irq */
#define IRQ_WAKEUP		0x00100000	/* IRQ triggers system wakeup */
#define IRQ_MOVE_PENDING	0x00200000	/* need to re-target IRQ destination */
#define IRQ_NO_BALANCING	0x00400000	/* IRQ is excluded from balancing */
#define IRQ_SPURIOUS_DISABLED	0x00800000	/* IRQ was disabled by the spurious trap */
#define IRQ_MOVE_PCNTXT		0x01000000	/* IRQ migration from process context */
#define IRQ_AFFINITY_SET	0x02000000	/* IRQ affinity was set from userspace*/

#ifdef CONFIG_IRQ_PER_CPU
# define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU)
# define IRQ_NO_BALANCING_MASK	(IRQ_PER_CPU | IRQ_NO_BALANCING)
#else
# define CHECK_IRQ_PER_CPU(var) 0
# define IRQ_NO_BALANCING_MASK	IRQ_NO_BALANCING
#endif

struct proc_dir_entry;
struct msi_desc;

/**
 * struct irq_chip - hardware interrupt chip descriptor
 *
 * @name:		name for /proc/interrupts
 * @startup:		start up the interrupt (defaults to ->enable if NULL)
 * @shutdown:		shut down the interrupt (defaults to ->disable if NULL)
 * @enable:		enable the interrupt (defaults to chip->unmask if NULL)
 * @disable:		disable the interrupt (defaults to chip->mask if NULL)
 * @ack:		start of a new interrupt
 * @mask:		mask an interrupt source
 * @mask_ack:		ack and mask an interrupt source
 * @unmask:		unmask an interrupt source
 * @eoi:		end of interrupt - chip level
 * @end:		end of interrupt - flow level
 * @set_affinity:	set the CPU affinity on SMP machines
 * @retrigger:		resend an IRQ to the CPU
 * @set_type:		set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
 * @set_wake:		enable/disable power-management wake-on of an IRQ
 *
 * @release:		release function solely used by UML
 * @typename:		obsoleted by name, kept as migration helper
 */
struct irq_chip {
	const char	*name;
	unsigned int	(*startup)(unsigned int irq);
	void		(*shutdown)(unsigned int irq);
	void		(*enable)(unsigned int irq);
	void		(*disable)(unsigned int irq);

	void		(*ack)(unsigned int irq);
	void		(*mask)(unsigned int irq);
	void		(*mask_ack)(unsigned int irq);
	void		(*unmask)(unsigned int irq);
	void		(*eoi)(unsigned int irq);

	void		(*end)(unsigned int irq);
	void		(*set_affinity)(unsigned int irq,
					const struct cpumask *dest);
	int		(*retrigger)(unsigned int irq);
	int		(*set_type)(unsigned int irq, unsigned int flow_type);
	int		(*set_wake)(unsigned int irq, unsigned int on);

	/* Currently used only by UML, might disappear one day.*/
#ifdef CONFIG_IRQ_RELEASE_METHOD
	void		(*release)(unsigned int irq, void *dev_id);
#endif
	/*
	 * For compatibility, ->typename is copied into ->name.
	 * Will disappear.
	 */
	const char	*typename;
};

struct timer_rand_state;
struct irq_2_iommu;
/**
 * struct irq_desc - interrupt descriptor
 * @irq:		interrupt number for this descriptor
 * @timer_rand_state:	pointer to timer rand state struct
 * @kstat_irqs:		irq stats per cpu
 * @irq_2_iommu:	iommu with this irq
 * @handle_irq:		highlevel irq-events handler [if NULL, __do_IRQ()]
 * @chip:		low level interrupt hardware access
 * @msi_desc:		MSI descriptor
 * @handler_data:	per-IRQ data for the irq_chip methods
 * @chip_data:		platform-specific per-chip private data for the chip
 *			methods, to allow shared chip implementations
 * @action:		the irq action chain
 * @status:		status information
 * @depth:		disable-depth, for nested irq_disable() calls
 * @wake_depth:		enable depth, for multiple set_irq_wake() callers
 * @irq_count:		stats field to detect stalled irqs
 * @last_unhandled:	aging timer for unhandled count
 * @irqs_unhandled:	stats field for spurious unhandled interrupts
 * @lock:		locking for SMP
 * @affinity:		IRQ affinity on SMP
 * @cpu:		cpu index useful for balancing
 * @pending_mask:	pending rebalanced interrupts
 * @threads_active:	number of irqaction threads currently running
 * @wait_for_threads:	wait queue for sync_irq to wait for threaded handlers
 * @dir:		/proc/irq/ procfs entry
 * @name:		flow handler name for /proc/interrupts output
 */
struct irq_desc {
	unsigned int		irq;
	struct timer_rand_state *timer_rand_state;
	unsigned int            *kstat_irqs;
#ifdef CONFIG_INTR_REMAP
	struct irq_2_iommu      *irq_2_iommu;
#endif
	irq_flow_handler_t	handle_irq;
	struct irq_chip		*chip;
	struct msi_desc		*msi_desc;
	void			*handler_data;
	void			*chip_data;
	struct irqaction	*action;	/* IRQ action list */
	unsigned int		status;		/* IRQ status */

	unsigned int		depth;		/* nested irq disables */
	unsigned int		wake_depth;	/* nested wake enables */
	unsigned int		irq_count;	/* For detecting broken IRQs */
	unsigned long		last_unhandled;	/* Aging timer for unhandled count */
	unsigned int		irqs_unhandled;
	spinlock_t		lock;
#ifdef CONFIG_SMP
	cpumask_var_t		affinity;
	unsigned int		cpu;
#ifdef CONFIG_GENERIC_PENDING_IRQ
	cpumask_var_t		pending_mask;
#endif
#endif
	atomic_t		threads_active;
	wait_queue_head_t       wait_for_threads;
#ifdef CONFIG_PROC_FS
	struct proc_dir_entry	*dir;
#endif
	const char		*name;
} ____cacheline_internodealigned_in_smp;

extern void arch_init_copy_chip_data(struct irq_desc *old_desc,
					struct irq_desc *desc, int cpu);
extern void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc);

#ifndef CONFIG_SPARSE_IRQ
extern struct irq_desc irq_desc[NR_IRQS];
#else /* CONFIG_SPARSE_IRQ */
extern struct irq_desc *move_irq_desc(struct irq_desc *old_desc, int cpu);
#endif /* CONFIG_SPARSE_IRQ */

extern struct irq_desc *irq_to_desc_alloc_cpu(unsigned int irq, int cpu);

static inline struct irq_desc *
irq_remap_to_desc(unsigned int irq, struct irq_desc *desc)
{
#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
	return irq_to_desc(irq);
#else
	return desc;
#endif
}

/*
 * Migration helpers for obsolete names, they will go away:
 */
#define hw_interrupt_type	irq_chip
#define no_irq_type		no_irq_chip
typedef struct irq_desc		irq_desc_t;

/*
 * Pick up the arch-dependent methods:
 */
#include <asm/hw_irq.h>

extern int setup_irq(unsigned int irq, struct irqaction *new);
extern void remove_irq(unsigned int irq, struct irqaction *act);

#ifdef CONFIG_GENERIC_HARDIRQS

#ifdef CONFIG_SMP

#ifdef CONFIG_GENERIC_PENDING_IRQ

void move_native_irq(int irq);
void move_masked_irq(int irq);

#else /* CONFIG_GENERIC_PENDING_IRQ */

static inline void move_irq(int irq)
{
}

static inline void move_native_irq(int irq)
{
}

static inline void move_masked_irq(int irq)
{
}

#endif /* CONFIG_GENERIC_PENDING_IRQ */

#else /* CONFIG_SMP */

#define move_native_irq(x)
#define move_masked_irq(x)

#endif /* CONFIG_SMP */

extern int no_irq_affinity;

static inline int irq_balancing_disabled(unsigned int irq)
{
	struct irq_desc *desc;

	desc = irq_to_desc(irq);
	return desc->status & IRQ_NO_BALANCING_MASK;
}

/* Handle irq action chains: */
extern irqreturn_t handle_IRQ_event(unsigned int irq, struct irqaction *action);

/*
 * Built-in IRQ handlers for various IRQ types,
 * callable via desc->chip->handle_irq()
 */
extern void handle_level_irq(unsigned int irq, struct irq_desc *desc);
extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc);
extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc);
extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);

/*
 * Monolithic do_IRQ implementation.
 */
#ifndef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ
extern unsigned int __do_IRQ(unsigned int irq);
#endif

/*
 * Architectures call this to let the generic IRQ layer
 * handle an interrupt. If the descriptor is attached to an
 * irqchip-style controller then we call the ->handle_irq() handler,
 * and it calls __do_IRQ() if it's attached to an irqtype-style controller.
 */
static inline void generic_handle_irq_desc(unsigned int irq, struct irq_desc *desc)
{
#ifdef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ
	desc->handle_irq(irq, desc);
#else
	if (likely(desc->handle_irq))
		desc->handle_irq(irq, desc);
	else
		__do_IRQ(irq);
#endif
}

static inline void generic_handle_irq(unsigned int irq)
{
	generic_handle_irq_desc(irq, irq_to_desc(irq));
}

/* Handling of unhandled and spurious interrupts: */
extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
			   irqreturn_t action_ret);

/* Resending of interrupts :*/
void check_irq_resend(struct irq_desc *desc, unsigned int irq);

/* Enable/disable irq debugging output: */
extern int noirqdebug_setup(char *str);

/* Checks whether the interrupt can be requested by request_irq(): */
extern int can_request_irq(unsigned int irq, unsigned long irqflags);

/* Dummy irq-chip implementations: */
extern struct irq_chip no_irq_chip;
extern struct irq_chip dummy_irq_chip;

extern void
set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip,
			 irq_flow_handler_t handle);
extern void
set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
			      irq_flow_handler_t handle, const char *name);

extern void
__set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
		  const char *name);

/* caller has locked the irq_desc and both params are valid */
static inline void __set_irq_handler_unlocked(int irq,
					      irq_flow_handler_t handler)
{
	struct irq_desc *desc;

	desc = irq_to_desc(irq);
	desc->handle_irq = handler;
}

/*
 * Set a highlevel flow handler for a given IRQ:
 */
static inline void
set_irq_handler(unsigned int irq, irq_flow_handler_t handle)
{
	__set_irq_handler(irq, handle, 0, NULL);
}

/*
 * Set a highlevel chained flow handler for a given IRQ.
 * (a chained handler is automatically enabled and set to
 *  IRQ_NOREQUEST and IRQ_NOPROBE)
 */
static inline void
set_irq_chained_handler(unsigned int irq,
			irq_flow_handler_t handle)
{
	__set_irq_handler(irq, handle, 1, NULL);
}

extern void set_irq_noprobe(unsigned int irq);
extern void set_irq_probe(unsigned int irq);

/* Handle dynamic irq creation and destruction */
extern unsigned int create_irq_nr(unsigned int irq_want);
extern int create_irq(void);
extern void destroy_irq(unsigned int irq);

/* Test to see if a driver has successfully requested an irq */
static inline int irq_has_action(unsigned int irq)
{
	struct irq_desc *desc = irq_to_desc(irq);
	return desc->action != NULL;
}

/* Dynamic irq helper functions */
extern void dynamic_irq_init(unsigned int irq);
extern void dynamic_irq_cleanup(unsigned int irq);

/* Set/get chip/data for an IRQ: */
extern int set_irq_chip(unsigned int irq, struct irq_chip *chip);
extern int set_irq_data(unsigned int irq, void *data);
extern int set_irq_chip_data(unsigned int irq, void *data);
extern int set_irq_type(unsigned int irq, unsigned int type);
extern int set_irq_msi(unsigned int irq, struct msi_desc *entry);

#define get_irq_chip(irq)	(irq_to_desc(irq)->chip)
#define get_irq_chip_data(irq)	(irq_to_desc(irq)->chip_data)
#define get_irq_data(irq)	(irq_to_desc(irq)->handler_data)
#define get_irq_msi(irq)	(irq_to_desc(irq)->msi_desc)

#define get_irq_desc_chip(desc)		((desc)->chip)
#define get_irq_desc_chip_data(desc)	((desc)->chip_data)
#define get_irq_desc_data(desc)		((desc)->handler_data)
#define get_irq_desc_msi(desc)		((desc)->msi_desc)

#endif /* CONFIG_GENERIC_HARDIRQS */

#endif /* !CONFIG_S390 */

#ifdef CONFIG_SMP
/**
 * init_alloc_desc_masks - allocate cpumasks for irq_desc
 * @desc:	pointer to irq_desc struct
 * @cpu:	cpu which will be handling the cpumasks
 * @boot:	true if need bootmem
 *
 * Allocates affinity and pending_mask cpumask if required.
 * Returns true if successful (or not required).
 * Side effect: affinity has all bits set, pending_mask has all bits clear.
 */
static inline bool init_alloc_desc_masks(struct irq_desc *desc, int cpu,
								bool boot)
{
	int node;

	if (boot) {
		alloc_bootmem_cpumask_var(&desc->affinity);
		cpumask_setall(desc->affinity);

#ifdef CONFIG_GENERIC_PENDING_IRQ
		alloc_bootmem_cpumask_var(&desc->pending_mask);
		cpumask_clear(desc->pending_mask);
#endif
		return true;
	}

	node = cpu_to_node(cpu);

	if (!alloc_cpumask_var_node(&desc->affinity, GFP_ATOMIC, node))
		return false;
	cpumask_setall(desc->affinity);

#ifdef CONFIG_GENERIC_PENDING_IRQ
	if (!alloc_cpumask_var_node(&desc->pending_mask, GFP_ATOMIC, node)) {
		free_cpumask_var(desc->affinity);
		return false;
	}
	cpumask_clear(desc->pending_mask);
#endif
	return true;
}

/**
 * init_copy_desc_masks - copy cpumasks for irq_desc
 * @old_desc:	pointer to old irq_desc struct
 * @new_desc:	pointer to new irq_desc struct
 *
 * Insures affinity and pending_masks are copied to new irq_desc.
 * If !CONFIG_CPUMASKS_OFFSTACK the cpumasks are embedded in the
 * irq_desc struct so the copy is redundant.
 */

static inline void init_copy_desc_masks(struct irq_desc *old_desc,
					struct irq_desc *new_desc)
{
#ifdef CONFIG_CPUMASKS_OFFSTACK
	cpumask_copy(new_desc->affinity, old_desc->affinity);

#ifdef CONFIG_GENERIC_PENDING_IRQ
	cpumask_copy(new_desc->pending_mask, old_desc->pending_mask);
#endif
#endif
}

#else /* !CONFIG_SMP */

static inline bool init_alloc_desc_masks(struct irq_desc *desc, int cpu,
								bool boot)
{
	return true;
}

static inline void init_copy_desc_masks(struct irq_desc *old_desc,
					struct irq_desc *new_desc)
{
}

#endif	/* CONFIG_SMP */

#endif /* _LINUX_IRQ_H */
Commit	Line	Data
06fcb0c6 IM	1	#ifndef _LINUX_IRQ_H
06fcb0c6 IM	2	#define _LINUX_IRQ_H
1da177e4 LT	3
	4	/*
	5	* Please do not include this file in generic code. There is currently
	6	* no requirement for any architecture to implement anything held
	7	* within this file.
	8	*
	9	* Thanks. --rmk
	10	*/
	11
23f9b317	12	#include <linux/smp.h>
1da177e4	13
06fcb0c6	14	#ifndef CONFIG_S390
1da177e4 LT	15
	16	#include <linux/linkage.h>
	17	#include <linux/cache.h>
	18	#include <linux/spinlock.h>
	19	#include <linux/cpumask.h>
908dcecd	20	#include <linux/irqreturn.h>
dd3a1db9	21	#include <linux/irqnr.h>
77904fd6	22	#include <linux/errno.h>
3aa551c9	23	#include <linux/wait.h>
1da177e4 LT	24
	25	#include <asm/irq.h>
	26	#include <asm/ptrace.h>
7d12e780	27	#include <asm/irq_regs.h>
1da177e4	28
57a58a94	29	struct irq_desc;
ec701584	30	typedef void (*irq_flow_handler_t)(unsigned int irq,
7d12e780	31	struct irq_desc *desc);
57a58a94 DH	32
57a58a94 DH	33
1da177e4 LT	34	/*
1da177e4 LT	35	* IRQ line status.
6e213616	36	*
950f4427	37	* Bits 0-7 are reserved for the IRQF_* bits in linux/interrupt.h
6e213616 TG	38	*
6e213616 TG	39	* IRQ types
1da177e4	40	*/
6e213616 TG	41	#define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */
	42	#define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */
	43	#define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */
	44	#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING)
	45	#define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */
	46	#define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */
	47	#define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */
	48	#define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */
	49
	50	/* Internal flags */
950f4427 TG	51	#define IRQ_INPROGRESS 0x00000100 /* IRQ handler active - do not enter! */
	52	#define IRQ_DISABLED 0x00000200 /* IRQ disabled - do not enter! */
	53	#define IRQ_PENDING 0x00000400 /* IRQ pending - replay on enable */
	54	#define IRQ_REPLAY 0x00000800 /* IRQ has been replayed but not acked yet */
	55	#define IRQ_AUTODETECT 0x00001000 /* IRQ is being autodetected */
	56	#define IRQ_WAITING 0x00002000 /* IRQ not yet seen - for autodetection */
	57	#define IRQ_LEVEL 0x00004000 /* IRQ level triggered */
	58	#define IRQ_MASKED 0x00008000 /* IRQ masked - shouldn't be seen again */
	59	#define IRQ_PER_CPU 0x00010000 /* IRQ is per CPU */
	60	#define IRQ_NOPROBE 0x00020000 /* IRQ is not valid for probing */
	61	#define IRQ_NOREQUEST 0x00040000 /* IRQ cannot be requested */
	62	#define IRQ_NOAUTOEN 0x00080000 /* IRQ will not be enabled on request irq */
d7e25f33 IM	63	#define IRQ_WAKEUP 0x00100000 /* IRQ triggers system wakeup */
	64	#define IRQ_MOVE_PENDING 0x00200000 /* need to re-target IRQ destination */
	65	#define IRQ_NO_BALANCING 0x00400000 /* IRQ is excluded from balancing */
1adb0850	66	#define IRQ_SPURIOUS_DISABLED 0x00800000 /* IRQ was disabled by the spurious trap */
f6d87f4b TG	67	#define IRQ_MOVE_PCNTXT 0x01000000 /* IRQ migration from process context */
f6d87f4b TG	68	#define IRQ_AFFINITY_SET 0x02000000 /* IRQ affinity was set from userspace*/
950f4427	69
0d7012a9	70	#ifdef CONFIG_IRQ_PER_CPU
f26fdd59	71	# define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU)
950f4427	72	# define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU \| IRQ_NO_BALANCING)
f26fdd59 KW	73	#else
f26fdd59 KW	74	# define CHECK_IRQ_PER_CPU(var) 0
950f4427	75	# define IRQ_NO_BALANCING_MASK IRQ_NO_BALANCING
f26fdd59	76	#endif
1da177e4	77
6a6de9ef	78	struct proc_dir_entry;
5b912c10	79	struct msi_desc;
6a6de9ef	80
8fee5c36	81	/**
6a6de9ef	82	* struct irq_chip - hardware interrupt chip descriptor
8fee5c36 IM	83	*
	84	* @name: name for /proc/interrupts
	85	* @startup: start up the interrupt (defaults to ->enable if NULL)
	86	* @shutdown: shut down the interrupt (defaults to ->disable if NULL)
	87	* @enable: enable the interrupt (defaults to chip->unmask if NULL)
	88	* @disable: disable the interrupt (defaults to chip->mask if NULL)
8fee5c36 IM	89	* @ack: start of a new interrupt
	90	* @mask: mask an interrupt source
	91	* @mask_ack: ack and mask an interrupt source
	92	* @unmask: unmask an interrupt source
47c2a3aa IM	93	* @eoi: end of interrupt - chip level
47c2a3aa IM	94	* @end: end of interrupt - flow level
8fee5c36 IM	95	* @set_affinity: set the CPU affinity on SMP machines
	96	* @retrigger: resend an IRQ to the CPU
	97	* @set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
	98	* @set_wake: enable/disable power-management wake-on of an IRQ
	99	*
	100	* @release: release function solely used by UML
6a6de9ef	101	* @typename: obsoleted by name, kept as migration helper
1da177e4	102	*/
6a6de9ef TG	103	struct irq_chip {
6a6de9ef TG	104	const char *name;
71d218b7 IM	105	unsigned int (*startup)(unsigned int irq);
	106	void (*shutdown)(unsigned int irq);
	107	void (*enable)(unsigned int irq);
	108	void (*disable)(unsigned int irq);
6a6de9ef	109
71d218b7	110	void (*ack)(unsigned int irq);
6a6de9ef TG	111	void (*mask)(unsigned int irq);
	112	void (*mask_ack)(unsigned int irq);
	113	void (*unmask)(unsigned int irq);
47c2a3aa	114	void (*eoi)(unsigned int irq);
6a6de9ef	115
71d218b7	116	void (*end)(unsigned int irq);
0de26520 RR	117	void (*set_affinity)(unsigned int irq,
0de26520 RR	118	const struct cpumask *dest);
c0ad90a3	119	int (*retrigger)(unsigned int irq);
6a6de9ef TG	120	int (*set_type)(unsigned int irq, unsigned int flow_type);
6a6de9ef TG	121	int (*set_wake)(unsigned int irq, unsigned int on);
c0ad90a3	122
b77d6adc PBG	123	/* Currently used only by UML, might disappear one day.*/
b77d6adc PBG	124	#ifdef CONFIG_IRQ_RELEASE_METHOD
71d218b7	125	void (release)(unsigned int irq, void dev_id);
b77d6adc	126	#endif
6a6de9ef TG	127	/*
	128	* For compatibility, ->typename is copied into ->name.
	129	* Will disappear.
	130	*/
	131	const char *typename;
1da177e4 LT	132	};
1da177e4 LT	133
0b8f1efa YL	134	struct timer_rand_state;
0b8f1efa YL	135	struct irq_2_iommu;
8fee5c36 IM	136	/**
8fee5c36 IM	137	* struct irq_desc - interrupt descriptor
2ed1cdcf	138	* @irq: interrupt number for this descriptor
078a55db YL	139	* @timer_rand_state: pointer to timer rand state struct
	140	* @kstat_irqs: irq stats per cpu
	141	* @irq_2_iommu: iommu with this irq
6a6de9ef TG	142	* @handle_irq: highlevel irq-events handler [if NULL, __do_IRQ()]
6a6de9ef TG	143	* @chip: low level interrupt hardware access
472900b8	144	* @msi_desc: MSI descriptor
6a6de9ef TG	145	* @handler_data: per-IRQ data for the irq_chip methods
	146	* @chip_data: platform-specific per-chip private data for the chip
	147	* methods, to allow shared chip implementations
8fee5c36 IM	148	* @action: the irq action chain
	149	* @status: status information
	150	* @depth: disable-depth, for nested irq_disable() calls
15a647eb	151	* @wake_depth: enable depth, for multiple set_irq_wake() callers
8fee5c36	152	* @irq_count: stats field to detect stalled irqs
5ac4d823	153	* @last_unhandled: aging timer for unhandled count
e262a7ba	154	* @irqs_unhandled: stats field for spurious unhandled interrupts
8fee5c36 IM	155	* @lock: locking for SMP
8fee5c36 IM	156	* @affinity: IRQ affinity on SMP
6a6de9ef	157	* @cpu: cpu index useful for balancing
8fee5c36	158	* @pending_mask: pending rebalanced interrupts
3aa551c9 TG	159	* @threads_active: number of irqaction threads currently running
3aa551c9 TG	160	* @wait_for_threads: wait queue for sync_irq to wait for threaded handlers
8fee5c36	161	* @dir: /proc/irq/ procfs entry
a460e745	162	* @name: flow handler name for /proc/interrupts output
1da177e4	163	*/
34ffdb72	164	struct irq_desc {
08678b08	165	unsigned int irq;
0b8f1efa YL	166	struct timer_rand_state *timer_rand_state;
0b8f1efa YL	167	unsigned int *kstat_irqs;
d7e51e66	168	#ifdef CONFIG_INTR_REMAP
0b8f1efa	169	struct irq_2_iommu *irq_2_iommu;
0b8f1efa	170	#endif
57a58a94	171	irq_flow_handler_t handle_irq;
6a6de9ef	172	struct irq_chip *chip;
5b912c10	173	struct msi_desc *msi_desc;
6a6de9ef	174	void *handler_data;
71d218b7 IM	175	void *chip_data;
	176	struct irqaction action; / IRQ action list */
	177	unsigned int status; /* IRQ status */
6a6de9ef	178
71d218b7	179	unsigned int depth; /* nested irq disables */
15a647eb	180	unsigned int wake_depth; /* nested wake enables */
71d218b7	181	unsigned int irq_count; /* For detecting broken IRQs */
4f27c00b	182	unsigned long last_unhandled; /* Aging timer for unhandled count */
e262a7ba	183	unsigned int irqs_unhandled;
71d218b7	184	spinlock_t lock;
a53da52f	185	#ifdef CONFIG_SMP
7f7ace0c	186	cpumask_var_t affinity;
6a6de9ef	187	unsigned int cpu;
8b8e8c1b	188	#ifdef CONFIG_GENERIC_PENDING_IRQ
7f7ace0c MT	189	cpumask_var_t pending_mask;
7f7ace0c MT	190	#endif
54d5d424	191	#endif
3aa551c9 TG	192	atomic_t threads_active;
3aa551c9 TG	193	wait_queue_head_t wait_for_threads;
4a733ee1	194	#ifdef CONFIG_PROC_FS
a460e745	195	struct proc_dir_entry *dir;
4a733ee1	196	#endif
a460e745	197	const char *name;
e729aa16	198	} ____cacheline_internodealigned_in_smp;
1da177e4	199
0b8f1efa YL	200	extern void arch_init_copy_chip_data(struct irq_desc *old_desc,
	201	struct irq_desc *desc, int cpu);
	202	extern void arch_free_chip_data(struct irq_desc old_desc, struct irq_desc desc);
9059d8fa	203
0b8f1efa	204	#ifndef CONFIG_SPARSE_IRQ
34ffdb72	205	extern struct irq_desc irq_desc[NR_IRQS];
f9af0e70	206	#else /* CONFIG_SPARSE_IRQ */
0b8f1efa	207	extern struct irq_desc move_irq_desc(struct irq_desc old_desc, int cpu);
d7e51e66	208	#endif /* CONFIG_SPARSE_IRQ */
0b8f1efa	209
f9af0e70	210	extern struct irq_desc *irq_to_desc_alloc_cpu(unsigned int irq, int cpu);
0b8f1efa	211
48a1b10a YL	212	static inline struct irq_desc *
	213	irq_remap_to_desc(unsigned int irq, struct irq_desc *desc)
	214	{
	215	#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
	216	return irq_to_desc(irq);
	217	#else
	218	return desc;
	219	#endif
c6b7674f TG	220	}
c6b7674f TG	221
34ffdb72 IM	222	/*
	223	* Migration helpers for obsolete names, they will go away:
	224	*/
6a6de9ef	225	#define hw_interrupt_type irq_chip
6a6de9ef	226	#define no_irq_type no_irq_chip
34ffdb72 IM	227	typedef struct irq_desc irq_desc_t;
	228
	229	/*
	230	* Pick up the arch-dependent methods:
	231	*/
	232	#include <asm/hw_irq.h>
1da177e4	233
06fcb0c6	234	extern int setup_irq(unsigned int irq, struct irqaction *new);
cbf94f06	235	extern void remove_irq(unsigned int irq, struct irqaction *act);
1da177e4 LT	236
1da177e4 LT	237	#ifdef CONFIG_GENERIC_HARDIRQS
06fcb0c6	238
54d5d424 AR	239	#ifdef CONFIG_SMP
54d5d424 AR	240
8b8e8c1b	241	#ifdef CONFIG_GENERIC_PENDING_IRQ
54d5d424	242
c777ac55	243	void move_native_irq(int irq);
e7b946e9	244	void move_masked_irq(int irq);
54d5d424	245
8b8e8c1b	246	#else /* CONFIG_GENERIC_PENDING_IRQ */
06fcb0c6 IM	247
	248	static inline void move_irq(int irq)
	249	{
	250	}
	251
	252	static inline void move_native_irq(int irq)
	253	{
	254	}
	255
e7b946e9 EB	256	static inline void move_masked_irq(int irq)
	257	{
	258	}
	259
06fcb0c6	260	#endif /* CONFIG_GENERIC_PENDING_IRQ */
54d5d424	261
06fcb0c6	262	#else /* CONFIG_SMP */
54d5d424	263
54d5d424	264	#define move_native_irq(x)
e7b946e9	265	#define move_masked_irq(x)
54d5d424	266
06fcb0c6	267	#endif /* CONFIG_SMP */
54d5d424	268
1da177e4	269	extern int no_irq_affinity;
1da177e4	270
950f4427 TG	271	static inline int irq_balancing_disabled(unsigned int irq)
950f4427 TG	272	{
08678b08 YL	273	struct irq_desc *desc;
	274
	275	desc = irq_to_desc(irq);
	276	return desc->status & IRQ_NO_BALANCING_MASK;
950f4427 TG	277	}
950f4427 TG	278
6a6de9ef	279	/* Handle irq action chains: */
bedd30d9	280	extern irqreturn_t handle_IRQ_event(unsigned int irq, struct irqaction *action);
6a6de9ef TG	281
	282	/*
	283	* Built-in IRQ handlers for various IRQ types,
	284	* callable via desc->chip->handle_irq()
	285	*/
ec701584 HH	286	extern void handle_level_irq(unsigned int irq, struct irq_desc *desc);
	287	extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
	288	extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc);
	289	extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc);
	290	extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
	291	extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);
6a6de9ef	292
2e60bbb6	293	/*
6a6de9ef	294	* Monolithic do_IRQ implementation.
2e60bbb6	295	*/
af8c65b5	296	#ifndef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ
ec701584	297	extern unsigned int __do_IRQ(unsigned int irq);
af8c65b5	298	#endif
2e60bbb6	299
dae86204 IM	300	/*
	301	* Architectures call this to let the generic IRQ layer
	302	* handle an interrupt. If the descriptor is attached to an
	303	* irqchip-style controller then we call the ->handle_irq() handler,
	304	* and it calls __do_IRQ() if it's attached to an irqtype-style controller.
	305	*/
46926b67	306	static inline void generic_handle_irq_desc(unsigned int irq, struct irq_desc *desc)
dae86204	307	{
af8c65b5	308	#ifdef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ
7d12e780	309	desc->handle_irq(irq, desc);
af8c65b5	310	#else
dae86204	311	if (likely(desc->handle_irq))
7d12e780	312	desc->handle_irq(irq, desc);
dae86204	313	else
7d12e780	314	__do_IRQ(irq);
af8c65b5	315	#endif
dae86204 IM	316	}
dae86204 IM	317
46926b67 YL	318	static inline void generic_handle_irq(unsigned int irq)
	319	{
	320	generic_handle_irq_desc(irq, irq_to_desc(irq));
	321	}
	322
6a6de9ef	323	/* Handling of unhandled and spurious interrupts: */
34ffdb72	324	extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
bedd30d9	325	irqreturn_t action_ret);
1da177e4	326
a4633adc TG	327	/* Resending of interrupts :*/
	328	void check_irq_resend(struct irq_desc *desc, unsigned int irq);
	329
6a6de9ef TG	330	/* Enable/disable irq debugging output: */
	331	extern int noirqdebug_setup(char *str);
	332
	333	/* Checks whether the interrupt can be requested by request_irq(): */
	334	extern int can_request_irq(unsigned int irq, unsigned long irqflags);
	335
f8b5473f	336	/* Dummy irq-chip implementations: */
6a6de9ef	337	extern struct irq_chip no_irq_chip;
f8b5473f	338	extern struct irq_chip dummy_irq_chip;
6a6de9ef	339
145fc655 IM	340	extern void
	341	set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip,
	342	irq_flow_handler_t handle);
6a6de9ef	343	extern void
a460e745 IM	344	set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
	345	irq_flow_handler_t handle, const char *name);
	346
6a6de9ef	347	extern void
a460e745 IM	348	__set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
a460e745 IM	349	const char *name);
1da177e4	350
b019e573 KH	351	/* caller has locked the irq_desc and both params are valid */
	352	static inline void __set_irq_handler_unlocked(int irq,
	353	irq_flow_handler_t handler)
	354	{
08678b08 YL	355	struct irq_desc *desc;
	356
	357	desc = irq_to_desc(irq);
	358	desc->handle_irq = handler;
b019e573 KH	359	}
b019e573 KH	360
6a6de9ef TG	361	/*
	362	* Set a highlevel flow handler for a given IRQ:
	363	*/
	364	static inline void
57a58a94	365	set_irq_handler(unsigned int irq, irq_flow_handler_t handle)
6a6de9ef	366	{
a460e745	367	__set_irq_handler(irq, handle, 0, NULL);
6a6de9ef TG	368	}
	369
	370	/*
	371	* Set a highlevel chained flow handler for a given IRQ.
	372	* (a chained handler is automatically enabled and set to
	373	* IRQ_NOREQUEST and IRQ_NOPROBE)
	374	*/
	375	static inline void
	376	set_irq_chained_handler(unsigned int irq,
57a58a94	377	irq_flow_handler_t handle)
6a6de9ef	378	{
a460e745	379	__set_irq_handler(irq, handle, 1, NULL);
6a6de9ef TG	380	}
6a6de9ef TG	381
46f4f8f6 RB	382	extern void set_irq_noprobe(unsigned int irq);
	383	extern void set_irq_probe(unsigned int irq);
	384
3a16d713	385	/* Handle dynamic irq creation and destruction */
6d50bc26	386	extern unsigned int create_irq_nr(unsigned int irq_want);
3a16d713 EB	387	extern int create_irq(void);
	388	extern void destroy_irq(unsigned int irq);
	389
1f80025e EB	390	/* Test to see if a driver has successfully requested an irq */
	391	static inline int irq_has_action(unsigned int irq)
	392	{
08678b08	393	struct irq_desc *desc = irq_to_desc(irq);
1f80025e EB	394	return desc->action != NULL;
	395	}
	396
3a16d713 EB	397	/* Dynamic irq helper functions */
	398	extern void dynamic_irq_init(unsigned int irq);
	399	extern void dynamic_irq_cleanup(unsigned int irq);
dd87eb3a	400
3a16d713	401	/* Set/get chip/data for an IRQ: */
dd87eb3a TG	402	extern int set_irq_chip(unsigned int irq, struct irq_chip *chip);
	403	extern int set_irq_data(unsigned int irq, void *data);
	404	extern int set_irq_chip_data(unsigned int irq, void *data);
	405	extern int set_irq_type(unsigned int irq, unsigned int type);
5b912c10	406	extern int set_irq_msi(unsigned int irq, struct msi_desc *entry);
dd87eb3a	407
08678b08 YL	408	#define get_irq_chip(irq) (irq_to_desc(irq)->chip)
	409	#define get_irq_chip_data(irq) (irq_to_desc(irq)->chip_data)
	410	#define get_irq_data(irq) (irq_to_desc(irq)->handler_data)
	411	#define get_irq_msi(irq) (irq_to_desc(irq)->msi_desc)
dd87eb3a	412
0b8f1efa YL	413	#define get_irq_desc_chip(desc) ((desc)->chip)
	414	#define get_irq_desc_chip_data(desc) ((desc)->chip_data)
	415	#define get_irq_desc_data(desc) ((desc)->handler_data)
	416	#define get_irq_desc_msi(desc) ((desc)->msi_desc)
	417
6a6de9ef	418	#endif /* CONFIG_GENERIC_HARDIRQS */
1da177e4	419
06fcb0c6	420	#endif /* !CONFIG_S390 */
1da177e4	421
7f7ace0c MT	422	#ifdef CONFIG_SMP
	423	/**
	424	* init_alloc_desc_masks - allocate cpumasks for irq_desc
	425	* @desc: pointer to irq_desc struct
802bf931	426	* @cpu: cpu which will be handling the cpumasks
7f7ace0c MT	427	* @boot: true if need bootmem
	428	*
	429	* Allocates affinity and pending_mask cpumask if required.
	430	* Returns true if successful (or not required).
	431	* Side effect: affinity has all bits set, pending_mask has all bits clear.
	432	*/
802bf931	433	static inline bool init_alloc_desc_masks(struct irq_desc *desc, int cpu,
7f7ace0c MT	434	bool boot)
7f7ace0c MT	435	{
802bf931 MT	436	int node;
802bf931 MT	437
7f7ace0c MT	438	if (boot) {
	439	alloc_bootmem_cpumask_var(&desc->affinity);
	440	cpumask_setall(desc->affinity);
	441
	442	#ifdef CONFIG_GENERIC_PENDING_IRQ
	443	alloc_bootmem_cpumask_var(&desc->pending_mask);
	444	cpumask_clear(desc->pending_mask);
	445	#endif
	446	return true;
	447	}
	448
802bf931 MT	449	node = cpu_to_node(cpu);
802bf931 MT	450
7f7ace0c MT	451	if (!alloc_cpumask_var_node(&desc->affinity, GFP_ATOMIC, node))
	452	return false;
	453	cpumask_setall(desc->affinity);
	454
	455	#ifdef CONFIG_GENERIC_PENDING_IRQ
	456	if (!alloc_cpumask_var_node(&desc->pending_mask, GFP_ATOMIC, node)) {
	457	free_cpumask_var(desc->affinity);
	458	return false;
	459	}
	460	cpumask_clear(desc->pending_mask);
	461	#endif
	462	return true;
	463	}
	464
	465	/**
	466	* init_copy_desc_masks - copy cpumasks for irq_desc
	467	* @old_desc: pointer to old irq_desc struct
	468	* @new_desc: pointer to new irq_desc struct
	469	*
	470	* Insures affinity and pending_masks are copied to new irq_desc.
	471	* If !CONFIG_CPUMASKS_OFFSTACK the cpumasks are embedded in the
	472	* irq_desc struct so the copy is redundant.
	473	*/
	474
	475	static inline void init_copy_desc_masks(struct irq_desc *old_desc,
	476	struct irq_desc *new_desc)
	477	{
	478	#ifdef CONFIG_CPUMASKS_OFFSTACK
	479	cpumask_copy(new_desc->affinity, old_desc->affinity);
	480
	481	#ifdef CONFIG_GENERIC_PENDING_IRQ
	482	cpumask_copy(new_desc->pending_mask, old_desc->pending_mask);
	483	#endif
	484	#endif
	485	}
	486
	487	#else /* !CONFIG_SMP */
	488
802bf931	489	static inline bool init_alloc_desc_masks(struct irq_desc *desc, int cpu,
7f7ace0c MT	490	bool boot)
	491	{
	492	return true;
	493	}
	494
	495	static inline void init_copy_desc_masks(struct irq_desc *old_desc,
	496	struct irq_desc *new_desc)
	497	{
	498	}
	499
	500	#endif /* CONFIG_SMP */
	501
06fcb0c6	502	#endif /* _LINUX_IRQ_H */