[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / i2c / twl4030.h

/*
 * twl4030.h - header for TWL4030 PM and audio CODEC device
 *
 * Copyright (C) 2005-2006 Texas Instruments, Inc.
 *
 * Based on tlv320aic23.c:
 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 *
 */

#ifndef __TWL4030_H_
#define __TWL4030_H_

#include <linux/types.h>
#include <linux/input/matrix_keypad.h>

/*
 * Using the twl4030 core we address registers using a pair
 *	{ module id, relative register offset }
 * which that core then maps to the relevant
 *	{ i2c slave, absolute register address }
 *
 * The module IDs are meaningful only to the twl4030 core code,
 * which uses them as array indices to look up the first register
 * address each module uses within a given i2c slave.
 */

/* Slave 0 (i2c address 0x48) */
#define TWL4030_MODULE_USB		0x00

/* Slave 1 (i2c address 0x49) */
#define TWL4030_MODULE_AUDIO_VOICE	0x01
#define TWL4030_MODULE_GPIO		0x02
#define TWL4030_MODULE_INTBR		0x03
#define TWL4030_MODULE_PIH		0x04
#define TWL4030_MODULE_TEST		0x05

/* Slave 2 (i2c address 0x4a) */
#define TWL4030_MODULE_KEYPAD		0x06
#define TWL4030_MODULE_MADC		0x07
#define TWL4030_MODULE_INTERRUPTS	0x08
#define TWL4030_MODULE_LED		0x09
#define TWL4030_MODULE_MAIN_CHARGE	0x0A
#define TWL4030_MODULE_PRECHARGE	0x0B
#define TWL4030_MODULE_PWM0		0x0C
#define TWL4030_MODULE_PWM1		0x0D
#define TWL4030_MODULE_PWMA		0x0E
#define TWL4030_MODULE_PWMB		0x0F

#define TWL5031_MODULE_ACCESSORY	0x10
#define TWL5031_MODULE_INTERRUPTS	0x11

/* Slave 3 (i2c address 0x4b) */
#define TWL4030_MODULE_BACKUP		0x12
#define TWL4030_MODULE_INT		0x13
#define TWL4030_MODULE_PM_MASTER	0x14
#define TWL4030_MODULE_PM_RECEIVER	0x15
#define TWL4030_MODULE_RTC		0x16
#define TWL4030_MODULE_SECURED_REG	0x17

/*
 * Read and write single 8-bit registers
 */
int twl4030_i2c_write_u8(u8 mod_no, u8 val, u8 reg);
int twl4030_i2c_read_u8(u8 mod_no, u8 *val, u8 reg);

/*
 * Read and write several 8-bit registers at once.
 *
 * IMPORTANT:  For twl4030_i2c_write(), allocate num_bytes + 1
 * for the value, and populate your data starting at offset 1.
 */
int twl4030_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
int twl4030_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);

/*----------------------------------------------------------------------*/

/*
 * NOTE:  at up to 1024 registers, this is a big chip.
 *
 * Avoid putting register declarations in this file, instead of into
 * a driver-private file, unless some of the registers in a block
 * need to be shared with other drivers.  One example is blocks that
 * have Secondary IRQ Handler (SIH) registers.
 */

#define TWL4030_SIH_CTRL_EXCLEN_MASK	BIT(0)
#define TWL4030_SIH_CTRL_PENDDIS_MASK	BIT(1)
#define TWL4030_SIH_CTRL_COR_MASK	BIT(2)

/*----------------------------------------------------------------------*/

/*
 * GPIO Block Register offsets (use TWL4030_MODULE_GPIO)
 */

#define REG_GPIODATAIN1			0x0
#define REG_GPIODATAIN2			0x1
#define REG_GPIODATAIN3			0x2
#define REG_GPIODATADIR1		0x3
#define REG_GPIODATADIR2		0x4
#define REG_GPIODATADIR3		0x5
#define REG_GPIODATAOUT1		0x6
#define REG_GPIODATAOUT2		0x7
#define REG_GPIODATAOUT3		0x8
#define REG_CLEARGPIODATAOUT1		0x9
#define REG_CLEARGPIODATAOUT2		0xA
#define REG_CLEARGPIODATAOUT3		0xB
#define REG_SETGPIODATAOUT1		0xC
#define REG_SETGPIODATAOUT2		0xD
#define REG_SETGPIODATAOUT3		0xE
#define REG_GPIO_DEBEN1			0xF
#define REG_GPIO_DEBEN2			0x10
#define REG_GPIO_DEBEN3			0x11
#define REG_GPIO_CTRL			0x12
#define REG_GPIOPUPDCTR1		0x13
#define REG_GPIOPUPDCTR2		0x14
#define REG_GPIOPUPDCTR3		0x15
#define REG_GPIOPUPDCTR4		0x16
#define REG_GPIOPUPDCTR5		0x17
#define REG_GPIO_ISR1A			0x19
#define REG_GPIO_ISR2A			0x1A
#define REG_GPIO_ISR3A			0x1B
#define REG_GPIO_IMR1A			0x1C
#define REG_GPIO_IMR2A			0x1D
#define REG_GPIO_IMR3A			0x1E
#define REG_GPIO_ISR1B			0x1F
#define REG_GPIO_ISR2B			0x20
#define REG_GPIO_ISR3B			0x21
#define REG_GPIO_IMR1B			0x22
#define REG_GPIO_IMR2B			0x23
#define REG_GPIO_IMR3B			0x24
#define REG_GPIO_EDR1			0x28
#define REG_GPIO_EDR2			0x29
#define REG_GPIO_EDR3			0x2A
#define REG_GPIO_EDR4			0x2B
#define REG_GPIO_EDR5			0x2C
#define REG_GPIO_SIH_CTRL		0x2D

/* Up to 18 signals are available as GPIOs, when their
 * pins are not assigned to another use (such as ULPI/USB).
 */
#define TWL4030_GPIO_MAX		18

/*----------------------------------------------------------------------*/

/*
 * Keypad register offsets (use TWL4030_MODULE_KEYPAD)
 * ... SIH/interrupt only
 */

#define TWL4030_KEYPAD_KEYP_ISR1	0x11
#define TWL4030_KEYPAD_KEYP_IMR1	0x12
#define TWL4030_KEYPAD_KEYP_ISR2	0x13
#define TWL4030_KEYPAD_KEYP_IMR2	0x14
#define TWL4030_KEYPAD_KEYP_SIR		0x15	/* test register */
#define TWL4030_KEYPAD_KEYP_EDR		0x16
#define TWL4030_KEYPAD_KEYP_SIH_CTRL	0x17

/*----------------------------------------------------------------------*/

/*
 * Multichannel ADC register offsets (use TWL4030_MODULE_MADC)
 * ... SIH/interrupt only
 */

#define TWL4030_MADC_ISR1		0x61
#define TWL4030_MADC_IMR1		0x62
#define TWL4030_MADC_ISR2		0x63
#define TWL4030_MADC_IMR2		0x64
#define TWL4030_MADC_SIR		0x65	/* test register */
#define TWL4030_MADC_EDR		0x66
#define TWL4030_MADC_SIH_CTRL		0x67

/*----------------------------------------------------------------------*/

/*
 * Battery charger register offsets (use TWL4030_MODULE_INTERRUPTS)
 */

#define TWL4030_INTERRUPTS_BCIISR1A	0x0
#define TWL4030_INTERRUPTS_BCIISR2A	0x1
#define TWL4030_INTERRUPTS_BCIIMR1A	0x2
#define TWL4030_INTERRUPTS_BCIIMR2A	0x3
#define TWL4030_INTERRUPTS_BCIISR1B	0x4
#define TWL4030_INTERRUPTS_BCIISR2B	0x5
#define TWL4030_INTERRUPTS_BCIIMR1B	0x6
#define TWL4030_INTERRUPTS_BCIIMR2B	0x7
#define TWL4030_INTERRUPTS_BCISIR1	0x8	/* test register */
#define TWL4030_INTERRUPTS_BCISIR2	0x9	/* test register */
#define TWL4030_INTERRUPTS_BCIEDR1	0xa
#define TWL4030_INTERRUPTS_BCIEDR2	0xb
#define TWL4030_INTERRUPTS_BCIEDR3	0xc
#define TWL4030_INTERRUPTS_BCISIHCTRL	0xd

/*----------------------------------------------------------------------*/

/*
 * Power Interrupt block register offsets (use TWL4030_MODULE_INT)
 */

#define TWL4030_INT_PWR_ISR1		0x0
#define TWL4030_INT_PWR_IMR1		0x1
#define TWL4030_INT_PWR_ISR2		0x2
#define TWL4030_INT_PWR_IMR2		0x3
#define TWL4030_INT_PWR_SIR		0x4	/* test register */
#define TWL4030_INT_PWR_EDR1		0x5
#define TWL4030_INT_PWR_EDR2		0x6
#define TWL4030_INT_PWR_SIH_CTRL	0x7

/*----------------------------------------------------------------------*/

/*
 * Accessory Interrupts
 */
#define TWL5031_ACIIMR_LSB		0x05
#define TWL5031_ACIIMR_MSB		0x06
#define TWL5031_ACIIDR_LSB		0x07
#define TWL5031_ACIIDR_MSB		0x08
#define TWL5031_ACCISR1			0x0F
#define TWL5031_ACCIMR1			0x10
#define TWL5031_ACCISR2			0x11
#define TWL5031_ACCIMR2			0x12
#define TWL5031_ACCSIR			0x13
#define TWL5031_ACCEDR1			0x14
#define TWL5031_ACCSIHCTRL		0x15

/*----------------------------------------------------------------------*/

/*
 * Battery Charger Controller
 */

#define TWL5031_INTERRUPTS_BCIISR1	0x0
#define TWL5031_INTERRUPTS_BCIIMR1	0x1
#define TWL5031_INTERRUPTS_BCIISR2	0x2
#define TWL5031_INTERRUPTS_BCIIMR2	0x3
#define TWL5031_INTERRUPTS_BCISIR	0x4
#define TWL5031_INTERRUPTS_BCIEDR1	0x5
#define TWL5031_INTERRUPTS_BCIEDR2	0x6
#define TWL5031_INTERRUPTS_BCISIHCTRL	0x7

/*----------------------------------------------------------------------*/

/* Power bus message definitions */

/* The TWL4030/5030 splits its power-management resources (the various
 * regulators, clock and reset lines) into 3 processor groups - P1, P2 and
 * P3. These groups can then be configured to transition between sleep, wait-on
 * and active states by sending messages to the power bus.  See Section 5.4.2
 * Power Resources of TWL4030 TRM
 */

/* Processor groups */
#define DEV_GRP_NULL		0x0
#define DEV_GRP_P1		0x1	/* P1: all OMAP devices */
#define DEV_GRP_P2		0x2	/* P2: all Modem devices */
#define DEV_GRP_P3		0x4	/* P3: all peripheral devices */

/* Resource groups */
#define RES_GRP_RES		0x0	/* Reserved */
#define RES_GRP_PP		0x1	/* Power providers */
#define RES_GRP_RC		0x2	/* Reset and control */
#define RES_GRP_PP_RC		0x3
#define RES_GRP_PR		0x4	/* Power references */
#define RES_GRP_PP_PR		0x5
#define RES_GRP_RC_PR		0x6
#define RES_GRP_ALL		0x7	/* All resource groups */

#define RES_TYPE2_R0		0x0

#define RES_TYPE_ALL		0x7

/* Resource states */
#define RES_STATE_WRST		0xF
#define RES_STATE_ACTIVE	0xE
#define RES_STATE_SLEEP		0x8
#define RES_STATE_OFF		0x0

/* Power resources */

/* Power providers */
#define RES_VAUX1               1
#define RES_VAUX2               2
#define RES_VAUX3               3
#define RES_VAUX4               4
#define RES_VMMC1               5
#define RES_VMMC2               6
#define RES_VPLL1               7
#define RES_VPLL2               8
#define RES_VSIM                9
#define RES_VDAC                10
#define RES_VINTANA1            11
#define RES_VINTANA2            12
#define RES_VINTDIG             13
#define RES_VIO                 14
#define RES_VDD1                15
#define RES_VDD2                16
#define RES_VUSB_1V5            17
#define RES_VUSB_1V8            18
#define RES_VUSB_3V1            19
#define RES_VUSBCP              20
#define RES_REGEN               21
/* Reset and control */
#define RES_NRES_PWRON          22
#define RES_CLKEN               23
#define RES_SYSEN               24
#define RES_HFCLKOUT            25
#define RES_32KCLKOUT           26
#define RES_RESET               27
/* Power Reference */
#define RES_Main_Ref            28

#define TOTAL_RESOURCES		28
/*
 * Power Bus Message Format ... these can be sent individually by Linux,
 * but are usually part of downloaded scripts that are run when various
 * power events are triggered.
 *
 *  Broadcast Message (16 Bits):
 *    DEV_GRP[15:13] MT[12]  RES_GRP[11:9]  RES_TYPE2[8:7] RES_TYPE[6:4]
 *    RES_STATE[3:0]
 *
 *  Singular Message (16 Bits):
 *    DEV_GRP[15:13] MT[12]  RES_ID[11:4]  RES_STATE[3:0]
 */

#define MSG_BROADCAST(devgrp, grp, type, type2, state) \
	( (devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \
	| (type) << 4 | (state))

#define MSG_SINGULAR(devgrp, id, state) \
	((devgrp) << 13 | 0 << 12 | (id) << 4 | (state))

/*----------------------------------------------------------------------*/

struct twl4030_clock_init_data {
	bool ck32k_lowpwr_enable;
};

struct twl4030_bci_platform_data {
	int *battery_tmp_tbl;
	unsigned int tblsize;
};

/* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */
struct twl4030_gpio_platform_data {
	int		gpio_base;
	unsigned	irq_base, irq_end;

	/* package the two LED signals as output-only GPIOs? */
	bool		use_leds;

	/* gpio-n should control VMMC(n+1) if BIT(n) in mmc_cd is set */
	u8		mmc_cd;

	/* if BIT(N) is set, or VMMC(n+1) is linked, debounce GPIO-N */
	u32		debounce;

	/* For gpio-N, bit (1 << N) in "pullups" is set if that pullup
	 * should be enabled.  Else, if that bit is set in "pulldowns",
	 * that pulldown is enabled.  Don't waste power by letting any
	 * digital inputs float...
	 */
	u32		pullups;
	u32		pulldowns;

	int		(*setup)(struct device *dev,
				unsigned gpio, unsigned ngpio);
	int		(*teardown)(struct device *dev,
				unsigned gpio, unsigned ngpio);
};

struct twl4030_madc_platform_data {
	int		irq_line;
};

/* Boards have uniqe mappings of {row, col} --> keycode.
 * Column and row are 8 bits each, but range only from 0..7.
 * a PERSISTENT_KEY is "always on" and never reported.
 */
#define PERSISTENT_KEY(r, c)	KEY((r), (c), KEY_RESERVED)

struct twl4030_keypad_data {
	const struct matrix_keymap_data *keymap_data;
	unsigned rows;
	unsigned cols;
	bool rep;
};

enum twl4030_usb_mode {
	T2_USB_MODE_ULPI = 1,
	T2_USB_MODE_CEA2011_3PIN = 2,
};

struct twl4030_usb_data {
	enum twl4030_usb_mode	usb_mode;
};

struct twl4030_ins {
	u16 pmb_message;
	u8 delay;
};

struct twl4030_script {
	struct twl4030_ins *script;
	unsigned size;
	u8 flags;
#define TWL4030_WRST_SCRIPT	(1<<0)
#define TWL4030_WAKEUP12_SCRIPT	(1<<1)
#define TWL4030_WAKEUP3_SCRIPT	(1<<2)
#define TWL4030_SLEEP_SCRIPT	(1<<3)
};

struct twl4030_resconfig {
	u8 resource;
	u8 devgroup;	/* Processor group that Power resource belongs to */
	u8 type;	/* Power resource addressed, 6 / broadcast message */
	u8 type2;	/* Power resource addressed, 3 / broadcast message */
	u8 remap_off;	/* off state remapping */
	u8 remap_sleep;	/* sleep state remapping */
};

struct twl4030_power_data {
	struct twl4030_script **scripts;
	unsigned num;
	struct twl4030_resconfig *resource_config;
#define TWL4030_RESCONFIG_UNDEF	((u8)-1)
};

extern void twl4030_power_init(struct twl4030_power_data *triton2_scripts);

struct twl4030_codec_audio_data {
	unsigned int	audio_mclk;
	unsigned int ramp_delay_value;
	unsigned int hs_extmute:1;
	void (*set_hs_extmute)(int mute);
};

struct twl4030_codec_vibra_data {
	unsigned int	audio_mclk;
	unsigned int	coexist;
};

struct twl4030_codec_data {
	unsigned int	audio_mclk;
	struct twl4030_codec_audio_data		*audio;
	struct twl4030_codec_vibra_data		*vibra;
};

struct twl4030_platform_data {
	unsigned				irq_base, irq_end;
	struct twl4030_clock_init_data		*clock;
	struct twl4030_bci_platform_data	*bci;
	struct twl4030_gpio_platform_data	*gpio;
	struct twl4030_madc_platform_data	*madc;
	struct twl4030_keypad_data		*keypad;
	struct twl4030_usb_data			*usb;
	struct twl4030_power_data		*power;
	struct twl4030_codec_data		*codec;

	/* LDO regulators */
	struct regulator_init_data		*vdac;
	struct regulator_init_data		*vpll1;
	struct regulator_init_data		*vpll2;
	struct regulator_init_data		*vmmc1;
	struct regulator_init_data		*vmmc2;
	struct regulator_init_data		*vsim;
	struct regulator_init_data		*vaux1;
	struct regulator_init_data		*vaux2;
	struct regulator_init_data		*vaux3;
	struct regulator_init_data		*vaux4;
	struct regulator_init_data		*vio;
	struct regulator_init_data		*vdd1;
	struct regulator_init_data		*vdd2;
	struct regulator_init_data		*vintana1;
	struct regulator_init_data		*vintana2;
	struct regulator_init_data		*vintdig;
};

/*----------------------------------------------------------------------*/

int twl4030_sih_setup(int module);

/* Offsets to Power Registers */
#define TWL4030_VDAC_DEV_GRP		0x3B
#define TWL4030_VDAC_DEDICATED		0x3E
#define TWL4030_VAUX1_DEV_GRP		0x17
#define TWL4030_VAUX1_DEDICATED		0x1A
#define TWL4030_VAUX2_DEV_GRP		0x1B
#define TWL4030_VAUX2_DEDICATED		0x1E
#define TWL4030_VAUX3_DEV_GRP		0x1F
#define TWL4030_VAUX3_DEDICATED		0x22

#if defined(CONFIG_TWL4030_BCI_BATTERY) || \
	defined(CONFIG_TWL4030_BCI_BATTERY_MODULE)
	extern int twl4030charger_usb_en(int enable);
#else
	static inline int twl4030charger_usb_en(int enable) { return 0; }
#endif

/*----------------------------------------------------------------------*/

/* Linux-specific regulator identifiers ... for now, we only support
 * the LDOs, and leave the three buck converters alone.  VDD1 and VDD2
 * need to tie into hardware based voltage scaling (cpufreq etc), while
 * VIO is generally fixed.
 */

/* EXTERNAL dc-to-dc buck converters */
#define TWL4030_REG_VDD1	0
#define TWL4030_REG_VDD2	1
#define TWL4030_REG_VIO		2

/* EXTERNAL LDOs */
#define TWL4030_REG_VDAC	3
#define TWL4030_REG_VPLL1	4
#define TWL4030_REG_VPLL2	5	/* not on all chips */
#define TWL4030_REG_VMMC1	6
#define TWL4030_REG_VMMC2	7	/* not on all chips */
#define TWL4030_REG_VSIM	8	/* not on all chips */
#define TWL4030_REG_VAUX1	9	/* not on all chips */
#define TWL4030_REG_VAUX2_4030	10	/* (twl4030-specific) */
#define TWL4030_REG_VAUX2	11	/* (twl5030 and newer) */
#define TWL4030_REG_VAUX3	12	/* not on all chips */
#define TWL4030_REG_VAUX4	13	/* not on all chips */

/* INTERNAL LDOs */
#define TWL4030_REG_VINTANA1	14
#define TWL4030_REG_VINTANA2	15
#define TWL4030_REG_VINTDIG	16
#define TWL4030_REG_VUSB1V5	17
#define TWL4030_REG_VUSB1V8	18
#define TWL4030_REG_VUSB3V1	19

#endif /* End of __TWL4030_H */
Commit	Line	Data
a603a7fa DB	1	/*
	2	* twl4030.h - header for TWL4030 PM and audio CODEC device
	3	*
	4	* Copyright (C) 2005-2006 Texas Instruments, Inc.
	5	*
	6	* Based on tlv320aic23.c:
	7	* Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	*/
	24
	25	#ifndef __TWL4030_H_
	26	#define __TWL4030_H_
	27
9d834068 DB	28	#include <linux/types.h>
	29	#include <linux/input/matrix_keypad.h>
	30
a603a7fa DB	31	/*
	32	* Using the twl4030 core we address registers using a pair
	33	* { module id, relative register offset }
	34	* which that core then maps to the relevant
	35	* { i2c slave, absolute register address }
	36	*
	37	* The module IDs are meaningful only to the twl4030 core code,
	38	* which uses them as array indices to look up the first register
	39	* address each module uses within a given i2c slave.
	40	*/
	41
	42	/* Slave 0 (i2c address 0x48) */
	43	#define TWL4030_MODULE_USB 0x00
	44
	45	/* Slave 1 (i2c address 0x49) */
	46	#define TWL4030_MODULE_AUDIO_VOICE 0x01
	47	#define TWL4030_MODULE_GPIO 0x02
	48	#define TWL4030_MODULE_INTBR 0x03
	49	#define TWL4030_MODULE_PIH 0x04
	50	#define TWL4030_MODULE_TEST 0x05
	51
	52	/* Slave 2 (i2c address 0x4a) */
	53	#define TWL4030_MODULE_KEYPAD 0x06
	54	#define TWL4030_MODULE_MADC 0x07
	55	#define TWL4030_MODULE_INTERRUPTS 0x08
	56	#define TWL4030_MODULE_LED 0x09
	57	#define TWL4030_MODULE_MAIN_CHARGE 0x0A
	58	#define TWL4030_MODULE_PRECHARGE 0x0B
	59	#define TWL4030_MODULE_PWM0 0x0C
	60	#define TWL4030_MODULE_PWM1 0x0D
	61	#define TWL4030_MODULE_PWMA 0x0E
	62	#define TWL4030_MODULE_PWMB 0x0F
	63
1920a61e IK	64	#define TWL5031_MODULE_ACCESSORY 0x10
	65	#define TWL5031_MODULE_INTERRUPTS 0x11
	66
a603a7fa	67	/* Slave 3 (i2c address 0x4b) */
1920a61e IK	68	#define TWL4030_MODULE_BACKUP 0x12
	69	#define TWL4030_MODULE_INT 0x13
	70	#define TWL4030_MODULE_PM_MASTER 0x14
	71	#define TWL4030_MODULE_PM_RECEIVER 0x15
	72	#define TWL4030_MODULE_RTC 0x16
	73	#define TWL4030_MODULE_SECURED_REG 0x17
a603a7fa DB	74
	75	/*
	76	* Read and write single 8-bit registers
	77	*/
	78	int twl4030_i2c_write_u8(u8 mod_no, u8 val, u8 reg);
	79	int twl4030_i2c_read_u8(u8 mod_no, u8 *val, u8 reg);
	80
	81	/*
	82	* Read and write several 8-bit registers at once.
	83	*
	84	* IMPORTANT: For twl4030_i2c_write(), allocate num_bytes + 1
	85	* for the value, and populate your data starting at offset 1.
	86	*/
3fba19ec DB	87	int twl4030_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
3fba19ec DB	88	int twl4030_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
a603a7fa DB	89
	90	/----------------------------------------------------------------------/
	91
	92	/*
	93	* NOTE: at up to 1024 registers, this is a big chip.
	94	*
	95	* Avoid putting register declarations in this file, instead of into
	96	* a driver-private file, unless some of the registers in a block
	97	* need to be shared with other drivers. One example is blocks that
	98	* have Secondary IRQ Handler (SIH) registers.
	99	*/
	100
	101	#define TWL4030_SIH_CTRL_EXCLEN_MASK BIT(0)
	102	#define TWL4030_SIH_CTRL_PENDDIS_MASK BIT(1)
	103	#define TWL4030_SIH_CTRL_COR_MASK BIT(2)
	104
	105	/----------------------------------------------------------------------/
	106
	107	/*
	108	* GPIO Block Register offsets (use TWL4030_MODULE_GPIO)
	109	*/
	110
	111	#define REG_GPIODATAIN1 0x0
	112	#define REG_GPIODATAIN2 0x1
	113	#define REG_GPIODATAIN3 0x2
	114	#define REG_GPIODATADIR1 0x3
	115	#define REG_GPIODATADIR2 0x4
	116	#define REG_GPIODATADIR3 0x5
	117	#define REG_GPIODATAOUT1 0x6
	118	#define REG_GPIODATAOUT2 0x7
	119	#define REG_GPIODATAOUT3 0x8
	120	#define REG_CLEARGPIODATAOUT1 0x9
	121	#define REG_CLEARGPIODATAOUT2 0xA
	122	#define REG_CLEARGPIODATAOUT3 0xB
	123	#define REG_SETGPIODATAOUT1 0xC
	124	#define REG_SETGPIODATAOUT2 0xD
	125	#define REG_SETGPIODATAOUT3 0xE
	126	#define REG_GPIO_DEBEN1 0xF
	127	#define REG_GPIO_DEBEN2 0x10
	128	#define REG_GPIO_DEBEN3 0x11
	129	#define REG_GPIO_CTRL 0x12
	130	#define REG_GPIOPUPDCTR1 0x13
	131	#define REG_GPIOPUPDCTR2 0x14
	132	#define REG_GPIOPUPDCTR3 0x15
	133	#define REG_GPIOPUPDCTR4 0x16
	134	#define REG_GPIOPUPDCTR5 0x17
	135	#define REG_GPIO_ISR1A 0x19
	136	#define REG_GPIO_ISR2A 0x1A
	137	#define REG_GPIO_ISR3A 0x1B
	138	#define REG_GPIO_IMR1A 0x1C
	139	#define REG_GPIO_IMR2A 0x1D
	140	#define REG_GPIO_IMR3A 0x1E
	141	#define REG_GPIO_ISR1B 0x1F
	142	#define REG_GPIO_ISR2B 0x20
	143	#define REG_GPIO_ISR3B 0x21
	144	#define REG_GPIO_IMR1B 0x22
	145	#define REG_GPIO_IMR2B 0x23
	146	#define REG_GPIO_IMR3B 0x24
	147	#define REG_GPIO_EDR1 0x28
	148	#define REG_GPIO_EDR2 0x29
	149	#define REG_GPIO_EDR3 0x2A
	150	#define REG_GPIO_EDR4 0x2B
	151	#define REG_GPIO_EDR5 0x2C
	152	#define REG_GPIO_SIH_CTRL 0x2D
153
154	/* Up to 18 signals are available as GPIOs, when their
155	* pins are not assigned to another use (such as ULPI/USB).
156	*/
157	#define TWL4030_GPIO_MAX 18
158
159	/----------------------------------------------------------------------/
160
161	/*
162	* Keypad register offsets (use TWL4030_MODULE_KEYPAD)
163	* ... SIH/interrupt only
164	*/
165
166	#define TWL4030_KEYPAD_KEYP_ISR1 0x11
167	#define TWL4030_KEYPAD_KEYP_IMR1 0x12
168	#define TWL4030_KEYPAD_KEYP_ISR2 0x13
169	#define TWL4030_KEYPAD_KEYP_IMR2 0x14
170	#define TWL4030_KEYPAD_KEYP_SIR 0x15 /* test register */
171	#define TWL4030_KEYPAD_KEYP_EDR 0x16
172	#define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17
173
174	/----------------------------------------------------------------------/
175
176	/*
177	* Multichannel ADC register offsets (use TWL4030_MODULE_MADC)
178	* ... SIH/interrupt only
179	*/
180
181	#define TWL4030_MADC_ISR1 0x61
182	#define TWL4030_MADC_IMR1 0x62
183	#define TWL4030_MADC_ISR2 0x63
184	#define TWL4030_MADC_IMR2 0x64
185	#define TWL4030_MADC_SIR 0x65 /* test register */
186	#define TWL4030_MADC_EDR 0x66
187	#define TWL4030_MADC_SIH_CTRL 0x67
188
189	/----------------------------------------------------------------------/
190
191	/*
192	* Battery charger register offsets (use TWL4030_MODULE_INTERRUPTS)
193	*/
194
195	#define TWL4030_INTERRUPTS_BCIISR1A 0x0
196	#define TWL4030_INTERRUPTS_BCIISR2A 0x1
197	#define TWL4030_INTERRUPTS_BCIIMR1A 0x2
198	#define TWL4030_INTERRUPTS_BCIIMR2A 0x3
199	#define TWL4030_INTERRUPTS_BCIISR1B 0x4
200	#define TWL4030_INTERRUPTS_BCIISR2B 0x5
201	#define TWL4030_INTERRUPTS_BCIIMR1B 0x6
202	#define TWL4030_INTERRUPTS_BCIIMR2B 0x7
203	#define TWL4030_INTERRUPTS_BCISIR1 0x8 /* test register */
204	#define TWL4030_INTERRUPTS_BCISIR2 0x9 /* test register */
205	#define TWL4030_INTERRUPTS_BCIEDR1 0xa
206	#define TWL4030_INTERRUPTS_BCIEDR2 0xb
207	#define TWL4030_INTERRUPTS_BCIEDR3 0xc
208	#define TWL4030_INTERRUPTS_BCISIHCTRL 0xd
209
210	/----------------------------------------------------------------------/
211
212	/*
213	* Power Interrupt block register offsets (use TWL4030_MODULE_INT)
214	*/
215
216	#define TWL4030_INT_PWR_ISR1 0x0
217	#define TWL4030_INT_PWR_IMR1 0x1
218	#define TWL4030_INT_PWR_ISR2 0x2
219	#define TWL4030_INT_PWR_IMR2 0x3
220	#define TWL4030_INT_PWR_SIR 0x4 /* test register */
221	#define TWL4030_INT_PWR_EDR1 0x5
222	#define TWL4030_INT_PWR_EDR2 0x6
223	#define TWL4030_INT_PWR_SIH_CTRL 0x7
224
225	/----------------------------------------------------------------------/
226
1920a61e IK	227	/*
	228	* Accessory Interrupts
	229	*/
	230	#define TWL5031_ACIIMR_LSB 0x05
	231	#define TWL5031_ACIIMR_MSB 0x06
	232	#define TWL5031_ACIIDR_LSB 0x07
	233	#define TWL5031_ACIIDR_MSB 0x08
	234	#define TWL5031_ACCISR1 0x0F
	235	#define TWL5031_ACCIMR1 0x10
	236	#define TWL5031_ACCISR2 0x11
	237	#define TWL5031_ACCIMR2 0x12
	238	#define TWL5031_ACCSIR 0x13
	239	#define TWL5031_ACCEDR1 0x14
	240	#define TWL5031_ACCSIHCTRL 0x15
	241
	242	/----------------------------------------------------------------------/
	243
	244	/*
	245	* Battery Charger Controller
	246	*/
	247
	248	#define TWL5031_INTERRUPTS_BCIISR1 0x0
	249	#define TWL5031_INTERRUPTS_BCIIMR1 0x1
	250	#define TWL5031_INTERRUPTS_BCIISR2 0x2
	251	#define TWL5031_INTERRUPTS_BCIIMR2 0x3
	252	#define TWL5031_INTERRUPTS_BCISIR 0x4
	253	#define TWL5031_INTERRUPTS_BCIEDR1 0x5
	254	#define TWL5031_INTERRUPTS_BCIEDR2 0x6
	255	#define TWL5031_INTERRUPTS_BCISIHCTRL 0x7
	256
	257	/----------------------------------------------------------------------/
	258
fa16a5c1 DB	259	/* Power bus message definitions */
fa16a5c1 DB	260
ebf0bd36 AK	261	/* The TWL4030/5030 splits its power-management resources (the various
	262	* regulators, clock and reset lines) into 3 processor groups - P1, P2 and
	263	* P3. These groups can then be configured to transition between sleep, wait-on
	264	* and active states by sending messages to the power bus. See Section 5.4.2
	265	* Power Resources of TWL4030 TRM
	266	*/
fa16a5c1	267
ebf0bd36 AK	268	/* Processor groups */
	269	#define DEV_GRP_NULL 0x0
	270	#define DEV_GRP_P1 0x1 /* P1: all OMAP devices */
	271	#define DEV_GRP_P2 0x2 /* P2: all Modem devices */
	272	#define DEV_GRP_P3 0x4 /* P3: all peripheral devices */
	273
	274	/* Resource groups */
	275	#define RES_GRP_RES 0x0 /* Reserved */
	276	#define RES_GRP_PP 0x1 /* Power providers */
	277	#define RES_GRP_RC 0x2 /* Reset and control */
fa16a5c1	278	#define RES_GRP_PP_RC 0x3
ebf0bd36	279	#define RES_GRP_PR 0x4 /* Power references */
fa16a5c1 DB	280	#define RES_GRP_PP_PR 0x5
fa16a5c1 DB	281	#define RES_GRP_RC_PR 0x6
ebf0bd36	282	#define RES_GRP_ALL 0x7 /* All resource groups */
fa16a5c1 DB	283
	284	#define RES_TYPE2_R0 0x0
	285
	286	#define RES_TYPE_ALL 0x7
	287
b4ead61e	288	/* Resource states */
fa16a5c1 DB	289	#define RES_STATE_WRST 0xF
	290	#define RES_STATE_ACTIVE 0xE
	291	#define RES_STATE_SLEEP 0x8
	292	#define RES_STATE_OFF 0x0
	293
ebf0bd36 AK	294	/* Power resources */
	295
	296	/* Power providers */
	297	#define RES_VAUX1 1
	298	#define RES_VAUX2 2
	299	#define RES_VAUX3 3
	300	#define RES_VAUX4 4
	301	#define RES_VMMC1 5
	302	#define RES_VMMC2 6
	303	#define RES_VPLL1 7
	304	#define RES_VPLL2 8
	305	#define RES_VSIM 9
	306	#define RES_VDAC 10
	307	#define RES_VINTANA1 11
	308	#define RES_VINTANA2 12
	309	#define RES_VINTDIG 13
	310	#define RES_VIO 14
	311	#define RES_VDD1 15
	312	#define RES_VDD2 16
	313	#define RES_VUSB_1V5 17
	314	#define RES_VUSB_1V8 18
	315	#define RES_VUSB_3V1 19
	316	#define RES_VUSBCP 20
	317	#define RES_REGEN 21
	318	/* Reset and control */
	319	#define RES_NRES_PWRON 22
	320	#define RES_CLKEN 23
	321	#define RES_SYSEN 24
	322	#define RES_HFCLKOUT 25
	323	#define RES_32KCLKOUT 26
	324	#define RES_RESET 27
	325	/* Power Reference */
	326	#define RES_Main_Ref 28
	327
	328	#define TOTAL_RESOURCES 28
fa16a5c1 DB	329	/*
	330	* Power Bus Message Format ... these can be sent individually by Linux,
	331	* but are usually part of downloaded scripts that are run when various
	332	* power events are triggered.
	333	*
	334	* Broadcast Message (16 Bits):
	335	* DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4]
	336	* RES_STATE[3:0]
	337	*
	338	* Singular Message (16 Bits):
	339	* DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0]
	340	*/
	341
	342	#define MSG_BROADCAST(devgrp, grp, type, type2, state) \
	343	( (devgrp) << 13 \| 1 << 12 \| (grp) << 9 \| (type2) << 7 \
	344	\| (type) << 4 \| (state))
	345
	346	#define MSG_SINGULAR(devgrp, id, state) \
	347	((devgrp) << 13 \| 0 << 12 \| (id) << 4 \| (state))
	348
	349	/----------------------------------------------------------------------/
	350
38a68496 IK	351	struct twl4030_clock_init_data {
	352	bool ck32k_lowpwr_enable;
	353	};
	354
a603a7fa DB	355	struct twl4030_bci_platform_data {
	356	int *battery_tmp_tbl;
	357	unsigned int tblsize;
	358	};
	359
	360	/* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */
	361	struct twl4030_gpio_platform_data {
	362	int gpio_base;
	363	unsigned irq_base, irq_end;
	364
a30d46c0 DB	365	/* package the two LED signals as output-only GPIOs? */
	366	bool use_leds;
	367
	368	/* gpio-n should control VMMC(n+1) if BIT(n) in mmc_cd is set */
	369	u8 mmc_cd;
	370
cabb3fc4 DB	371	/* if BIT(N) is set, or VMMC(n+1) is linked, debounce GPIO-N */
	372	u32 debounce;
	373
a603a7fa DB	374	/* For gpio-N, bit (1 << N) in "pullups" is set if that pullup
	375	* should be enabled. Else, if that bit is set in "pulldowns",
	376	* that pulldown is enabled. Don't waste power by letting any
	377	* digital inputs float...
	378	*/
	379	u32 pullups;
	380	u32 pulldowns;
	381
	382	int (setup)(struct device dev,
	383	unsigned gpio, unsigned ngpio);
	384	int (teardown)(struct device dev,
	385	unsigned gpio, unsigned ngpio);
	386	};
	387
	388	struct twl4030_madc_platform_data {
	389	int irq_line;
	390	};
	391
acf442dc AK	392	/* Boards have uniqe mappings of {row, col} --> keycode.
acf442dc AK	393	* Column and row are 8 bits each, but range only from 0..7.
9d834068 DB	394	* a PERSISTENT_KEY is "always on" and never reported.
9d834068 DB	395	*/
acf442dc	396	#define PERSISTENT_KEY(r, c) KEY((r), (c), KEY_RESERVED)
9d834068	397
a603a7fa	398	struct twl4030_keypad_data {
9d834068 DB	399	const struct matrix_keymap_data *keymap_data;
	400	unsigned rows;
	401	unsigned cols;
	402	bool rep;
a603a7fa DB	403	};
	404
	405	enum twl4030_usb_mode {
	406	T2_USB_MODE_ULPI = 1,
	407	T2_USB_MODE_CEA2011_3PIN = 2,
	408	};
	409
	410	struct twl4030_usb_data {
	411	enum twl4030_usb_mode usb_mode;
	412	};
	413
ebf0bd36 AK	414	struct twl4030_ins {
	415	u16 pmb_message;
	416	u8 delay;
	417	};
	418
	419	struct twl4030_script {
	420	struct twl4030_ins *script;
	421	unsigned size;
	422	u8 flags;
	423	#define TWL4030_WRST_SCRIPT (1<<0)
	424	#define TWL4030_WAKEUP12_SCRIPT (1<<1)
	425	#define TWL4030_WAKEUP3_SCRIPT (1<<2)
	426	#define TWL4030_SLEEP_SCRIPT (1<<3)
	427	};
	428
	429	struct twl4030_resconfig {
	430	u8 resource;
	431	u8 devgroup; /* Processor group that Power resource belongs to */
	432	u8 type; /* Power resource addressed, 6 / broadcast message */
	433	u8 type2; /* Power resource addressed, 3 / broadcast message */
b4ead61e AK	434	u8 remap_off; /* off state remapping */
b4ead61e AK	435	u8 remap_sleep; /* sleep state remapping */
ebf0bd36 AK	436	};
	437
	438	struct twl4030_power_data {
	439	struct twl4030_script **scripts;
	440	unsigned num;
	441	struct twl4030_resconfig *resource_config;
56baa667	442	#define TWL4030_RESCONFIG_UNDEF ((u8)-1)
ebf0bd36 AK	443	};
	444
	445	extern void twl4030_power_init(struct twl4030_power_data *triton2_scripts);
	446
0b83ddeb PU	447	struct twl4030_codec_audio_data {
	448	unsigned int audio_mclk;
	449	unsigned int ramp_delay_value;
	450	unsigned int hs_extmute:1;
	451	void (*set_hs_extmute)(int mute);
	452	};
	453
	454	struct twl4030_codec_vibra_data {
	455	unsigned int audio_mclk;
	456	unsigned int coexist;
	457	};
	458
	459	struct twl4030_codec_data {
cfd5324e	460	unsigned int audio_mclk;
0b83ddeb PU	461	struct twl4030_codec_audio_data *audio;
	462	struct twl4030_codec_vibra_data *vibra;
	463	};
	464
a603a7fa DB	465	struct twl4030_platform_data {
a603a7fa DB	466	unsigned irq_base, irq_end;
38a68496	467	struct twl4030_clock_init_data *clock;
a603a7fa DB	468	struct twl4030_bci_platform_data *bci;
	469	struct twl4030_gpio_platform_data *gpio;
	470	struct twl4030_madc_platform_data *madc;
	471	struct twl4030_keypad_data *keypad;
	472	struct twl4030_usb_data *usb;
ebf0bd36	473	struct twl4030_power_data *power;
0b83ddeb	474	struct twl4030_codec_data *codec;
a603a7fa	475
dad759ff DB	476	/* LDO regulators */
	477	struct regulator_init_data *vdac;
	478	struct regulator_init_data *vpll1;
	479	struct regulator_init_data *vpll2;
	480	struct regulator_init_data *vmmc1;
	481	struct regulator_init_data *vmmc2;
	482	struct regulator_init_data *vsim;
	483	struct regulator_init_data *vaux1;
	484	struct regulator_init_data *vaux2;
	485	struct regulator_init_data *vaux3;
	486	struct regulator_init_data *vaux4;
ab4abe05 JKS	487	struct regulator_init_data *vio;
	488	struct regulator_init_data *vdd1;
	489	struct regulator_init_data *vdd2;
	490	struct regulator_init_data *vintana1;
	491	struct regulator_init_data *vintana2;
	492	struct regulator_init_data *vintdig;
a603a7fa DB	493	};
	494
	495	/----------------------------------------------------------------------/
	496
a30d46c0 DB	497	int twl4030_sih_setup(int module);
a30d46c0 DB	498
a603a7fa DB	499	/* Offsets to Power Registers */
	500	#define TWL4030_VDAC_DEV_GRP 0x3B
	501	#define TWL4030_VDAC_DEDICATED 0x3E
	502	#define TWL4030_VAUX1_DEV_GRP 0x17
	503	#define TWL4030_VAUX1_DEDICATED 0x1A
	504	#define TWL4030_VAUX2_DEV_GRP 0x1B
	505	#define TWL4030_VAUX2_DEDICATED 0x1E
	506	#define TWL4030_VAUX3_DEV_GRP 0x1F
	507	#define TWL4030_VAUX3_DEDICATED 0x22
	508
a603a7fa DB	509	#if defined(CONFIG_TWL4030_BCI_BATTERY) \|\| \
	510	defined(CONFIG_TWL4030_BCI_BATTERY_MODULE)
	511	extern int twl4030charger_usb_en(int enable);
	512	#else
	513	static inline int twl4030charger_usb_en(int enable) { return 0; }
	514	#endif
	515
dad759ff DB	516	/----------------------------------------------------------------------/
	517
	518	/* Linux-specific regulator identifiers ... for now, we only support
	519	* the LDOs, and leave the three buck converters alone. VDD1 and VDD2
	520	* need to tie into hardware based voltage scaling (cpufreq etc), while
	521	* VIO is generally fixed.
	522	*/
	523
	524	/* EXTERNAL dc-to-dc buck converters */
	525	#define TWL4030_REG_VDD1 0
	526	#define TWL4030_REG_VDD2 1
	527	#define TWL4030_REG_VIO 2
	528
	529	/* EXTERNAL LDOs */
	530	#define TWL4030_REG_VDAC 3
	531	#define TWL4030_REG_VPLL1 4
	532	#define TWL4030_REG_VPLL2 5 /* not on all chips */
	533	#define TWL4030_REG_VMMC1 6
	534	#define TWL4030_REG_VMMC2 7 /* not on all chips */
	535	#define TWL4030_REG_VSIM 8 /* not on all chips */
	536	#define TWL4030_REG_VAUX1 9 /* not on all chips */
	537	#define TWL4030_REG_VAUX2_4030 10 /* (twl4030-specific) */
	538	#define TWL4030_REG_VAUX2 11 /* (twl5030 and newer) */
	539	#define TWL4030_REG_VAUX3 12 /* not on all chips */
	540	#define TWL4030_REG_VAUX4 13 /* not on all chips */
	541
	542	/* INTERNAL LDOs */
	543	#define TWL4030_REG_VINTANA1 14
	544	#define TWL4030_REG_VINTANA2 15
	545	#define TWL4030_REG_VINTDIG 16
	546	#define TWL4030_REG_VUSB1V5 17
	547	#define TWL4030_REG_VUSB1V8 18
	548	#define TWL4030_REG_VUSB3V1 19
dad759ff	549
a603a7fa	550	#endif /* End of __TWL4030_H */