powerpc: Fix wrong error code from ppc32 select syscall
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / fsl_devices.h
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1/*
2 * include/linux/fsl_devices.h
3 *
4 * Definitions for any platform device related flags or structures for
5 * Freescale processor devices
6 *
4c8d3d99 7 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
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8 *
9 * Copyright 2004 Freescale Semiconductor, Inc
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
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17#ifndef _FSL_DEVICE_H_
18#define _FSL_DEVICE_H_
19
20#include <linux/types.h>
21
22/*
23 * Some conventions on how we handle peripherals on Freescale chips
24 *
25 * unique device: a platform_device entry in fsl_plat_devs[] plus
26 * associated device information in its platform_data structure.
27 *
28 * A chip is described by a set of unique devices.
29 *
30 * Each sub-arch has its own master list of unique devices and
31 * enumerates them by enum fsl_devices in a sub-arch specific header
32 *
33 * The platform data structure is broken into two parts. The
34 * first is device specific information that help identify any
35 * unique features of a peripheral. The second is any
36 * information that may be defined by the board or how the device
37 * is connected externally of the chip.
38 *
39 * naming conventions:
40 * - platform data structures: <driver>_platform_data
41 * - platform data device flags: FSL_<driver>_DEV_<FLAG>
42 * - platform data board flags: FSL_<driver>_BRD_<FLAG>
43 *
44 */
45
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46enum fsl_usb2_operating_modes {
47 FSL_USB2_MPH_HOST,
48 FSL_USB2_DR_HOST,
49 FSL_USB2_DR_DEVICE,
50 FSL_USB2_DR_OTG,
51};
52
53enum fsl_usb2_phy_modes {
54 FSL_USB2_PHY_NONE,
55 FSL_USB2_PHY_ULPI,
56 FSL_USB2_PHY_UTMI,
57 FSL_USB2_PHY_UTMI_WIDE,
58 FSL_USB2_PHY_SERIAL,
59};
60
61struct fsl_usb2_platform_data {
62 /* board specific information */
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63 enum fsl_usb2_operating_modes operating_mode;
64 enum fsl_usb2_phy_modes phy_mode;
65 unsigned int port_enables;
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66};
67
68/* Flags in fsl_usb2_mph_platform_data */
69#define FSL_USB2_PORT0_ENABLED 0x00000001
70#define FSL_USB2_PORT1_ENABLED 0x00000002
71
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72struct spi_device;
73
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74struct fsl_spi_platform_data {
75 u32 initial_spmode; /* initial SPMODE value */
35b4b3c0 76 s16 bus_num;
87ec0e98 77 unsigned int flags;
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78 /* board specific information */
79 u16 max_chipselect;
364fdbc0 80 void (*cs_control)(struct spi_device *spi, bool on);
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81 u32 sysclk;
82};
83
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84struct mpc8xx_pcmcia_ops {
85 void(*hw_ctrl)(int slot, int enable);
86 int(*voltage_set)(int slot, int vcc, int vpp);
87};
88
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89/* Returns non-zero if the current suspend operation would
90 * lead to a deep sleep (i.e. power removed from the core,
91 * instead of just the clock).
92 */
2e9d546e 93#if defined(CONFIG_PPC_83xx) && defined(CONFIG_SUSPEND)
d49747bd 94int fsl_deep_sleep(void);
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95#else
96static inline int fsl_deep_sleep(void) { return 0; }
97#endif
d49747bd 98
98658538 99#endif /* _FSL_DEVICE_H_ */