[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / fsl_devices.h

/*
 * include/linux/fsl_devices.h
 *
 * Definitions for any platform device related flags or structures for
 * Freescale processor devices
 *
 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
 *
 * Copyright 2004 Freescale Semiconductor, Inc
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#ifndef _FSL_DEVICE_H_
#define _FSL_DEVICE_H_

#include <linux/types.h>
#include <linux/phy.h>

/*
 * Some conventions on how we handle peripherals on Freescale chips
 *
 * unique device: a platform_device entry in fsl_plat_devs[] plus
 * associated device information in its platform_data structure.
 *
 * A chip is described by a set of unique devices.
 *
 * Each sub-arch has its own master list of unique devices and
 * enumerates them by enum fsl_devices in a sub-arch specific header
 *
 * The platform data structure is broken into two parts.  The
 * first is device specific information that help identify any
 * unique features of a peripheral.  The second is any
 * information that may be defined by the board or how the device
 * is connected externally of the chip.
 *
 * naming conventions:
 * - platform data structures: <driver>_platform_data
 * - platform data device flags: FSL_<driver>_DEV_<FLAG>
 * - platform data board flags: FSL_<driver>_BRD_<FLAG>
 *
 */

struct gianfar_platform_data {
	/* device specific information */
	u32	device_flags;
	/* board specific information */
	u32	board_flags;
	char	bus_id[MII_BUS_ID_SIZE];
	u32	phy_id;
	u8	mac_addr[6];
	phy_interface_t interface;
};

struct gianfar_mdio_data {
	/* board specific information */
	int	irq[32];
};

/* Flags related to gianfar device features */
#define FSL_GIANFAR_DEV_HAS_GIGABIT		0x00000001
#define FSL_GIANFAR_DEV_HAS_COALESCE		0x00000002
#define FSL_GIANFAR_DEV_HAS_RMON		0x00000004
#define FSL_GIANFAR_DEV_HAS_MULTI_INTR		0x00000008
#define FSL_GIANFAR_DEV_HAS_CSUM		0x00000010
#define FSL_GIANFAR_DEV_HAS_VLAN		0x00000020
#define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH	0x00000040
#define FSL_GIANFAR_DEV_HAS_PADDING		0x00000080

/* Flags in gianfar_platform_data */
#define FSL_GIANFAR_BRD_HAS_PHY_INTR	0x00000001 /* set or use a timer */
#define FSL_GIANFAR_BRD_IS_REDUCED	0x00000002 /* Set if RGMII, RMII */

struct fsl_i2c_platform_data {
	/* device specific information */
	u32	device_flags;
};

/* Flags related to I2C device features */
#define FSL_I2C_DEV_SEPARATE_DFSRR	0x00000001
#define FSL_I2C_DEV_CLOCK_5200		0x00000002

enum fsl_usb2_operating_modes {
	FSL_USB2_MPH_HOST,
	FSL_USB2_DR_HOST,
	FSL_USB2_DR_DEVICE,
	FSL_USB2_DR_OTG,
};

enum fsl_usb2_phy_modes {
	FSL_USB2_PHY_NONE,
	FSL_USB2_PHY_ULPI,
	FSL_USB2_PHY_UTMI,
	FSL_USB2_PHY_UTMI_WIDE,
	FSL_USB2_PHY_SERIAL,
};

struct fsl_usb2_platform_data {
	/* board specific information */
	enum fsl_usb2_operating_modes	operating_mode;
	enum fsl_usb2_phy_modes		phy_mode;
	unsigned int			port_enables;
};

/* Flags in fsl_usb2_mph_platform_data */
#define FSL_USB2_PORT0_ENABLED	0x00000001
#define FSL_USB2_PORT1_ENABLED	0x00000002

struct fsl_spi_platform_data {
	u32 	initial_spmode;	/* initial SPMODE value */
	u16	bus_num;
	bool	qe_mode;
	/* board specific information */
	u16	max_chipselect;
	void	(*activate_cs)(u8 cs, u8 polarity);
	void	(*deactivate_cs)(u8 cs, u8 polarity);
	u32	sysclk;
};

struct mpc8xx_pcmcia_ops {
	void(*hw_ctrl)(int slot, int enable);
	int(*voltage_set)(int slot, int vcc, int vpp);
};

#endif /* _FSL_DEVICE_H_ */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* include/linux/fsl_devices.h
	3	*
	4	* Definitions for any platform device related flags or structures for
	5	* Freescale processor devices
	6	*
4c8d3d99	7	* Maintainer: Kumar Gala <galak@kernel.crashing.org>
1da177e4 LT	8	*
	9	* Copyright 2004 Freescale Semiconductor, Inc
	10	*
	11	* This program is free software; you can redistribute it and/or modify it
	12	* under the terms of the GNU General Public License as published by the
	13	* Free Software Foundation; either version 2 of the License, or (at your
	14	* option) any later version.
	15	*/
	16
1da177e4 LT	17	#ifndef _FSL_DEVICE_H_
	18	#define _FSL_DEVICE_H_
	19
	20	#include <linux/types.h>
d10f7348	21	#include <linux/phy.h>
1da177e4 LT	22
	23	/*
	24	* Some conventions on how we handle peripherals on Freescale chips
	25	*
	26	* unique device: a platform_device entry in fsl_plat_devs[] plus
	27	* associated device information in its platform_data structure.
	28	*
	29	* A chip is described by a set of unique devices.
	30	*
	31	* Each sub-arch has its own master list of unique devices and
	32	* enumerates them by enum fsl_devices in a sub-arch specific header
	33	*
	34	* The platform data structure is broken into two parts. The
	35	* first is device specific information that help identify any
	36	* unique features of a peripheral. The second is any
	37	* information that may be defined by the board or how the device
	38	* is connected externally of the chip.
	39	*
	40	* naming conventions:
	41	* - platform data structures: <driver>_platform_data
	42	* - platform data device flags: FSL_<driver>_DEV_<FLAG>
	43	* - platform data board flags: FSL_<driver>_BRD_<FLAG>
	44	*
	45	*/
	46
	47	struct gianfar_platform_data {
	48	/* device specific information */
98658538	49	u32 device_flags;
1da177e4	50	/* board specific information */
98658538	51	u32 board_flags;
9d9326d3	52	char bus_id[MII_BUS_ID_SIZE];
98658538 LY	53	u32 phy_id;
98658538 LY	54	u8 mac_addr[6];
7132ab7f	55	phy_interface_t interface;
1da177e4 LT	56	};
1da177e4 LT	57
b37665e0	58	struct gianfar_mdio_data {
b37665e0	59	/* board specific information */
98658538	60	int irq[32];
b37665e0 AF	61	};
b37665e0 AF	62
1da177e4 LT	63	/* Flags related to gianfar device features */
	64	#define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001
	65	#define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002
	66	#define FSL_GIANFAR_DEV_HAS_RMON 0x00000004
	67	#define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008
5b37b700 KG	68	#define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010
	69	#define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020
	70	#define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040
	71	#define FSL_GIANFAR_DEV_HAS_PADDING 0x00000080
1da177e4 LT	72
1da177e4 LT	73	/* Flags in gianfar_platform_data */
5b37b700 KG	74	#define FSL_GIANFAR_BRD_HAS_PHY_INTR 0x00000001 /* set or use a timer */
5b37b700 KG	75	#define FSL_GIANFAR_BRD_IS_REDUCED 0x00000002 /* Set if RGMII, RMII */
1da177e4 LT	76
	77	struct fsl_i2c_platform_data {
	78	/* device specific information */
98658538	79	u32 device_flags;
1da177e4 LT	80	};
	81
	82	/* Flags related to I2C device features */
	83	#define FSL_I2C_DEV_SEPARATE_DFSRR 0x00000001
	84	#define FSL_I2C_DEV_CLOCK_5200 0x00000002
	85
80cb9aee RV	86	enum fsl_usb2_operating_modes {
	87	FSL_USB2_MPH_HOST,
	88	FSL_USB2_DR_HOST,
	89	FSL_USB2_DR_DEVICE,
	90	FSL_USB2_DR_OTG,
	91	};
	92
	93	enum fsl_usb2_phy_modes {
	94	FSL_USB2_PHY_NONE,
	95	FSL_USB2_PHY_ULPI,
	96	FSL_USB2_PHY_UTMI,
	97	FSL_USB2_PHY_UTMI_WIDE,
	98	FSL_USB2_PHY_SERIAL,
	99	};
	100
	101	struct fsl_usb2_platform_data {
	102	/* board specific information */
98658538 LY	103	enum fsl_usb2_operating_modes operating_mode;
	104	enum fsl_usb2_phy_modes phy_mode;
	105	unsigned int port_enables;
80cb9aee RV	106	};
	107
	108	/* Flags in fsl_usb2_mph_platform_data */
	109	#define FSL_USB2_PORT0_ENABLED 0x00000001
	110	#define FSL_USB2_PORT1_ENABLED 0x00000002
	111
ccf06998 KG	112	struct fsl_spi_platform_data {
	113	u32 initial_spmode; /* initial SPMODE value */
	114	u16 bus_num;
f29ba280	115	bool qe_mode;
ccf06998 KG	116	/* board specific information */
	117	u16 max_chipselect;
	118	void (*activate_cs)(u8 cs, u8 polarity);
	119	void (*deactivate_cs)(u8 cs, u8 polarity);
	120	u32 sysclk;
	121	};
	122
80128ff7 VB	123	struct mpc8xx_pcmcia_ops {
	124	void(*hw_ctrl)(int slot, int enable);
	125	int(*voltage_set)(int slot, int vcc, int vpp);
	126	};
	127
98658538	128	#endif /* _FSL_DEVICE_H_ */