[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / dw_dmac.h

/*
 * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
 * AVR32 systems.)
 *
 * Copyright (C) 2007 Atmel Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef DW_DMAC_H
#define DW_DMAC_H

#include <linux/dmaengine.h>

/**
 * struct dw_dma_platform_data - Controller configuration parameters
 * @nr_channels: Number of channels supported by hardware (max 8)
 * @is_private: The device channels should be marked as private and not for
 *	by the general purpose DMA channel allocator.
 */
struct dw_dma_platform_data {
	unsigned int	nr_channels;
	bool		is_private;
#define CHAN_ALLOCATION_ASCENDING	0	/* zero to seven */
#define CHAN_ALLOCATION_DESCENDING	1	/* seven to zero */
	unsigned char	chan_allocation_order;
};

/**
 * enum dw_dma_slave_width - DMA slave register access width.
 * @DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses
 * @DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses
 * @DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses
 */
enum dw_dma_slave_width {
	DW_DMA_SLAVE_WIDTH_8BIT,
	DW_DMA_SLAVE_WIDTH_16BIT,
	DW_DMA_SLAVE_WIDTH_32BIT,
};

/**
 * struct dw_dma_slave - Controller-specific information about a slave
 *
 * @dma_dev: required DMA master device
 * @tx_reg: physical address of data register used for
 *	memory-to-peripheral transfers
 * @rx_reg: physical address of data register used for
 *	peripheral-to-memory transfers
 * @reg_width: peripheral register width
 * @cfg_hi: Platform-specific initializer for the CFG_HI register
 * @cfg_lo: Platform-specific initializer for the CFG_LO register
 */
struct dw_dma_slave {
	struct device		*dma_dev;
	dma_addr_t		tx_reg;
	dma_addr_t		rx_reg;
	enum dw_dma_slave_width	reg_width;
	u32			cfg_hi;
	u32			cfg_lo;
	int			src_master;
	int			dst_master;
};

/* Platform-configurable bits in CFG_HI */
#define DWC_CFGH_FCMODE		(1 << 0)
#define DWC_CFGH_FIFO_MODE	(1 << 1)
#define DWC_CFGH_PROTCTL(x)	((x) << 2)
#define DWC_CFGH_SRC_PER(x)	((x) << 7)
#define DWC_CFGH_DST_PER(x)	((x) << 11)

/* Platform-configurable bits in CFG_LO */
#define DWC_CFGL_PRIO(x)	((x) << 5)	/* priority */
#define DWC_CFGL_LOCK_CH_XFER	(0 << 12)	/* scope of LOCK_CH */
#define DWC_CFGL_LOCK_CH_BLOCK	(1 << 12)
#define DWC_CFGL_LOCK_CH_XACT	(2 << 12)
#define DWC_CFGL_LOCK_BUS_XFER	(0 << 14)	/* scope of LOCK_BUS */
#define DWC_CFGL_LOCK_BUS_BLOCK	(1 << 14)
#define DWC_CFGL_LOCK_BUS_XACT	(2 << 14)
#define DWC_CFGL_LOCK_CH	(1 << 15)	/* channel lockout */
#define DWC_CFGL_LOCK_BUS	(1 << 16)	/* busmaster lockout */
#define DWC_CFGL_HS_DST_POL	(1 << 18)	/* dst handshake active low */
#define DWC_CFGL_HS_SRC_POL	(1 << 19)	/* src handshake active low */

/* DMA API extensions */
struct dw_cyclic_desc {
	struct dw_desc	**desc;
	unsigned long	periods;
	void		(*period_callback)(void *param);
	void		*period_callback_param;
};

struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
		dma_addr_t buf_addr, size_t buf_len, size_t period_len,
		enum dma_data_direction direction);
void dw_dma_cyclic_free(struct dma_chan *chan);
int dw_dma_cyclic_start(struct dma_chan *chan);
void dw_dma_cyclic_stop(struct dma_chan *chan);

dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan);

dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan);

#endif /* DW_DMAC_H */
Commit	Line	Data
3bfb1d20 HS	1	/*
	2	* Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
	3	* AVR32 systems.)
	4	*
	5	* Copyright (C) 2007 Atmel Corporation
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11	#ifndef DW_DMAC_H
	12	#define DW_DMAC_H
	13
	14	#include <linux/dmaengine.h>
	15
	16	/**
	17	* struct dw_dma_platform_data - Controller configuration parameters
	18	* @nr_channels: Number of channels supported by hardware (max 8)
95ea759e JI	19	* @is_private: The device channels should be marked as private and not for
95ea759e JI	20	* by the general purpose DMA channel allocator.
3bfb1d20 HS	21	*/
	22	struct dw_dma_platform_data {
	23	unsigned int nr_channels;
95ea759e	24	bool is_private;
b0c3130d VK	25	#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */
	26	#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */
	27	unsigned char chan_allocation_order;
3bfb1d20 HS	28	};
3bfb1d20 HS	29
74465b4f DW	30	/**
	31	* enum dw_dma_slave_width - DMA slave register access width.
	32	* @DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses
	33	* @DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses
	34	* @DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses
	35	*/
	36	enum dw_dma_slave_width {
	37	DW_DMA_SLAVE_WIDTH_8BIT,
	38	DW_DMA_SLAVE_WIDTH_16BIT,
	39	DW_DMA_SLAVE_WIDTH_32BIT,
	40	};
	41
3bfb1d20 HS	42	/**
3bfb1d20 HS	43	* struct dw_dma_slave - Controller-specific information about a slave
74465b4f DW	44	*
	45	* @dma_dev: required DMA master device
	46	* @tx_reg: physical address of data register used for
	47	* memory-to-peripheral transfers
	48	* @rx_reg: physical address of data register used for
	49	* peripheral-to-memory transfers
	50	* @reg_width: peripheral register width
3bfb1d20 HS	51	* @cfg_hi: Platform-specific initializer for the CFG_HI register
	52	* @cfg_lo: Platform-specific initializer for the CFG_LO register
	53	*/
	54	struct dw_dma_slave {
74465b4f DW	55	struct device *dma_dev;
	56	dma_addr_t tx_reg;
	57	dma_addr_t rx_reg;
	58	enum dw_dma_slave_width reg_width;
3bfb1d20 HS	59	u32 cfg_hi;
3bfb1d20 HS	60	u32 cfg_lo;
f301c062 JI	61	int src_master;
f301c062 JI	62	int dst_master;
3bfb1d20 HS	63	};
	64
	65	/* Platform-configurable bits in CFG_HI */
	66	#define DWC_CFGH_FCMODE (1 << 0)
	67	#define DWC_CFGH_FIFO_MODE (1 << 1)
	68	#define DWC_CFGH_PROTCTL(x) ((x) << 2)
	69	#define DWC_CFGH_SRC_PER(x) ((x) << 7)
	70	#define DWC_CFGH_DST_PER(x) ((x) << 11)
	71
	72	/* Platform-configurable bits in CFG_LO */
	73	#define DWC_CFGL_PRIO(x) ((x) << 5) /* priority */
	74	#define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */
	75	#define DWC_CFGL_LOCK_CH_BLOCK (1 << 12)
	76	#define DWC_CFGL_LOCK_CH_XACT (2 << 12)
	77	#define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */
	78	#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
	79	#define DWC_CFGL_LOCK_BUS_XACT (2 << 14)
	80	#define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */
	81	#define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */
	82	#define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */
	83	#define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */
	84
d9de4519 HCE	85	/* DMA API extensions */
	86	struct dw_cyclic_desc {
	87	struct dw_desc **desc;
	88	unsigned long periods;
	89	void (period_callback)(void param);
	90	void *period_callback_param;
	91	};
	92
	93	struct dw_cyclic_desc dw_dma_cyclic_prep(struct dma_chan chan,
	94	dma_addr_t buf_addr, size_t buf_len, size_t period_len,
	95	enum dma_data_direction direction);
	96	void dw_dma_cyclic_free(struct dma_chan *chan);
	97	int dw_dma_cyclic_start(struct dma_chan *chan);
	98	void dw_dma_cyclic_stop(struct dma_chan *chan);
	99
	100	dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan);
	101
	102	dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan);
	103
3bfb1d20	104	#endif /* DW_DMAC_H */