[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / dma-mapping.h

#ifndef _LINUX_DMA_MAPPING_H
#define _LINUX_DMA_MAPPING_H

#include <linux/device.h>
#include <linux/err.h>
#include <linux/dma-attrs.h>
#include <linux/scatterlist.h>

/* These definitions mirror those in pci.h, so they can be used
 * interchangeably with their PCI_ counterparts */
enum dma_data_direction {
	DMA_BIDIRECTIONAL = 0,
	DMA_TO_DEVICE = 1,
	DMA_FROM_DEVICE = 2,
	DMA_NONE = 3,
};

struct dma_map_ops {
	void* (*alloc_coherent)(struct device *dev, size_t size,
				dma_addr_t *dma_handle, gfp_t gfp);
	void (*free_coherent)(struct device *dev, size_t size,
			      void *vaddr, dma_addr_t dma_handle);
	dma_addr_t (*map_page)(struct device *dev, struct page *page,
			       unsigned long offset, size_t size,
			       enum dma_data_direction dir,
			       struct dma_attrs *attrs);
	void (*unmap_page)(struct device *dev, dma_addr_t dma_handle,
			   size_t size, enum dma_data_direction dir,
			   struct dma_attrs *attrs);
	int (*map_sg)(struct device *dev, struct scatterlist *sg,
		      int nents, enum dma_data_direction dir,
		      struct dma_attrs *attrs);
	void (*unmap_sg)(struct device *dev,
			 struct scatterlist *sg, int nents,
			 enum dma_data_direction dir,
			 struct dma_attrs *attrs);
	void (*sync_single_for_cpu)(struct device *dev,
				    dma_addr_t dma_handle, size_t size,
				    enum dma_data_direction dir);
	void (*sync_single_for_device)(struct device *dev,
				       dma_addr_t dma_handle, size_t size,
				       enum dma_data_direction dir);
	void (*sync_single_range_for_cpu)(struct device *dev,
					  dma_addr_t dma_handle,
					  unsigned long offset,
					  size_t size,
					  enum dma_data_direction dir);
	void (*sync_single_range_for_device)(struct device *dev,
					     dma_addr_t dma_handle,
					     unsigned long offset,
					     size_t size,
					     enum dma_data_direction dir);
	void (*sync_sg_for_cpu)(struct device *dev,
				struct scatterlist *sg, int nents,
				enum dma_data_direction dir);
	void (*sync_sg_for_device)(struct device *dev,
				   struct scatterlist *sg, int nents,
				   enum dma_data_direction dir);
	int (*mapping_error)(struct device *dev, dma_addr_t dma_addr);
	int (*dma_supported)(struct device *dev, u64 mask);
	int is_phys;
};

#define DMA_BIT_MASK(n)	(((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))

/*
 * NOTE: do not use the below macros in new code and do not add new definitions
 * here.
 *
 * Instead, just open-code DMA_BIT_MASK(n) within your driver
 */
#define DMA_64BIT_MASK	DMA_BIT_MASK(64)
#define DMA_48BIT_MASK	DMA_BIT_MASK(48)
#define DMA_47BIT_MASK	DMA_BIT_MASK(47)
#define DMA_40BIT_MASK	DMA_BIT_MASK(40)
#define DMA_39BIT_MASK	DMA_BIT_MASK(39)
#define DMA_35BIT_MASK	DMA_BIT_MASK(35)
#define DMA_32BIT_MASK	DMA_BIT_MASK(32)
#define DMA_31BIT_MASK	DMA_BIT_MASK(31)
#define DMA_30BIT_MASK	DMA_BIT_MASK(30)
#define DMA_29BIT_MASK	DMA_BIT_MASK(29)
#define DMA_28BIT_MASK	DMA_BIT_MASK(28)
#define DMA_24BIT_MASK	DMA_BIT_MASK(24)

#define DMA_MASK_NONE	0x0ULL

static inline int valid_dma_direction(int dma_direction)
{
	return ((dma_direction == DMA_BIDIRECTIONAL) ||
		(dma_direction == DMA_TO_DEVICE) ||
		(dma_direction == DMA_FROM_DEVICE));
}

static inline int is_device_dma_capable(struct device *dev)
{
	return dev->dma_mask != NULL && *dev->dma_mask != DMA_MASK_NONE;
}

static inline int is_buffer_dma_capable(u64 mask, dma_addr_t addr, size_t size)
{
	return addr + size <= mask;
}

#ifdef CONFIG_HAS_DMA
#include <asm/dma-mapping.h>
#else
#include <asm-generic/dma-mapping-broken.h>
#endif

/* Backwards compat, remove in 2.7.x */
#define dma_sync_single		dma_sync_single_for_cpu
#define dma_sync_sg		dma_sync_sg_for_cpu

static inline u64 dma_get_mask(struct device *dev)
{
	if (dev && dev->dma_mask && *dev->dma_mask)
		return *dev->dma_mask;
	return DMA_32BIT_MASK;
}

extern u64 dma_get_required_mask(struct device *dev);

static inline unsigned int dma_get_max_seg_size(struct device *dev)
{
	return dev->dma_parms ? dev->dma_parms->max_segment_size : 65536;
}

static inline unsigned int dma_set_max_seg_size(struct device *dev,
						unsigned int size)
{
	if (dev->dma_parms) {
		dev->dma_parms->max_segment_size = size;
		return 0;
	} else
		return -EIO;
}

static inline unsigned long dma_get_seg_boundary(struct device *dev)
{
	return dev->dma_parms ?
		dev->dma_parms->segment_boundary_mask : 0xffffffff;
}

static inline int dma_set_seg_boundary(struct device *dev, unsigned long mask)
{
	if (dev->dma_parms) {
		dev->dma_parms->segment_boundary_mask = mask;
		return 0;
	} else
		return -EIO;
}

/* flags for the coherent memory api */
#define	DMA_MEMORY_MAP			0x01
#define DMA_MEMORY_IO			0x02
#define DMA_MEMORY_INCLUDES_CHILDREN	0x04
#define DMA_MEMORY_EXCLUSIVE		0x08

#ifndef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
static inline int
dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
			    dma_addr_t device_addr, size_t size, int flags)
{
	return 0;
}

static inline void
dma_release_declared_memory(struct device *dev)
{
}

static inline void *
dma_mark_declared_memory_occupied(struct device *dev,
				  dma_addr_t device_addr, size_t size)
{
	return ERR_PTR(-EBUSY);
}
#endif

/*
 * Managed DMA API
 */
extern void *dmam_alloc_coherent(struct device *dev, size_t size,
				 dma_addr_t *dma_handle, gfp_t gfp);
extern void dmam_free_coherent(struct device *dev, size_t size, void *vaddr,
			       dma_addr_t dma_handle);
extern void *dmam_alloc_noncoherent(struct device *dev, size_t size,
				    dma_addr_t *dma_handle, gfp_t gfp);
extern void dmam_free_noncoherent(struct device *dev, size_t size, void *vaddr,
				  dma_addr_t dma_handle);
#ifdef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
extern int dmam_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
					dma_addr_t device_addr, size_t size,
					int flags);
extern void dmam_release_declared_memory(struct device *dev);
#else /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */
static inline int dmam_declare_coherent_memory(struct device *dev,
				dma_addr_t bus_addr, dma_addr_t device_addr,
				size_t size, gfp_t gfp)
{
	return 0;
}

static inline void dmam_release_declared_memory(struct device *dev)
{
}
#endif /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */

#ifndef CONFIG_HAVE_DMA_ATTRS
struct dma_attrs;

#define dma_map_single_attrs(dev, cpu_addr, size, dir, attrs) \
	dma_map_single(dev, cpu_addr, size, dir)

#define dma_unmap_single_attrs(dev, dma_addr, size, dir, attrs) \
	dma_unmap_single(dev, dma_addr, size, dir)

#define dma_map_sg_attrs(dev, sgl, nents, dir, attrs) \
	dma_map_sg(dev, sgl, nents, dir)

#define dma_unmap_sg_attrs(dev, sgl, nents, dir, attrs) \
	dma_unmap_sg(dev, sgl, nents, dir)

#endif /* CONFIG_HAVE_DMA_ATTRS */

#endif
Commit	Line	Data
96532bab RD	1	#ifndef _LINUX_DMA_MAPPING_H
96532bab RD	2	#define _LINUX_DMA_MAPPING_H
1da177e4 LT	3
	4	#include <linux/device.h>
	5	#include <linux/err.h>
f0402a26 FT	6	#include <linux/dma-attrs.h>
f0402a26 FT	7	#include <linux/scatterlist.h>
1da177e4 LT	8
	9	/* These definitions mirror those in pci.h, so they can be used
	10	* interchangeably with their PCI_ counterparts */
	11	enum dma_data_direction {
	12	DMA_BIDIRECTIONAL = 0,
	13	DMA_TO_DEVICE = 1,
	14	DMA_FROM_DEVICE = 2,
	15	DMA_NONE = 3,
	16	};
	17
f0402a26 FT	18	struct dma_map_ops {
	19	void* (alloc_coherent)(struct device dev, size_t size,
	20	dma_addr_t *dma_handle, gfp_t gfp);
	21	void (free_coherent)(struct device dev, size_t size,
	22	void *vaddr, dma_addr_t dma_handle);
	23	dma_addr_t (map_page)(struct device dev, struct page *page,
	24	unsigned long offset, size_t size,
	25	enum dma_data_direction dir,
	26	struct dma_attrs *attrs);
	27	void (unmap_page)(struct device dev, dma_addr_t dma_handle,
	28	size_t size, enum dma_data_direction dir,
	29	struct dma_attrs *attrs);
	30	int (map_sg)(struct device dev, struct scatterlist *sg,
	31	int nents, enum dma_data_direction dir,
	32	struct dma_attrs *attrs);
	33	void (unmap_sg)(struct device dev,
	34	struct scatterlist *sg, int nents,
	35	enum dma_data_direction dir,
	36	struct dma_attrs *attrs);
	37	void (sync_single_for_cpu)(struct device dev,
	38	dma_addr_t dma_handle, size_t size,
	39	enum dma_data_direction dir);
	40	void (sync_single_for_device)(struct device dev,
	41	dma_addr_t dma_handle, size_t size,
	42	enum dma_data_direction dir);
	43	void (sync_single_range_for_cpu)(struct device dev,
	44	dma_addr_t dma_handle,
	45	unsigned long offset,
	46	size_t size,
	47	enum dma_data_direction dir);
	48	void (sync_single_range_for_device)(struct device dev,
	49	dma_addr_t dma_handle,
	50	unsigned long offset,
	51	size_t size,
	52	enum dma_data_direction dir);
	53	void (sync_sg_for_cpu)(struct device dev,
	54	struct scatterlist *sg, int nents,
	55	enum dma_data_direction dir);
	56	void (sync_sg_for_device)(struct device dev,
	57	struct scatterlist *sg, int nents,
	58	enum dma_data_direction dir);
	59	int (mapping_error)(struct device dev, dma_addr_t dma_addr);
	60	int (dma_supported)(struct device dev, u64 mask);
	61	int is_phys;
	62	};
	63
8f286c33	64	#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
34c65384	65
8f286c33 AM	66	/*
	67	* NOTE: do not use the below macros in new code and do not add new definitions
	68	* here.
	69	*
	70	* Instead, just open-code DMA_BIT_MASK(n) within your driver
	71	*/
	72	#define DMA_64BIT_MASK DMA_BIT_MASK(64)
34c65384 BP	73	#define DMA_48BIT_MASK DMA_BIT_MASK(48)
	74	#define DMA_47BIT_MASK DMA_BIT_MASK(47)
	75	#define DMA_40BIT_MASK DMA_BIT_MASK(40)
	76	#define DMA_39BIT_MASK DMA_BIT_MASK(39)
	77	#define DMA_35BIT_MASK DMA_BIT_MASK(35)
	78	#define DMA_32BIT_MASK DMA_BIT_MASK(32)
	79	#define DMA_31BIT_MASK DMA_BIT_MASK(31)
	80	#define DMA_30BIT_MASK DMA_BIT_MASK(30)
	81	#define DMA_29BIT_MASK DMA_BIT_MASK(29)
	82	#define DMA_28BIT_MASK DMA_BIT_MASK(28)
	83	#define DMA_24BIT_MASK DMA_BIT_MASK(24)
1da177e4	84
32e8f702 JB	85	#define DMA_MASK_NONE 0x0ULL
32e8f702 JB	86
d6bd3a39 REB	87	static inline int valid_dma_direction(int dma_direction)
	88	{
	89	return ((dma_direction == DMA_BIDIRECTIONAL) \|\|
	90	(dma_direction == DMA_TO_DEVICE) \|\|
	91	(dma_direction == DMA_FROM_DEVICE));
	92	}
	93
32e8f702 JB	94	static inline int is_device_dma_capable(struct device *dev)
	95	{
	96	return dev->dma_mask != NULL && *dev->dma_mask != DMA_MASK_NONE;
	97	}
	98
636dc67c FT	99	static inline int is_buffer_dma_capable(u64 mask, dma_addr_t addr, size_t size)
	100	{
	101	return addr + size <= mask;
	102	}
	103
1b0fac45	104	#ifdef CONFIG_HAS_DMA
1da177e4	105	#include <asm/dma-mapping.h>
1b0fac45 DW	106	#else
	107	#include <asm-generic/dma-mapping-broken.h>
	108	#endif
1da177e4 LT	109
	110	/* Backwards compat, remove in 2.7.x */
	111	#define dma_sync_single dma_sync_single_for_cpu
	112	#define dma_sync_sg dma_sync_sg_for_cpu
	113
589fc9a6 FT	114	static inline u64 dma_get_mask(struct device *dev)
589fc9a6 FT	115	{
07a2c01a	116	if (dev && dev->dma_mask && *dev->dma_mask)
589fc9a6 FT	117	return *dev->dma_mask;
	118	return DMA_32BIT_MASK;
	119	}
	120
1da177e4 LT	121	extern u64 dma_get_required_mask(struct device *dev);
1da177e4 LT	122
6b7b6510 FT	123	static inline unsigned int dma_get_max_seg_size(struct device *dev)
	124	{
	125	return dev->dma_parms ? dev->dma_parms->max_segment_size : 65536;
	126	}
	127
	128	static inline unsigned int dma_set_max_seg_size(struct device *dev,
	129	unsigned int size)
	130	{
	131	if (dev->dma_parms) {
	132	dev->dma_parms->max_segment_size = size;
	133	return 0;
	134	} else
	135	return -EIO;
	136	}
	137
d22a6966 FT	138	static inline unsigned long dma_get_seg_boundary(struct device *dev)
	139	{
	140	return dev->dma_parms ?
	141	dev->dma_parms->segment_boundary_mask : 0xffffffff;
	142	}
	143
	144	static inline int dma_set_seg_boundary(struct device *dev, unsigned long mask)
	145	{
	146	if (dev->dma_parms) {
	147	dev->dma_parms->segment_boundary_mask = mask;
	148	return 0;
	149	} else
	150	return -EIO;
	151	}
	152
1da177e4 LT	153	/* flags for the coherent memory api */
	154	#define DMA_MEMORY_MAP 0x01
	155	#define DMA_MEMORY_IO 0x02
	156	#define DMA_MEMORY_INCLUDES_CHILDREN 0x04
	157	#define DMA_MEMORY_EXCLUSIVE 0x08
	158
	159	#ifndef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
	160	static inline int
	161	dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
	162	dma_addr_t device_addr, size_t size, int flags)
	163	{
	164	return 0;
	165	}
	166
	167	static inline void
	168	dma_release_declared_memory(struct device *dev)
	169	{
	170	}
	171
	172	static inline void *
	173	dma_mark_declared_memory_occupied(struct device *dev,
	174	dma_addr_t device_addr, size_t size)
	175	{
	176	return ERR_PTR(-EBUSY);
	177	}
	178	#endif
	179
9ac7849e TH	180	/*
	181	* Managed DMA API
	182	*/
	183	extern void dmam_alloc_coherent(struct device dev, size_t size,
	184	dma_addr_t *dma_handle, gfp_t gfp);
	185	extern void dmam_free_coherent(struct device dev, size_t size, void vaddr,
	186	dma_addr_t dma_handle);
	187	extern void dmam_alloc_noncoherent(struct device dev, size_t size,
	188	dma_addr_t *dma_handle, gfp_t gfp);
	189	extern void dmam_free_noncoherent(struct device dev, size_t size, void vaddr,
	190	dma_addr_t dma_handle);
	191	#ifdef ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
	192	extern int dmam_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
	193	dma_addr_t device_addr, size_t size,
	194	int flags);
	195	extern void dmam_release_declared_memory(struct device *dev);
	196	#else /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */
	197	static inline int dmam_declare_coherent_memory(struct device *dev,
	198	dma_addr_t bus_addr, dma_addr_t device_addr,
	199	size_t size, gfp_t gfp)
	200	{
	201	return 0;
	202	}
1da177e4	203
9ac7849e TH	204	static inline void dmam_release_declared_memory(struct device *dev)
	205	{
	206	}
	207	#endif /* ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY */
1da177e4	208
74bc7cee AK	209	#ifndef CONFIG_HAVE_DMA_ATTRS
	210	struct dma_attrs;
	211
	212	#define dma_map_single_attrs(dev, cpu_addr, size, dir, attrs) \
	213	dma_map_single(dev, cpu_addr, size, dir)
	214
	215	#define dma_unmap_single_attrs(dev, dma_addr, size, dir, attrs) \
	216	dma_unmap_single(dev, dma_addr, size, dir)
	217
	218	#define dma_map_sg_attrs(dev, sgl, nents, dir, attrs) \
	219	dma_map_sg(dev, sgl, nents, dir)
	220
	221	#define dma_unmap_sg_attrs(dev, sgl, nents, dir, attrs) \
	222	dma_unmap_sg(dev, sgl, nents, dir)
	223
	224	#endif /* CONFIG_HAVE_DMA_ATTRS */
	225
9ac7849e	226	#endif