[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / drm / savage_drm.h

/* savage_drm.h -- Public header for the savage driver
 *
 * Copyright 2004  Felix Kuehling
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sub license,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef __SAVAGE_DRM_H__
#define __SAVAGE_DRM_H__

#ifndef __SAVAGE_SAREA_DEFINES__
#define __SAVAGE_SAREA_DEFINES__

/* 2 heaps (1 for card, 1 for agp), each divided into up to 128
 * regions, subject to a minimum region size of (1<<16) == 64k.
 *
 * Clients may subdivide regions internally, but when sharing between
 * clients, the region size is the minimum granularity.
 */

#define SAVAGE_CARD_HEAP		0
#define SAVAGE_AGP_HEAP			1
#define SAVAGE_NR_TEX_HEAPS		2
#define SAVAGE_NR_TEX_REGIONS		16
#define SAVAGE_LOG_MIN_TEX_REGION_SIZE	16

#endif				/* __SAVAGE_SAREA_DEFINES__ */

typedef struct _drm_savage_sarea {
	/* LRU lists for texture memory in agp space and on the card.
	 */
	struct drm_tex_region texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS +
						      1];
	unsigned int texAge[SAVAGE_NR_TEX_HEAPS];

	/* Mechanism to validate card state.
	 */
	int ctxOwner;
} drm_savage_sarea_t, *drm_savage_sarea_ptr;

/* Savage-specific ioctls
 */
#define DRM_SAVAGE_BCI_INIT		0x00
#define DRM_SAVAGE_BCI_CMDBUF           0x01
#define DRM_SAVAGE_BCI_EVENT_EMIT	0x02
#define DRM_SAVAGE_BCI_EVENT_WAIT	0x03

#define DRM_IOCTL_SAVAGE_BCI_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_INIT, drm_savage_init_t)
#define DRM_IOCTL_SAVAGE_BCI_CMDBUF		DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_CMDBUF, drm_savage_cmdbuf_t)
#define DRM_IOCTL_SAVAGE_BCI_EVENT_EMIT	DRM_IOWR(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_EMIT, drm_savage_event_emit_t)
#define DRM_IOCTL_SAVAGE_BCI_EVENT_WAIT	DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_WAIT, drm_savage_event_wait_t)

#define SAVAGE_DMA_PCI	1
#define SAVAGE_DMA_AGP	3
typedef struct drm_savage_init {
	enum {
		SAVAGE_INIT_BCI = 1,
		SAVAGE_CLEANUP_BCI = 2
	} func;
	unsigned int sarea_priv_offset;

	/* some parameters */
	unsigned int cob_size;
	unsigned int bci_threshold_lo, bci_threshold_hi;
	unsigned int dma_type;

	/* frame buffer layout */
	unsigned int fb_bpp;
	unsigned int front_offset, front_pitch;
	unsigned int back_offset, back_pitch;
	unsigned int depth_bpp;
	unsigned int depth_offset, depth_pitch;

	/* local textures */
	unsigned int texture_offset;
	unsigned int texture_size;

	/* physical locations of non-permanent maps */
	unsigned long status_offset;
	unsigned long buffers_offset;
	unsigned long agp_textures_offset;
	unsigned long cmd_dma_offset;
} drm_savage_init_t;

typedef union drm_savage_cmd_header drm_savage_cmd_header_t;
typedef struct drm_savage_cmdbuf {
	/* command buffer in client's address space */
	drm_savage_cmd_header_t __user *cmd_addr;
	unsigned int size;	/* size of the command buffer in 64bit units */

	unsigned int dma_idx;	/* DMA buffer index to use */
	int discard;		/* discard DMA buffer when done */
	/* vertex buffer in client's address space */
	unsigned int __user *vb_addr;
	unsigned int vb_size;	/* size of client vertex buffer in bytes */
	unsigned int vb_stride;	/* stride of vertices in 32bit words */
	/* boxes in client's address space */
	struct drm_clip_rect __user *box_addr;
	unsigned int nbox;	/* number of clipping boxes */
} drm_savage_cmdbuf_t;

#define SAVAGE_WAIT_2D  0x1	/* wait for 2D idle before updating event tag */
#define SAVAGE_WAIT_3D  0x2	/* wait for 3D idle before updating event tag */
#define SAVAGE_WAIT_IRQ 0x4	/* emit or wait for IRQ, not implemented yet */
typedef struct drm_savage_event {
	unsigned int count;
	unsigned int flags;
} drm_savage_event_emit_t, drm_savage_event_wait_t;

/* Commands for the cmdbuf ioctl
 */
#define SAVAGE_CMD_STATE	0	/* a range of state registers */
#define SAVAGE_CMD_DMA_PRIM	1	/* vertices from DMA buffer */
#define SAVAGE_CMD_VB_PRIM	2	/* vertices from client vertex buffer */
#define SAVAGE_CMD_DMA_IDX	3	/* indexed vertices from DMA buffer */
#define SAVAGE_CMD_VB_IDX	4	/* indexed vertices client vertex buffer */
#define SAVAGE_CMD_CLEAR	5	/* clear buffers */
#define SAVAGE_CMD_SWAP		6	/* swap buffers */

/* Primitive types
*/
#define SAVAGE_PRIM_TRILIST	0	/* triangle list */
#define SAVAGE_PRIM_TRISTRIP	1	/* triangle strip */
#define SAVAGE_PRIM_TRIFAN	2	/* triangle fan */
#define SAVAGE_PRIM_TRILIST_201	3	/* reorder verts for correct flat
					 * shading on s3d */

/* Skip flags (vertex format)
 */
#define SAVAGE_SKIP_Z		0x01
#define SAVAGE_SKIP_W		0x02
#define SAVAGE_SKIP_C0		0x04
#define SAVAGE_SKIP_C1		0x08
#define SAVAGE_SKIP_S0		0x10
#define SAVAGE_SKIP_T0		0x20
#define SAVAGE_SKIP_ST0		0x30
#define SAVAGE_SKIP_S1		0x40
#define SAVAGE_SKIP_T1		0x80
#define SAVAGE_SKIP_ST1		0xc0
#define SAVAGE_SKIP_ALL_S3D	0x3f
#define SAVAGE_SKIP_ALL_S4	0xff

/* Buffer names for clear command
 */
#define SAVAGE_FRONT		0x1
#define SAVAGE_BACK		0x2
#define SAVAGE_DEPTH		0x4

/* 64-bit command header
 */
union drm_savage_cmd_header {
	struct {
		unsigned char cmd;	/* command */
		unsigned char pad0;
		unsigned short pad1;
		unsigned short pad2;
		unsigned short pad3;
	} cmd;			/* generic */
	struct {
		unsigned char cmd;
		unsigned char global;	/* need idle engine? */
		unsigned short count;	/* number of consecutive registers */
		unsigned short start;	/* first register */
		unsigned short pad3;
	} state;		/* SAVAGE_CMD_STATE */
	struct {
		unsigned char cmd;
		unsigned char prim;	/* primitive type */
		unsigned short skip;	/* vertex format (skip flags) */
		unsigned short count;	/* number of vertices */
		unsigned short start;	/* first vertex in DMA/vertex buffer */
	} prim;			/* SAVAGE_CMD_DMA_PRIM, SAVAGE_CMD_VB_PRIM */
	struct {
		unsigned char cmd;
		unsigned char prim;
		unsigned short skip;
		unsigned short count;	/* number of indices that follow */
		unsigned short pad3;
	} idx;			/* SAVAGE_CMD_DMA_IDX, SAVAGE_CMD_VB_IDX */
	struct {
		unsigned char cmd;
		unsigned char pad0;
		unsigned short pad1;
		unsigned int flags;
	} clear0;		/* SAVAGE_CMD_CLEAR */
	struct {
		unsigned int mask;
		unsigned int value;
	} clear1;		/* SAVAGE_CMD_CLEAR data */
};

#endif
Commit	Line	Data
282a1674 DA	1	/* savage_drm.h -- Public header for the savage driver
	2	*
	3	* Copyright 2004 Felix Kuehling
	4	* All Rights Reserved.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sub license,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice (including the
	14	* next paragraph) shall be included in all copies or substantial portions
	15	* of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	18	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	19	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	20	* NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
	21	* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
	22	* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
	23	* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	24	*/
	25
	26	#ifndef __SAVAGE_DRM_H__
	27	#define __SAVAGE_DRM_H__
	28
	29	#ifndef __SAVAGE_SAREA_DEFINES__
	30	#define __SAVAGE_SAREA_DEFINES__
	31
25985edc	32	/* 2 heaps (1 for card, 1 for agp), each divided into up to 128
282a1674 DA	33	* regions, subject to a minimum region size of (1<<16) == 64k.
	34	*
	35	* Clients may subdivide regions internally, but when sharing between
	36	* clients, the region size is the minimum granularity.
	37	*/
	38
	39	#define SAVAGE_CARD_HEAP 0
	40	#define SAVAGE_AGP_HEAP 1
	41	#define SAVAGE_NR_TEX_HEAPS 2
	42	#define SAVAGE_NR_TEX_REGIONS 16
	43	#define SAVAGE_LOG_MIN_TEX_REGION_SIZE 16
	44
b5e89ed5	45	#endif /* __SAVAGE_SAREA_DEFINES__ */
282a1674 DA	46
	47	typedef struct _drm_savage_sarea {
	48	/* LRU lists for texture memory in agp space and on the card.
	49	*/
eddca551	50	struct drm_tex_region texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS +
b5e89ed5	51	1];
282a1674 DA	52	unsigned int texAge[SAVAGE_NR_TEX_HEAPS];
	53
	54	/* Mechanism to validate card state.
	55	*/
	56	int ctxOwner;
	57	} drm_savage_sarea_t, *drm_savage_sarea_ptr;
	58
	59	/* Savage-specific ioctls
	60	*/
	61	#define DRM_SAVAGE_BCI_INIT 0x00
	62	#define DRM_SAVAGE_BCI_CMDBUF 0x01
	63	#define DRM_SAVAGE_BCI_EVENT_EMIT 0x02
	64	#define DRM_SAVAGE_BCI_EVENT_WAIT 0x03
	65
1b2f1489 DA	66	#define DRM_IOCTL_SAVAGE_BCI_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_INIT, drm_savage_init_t)
	67	#define DRM_IOCTL_SAVAGE_BCI_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_CMDBUF, drm_savage_cmdbuf_t)
	68	#define DRM_IOCTL_SAVAGE_BCI_EVENT_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_EMIT, drm_savage_event_emit_t)
	69	#define DRM_IOCTL_SAVAGE_BCI_EVENT_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_WAIT, drm_savage_event_wait_t)
282a1674 DA	70
	71	#define SAVAGE_DMA_PCI 1
	72	#define SAVAGE_DMA_AGP 3
	73	typedef struct drm_savage_init {
	74	enum {
	75	SAVAGE_INIT_BCI = 1,
	76	SAVAGE_CLEANUP_BCI = 2
	77	} func;
	78	unsigned int sarea_priv_offset;
	79
	80	/* some parameters */
	81	unsigned int cob_size;
	82	unsigned int bci_threshold_lo, bci_threshold_hi;
	83	unsigned int dma_type;
	84
	85	/* frame buffer layout */
	86	unsigned int fb_bpp;
	87	unsigned int front_offset, front_pitch;
	88	unsigned int back_offset, back_pitch;
	89	unsigned int depth_bpp;
	90	unsigned int depth_offset, depth_pitch;
	91
	92	/* local textures */
	93	unsigned int texture_offset;
	94	unsigned int texture_size;
	95
	96	/* physical locations of non-permanent maps */
	97	unsigned long status_offset;
	98	unsigned long buffers_offset;
	99	unsigned long agp_textures_offset;
	100	unsigned long cmd_dma_offset;
	101	} drm_savage_init_t;
	102
	103	typedef union drm_savage_cmd_header drm_savage_cmd_header_t;
	104	typedef struct drm_savage_cmdbuf {
b5e89ed5	105	/* command buffer in client's address space */
282a1674 DA	106	drm_savage_cmd_header_t __user *cmd_addr;
	107	unsigned int size; /* size of the command buffer in 64bit units */
	108
	109	unsigned int dma_idx; /* DMA buffer index to use */
	110	int discard; /* discard DMA buffer when done */
b5e89ed5	111	/* vertex buffer in client's address space */
282a1674 DA	112	unsigned int __user *vb_addr;
	113	unsigned int vb_size; /* size of client vertex buffer in bytes */
	114	unsigned int vb_stride; /* stride of vertices in 32bit words */
b5e89ed5	115	/* boxes in client's address space */
eddca551	116	struct drm_clip_rect __user *box_addr;
282a1674 DA	117	unsigned int nbox; /* number of clipping boxes */
	118	} drm_savage_cmdbuf_t;
	119
b5e89ed5 DA	120	#define SAVAGE_WAIT_2D 0x1 /* wait for 2D idle before updating event tag */
	121	#define SAVAGE_WAIT_3D 0x2 /* wait for 3D idle before updating event tag */
	122	#define SAVAGE_WAIT_IRQ 0x4 /* emit or wait for IRQ, not implemented yet */
282a1674 DA	123	typedef struct drm_savage_event {
	124	unsigned int count;
	125	unsigned int flags;
	126	} drm_savage_event_emit_t, drm_savage_event_wait_t;
	127
	128	/* Commands for the cmdbuf ioctl
	129	*/
b5e89ed5 DA	130	#define SAVAGE_CMD_STATE 0 /* a range of state registers */
	131	#define SAVAGE_CMD_DMA_PRIM 1 /* vertices from DMA buffer */
	132	#define SAVAGE_CMD_VB_PRIM 2 /* vertices from client vertex buffer */
	133	#define SAVAGE_CMD_DMA_IDX 3 /* indexed vertices from DMA buffer */
	134	#define SAVAGE_CMD_VB_IDX 4 /* indexed vertices client vertex buffer */
	135	#define SAVAGE_CMD_CLEAR 5 /* clear buffers */
	136	#define SAVAGE_CMD_SWAP 6 /* swap buffers */
282a1674 DA	137
	138	/* Primitive types
	139	*/
b5e89ed5 DA	140	#define SAVAGE_PRIM_TRILIST 0 /* triangle list */
	141	#define SAVAGE_PRIM_TRISTRIP 1 /* triangle strip */
	142	#define SAVAGE_PRIM_TRIFAN 2 /* triangle fan */
	143	#define SAVAGE_PRIM_TRILIST_201 3 /* reorder verts for correct flat
	144	* shading on s3d */
282a1674 DA	145
	146	/* Skip flags (vertex format)
	147	*/
	148	#define SAVAGE_SKIP_Z 0x01
	149	#define SAVAGE_SKIP_W 0x02
	150	#define SAVAGE_SKIP_C0 0x04
	151	#define SAVAGE_SKIP_C1 0x08
	152	#define SAVAGE_SKIP_S0 0x10
	153	#define SAVAGE_SKIP_T0 0x20
	154	#define SAVAGE_SKIP_ST0 0x30
	155	#define SAVAGE_SKIP_S1 0x40
	156	#define SAVAGE_SKIP_T1 0x80
	157	#define SAVAGE_SKIP_ST1 0xc0
	158	#define SAVAGE_SKIP_ALL_S3D 0x3f
	159	#define SAVAGE_SKIP_ALL_S4 0xff
	160
	161	/* Buffer names for clear command
	162	*/
	163	#define SAVAGE_FRONT 0x1
	164	#define SAVAGE_BACK 0x2
	165	#define SAVAGE_DEPTH 0x4
	166
	167	/* 64-bit command header
	168	*/
	169	union drm_savage_cmd_header {
	170	struct {
	171	unsigned char cmd; /* command */
	172	unsigned char pad0;
	173	unsigned short pad1;
	174	unsigned short pad2;
	175	unsigned short pad3;
b5e89ed5	176	} cmd; /* generic */
282a1674 DA	177	struct {
	178	unsigned char cmd;
	179	unsigned char global; /* need idle engine? */
	180	unsigned short count; /* number of consecutive registers */
	181	unsigned short start; /* first register */
	182	unsigned short pad3;
b5e89ed5	183	} state; /* SAVAGE_CMD_STATE */
282a1674 DA	184	struct {
	185	unsigned char cmd;
	186	unsigned char prim; /* primitive type */
	187	unsigned short skip; /* vertex format (skip flags) */
	188	unsigned short count; /* number of vertices */
	189	unsigned short start; /* first vertex in DMA/vertex buffer */
b5e89ed5	190	} prim; /* SAVAGE_CMD_DMA_PRIM, SAVAGE_CMD_VB_PRIM */
282a1674 DA	191	struct {
	192	unsigned char cmd;
	193	unsigned char prim;
	194	unsigned short skip;
	195	unsigned short count; /* number of indices that follow */
	196	unsigned short pad3;
b5e89ed5	197	} idx; /* SAVAGE_CMD_DMA_IDX, SAVAGE_CMD_VB_IDX */
282a1674 DA	198	struct {
	199	unsigned char cmd;
	200	unsigned char pad0;
	201	unsigned short pad1;
	202	unsigned int flags;
b5e89ed5	203	} clear0; /* SAVAGE_CMD_CLEAR */
282a1674 DA	204	struct {
	205	unsigned int mask;
	206	unsigned int value;
b5e89ed5	207	} clear1; /* SAVAGE_CMD_CLEAR data */
282a1674 DA	208	};
	209
	210	#endif