[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / drm / nouveau_drm.h

/*
 * Copyright 2005 Stephane Marchesin.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef __NOUVEAU_DRM_H__
#define __NOUVEAU_DRM_H__

#define NOUVEAU_DRM_HEADER_PATCHLEVEL 16

struct drm_nouveau_channel_alloc {
	uint32_t     fb_ctxdma_handle;
	uint32_t     tt_ctxdma_handle;

	int          channel;
	uint32_t     pushbuf_domains;

	/* Notifier memory */
	uint32_t     notifier_handle;

	/* DRM-enforced subchannel assignments */
	struct {
		uint32_t handle;
		uint32_t grclass;
	} subchan[8];
	uint32_t nr_subchan;
};

struct drm_nouveau_channel_free {
	int channel;
};

struct drm_nouveau_grobj_alloc {
	int      channel;
	uint32_t handle;
	int      class;
};

struct drm_nouveau_notifierobj_alloc {
	uint32_t channel;
	uint32_t handle;
	uint32_t size;
	uint32_t offset;
};

struct drm_nouveau_gpuobj_free {
	int      channel;
	uint32_t handle;
};

/* FIXME : maybe unify {GET,SET}PARAMs */
#define NOUVEAU_GETPARAM_PCI_VENDOR      3
#define NOUVEAU_GETPARAM_PCI_DEVICE      4
#define NOUVEAU_GETPARAM_BUS_TYPE        5
#define NOUVEAU_GETPARAM_FB_SIZE         8
#define NOUVEAU_GETPARAM_AGP_SIZE        9
#define NOUVEAU_GETPARAM_CHIPSET_ID      11
#define NOUVEAU_GETPARAM_VM_VRAM_BASE    12
#define NOUVEAU_GETPARAM_GRAPH_UNITS     13
#define NOUVEAU_GETPARAM_PTIMER_TIME     14
#define NOUVEAU_GETPARAM_HAS_BO_USAGE    15
#define NOUVEAU_GETPARAM_HAS_PAGEFLIP    16
struct drm_nouveau_getparam {
	uint64_t param;
	uint64_t value;
};

struct drm_nouveau_setparam {
	uint64_t param;
	uint64_t value;
};

#define NOUVEAU_GEM_DOMAIN_CPU       (1 << 0)
#define NOUVEAU_GEM_DOMAIN_VRAM      (1 << 1)
#define NOUVEAU_GEM_DOMAIN_GART      (1 << 2)
#define NOUVEAU_GEM_DOMAIN_MAPPABLE  (1 << 3)

#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
#define NOUVEAU_GEM_TILE_16BPP       0x00000001
#define NOUVEAU_GEM_TILE_32BPP       0x00000002
#define NOUVEAU_GEM_TILE_ZETA        0x00000004
#define NOUVEAU_GEM_TILE_NONCONTIG   0x00000008

struct drm_nouveau_gem_info {
	uint32_t handle;
	uint32_t domain;
	uint64_t size;
	uint64_t offset;
	uint64_t map_handle;
	uint32_t tile_mode;
	uint32_t tile_flags;
};

struct drm_nouveau_gem_new {
	struct drm_nouveau_gem_info info;
	uint32_t channel_hint;
	uint32_t align;
};

#define NOUVEAU_GEM_MAX_BUFFERS 1024
struct drm_nouveau_gem_pushbuf_bo_presumed {
	uint32_t valid;
	uint32_t domain;
	uint64_t offset;
};

struct drm_nouveau_gem_pushbuf_bo {
	uint64_t user_priv;
	uint32_t handle;
	uint32_t read_domains;
	uint32_t write_domains;
	uint32_t valid_domains;
	struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
};

#define NOUVEAU_GEM_RELOC_LOW  (1 << 0)
#define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
#define NOUVEAU_GEM_RELOC_OR   (1 << 2)
#define NOUVEAU_GEM_MAX_RELOCS 1024
struct drm_nouveau_gem_pushbuf_reloc {
	uint32_t reloc_bo_index;
	uint32_t reloc_bo_offset;
	uint32_t bo_index;
	uint32_t flags;
	uint32_t data;
	uint32_t vor;
	uint32_t tor;
};

#define NOUVEAU_GEM_MAX_PUSH 512
struct drm_nouveau_gem_pushbuf_push {
	uint32_t bo_index;
	uint32_t pad;
	uint64_t offset;
	uint64_t length;
};

struct drm_nouveau_gem_pushbuf {
	uint32_t channel;
	uint32_t nr_buffers;
	uint64_t buffers;
	uint32_t nr_relocs;
	uint32_t nr_push;
	uint64_t relocs;
	uint64_t push;
	uint32_t suffix0;
	uint32_t suffix1;
	uint64_t vram_available;
	uint64_t gart_available;
};

#define NOUVEAU_GEM_CPU_PREP_NOWAIT                                  0x00000001
#define NOUVEAU_GEM_CPU_PREP_WRITE                                   0x00000004
struct drm_nouveau_gem_cpu_prep {
	uint32_t handle;
	uint32_t flags;
};

struct drm_nouveau_gem_cpu_fini {
	uint32_t handle;
};

enum nouveau_bus_type {
	NV_AGP     = 0,
	NV_PCI     = 1,
	NV_PCIE    = 2,
};

struct drm_nouveau_sarea {
};

#define DRM_NOUVEAU_GETPARAM           0x00
#define DRM_NOUVEAU_SETPARAM           0x01
#define DRM_NOUVEAU_CHANNEL_ALLOC      0x02
#define DRM_NOUVEAU_CHANNEL_FREE       0x03
#define DRM_NOUVEAU_GROBJ_ALLOC        0x04
#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC  0x05
#define DRM_NOUVEAU_GPUOBJ_FREE        0x06
#define DRM_NOUVEAU_GEM_NEW            0x40
#define DRM_NOUVEAU_GEM_PUSHBUF        0x41
#define DRM_NOUVEAU_GEM_CPU_PREP       0x42
#define DRM_NOUVEAU_GEM_CPU_FINI       0x43
#define DRM_NOUVEAU_GEM_INFO           0x44

#define DRM_IOCTL_NOUVEAU_GETPARAM           DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
#define DRM_IOCTL_NOUVEAU_SETPARAM           DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SETPARAM, struct drm_nouveau_setparam)
#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC      DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
#define DRM_IOCTL_NOUVEAU_CHANNEL_FREE       DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
#define DRM_IOCTL_NOUVEAU_GROBJ_ALLOC        DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GROBJ_ALLOC, struct drm_nouveau_grobj_alloc)
#define DRM_IOCTL_NOUVEAU_NOTIFIEROBJ_ALLOC  DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, struct drm_nouveau_notifierobj_alloc)
#define DRM_IOCTL_NOUVEAU_GPUOBJ_FREE        DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GPUOBJ_FREE, struct drm_nouveau_gpuobj_free)
#define DRM_IOCTL_NOUVEAU_GEM_NEW            DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF        DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP       DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI       DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
#define DRM_IOCTL_NOUVEAU_GEM_INFO           DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)

#endif /* __NOUVEAU_DRM_H__ */
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright 2005 Stephane Marchesin.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*/
	24
	25	#ifndef __NOUVEAU_DRM_H__
	26	#define __NOUVEAU_DRM_H__
	27
a1606a95	28	#define NOUVEAU_DRM_HEADER_PATCHLEVEL 16
6ee73861 BS	29
	30	struct drm_nouveau_channel_alloc {
	31	uint32_t fb_ctxdma_handle;
	32	uint32_t tt_ctxdma_handle;
	33
	34	int channel;
a1606a95	35	uint32_t pushbuf_domains;
6ee73861 BS	36
	37	/* Notifier memory */
	38	uint32_t notifier_handle;
	39
	40	/* DRM-enforced subchannel assignments */
	41	struct {
	42	uint32_t handle;
	43	uint32_t grclass;
	44	} subchan[8];
	45	uint32_t nr_subchan;
	46	};
	47
	48	struct drm_nouveau_channel_free {
	49	int channel;
	50	};
	51
	52	struct drm_nouveau_grobj_alloc {
	53	int channel;
	54	uint32_t handle;
	55	int class;
	56	};
	57
	58	struct drm_nouveau_notifierobj_alloc {
	59	uint32_t channel;
	60	uint32_t handle;
	61	uint32_t size;
	62	uint32_t offset;
	63	};
	64
	65	struct drm_nouveau_gpuobj_free {
	66	int channel;
	67	uint32_t handle;
	68	};
	69
	70	/* FIXME : maybe unify {GET,SET}PARAMs */
	71	#define NOUVEAU_GETPARAM_PCI_VENDOR 3
	72	#define NOUVEAU_GETPARAM_PCI_DEVICE 4
	73	#define NOUVEAU_GETPARAM_BUS_TYPE 5
6ee73861 BS	74	#define NOUVEAU_GETPARAM_FB_SIZE 8
6ee73861 BS	75	#define NOUVEAU_GETPARAM_AGP_SIZE 9
6ee73861 BS	76	#define NOUVEAU_GETPARAM_CHIPSET_ID 11
6ee73861 BS	77	#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
69c9700b	78	#define NOUVEAU_GETPARAM_GRAPH_UNITS 13
7fc74f17	79	#define NOUVEAU_GETPARAM_PTIMER_TIME 14
f13b3263	80	#define NOUVEAU_GETPARAM_HAS_BO_USAGE 15
332b242f	81	#define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16
6ee73861 BS	82	struct drm_nouveau_getparam {
	83	uint64_t param;
	84	uint64_t value;
	85	};
	86
	87	struct drm_nouveau_setparam {
	88	uint64_t param;
	89	uint64_t value;
	90	};
	91
	92	#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
	93	#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
	94	#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
	95	#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
	96
f13b3263 FJ	97	#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
	98	#define NOUVEAU_GEM_TILE_16BPP 0x00000001
	99	#define NOUVEAU_GEM_TILE_32BPP 0x00000002
	100	#define NOUVEAU_GEM_TILE_ZETA 0x00000004
	101	#define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008
	102
6ee73861 BS	103	struct drm_nouveau_gem_info {
	104	uint32_t handle;
	105	uint32_t domain;
	106	uint64_t size;
	107	uint64_t offset;
	108	uint64_t map_handle;
	109	uint32_t tile_mode;
	110	uint32_t tile_flags;
	111	};
	112
	113	struct drm_nouveau_gem_new {
	114	struct drm_nouveau_gem_info info;
	115	uint32_t channel_hint;
	116	uint32_t align;
	117	};
	118
a1606a95 BS	119	#define NOUVEAU_GEM_MAX_BUFFERS 1024
	120	struct drm_nouveau_gem_pushbuf_bo_presumed {
	121	uint32_t valid;
	122	uint32_t domain;
	123	uint64_t offset;
	124	};
	125
6ee73861 BS	126	struct drm_nouveau_gem_pushbuf_bo {
	127	uint64_t user_priv;
	128	uint32_t handle;
	129	uint32_t read_domains;
	130	uint32_t write_domains;
	131	uint32_t valid_domains;
a1606a95	132	struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
6ee73861 BS	133	};
	134
	135	#define NOUVEAU_GEM_RELOC_LOW (1 << 0)
	136	#define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
	137	#define NOUVEAU_GEM_RELOC_OR (1 << 2)
a1606a95	138	#define NOUVEAU_GEM_MAX_RELOCS 1024
6ee73861	139	struct drm_nouveau_gem_pushbuf_reloc {
a1606a95 BS	140	uint32_t reloc_bo_index;
a1606a95 BS	141	uint32_t reloc_bo_offset;
6ee73861	142	uint32_t bo_index;
6ee73861 BS	143	uint32_t flags;
	144	uint32_t data;
	145	uint32_t vor;
	146	uint32_t tor;
	147	};
	148
a1606a95 BS	149	#define NOUVEAU_GEM_MAX_PUSH 512
	150	struct drm_nouveau_gem_pushbuf_push {
	151	uint32_t bo_index;
	152	uint32_t pad;
	153	uint64_t offset;
	154	uint64_t length;
	155	};
6ee73861 BS	156
	157	struct drm_nouveau_gem_pushbuf {
	158	uint32_t channel;
6ee73861	159	uint32_t nr_buffers;
6ee73861	160	uint64_t buffers;
6ee73861	161	uint32_t nr_relocs;
a1606a95	162	uint32_t nr_push;
6ee73861	163	uint64_t relocs;
a1606a95	164	uint64_t push;
6ee73861 BS	165	uint32_t suffix0;
6ee73861 BS	166	uint32_t suffix1;
6ee73861 BS	167	uint64_t vram_available;
	168	uint64_t gart_available;
	169	};
	170
6ee73861	171	#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
6ee73861 BS	172	#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
	173	struct drm_nouveau_gem_cpu_prep {
	174	uint32_t handle;
	175	uint32_t flags;
	176	};
	177
	178	struct drm_nouveau_gem_cpu_fini {
	179	uint32_t handle;
	180	};
	181
6ee73861 BS	182	enum nouveau_bus_type {
	183	NV_AGP = 0,
	184	NV_PCI = 1,
	185	NV_PCIE = 2,
	186	};
	187
	188	struct drm_nouveau_sarea {
	189	};
	190
a1606a95 BS	191	#define DRM_NOUVEAU_GETPARAM 0x00
	192	#define DRM_NOUVEAU_SETPARAM 0x01
	193	#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
	194	#define DRM_NOUVEAU_CHANNEL_FREE 0x03
	195	#define DRM_NOUVEAU_GROBJ_ALLOC 0x04
	196	#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05
	197	#define DRM_NOUVEAU_GPUOBJ_FREE 0x06
6ee73861 BS	198	#define DRM_NOUVEAU_GEM_NEW 0x40
6ee73861 BS	199	#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
a1606a95 BS	200	#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
	201	#define DRM_NOUVEAU_GEM_CPU_FINI 0x43
	202	#define DRM_NOUVEAU_GEM_INFO 0x44
6ee73861	203
1b2f1489 DA	204	#define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
	205	#define DRM_IOCTL_NOUVEAU_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SETPARAM, struct drm_nouveau_setparam)
	206	#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
	207	#define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
	208	#define DRM_IOCTL_NOUVEAU_GROBJ_ALLOC DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GROBJ_ALLOC, struct drm_nouveau_grobj_alloc)
	209	#define DRM_IOCTL_NOUVEAU_NOTIFIEROBJ_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, struct drm_nouveau_notifierobj_alloc)
	210	#define DRM_IOCTL_NOUVEAU_GPUOBJ_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GPUOBJ_FREE, struct drm_nouveau_gpuobj_free)
	211	#define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
	212	#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
	213	#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
	214	#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
	215	#define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
	216
6ee73861	217	#endif /* __NOUVEAU_DRM_H__ */